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Practice 12 Dynamic Logic 2011 12 A

Dynamic logic uses a precharge-evaluate cycle controlled by a clock signal instead of static logic. During precharge, the output is charged high regardless of inputs. During evaluate, the output either stays high or discharges low based on inputs. Problems include output degradation from glitches, leakage currents, and charge sharing between transistors. Cascading dynamic gates can fail if the output transition of one stage does not match the input requirements of the next stage. Charge sharing calculations can determine voltage drops at nodes from multiple conducting transistors.

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64 views

Practice 12 Dynamic Logic 2011 12 A

Dynamic logic uses a precharge-evaluate cycle controlled by a clock signal instead of static logic. During precharge, the output is charged high regardless of inputs. During evaluate, the output either stays high or discharges low based on inputs. Problems include output degradation from glitches, leakage currents, and charge sharing between transistors. Cascading dynamic gates can fail if the output transition of one stage does not match the input requirements of the next stage. Charge sharing calculations can determine voltage drops at nodes from multiple conducting transistors.

Uploaded by

Kamlesh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Practice 12: Dynamic Logic

Dynamic Logic:
Dynamic logic is an alternative to standard Static Logic that we discussed up till now.
It generally consists of a PDN that is constructed identically to a CMOS PDN, but instead of a
PUN, it has a pair of complementary transistors that connected to the clock. These divide the
operation of the dynamic gate into Precharge and Evaluation phases.

When the clock is low (“Precharge”), the PDN is off (regardless of it’s logic state) and the
Precharge transistor is open, providing a high value to the output. When the clock toggles, the
Evaluation transistor (nMOS) opens, providing a conditional discharge path, depending on the
logic state of the PDN. Thus, either the output is discharged to a low value, or stays at its high
output from the Precharge stage.

Properties of Dynamic Gates:


1. N+2 transistors
2. High Operation Speed
3. Non-Ratioed
4. Low static power consumption
5. High dynamic power consumption
6. Zero short circuit power
Problems with Dynamic Gates:
High Output degradation can occur due to:
1. Input Glitches: the PDN is mistakenly open for a segment of the Evaluation phase.
2. Leakage Currents: There is not direct path to VDD for a high output during the Evaluation
phase.
3. Charge Sharing:
Output capacitances of transistors with a path to Vout
in a closed PDN share charge with the output.

4. Cascading Problem:
During Precharge the output of each stage is ‘1’,
opening all nMOS transistors in the following stage.
Until the output of the first stage discharges,
the output of the second stage will mistakenly
discharge.
Exercise 1: Dynamic Logic Cascading Problem
Suppose we want to implement two logic functions given by F=A+B+C and G=A+B+C+D. Assume
both true and complementary signals are available.
a) Implement these functions in dynamic CMOS as cascaded  stages so as to minimize
the total transistor count.
b) Discuss any conditions under which this implementation would fail to operate
properly.
c) Design an np-CMOS implementation of the same logic functions. Does this design
display any of the difficulties of part b)? VDD VDD

Solution:
 
a. Implementation of the functions in simple dynamic CMOS:
G
F
G  FD  A BC D

A B C
D

 

b. This circuit will fail to operate. When A+B+C=1, F will make a transition 1->0, which
cannot be applied directly to the second stage. If D=0 for example, G will be discharged
at the beginning of the evaluation phase. Therefore G will have an incorrect value (0) for
this combination of input signals.
c. To ensure operation, we can use an np-CMOS implementation. The stages in np-CMOS
can be cascaded directly since every stage produces the correct signal transition for the
opposite type of logic connected to its output.

VDD VDD

 

F
D
A B C
G

 
Exercise 2: Charge Sharing in Dynamic Circuits
Given the following circuit, assuming that all inputs of the circuit
shown in Figure 1 below are initially 0 during the precharge phase
and that all internal nodes are at 0V:
a. Calculate the voltage drop on Vo, if A changes to 1 (VDD=2.5V)
during the evaluate phase. It is given that Vtn0=0.5V,
2φF=0.6V and γ=0.4V0.5.
Hint: Don’t forget the body effect.
b. Now calculate the voltage drop on Vo if both A and B change to 1
(under the above conditions).
c. What is the maximum number of transistors that can be connected
in series to M1 and M2 (including M1 and M2, excluding M0) if the
output should not fall below 0.9V during the evaluate phase? Assume
that each one of the new transistors has the same intrinsic capacitance
(to ground) as M1 and M2 (C=10fF).

Solution
a. Assuming that ΔVout  Vtn , the capacitor C1 is charged to a voltage VS , which is the
maximum voltage for which M1 conducts. VS is calculated using the equation that is valid at
the edge of conduction and cut-off:

VGS  Vtn  VGS  Vtn 0  γ  2φF  VSB  2φF 


Since the bulk of the NMOS transistors is connected to ground, the previous equation
can be rewritten as:

VG  VS  Vtn 0  γ  2φF  VS  2φF  VG  VS  Vtn 0  γ 2φF  γ  2φF  VS 



 VG  VS  Vtn 0  γ 2φF   γ 2φ
2
2
F  VS   VS2  4.78VS  5.234  0
4.78V  1.38V
 VS   1.7V
2
(We accept only the lower solution of the quadratic equation, since after reaching this
voltage the transistor doesn’t conduct and can’t thus reach the higher value).
Hence, charge conservation yields:
CLVDD  CLVo  C1VS  CL ΔVo  C1VS  ΔVo  C1VS / CL  0.44V
Since VG  VS  Vtn , Vtn  0.8V .

Hence, our assumption about ΔVo  Vtn  0.8V was correct.

b. Similarly to (a), capacitors C1 and C 2 will be charged to a final voltage of 1.7V.


Hence, charge conservation gives: CL ΔVo  C1VS  C2VS  ΔVo  0.88V  Vtn

Hence, our assumption that ΔVout  Vtn doesn’t hold anymore and ΔVo is calculated as
Cs
follows: ΔVo  VDD , where Cs  C1  C2 .
Cs  CL
20
Hence, ΔVo  2.5V  0.83V
20  40
c. The final value of Vo  0.9V corresponds to ΔVo  1.6V  Vtn . Hence, the following
equation is valid:
Cs
ΔVo  VDD (1)
Cs  CL
where C s the total intrinsic capacitance to be charged.

The worst case is when all of the connected transistors conduct and thus Cs  NC
(where N the number of the transistors). In this case (1) gives:
ΔVo ( NC  CL )  VDD NC
 NC(VDD  ΔVo )  ΔVo CL
1.6V  40 fF
N  7.1 , hence N = 7.
0.9V  10 fF

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