Machine Learning in Computational Lithography

Yu Cao
ASML-Brion

San Jose, February 2019

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This is really a no-brainer …
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Slide 2

What’s Happening and What’s the Meaning:

ASML introduces AI to its product portfolio: This is really a no-brainer. That said, the
problem that most equipment companies have is finding good applications for it, as they find all
they have is little data to feed the NN (more on that below). Anyway, this will be a good test for
DLNNs as to whether engineers will accept results without knowing what’s in the ‘blackbox,’
which is a classic barrier to this technology. I believe they will because comparing results to
input consistency are pretty easy to test out in this case. Especially since ASML led the way into
computational lithography, albeit with plenty of customer pull.

Source: The Chip Insider®

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Machine learning brings revolution to many applications!
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Slide 3

Can machine learning be the moonshot for us?

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 We have been doing machine learning for a long time …
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with manual feature engineering Slide 4

Mask layout Optical model design Optical kernels Aerial image

1: E. Abbe, H. H. Hopkins Aerial image Resist model design Resist kernels Resist contour

2: F. H. Dill, C. Mack Few hidden layers = Shallow neural network Public

 Machine Learning evolved to Deep Learning
Less human intervention in growing data volume analysis Public
Slide 5

Machine Learning
95% cat
5% dog
Input Feature extraction Classification Output

Feature extraction & classification

95% cat
5% dog
Input Deep Learning
Feature extraction + Classification Output
Based on: Jagreet Kaur Gill, “Log Analytics With Deep Learning And Machine Learning” April 28, 2017 Public
 Massive metrology data & deep learning models further
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improve OPC accuracy in customer case Slide 6

• Big data improve pattern coverage & enhance model accuracy

• Deep Learning Model has more benefits with big data vs Traditional Model

Model accuracy improvement

with big data

(1 / Model Error, 3-sigma, nm-1)

0.4

Model Accuracy
0.3
Deep Learning Model
Traditional Model
0.2
~16,000 verification gauges
Regular hole patterns
0.1

0
0 600 800 1000 2000 8000 16000
Source: Jeff Dean, Google, “Trends and developments in deep learning”, Jan’17 Calibration gauge number

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High speed e-beam metrology and large field of view
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Slide 7
Excellent precision across large field of view

#1 #2 #3

eP5 Field of View

(12um x 12um)

Throughput advantage over CD-SEM

#4 #5 #6
CD-SEM CD-SEM eP5 68
Resolution 1 nm 1 nm
Field of View

Metrology Throughput
Current 8 pA 250 pA
(1um x 1um) Scan Rate 16 MHz 100 MHz
Field of view 1 um 12 um

12
#7 #8 #9 1

CD-SEM eP5 eP5

(1um FOV) (1um FOV) (12um FOV)
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 Improving OPC model accuracy by 2X on DRAM Public
enabled by deep learning, fast e-beam, and metrology processing Slide 8

Model prediction error (RMS) eP5-MXP metrology

validated with >150k Edge Placement (EP) Gauges Improving 2D metrology accuracy
with contour based measurement
-32%
• Systematic error removal
• Random noise reduction
• Improved pattern coverage
-18% 1.3
nm
• Capture unknown Irregular shape Center shift
physical effects Systematic error reduction EP gauges capture
without shape fitting pattern shift

Deep learning resist model

Improve OPC model accuracy

Baseline metrology eP5-MXP eP5-MXP

w/o deep learning w/o deep learning

Error
with deep learning 0

(CD gauges) 3.3x (CD+EP gauges) 3.3x (CD+EP gauges)

~18 hours ~3 hours
Metrology collection time Metrology collection time Gauges
3x images
OPC Model accuracy study using high volume contour based gauges and deep learning on memory device, Young-Seok Kim et al., SPIE 2019, 10959-37 Public
 Better accuracy of lithography models by deep learning
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Enabled by fast e-beam metrology and physical based models Slide 9

Model Prediction Accuracy

Physical driven training using (RMS in nm)
physics based lithography models EUV Cases: 7 nm and 5 nm logic
Stability

1.0
0.7
0.6
ASML Deep 0.4
0.5 0.7

Learning model 0.34 0.32

Physical Resist Data expansion
1D 2D 1D 2D
Resist surface through simulated
Shrinkage stress contours DUV Cases: 7 nm and 5 nm logic

1.2 1.3
Data-driven training based on fitting 1.1 1.1
1.0
0.8
spec and wafer measurements 0.7
0.4
Accuracy

EP SET1 EP SET2 1D 2D

with Deep Learning

without Deep Learning
Large volume wafer metrology data,
further enhanced by fast e-beam
“EP SET1”  Edge Placement Gauge Set 1
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“Moore’s Law” of Computational Lithography
Runtime and cost of OPC increases node-by-node Public
Slide 10

Technology Node 28nm 22nm 14nm 10nm 7nm 5nm

Production start 2011 2013 2014 2016 2017 2019
Average transistor density (billion/cm2) 1.17 1.63 2.34 3.75 6.25 10.71
Number of critical layer masks 18 24 33 37 47 66
Normalized OPC runtime per layer per unit area 1 1.4 2 2.7 4 5.6

Node-on-node OPC runtime trends

6.0
OPC runtime per layer (normalized)

5.0 Total computational litho

capacity worldwide on the
4.0
order of 10 petaflops
3.0

2.0

1.0

0.0
28nm 22nm 14nm 10nm 7nm 5nm Public
 Deep learning inverse model speeds up full-chip OPC
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by providing a good starting point Slide 11

Design target Inverse mask image

Selected clips

Complex, Iterative Deep Learning Inverse Model

Optimization
Training on clips Training input Training input

Inference on full chip Design target Inverse mask image

Full chip layout Full chip layout (Post-OPC)

Deep Learning Inverse Model

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 Improving training pattern coverage
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using machine-learning-based pattern selection Slide 12

Full-chip Layout Pattern Library Machine-learning-based pattern selection Training Pattern Set

Pattern Representative
… Feature Clustering Selection
Pattern Generation
Collector
…

…
Normalized RMS between prediction
and ground-truth (inverse solution) Critical PV-band (>15% CD error ) Comparison

This Manual This Manual

Random selections Random selections
method selection method selection

Full-chip application of machine learning SRAFs on DRAM case using auto pattern selection K. Chen et al., SPIE 2019, 10961-37 Public
 Deep learning SRAF improves full-chip DoF by 24%
for DRAM contact hole layer, validated on wafer Slide 13

Newron SRAF places more accurate assist Newron SRAF wafer validation
features to remove the process window limiter shows 24% DoF improvement
Off-nominal
OPC Mask
(-40nm defocus)
9

Exposure Latitude (%)

8
7
6
5 24%
Baseline solution
4
(Rule-Based SRAF) 3
2
1
0
-10 40 90 140
Depth Of Focus (nm)
Newron SRAF
Baseline Newron
(Deep Learning)
(RB-SRAF) SRAF
DOF @ 5%
102 nm 126 nm
EL

Full-chip application of machine learning SRAFs on DRAM case using auto pattern selection K. Chen et al., SPIE 2019, 10961-37 Public
 Leverage confluence of new technologies to meet OPC
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technology and cost requirements Slide 14

2016 2017 2018 2019 2020 2021

Inverse OPC Inverse OPC (CTM+) Inverse with phase control

(CTM) Intel DL Boost Deep Learning Inverse Hardware Accel. (tentative)

14  10 nm
Skylake Cascade Lake Cooper Lake Ice Lake

Spring Crest

Pascal Volta Turing Next Gen?

Mask making
Mask writer Mask infrastructure is ready
& inspection inspection for inverse OPC &
available curvi-linear masks
Multi-beam Mask Writer available Public
Context-aware control extends holistic solutions
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Slide 15

Lithography Step N-2

Etch

Dep

CMP

Lithography Step N-1

Etch

Dep
CMP

Lithography Step N
Context Data Corrections

Litho InSight and Pattern Fidelity Enhancements

Leveling, Alignment, Metrology Overlay, Focus, pattern defect control and scanner/etcher co-optimization

Metrology design & Model, sampling & Monitoring &

setup control setup analytics Public
 Leverage machine learning to address wafer-to-wafer
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variation induced by different wafer process routes Slide 16

16

Overlay Variations
Wafer to Wafer Variation

Context based Overlay Control results

ASML Machine
Learning Model

Every month > 100,000 wafers

exposed per scanner

Different Process Route

Correlate wafer-to-wafer variation
Number of Wafer Routes
Variation source

100,000,000 to process context and apply run-

10,000,000
1,000,000
to-run control with context-based
100,000 grouping
10,000
1,000
100
10
A novel patterning control strategy based on
1
1context 2contexts 3contexts … All real-time fingerprint recognition and adaptive
contexts
wafer level scanner optimization
H. E. Hakli et al., SPIE 2018, 10585:105851N
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Predict dense alignment from dense leveling data
hybrid metrology enabled by machine learning Public
Slide 17

Known input Type 1

• Leveling &
Alignment all wafers

• Overlay or alignment
sampling from same
wafer (blue points)

Machine Learning
Prediction

Unknown (orange points)

• Overlay or alignment from
same wafer at different Pairing wafer leveling metrology from a lithographic
coordinate locations apparatus with deep learning to enable cost effective dense
wafer alignment metrology
E. Schmitt-Weaver & K. Bhattacharyya, SPIE 2019, 10961-7 Public
 Holistic Lithography delivering significant customer value
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Lithography scanner with advanced control capability Slide 18

Etch and deposition tools

Applications
Patterning Control

Algorithms Data
Physical Models, Scatterometry, SEM,
Optimization, & other fab
Machine Learning equipment

Computational Optical and e-beam metrology

lithography and metrology
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Major trends in semiconductor-enabled computing
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Autonomous decisions Slide 19

Immersive experience
Applications

Moore’s Law
Performance Connectivity
Data  Value
Algorithms Cost Data Real-time
Deep Learning
Volume

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