Combinational logic Possible logic functions of two variables

n  Basic logic n  There are 16 possible functions of 2 input variables:
q  Boolean algebra, proofs by re-writing, proofs by perfect induction q  in general, there are 2**(2**n) functions of n inputs
q  logic functions, truth tables, and switches
q  NOT, AND, OR, NAND, NOR, XOR, . . ., minimal set
X F
n  Logic realization Y
q  two-level logic and canonical forms
q  incompletely specified functions X Y 16 possible functions (F0–F15)
n  Simplification 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
q  uniting theorem 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
q  grouping of terms in Boolean functions 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
n  Alternate representations of Boolean functions 0
X Y not Y not X
1
X and Y X xor Y X=Y X nand Y
q  cubes
X or Y X nor Y not (X and Y)
q  Karnaugh maps not (X or Y)

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Cost of different logic functions Minimal set of functions

n  Different functions are easier or harder to implement n  Can we implement all logic functions from NOT, NOR, and NAND?
q  For example, implementing X and Y
q  each has a cost associated with the number of switches needed
is the same as implementing not (X nand Y)
q  0 (F0) and 1 (F15): require 0 switches, directly connect output to n  In fact, we can do it with only NOR or only NAND
low/high q  NOT is just a NAND or a NOR with both inputs tied together
q  X (F3) and Y (F5): require 0 switches, output is one of inputs X Y X nor Y X Y X nand Y
0 0 1 0 0 1
q  X’ (F12) and Y’ (F10): require 2 switches for "inverter" or NOT- 1 1 0 1 1 0
gate
q  X nor Y (F4) and X nand Y (F14): require 4 switches q  and NAND and NOR are "duals",
that is, its easy to implement one using the other
q  X or Y (F7) and X and Y (F1): require 6 switches
X nand Y ≡ not ( (not X) nor (not Y) )
q  X = Y (F9) and X ⊕ Y (F6): require 16 switches
X nor Y ≡ not ( (not X) nand (not Y) )

q  thus, because NOT, NOR, and NAND are the cheapest they are n  But lets not move too fast . . .
the functions we implement the most in practice q  lets look at the mathematical foundation of logic

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An algebraic structure Boolean algebra

n  An algebraic structure consists of n  Boolean algebra

q  a set of elements B q  B = {0, 1}
q  binary operations { + , • } q  variables
q  and a unary operation { ’ } q  + is logical OR, • is logical AND
q  such that the following axioms hold: q  ’ is logical NOT
n  All algebraic axioms hold
1. the set B contains at least two elements: a, b
2. closure: a + b is in B a • b is in B
3. commutativity: a+b=b+a a•b=b•a
4. associativity: a + (b + c) = (a + b) + c a • (b • c) = (a • b) • c
5. identity: a+0=a a•1=a
6. distributivity: a + (b • c) = (a + b) • (a + c) a • (b + c) = (a • b) + (a • c)
7. complementarity: a + a’ = 1 a • a’ = 0

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Logic functions and Boolean algebra Axioms and theorems of Boolean algebra

n  Any logic function that can be expressed as a truth table can n  identity
be written as an expression in Boolean algebra using the 1. X + 0 = X 1D. X • 1 = X
operators: ’, +, and • n  null
X Y X•Y X Y X’ X’ • Y
2. X + 1 = 1 2D. X • 0 = 0
0 0 0 0 0 1 0 n  idempotency:
0 1 0 0 1 1 1
1 0 0 1 0 0 0 3. X + X = X 3D. X • X = X
1 1 1 1 1 0 0
n  involution:
4. (X’)’ = X
X Y X’ Y’ X•Y X’ • Y’ ( X • Y ) + ( X’ • Y’ ) n  complementarity:
0 0 1 1 0 1 1
0 1 1 0 0 0 0 5. X + X’ = 1 5D. X • X’ = 0
1 0 0 1 0 0 0 ( X • Y ) + ( X’ • Y’ ) ≡ X=Y
1 1 0 0 1 0 1
n  commutativity:
6. X + Y = Y + X 6D. X • Y = Y • X
Boolean expression that is n  associativity:
true when the variables X
and Y have the same value 7. (X + Y) + Z = X + (Y + Z) 7D. (X • Y) • Z = X • (Y • Z)
X, Y are Boolean algebra variables and false, otherwise
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Axioms and theorems of Boolean algebra (cont’d) Axioms and theorems of Boolean algebra (cont’d)

n  distributivity: n  de Morgan’s:

8. X • (Y + Z) = (X • Y) + (X • Z) 8D. X + (Y • Z) = (X + Y) • (X + 14. (X + Y + ...)’ = X’ • Y’ • ... 14D. (X • Y • ...)’ = X’ + Y’
Z) + ...
n  uniting: n  generalized de Morgan’s:
9. X • Y + X • Y’ = X 9D. (X + Y) • (X + Y’) = X
15. f’(X1,X2,...,Xn,0,1,+,•) = f(X1’,X2’,...,Xn’,1,0,•,+)
n  absorption:
10. X + X • Y = X 10D. X • (X + Y) = X
11. (X + Y’) • Y = X • Y 11D. (X • Y’) + Y = X + Y n  establishes relationship between • and +
n  factoring:
12. (X + Y) • (X’ + Z) = 12D. X • Y + X’ • Z =
X • Z + X’ • Y (X + Z) • (X’ + Y)
n  concensus:
13. (X • Y) + (Y • Z) + (X’ • Z) = 13D. (X + Y) • (Y + Z) • (X’ + Z) =
X • Y + X’ • Z (X + Y) • (X’ + Z)

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Axioms and theorems of Boolean algebra Proving theorems (rewriting)

(cont’d)
n  Duality n  Using the axioms of Boolean algebra:
q  a dual of a Boolean expression is derived by replacing q  e.g., prove the theorem: X • Y + X • Y’ = X
• by +, + by •, 0 by 1, and 1 by 0, and leaving variables
unchanged distributivity (8) X • Y + X • Y’ = X • (Y + Y’)
q  any theorem that can be proven is thus also proven for its dual! complementarity (5) X • (Y + Y’) = X • (1)
identity (1D) X • (1) = X ➼
q  a meta-theorem (a theorem about theorems)
n  duality:
16. X + Y + ... ⇔ X • Y • ...
n  generalized duality: q  e.g., prove the theorem: X+X•Y = X
17. f (X1,X2,...,Xn,0,1,+,•) ⇔ f(X1,X2,...,Xn,1,0,•,+)
identity (1D) X + X•Y = X•1 + X•Y
distributivity (8) X • 1 + X • Y = X • (1 + Y)
n  Different than deMorgan’s Law identity (2) X • (1 + Y) = X • (1)
q  this is a statement about theorems identity (1D) X • (1) = X ➼
q  this is not a way to manipulate (re-write) expressions

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Activity Proving theorems (perfect induction)

n  Prove the following using the laws of Boolean algebra: n  Using perfect induction (complete truth table):
q  (X • Y) + (Y • Z) + (X’ • Z) = X • Y + X’ • Z q  e.g., de Morgan’s:

(X • Y) + (Y • Z) + (X’ • Z)
X Y X’ Y’ (X + Y)’ X’ • Y’
(X + Y)’ = X’ • Y’ 0 0 1 1 1 1
identity (X • Y) + (1) • (Y • Z) + (X’ • Z) NOR is equivalent to AND 0 1 1 0 0 0
1 0 0 1 0 0
with inputs complemented 1 1 0 0 0 0
complementarity (X • Y) + (X’ + X) • (Y • Z) + (X’ • Z)

distributivity (X • Y) + (X’ • Y • Z) + (X • Y • Z) + (X’ • Z) X Y X’ Y’ (X • Y)’ X’ + Y’

(X • Y)’ = X’ + Y’ 0 0 1 1 1 1
commutativity (X • Y) + (X • Y • Z) + (X’ • Y • Z) + (X’ • Z) NAND is equivalent to OR 0 1 1 0 1 1
with inputs complemented 1 0 0 1 1 1
1 1 0 0 0 0
factoring (X • Y) • (1 + Z) + (X’ • Z) • (1 + Y)

null (X • Y) • (1) + (X’ • Z) • (1)

identity (X • Y) + (X’ • Z) ➼

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A simple example: 1-bit binary adder Apply the theorems to simplify expressions
Cout Cin

n  Inputs: A, B, Carry-in A A A A A n  The theorems of Boolean algebra can simplify Boolean
n  Outputs: Sum, Carry-out B B B B B expressions
S S S S S q  e.g., full adder’s carry-out function (same rules apply to any
function)
Cout = A’ B Cin + A B’ Cin + A B Cin’ + A B Cin
= A’ B Cin + A B’ Cin + A B Cin’ + A B Cin + A B Cin
A
S = A’ B Cin + A B Cin + A B’ Cin + A B Cin’ + A B Cin
A B Cin Cout S B = (A’ + A) B Cin + A B’ Cin + A B Cin’ + A B Cin
0 0 0 0 0 Cout
Cin = (1) B Cin + A B’ Cin + A B Cin’ + A B Cin
0 0 1 0 1
0 1 0 0 1 = B Cin + A B’ Cin + A B Cin’ + A B Cin + A B Cin
0 1 1 1 0 = B Cin + A B’ Cin + A B Cin + A B Cin’ + A B Cin
1 0 0 0 1 S = A’ B’ Cin + A’ B Cin’ + A B’ Cin’ + A B Cin
1 0 1 1 0 = B Cin + A (B’ + B) Cin + A B Cin’ + A B Cin
1 1 0 1 0
Cout = A’ B Cin + A B’ Cin + A B Cin’ + A B Cin
= B Cin + A (1) Cin + A B Cin’ + A B Cin
1 1 1 1 1
= B Cin + A Cin + A B (Cin’ + Cin)
= B Cin + A Cin + A B (1)
= B Cin + A Cin + A B adding extra terms
creates new factoring
opportunities
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Activity Activity

X8 X4 X2 X1 By2 By3 By5

n  Fill in the truth-table for a circuit that checks that a 4-bit 0 0 0 0 1 1 1
number is divisible by 2, 3, or 5 0 0 0 1 0 0 0
0 0 1 0 1 0 0
X8 X4 X2 X1 By2 By3 By5 0 0 1 1 0 1 0
0 0 0 0 1 1 1 0 1 0 0 1 0 0
0 0 0 1 0 0 0 0 1 0 1 0 0 1
0 0 1 0 1 0 0 0 1 1 0 1 1 0
0 0 1 1 0 1 0 0 1 1 1 0 0 0 By2 = X8’X4’X2’X1’ +
1 0 0 0 1 0 0 X8’X4’X2X1’
1 0 0 1 0 1 0
1 0 1 0 1 0 1
+ X8’X4X2’X1’ + X8’X4X2X1’
1 0 1 1 0 0 0 + X8X4’X2’X1’ + X8X4’X2X1’
1 1 0 0 1 1 0 + X8X4X2’X1’ + X8X4X2X1’
1 1 0 1 0 0 0 = X1’
1 1 1 0 1 0 0
1 1 1 1 0 1 1
By3 = X8’X4’X2’X1’ +
X8’X4’X2X1
n  Write down Boolean expressions for By2, By3, and By5 + X8’X4X2X1’ + X8X4’X2’X1
+ X8X4X2’X1’ + X8X4X2X1

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© Copyright 2004, Gaetano Borriello and Randy + 18
X8’X4X2’X1
+ X8X4’X2X1’ + X8X4X2X1

From Boolean expressions to logic gates From Boolean expressions to logic gates
(cont’d)
X Y X Y Z
X 0 0 1
n  NOT X’ X ~X X Y 0 1 n  NAND Z 0 1 1
1 0 Y
1 0 1
1 1 0
X Y Z
X 0 0 0
AND X • Y XY X∧Y Z 0 1 0 X Y Z
n  Y 1 0 0 n  NOR X 0 0 1
1 1 1 Z 0 1 0
Y 1 0 0
X Y Z 1 1 0
X 0 0 0
n  OR X+Y X∨Y Z 0 1 1
Y
1 0 1 X Y Z
1 1 1 n  XOR X 0 0 0 X xor Y = X Y’ + X’ Y
X⊕Y Z 0 1 1
Y X or Y but not both
1 0 1 ("inequality", "difference")
1 1 0

n  XNOR X Y Z
X 0 0 1 X xnor Y = X Y + X’ Y’
X=Y Y
Z 0 1 0 X and Y are the same
1 0 0
1 1 1 ("equality", "coincidence")
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From Boolean expressions to logic gates Waveform view of logic functions
(cont’d)
n  More than one way to map expressions to gates n  Just a sideways truth table
q  but note how edges don’t line up exactly
q  it takes time for a gate to switch its output!
q  e.g., Z = A’ • B’ • (C + D) = (A’ • (B’ • (C + D))) time
T2
T1

use of 3-input gate

A Z A
B T1 B Z
C T2 C
D D

change in Y takes time to "propagate" through gates

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Choosing different realizations of a function Which realization is best?

A B C Z
0 0 0 0 n  Reduce number of inputs
0 0 1 1
0 1 0 0 q  literal: input variable (complemented or not)
0 1 1 1 n  can approximate cost of logic gate as 2 transitors per literal
1 0 0 0
1 0 1 1 n  why not count inverters?
1 1 0 1 two-level realization
1 1 1 0 (we don’t count NOT gates) q  fewer literals means less transistors
n  smaller circuits
q  fewer inputs implies faster gates
n  gates are smaller and thus also faster
multi-level realization
(gates with fewer inputs) q  fan-ins (# of gate inputs) are limited in some technologies
n  Reduce number of gates
q  fewer gates (and the packages they come in) means smaller
circuits
XOR gate (easier to draw n  directly influences manufacturing costs
but costlier to build)

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Which is the best realization? (cont’d) Are all realizations equivalent?

n  Reduce number of levels of gates n  Under the same input stimuli, the three alternative
q  fewer level of gates implies reduced signal propagation delays implementations have almost the same waveform behavior
q  minimum delay configuration typically requires more gates q  delays are different
n  wider, less deep circuits q  glitches (hazards) may arise – these could be bad, it depends
n  How do we explore tradeoffs between increased circuit delay q  variations due to differences in number of gate levels and structure
and size? n  The three implementations are functionally equivalent
q  automated tools to generate different solutions
q  logic minimization: reduce number of gates and complexity
q  logic optimization: reduction while trading off against delay

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Implementing Boolean functions Canonical forms

n  Technology independent n  Truth table is the unique signature of a Boolean function
q  canonical forms n  The same truth table can have many gate realizations
q  two-level forms n  Canonical forms
q  multi-level forms q  standard forms for a Boolean expression
q  provides a unique algebraic signature
n  Technology choices
q  packages of a few gates
q  regular logic
q  two-level programmable logic
q  multi-level programmable logic

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Sum-of-products canonical forms Sum-of-products canonical form (cont’d)

n  Also known as disjunctive normal form n  Product term (or minterm)
n  Also known as minterm expansion q  ANDed product of literals – input combination for which output is
true
q  each variable appears exactly once, true or inverted (but not both)
F = 001 011 101 110 111
A B C minterms
F = A’B’C+ A’BC + AB’C + ABC’ + ABC F in canonical form:
0 0 0 A’B’C’ m0
F(A, B, C) = Σm(1,3,5,6,7)
0 0 1 A’B’C m1
A B C F F’ = m1 + m3 + m5 + m6 + m7
0 1 0 A’BC’ m2
0 0 0 0 1 = A’B’C + A’BC + AB’C + ABC’ + ABC
0 0 1 1 0 0 1 1 A’BC m3
0 1 0 0 1 1 0 0 AB’C’ m4
0 1 1 1 0 canonical form ≠ minimal form
1 0 1 AB’C m5
1 0 0 0 1 F(A, B, C) = A’B’C + A’BC + AB’C + ABC + ABC’
1 0 1 1 0 1 1 0 ABC’ m6
= (A’B’ + A’B + AB’ + AB)C + ABC’
1 1 0 1 0 1 1 1 ABC m7
1 1 1 1 0 F’ = A’B’C’ + A’BC’ + AB’C’ = ((A’ + A)(B’ + B))C + ABC’
= C + ABC’
short-hand notation for = ABC’ + C
minterms of 3 variables = AB + C

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Product-of-sums canonical form Product-of-sums canonical form (cont’d)

n  Also known as conjunctive normal form n  Sum term (or maxterm)
n  Also known as maxterm expansion q  ORed sum of literals – input combination for which output is false
q  each variable appears exactly once, true or inverted (but not both)
F= 000 010 100
F = (A + B + C) (A + B’ + C) (A’ + B + C) A B C maxterms F in canonical form:
0 0 0 A+B+C M0 F(A, B, C) = ΠM(0,2,4)
A B C F F’ 0 0 1 A+B+C’ M1 = M0 • M2 • M4
0 0 0 0 1 0 1 0 A+B’+C M2
0 0 1 1 0 = (A + B + C) (A + B’ + C) (A’ + B + C)
0 1 0 0 1 0 1 1 A+B’+C’ M3
0 1 1 1 0 1 0 0 A’+B+C M4 canonical form ≠ minimal form
1 0 0 0 1 1 0 1 A’+B+C’ M5
1 0 1 1 0 F(A, B, C) = (A + B + C) (A + B’ + C) (A’ + B + C)
1 1 0 1 0 1 1 0 A’+B’+C M6 = (A + B + C) (A + B’ + C)
1 1 1 1 0 1 1 1 A’+B’+C’ M7 (A + B + C) (A’ + B + C)
= (A + C) (B + C)
short-hand notation for
F’ = (A + B + C’) (A + B’ + C’) (A’ + B + C’) (A’ + B’ + C) (A’ + B’ + C’) maxterms of 3 variables

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S-o-P, P-o-S, and de Morgan’s theorem Four alternative two-level implementations
of F = AB + C
n  Sum-of-products A
q  F’ = A’B’C’ + A’BC’ + AB’C’
n  Apply de Morgan’s B canonical sum-of-products
F1
q  (F’)’ = (A’B’C’ + A’BC’ + AB’C’)’
q  F = (A + B + C) (A + B’ + C) (A’ + B + C) C

minimized sum-of-products
F2
n  Product-of-sums
q  F’ = (A + B + C’) (A + B’ + C’) (A’ + B + C’) (A’ + B’ + C) (A’ + B’ +
C’) canonical product-of-sums
n  Apply de Morgan’s F3

q  (F’)’ = ( (A + B + C’)(A + B’ + C’)(A’ + B + C’)(A’ + B’ + C)(A’ + B’ +

C’) )’ minimized product-of-sums
q  F = A’B’C + A’BC + AB’C + ABC’ + ABC F4

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Waveforms for the four alternatives Mapping between canonical forms

n  Waveforms are essentially identical n  Minterm to maxterm conversion

q  except for timing hazards (glitches) q  use maxterms whose indices do not appear in minterm
q  delays almost identical (modeled as a delay per level, not type of expansion
gate or number of inputs to gate) q  e.g., F(A,B,C) = Σm(1,3,5,6,7) = ΠM(0,2,4)
n  Maxterm to minterm conversion
q  use minterms whose indices do not appear in maxterm
expansion
q  e.g., F(A,B,C) = ΠM(0,2,4) = Σm(1,3,5,6,7)
n  Minterm expansion of F to minterm expansion of F’
q  use minterms whose indices do not appear
q  e.g., F(A,B,C) = Σm(1,3,5,6,7) F’(A,B,C) = Σm(0,2,4)
n  Maxterm expansion of F to maxterm expansion of F’
q  use maxterms whose indices do not appear
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q  e.g., F(A,B,C) =© Copyright
II - Combinational Logic
ΠM(0,2,4) F’(A,B,C) = ΠM(1,3,5,6,7)
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Incompleteley specified functions Notation for incompletely specified functions

n  Example: binary coded decimal increment by 1 n  Don’t cares and canonical forms
q  BCD digits encode the decimal digits 0 – 9 q  so far, only represented on-set
in the bit patterns 0000 – 1001 q  also represent don’t-care-set
A B C D W X Y Z
0 0 0 0 0 0 0 1 q  need two of the three sets (on-set, off-set, dc-set)
0 0 0 1 0 0 1 0 off-set of W
0 0 1 0 0 0 1 1
0 0 1 1 0 1 0 0 on-set of W
n  Canonical representations of the BCD increment by 1 function:
0 1 0 0 0 1 0 1
0 1 0 1 0 1 1 0
don’t care (DC) set of W
0 1 1 0 0 1 1 1 q  Z = m0 + m2 + m4 + m6 + m8 + d10 + d11 + d12 + d13 + d14 +
0 1 1 1 1 0 0 0
1 0 0 0 1 0 0 1 d15
1 0 0 1 0 0 0 0 q  Z = Σ [ m(0,2,4,6,8) + d(10,11,12,13,14,15) ]
1 0 1 0 X X X X
1 0 1 1 X X X X these inputs patterns should
1 1 0 0 X X X X never be encountered in practice
1 1 0 1 X X X X – "don’t care" about associated q  Z = M1 • M3 • M5 • M7 • M9 • D10 • D11 • D12 • D13 • D14 • D15
1 1 1 0 X X X X output values, can be exploited
in minimization
q  Z = Π [ M(1,3,5,7,9) • D(10,11,12,13,14,15) ]
1 1 1 1 X X X X

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Simplification of two-level combinational The uniting theorem

logic
n  Finding a minimal sum of products or product of sums realization n  Key tool to simplification: A (B’ + B) = A
q  exploit don’t care information in the process n  Essence of simplification of two-level logic
n  Algebraic simplification q  find two element subsets of the ON-set where only one variable
q  not an algorithmic/systematic procedure changes its value – this single varying variable can be eliminated
q  how do you know when the minimum realization has been found? and a single product term used to represent both elements
n  Computer-aided design tools
q  precise solutions require very long computation times, especially for F = A’B’+AB’ = (A’+A)B’ = B’
functions with many inputs (> 10) A B F
q  heuristic methods employed – "educated guesses" to reduce amount of B has the same value in both on-set rows
0 0 1
computation and yield good if not best solutions – B remains
0 1 0
n  Hand methods still relevant
1 0 1
q  to understand automatic tools and their strengths and weaknesses
1 1 0
q  ability to check results (on small examples) A has a different value in the two rows
– A is eliminated

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Boolean cubes Mapping truth tables onto Boolean cubes

n  Visual technique for identifying when the uniting theorem n  Uniting theorem combines two "faces" of a cube
can be applied into a larger "face"
n  n input variables = n-dimensional "cube" n  Example:
F two faces of size 0 (nodes)
01 11 A B F combine into a face of size 1(line)
0 1 01 11
Y 2-cube 0 0 1
1-cube
X 0 1 0 B
00 10
X 1 0 1 00 10
A
111 1111 1 1 0
0111
A varies within face, B does not
3-cube Y Z 4-cube this face represents the literal B'
101
Y ON-set = solid nodes
Z
000 X W OFF-set = empty nodes
1000
0000 X DC-set = ×'d nodes

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Three variable example Higher dimensional cubes

n  Binary full-adder carry-out logic n  Sub-cubes of higher dimension than 2
(A'+A)BCin

A B Cin Cout AB(Cin'+Cin) F(A,B,C) = Σm(4,5,6,7)

111
0 0 0 0
on-set forms a square
0 0 1 0 i.e., a cube of dimension 2
0 1 0 0 011 111
0 1 1 1 B C 101 110 represents an expression in one variable
010 i.e., 3 dimensions – 2 dimensions
1 0 0 0
000 A(B+B')Cin 001
1 0 1 1 A B C 101 A is asserted (true) and unchanged
1 1 0 1 B and C vary
1 1 1 1 the on-set is completely covered by 000 A 100
the combination (OR) of the subcubes This subcube represents the
of lower dimensionality - note that “111” literal A
is covered three times

Cout = BCin+AB+ACin

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m-dimensional cubes in a n-dimensional Karnaugh maps
Boolean space
n  In a 3-cube (three variables): n  Flat map of Boolean cube
q  a 0-cube, i.e., a single node, yields a term in 3 literals q  wrap–around at edges
q  a 1-cube, i.e., a line of two nodes, yields a term in 2 literals q  hard to draw and visualize for more than 4 dimensions
q  a 2-cube, i.e., a plane of four nodes, yields a term in 1 literal q  virtually impossible for more than 6 dimensions
q  a 3-cube, i.e., a cube of eight nodes, yields a constant term "1" n  Alternative to truth-tables to help visualize adjacencies
n  In general, q  guide to applying the uniting theorem
q  an m-subcube within an n-cube (m < n) yields a term q  on-set elements with only one variable changing value are
with n – m literals adjacent unlike the situation in a linear truth-table
A B F
A
B 0 1 0 0 1
0 1 1 0 1 0
0 2
1 0 0 1 0 1
1 3
1 1 0

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Karnaugh maps (cont’d) Adjacencies in Karnaugh maps

n  Numbering scheme based on Gray–code n  Wrap from first to last column
q  e.g., 00, 01, 11, 10 n  Wrap top row to bottom row
q  only a single bit changes in code for adjacent map cells

AB A
C 00 01 11 10
A 011 111
0 A
0 2 6 4 110
0 4 12 8 000 010 110 100 010
C 1
1 3 7 5
1 5 13 9 B C 001
D C 001 011 111 101 101
B
B 100
A 3 7 15 11 000 A
C
0 2 6 4 2 6 14 10
B
C 13 = 1101= ABC’D
1 3 7 5
B

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Karnaugh map examples More Karnaugh map examples

A
n  F= A 0 0 1 1
1 1 G(A,B,C) = A
B’ C 0 0 1 1
n  Cout = B 0 0
B

A
n  f(A,B,C) = Σm(0,4,5,7)
1 0 0 1
A F(A,B,C) = Σm(0,4,5,7) = AC + B’C’
0 0 1 0 AB + ACin + BCin C 0 0 1 1

Cin 0 1 1 1
B

B A
A
1 0 0 1 0 1 1 0 F' simply replace 1's with 0's and vice versa
obtain the F'(A,B,C) = Σ m(1,2,3,6)= BC’ + A’C
C 0 0 1 1 complement C 1 1 0 0
of the function B
B AC + B’C’+ AB’
by covering 0s
with subcubes
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Karnaugh map: 4-variable example Karnaugh maps: don’t cares

n  F(A,B,C,D) = Σm(0,2,3,5,6,7,8,10,11,14,15) n  f(A,B,C,D) = Σ m(1,3,5,7,9) + d(6,12,13)

q  without don't cares
F = C + A’BD + B’D’ n  f = A’D + B’C’D

A 1111
0111
1 0 0 1
A
0 1 0 0
D 0 0 X 0
C
1 1 1 1 D 1 1 X 1
C A D
1000
1 1 1 1 0000 B
1 1 0 0
B C
0 X 0 0
find the smallest number of the largest possible
B
subcubes to cover the ON-set
(fewer terms with fewer inputs per term)

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Karnaugh maps: don’t cares (cont’d) Activity

n  f(A,B,C,D) = Σ m(1,3,5,7,9) + d(6,12,13) n  Minimize the function F = Σ m(0, 2, 7, 8, 14, 15) + d(3, 6, 9, 12, 13)
q  f = A'D + B'C'D without don't cares A
q  f = A'D + C'D with don't cares A 1 0 X 1
1 0 X 1 F = AC’ +
0 0 X X
A’C + D
0 0 X X BC +
A D X 1 1 0
by using don't care as a "1" AB + C
0 0 X 0 X 1 1 0
a 2-cube can be formed C A’B’D’ + 1 X 1 0
1 1 X 1 rather than a 1-cube to cover 1 X 1 0 B’C’D’ B
D this node A
B
1 1 0 0 1 0 X 1
C don't cares can be treated as
0 X 0 0 1s or 0s F = BC + A’B’D’ + B’C’D’ 0 0 X X
D
B depending on which is more
F = A’C + AB + B’C’D’ X 1 1 0
advantageous
C
1 X 1 0
B
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Combinational logic summary

n  Logic functions, truth tables, and switches

q  NOT, AND, OR, NAND, NOR, XOR, . . ., minimal set
n  Axioms and theorems of Boolean algebra
q  proofs by re-writing and perfect induction
n  Gate logic
q  networks of Boolean functions and their time behavior
n  Canonical forms
q  two-level and incompletely specified functions
n  Simplification
q  a start at understanding two-level simplification
n  Later
q  automation of simplification
q  multi-level logic
q  time behavior
q  hardware description languages
q  design case studies

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