electronics

Article
An Impedance Source Multi-Level Three Phase
Inverter with Common Mode Voltage Elimination
and Dead Time Compensation
Mehrdad Mahmoudian 1, * , Maziyar Fakhraei 2 , Edris Pouresmaeil 3 and
Eduardo M. G. Rodrigues 4, *
1 Electrical Engineering Department, Firouzabad Institute of Higher Education, Firouzabad 74717, Iran
2 Control and Dispatching Department, Fars Regional Electric Company, Shiraz 71346, Iran;
[email protected]
3 Department of Electrical Engineering and Automation, Aalto University, 02150 Espoo, Finland;
[email protected]
4 Management and Production Technologies of Northern Aveiro—ESAN, Estrada do Cercal 449,
Santiago de Riba-Ul, 3720-509 Oliveira de Azeméis, Portugal
* Correspondence: [email protected] (M.M.); [email protected] (E.M.G.R.)




Received: 28 August 2020; Accepted: 30 September 2020; Published: 4 October 2020


Abstract: Currently, most electro-mechanical drive systems that require speed control use pulse-width
modulated (PWM) variable frequency drives known as adjustable speed drives (ASD). The high
switching speeds of the electronics switches are essential for proper operation of the ASD. Common
mode voltage (CMV) has its origin in the PWM switching. The CMV increases the stress on the coils
and windings, reduces the life of the bearing and, therefore, has a significant impact on motor life cycle.
In this paper, a variant of a PWM-based space vector modulation (SVPWM) switching algorithm
is proposed to control both the shoot-through intervals and the dead time of the power switches
that could be compensated. The proposed algorithm is implemented on a platform consisting of
an impedance source network in the DC side of the topology with the purpose of mitigating the
CMV and capability of voltage boosting. Since similar methods have achieved a CMV reduction of
1/6 of the DC link voltage so far, in this paper, while surpassing the disturbing current harmonics,
the high efficiency is fully accessible. The presented experimental results verify the effectiveness of
the proposed approach by slightly increasing the total harmonic distortion (THD) and reducing the
converter losses.

Keywords: common-mode voltage (CMV); adjustable speed drive (ASD); three-level NPC inverter

1. Introduction
The three-phase voltage-source inverter is the power conversion basis for modern industrial
motor drive systems due to its high flexibility to perform speed and torque control in the whole range
of AC motors. Inside of a motor speed drive, PWM control signals are crucial to perform the control
requirement, being a control interface standard among industrial inverters. PWM control techniques
are really popular because can be easily implemented in modern digital signal controller-based
software [1–3].
On the other hand, PWM speed inverters are prone to generate high frequency noise that is
conducted and radiated if not properly designed. The PWM-based three-phase waveforms generation
technique is also a source of issues because the vector sum of the three-phase voltage is never null.
Consequently, it appears as CMV in the motor [4,5]. The consequences of CMV due to PWM inverters
are well known: a voltage induction in the rotor shaft allows a significant current to flow through the

Electronics 2020, 9, 1639; doi:10.3390/electronics9101639 www.mdpi.com/journal/electronics

Electronics 2020, 9, 1639 2 of 18

rotor support bearings and the grounding system. This is one of causes for motor failures. In addition,
high CMV may led to motor electrical insulation disruption, which prevents its operation.
Since a new generation of nitride (GaN) and silicon carbide (SiC) power switches with much
higher switching frequency capability will take the preference of power converter designers, including
ASD manufacturers, an intensification of CMV issues and additional challenges to comply with
electromagnetic compatibility (EMC) standards are expected [6].
Mitigation techniques are recurrent in the technical and scientific literature [7,8]. Basically,
the solutions can be divided into three groups. One approach is to reduce induced bearing currents
via increasing the impedance between the rotor shaft contact points and the inner ring in bearings.
A less expensive option involves the replacement of standard bearings with electrical isolated bearings.
The common-mode voltage and current generated by the converter can be reduced by passive or active
filters. The CMV can be reduced or even cancelled by special converter topologies or modulation
techniques. In the following, a review of these methods is presented. Some basic motor modifications
(e.g., carbon brushes and bearing insulations) developed against the classical bearing currents are
still in use for the mitigation of converter-generated bearing currents. Carbon brushes are used for
grounding the rotating shaft and shunting the bearing current to the ground. A drawback of the
carbon brush is that a motor equipped with a brush needs more maintenance. Bearing currents can be
prevented by bearing insulations embedded in the end shields, or by hybrid bearings with ceramic
rolling elements [9].
Passive filters are used in electric drives to reduce over-voltages at the motor terminals, the EMI,
the output current harmonics and the common-mode current [10]. Active filters and modulation
techniques are some other CMV mitigating strategies that are used in some scholarly papers. An active
common-mode voltage canceller employing the common-mode transformer was proposed in [11].
An emitter-follower, controlled by the CMV obtained using an artificial neutral point, connects the
DC-link voltage in the secondary winding in order to compensate the common-mode voltage at the
motor terminals. The authors of [12] proposed a similar active filter where the emitter-follower was
replaced by a single-phase multilevel half-bridge inverter, which is more suitable for voltage levels
commonly used in frequency converters than the emitter-follower. In the simulations, the filter reduced
all relevant quantities to about 2% of the original values. Modulation techniques have also been
proposed for the reduction of the common-mode voltage of the inverter. The authors of [13] have
proposed a method that reduces the common-mode voltage by 50%. It is based on a modulation
pattern that does not apply zero vectors. Hence, the common-mode voltage will have only two possible
values instead of four. This method is not suitable for modulation methods that actively use the zero
vectors, such as the direct torque control (DTC). The authors of [14] proposed the zero vector to be
produced by shorting the motor terminals with three auxiliary star-connected switches, which reduces
the common-mode voltage without the restriction on the use of the zero vector. In a neutral point
clamped (NPC) three-level inverter, it is possible to use only the voltage vectors that give exactly zero
common-mode voltage. However, such modulation reduces the number of applicable voltage vectors
from the original 27 to 7 [15–17]. Special converters as the topologies can also be modified in such a
way that the CMV is compensated, are the other approach. Several methods based on altering the
number of inverter legs to an even number have been presented. The advantage of an even number
of inverter legs is that the common-mode voltage, which is the average of the phase voltages, can be
controlled to zero [18,19].
In general, the solutions to face CMV could be classified into two types: hardware solutions
and software solutions. Hardware-based strategies make use of elements such as the common-mode
choke filter, passive and active filters, as well as approaches with topology changed such as the
four-phase inverter. Though capable of suppressing CMV to some degree, the hardware solutions
require additional components, which increase the size, cost and complexity of control and parameter
design, whereas the software solutions for suppressing CMV are realised through adjusting the
Electronics 2020, 9, 1639
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whereas the software solutions for suppressing CMV are realised through adjusting the switching
switching
control control
signals or signals or modulation
modulation algorithmalgorithm of the inverters.
of the inverters. They are They
more are more economical
economical and
and flexible,
flexible, especially when used along with digital signal processing
especially when used along with digital signal processing (DSP) technology. (DSP) technology.
So far,
So far, software
software strategies based on
strategies based on PWM
PWM modifications
modifications have
have aroused
aroused widespread
widespread attention.
attention.
Previous studies of reduced CMV PWM (RCMVPWM) were mainly conducted
Previous studies of reduced CMV PWM (RCMVPWM) were mainly conducted on modifications on modifications from
space vector modulation (SVM) [20–23], carrier-based PWM (CBPWM)
from space vector modulation (SVM) [20–23], carrier-based PWM (CBPWM) [24,25], selected [24,25], selected harmonic
elimination
harmonic PWM (SHEPWM)
elimination [26–28] and
PWM (SHEPWM) so on.and
[26–28] Of these,
so on. the RCMV-PWM
Of these, based on based
the RCMV-PWM SVM attracted
on SVM
more attention. These RCMV methods can be applied in various inverters with
attracted more attention. These RCMV methods can be applied in various inverters with different different levels.
Considering
levels. the diversity
Considering of topologies
the diversity and the
of topologies universality
and of application,
the universality we focus
of application, we on three-phase
focus on three-
two-level driving systems here, such as space vector PWM (SVPWM), discrete
phase two-level driving systems here, such as space vector PWM (SVPWM), discrete PWM (DPWM), PWM (DPWM), active
zero state (AZSPWM), sinusoidal PWM (SPWM) and real state PWM
active zero state (AZSPWM), sinusoidal PWM (SPWM) and real state PWM (RSPWM). These(RSPWM). These strategies are
depicted in
strategies areFigure 1 to in
depicted show the 1switching
Figure to show thevector areas. vector areas.
switching

(a) (b)

(c) (d)

Figure 1. PWM switching algorithms: (a) SVPWM, DPWM, AZSPWM; (b) SPWM; (c) RSPWM;
Figure 1. PWM switching algorithms: (a) SVPWM, DPWM, AZSPWM; (b) SPWM; (c) RSPWM; (d)
(d) RCMV-PWM.
RCMV-PWM.
2. CMV Generation
2. CMV Generation
In Figure 2, a conventional three-phase inverter is represented that can be used as a speed control
In Figure
drive for 2, a conventional
three-phase inductionthree-phase inverter
motors. In this is represented
Figure, indices g, 0 that
and can be used
n imply the as a speed ground
reference control
drive zero
with for three-phase induction
potential, middle of motors.
DC linkInpotential
this Figure,
andindices
motor g,neutral
0 and npoint
imply the reference
potential, ground
respectively.
with zero potential, middle of DC link potential and motor neutral
Therefore, three-phase output voltages of the inverter could be written by: point potential, respectively.
Therefore, three-phase output voltages of the inverter could be written by:
Va0 = Van + Vn0 (1)
𝑉 =𝑉 +𝑉 (1)
Vb0 = Vbn + Vn0 (2)
𝑉 =𝑉 +𝑉 (2)
Vc0 = Vcn + Vn0 (3)

𝑉 =𝑉 +𝑉 (3)
 (DC bus midpoint). Combining equations from (1) to (3), 𝑉 is given as:

𝑉 +𝑉 +𝑉 −𝑉 −𝑉 −𝑉
𝑉 = (4)
3
Assuming
Electronics
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2020, balanced
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PEER REVIEW = 0): 44of
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where 𝑉 are the line-to-neutral voltages and 𝑉 + 𝑉 three-phase

are +𝑉 output voltages with respect to 0
𝑉 and= x0 are three-phase output voltages with respect to (5)0
(DC busVxn
where are the line-to-neutral
midpoint). voltages
Combining equations from V 3 𝑉 is given as:
(1) to (3),
(DC bus midpoint). Combining equations from (1) to (3), Vn0 is given as:
The quantity 𝑉 is the average of the AC output voltage in relation to the ground, or known as
𝑉 +𝑉 +𝑉 −𝑉 −𝑉 −𝑉
CMV. This voltage is also available
𝑉 = Va0 in + Vmulti-level
b0 + Vc0 − Vinverters
an − Vbn −that
Vcn have more advantages (4) than
Vn0 =
conventional three-phase bridges, 3
which should be removed. As mentioned before, the CMV usually
(4)
3
Assuming
appears balanced
on stray load (Vofanthe
capacitances +Vbnsystem.
+Vcn = 0):

𝑉 +𝑉 +𝑉 S1 S3 S5
Vdc 3𝑉 = (5)
A
VAC C1 e R L ia
2
The quantity 𝑉B is the average of the AC output a ground, or known as
voltage in relation to the
VAC o n ib
CMV. This voltage is also available in multi-levelVno inverters that have more b advantages than
ic
C
VAC
conventional three-phase bridges, which should be removed. As mentioned before, the c CMV usually
appears on stray capacitances of the system.C 2 Vdc
Source 2 MOTOR
g Impedance
S S2 S4 6

S1 S3 S5
V e R L machine.
VACA Figure2.2. PWM
Figure dc
PWM inverter-controlled
inverter-controlled
C1 induction
induction ia
machine.
2 a
V B
o n ib
Assuming balanced
AC load (V an + V +
Figure 3 highlights the parasitic capacitance V cn = 0):
paths between stator windingsb and the motor frame
bn
Vno ic
where Csf is theV Ccapacitance between stator windings and the motor frame, Ccsr represents the
AC VVa0 + Vb0 + Vc0
capacitance between stator and rotor, CVrfn0 isC =
the rotor
dc to frame capacitance, and finally Crf is the bearing (5)
Source 2 3 MOTOR
capacitance. 2
g Impedance S2 S4 S6
The quantity Vn0 is the average of the AC output voltage in relation to the ground, or known as
CMV. This voltage is also available in multi-level
Figure 2. PWM inverters that
inverter-controlled have more
induction advantages than conventional
machine.
C
three-phase bridges, which should be removed. As mentioned before, the CMV usually appears on
sf
C sr
strayFigure
capacitances of thethe
system. Stator
3 highlights parasitic
Cb capacitance paths between stator windings and the motor frame
whereFigure
Csf is3 the
highlights the parasitic
capacitance between capacitance paths between
stator windings and the stator windings
motor frame,and Csr the motor frame
represents the
Bearings Rotor
where Csf is the
capacitance capacitance
between stator between
and rotor, stator
Crf iswindings
the rotor and the motor
to frame frame, Cand
capacitance, sr represents
finally Crfthe capacitance
is the bearing
between stator and rotor, Crf is the rotor to frame Motor
capacitance. capacitance,
frame C rf finally Crf is the bearing capacitance.
and

Figure 3. Motor stray capacitances.

C sf
C sr
For analysis purposes, an equivalent electrical Stator model provides a way to evaluate the leakage and
Cb
the bearing currents in an AC motor [2]. It is shown in Figure 4. The elements causing line frequency
currents to flow over the motor are: (a) the AC or DCRotor
Bearings magnetic flux circulating through different
paths such as the rotor shaft, bearings and motor frame; (b) C rf the voltage between shaft and ground
Motor frame
that is distributed by the electrostatic field resulting from the friction of mechanical parts such as
pulleys, belts, self-bearings and Figureeven ionized air; (c) the AC voltage induced in the motor shaft
Figure 3. 3. Motor
Motorstray
straycapacitances.
capacitances.
produced by the monopole magnetic flux passing through the shaft. The third case is the most
problematic
For by inducing
For analysis
analysis purposes,aan
purposes, current
an in the
equivalent
equivalent rotor shaft,
electrical
electrical model
model which
provides
providesin turn it closes
aa way
way to through
to evaluate
evaluate thethe
the bearings,
leakage
leakage and
and
motor
the
the support
bearing
bearing andin
currents
currents concrete
in an
an AC foundations,
AC motor
motor [2]. which
showncause
[2]. ItItisisshown in
inFigure the4.
Figure appearance
4. The
Theelements
elements of causing
acausing
phenomenon
line named
linefrequency
frequency
Electrical
currents
currents toDischarge
flow over
flow Machining
overthe
themotor (EDM).
motorare:are:(a)(a)
thetheACAC or DC
or DC magnetic
magnetic fluxflux circulating
circulating throughthrough different
different paths
paths
such assuch
theas the shaft,
rotor rotor shaft, bearings
bearings and motorand motorframe;frame;
(b) the(b) the voltage
voltage between between
shaft andshaft and ground
ground that is
that is distributed
distributed by the by the electrostatic
electrostatic field resulting
field resulting from the from the friction
friction of mechanical
of mechanical parts suchpartsas such as
pulleys,
pulleys, belts, self-bearings
belts, self-bearings and evenand even air;
ionized ionized
(c) theair;AC(c)voltage
the ACinduced voltage in induced
the motorin the motor
shaft shaft
produced
produced by the monopole
by the monopole magnetic fluxmagnetic
passing flux passing
through thethrough
shaft. The the third
shaft.caseTheisthird case problematic
the most is the most
problematic
by inducing by inducing
a current a current
in the in thewhich
rotor shaft, rotorin shaft,
turnwhich
it closes in through
turn it closes throughmotor
the bearings, the bearings,
support
motor support
and concrete and concrete
foundations, foundations,
which which causeofthe
cause the appearance appearance named
a phenomenon of a phenomenon named
Electrical Discharge
Electrical
Machining Discharge
(EDM). Machining (EDM).
Electronics 2020, 9, 1639 5 of 18
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C sr
Cb +
Vng Vshaft
C sf Crf
_

Figure 4. Electrical model of stray capacitances.

3. Proposed Topology
3. Proposed Topology Principles
Principles and
and Evaluation
Evaluation
The
The three-level
three-level NPC NPC inverter
inverter isis commonly
commonly used used asas the
the preferred
preferred choice
choice for
for medium
medium voltage
voltage AC AC
drives. More recently, low voltage renewable grid-interfacing applications are
drives. More recently, low voltage renewable grid-interfacing applications are taking advantage of taking advantage of this
topology.
this topology. Despite their their
Despite generally favorable
generally outputoutput
favorable performance, the basic
performance, theNPC
basicinverter has a known
NPC inverter has a
drawback related to its operation. Without an additional power conversion
known drawback related to its operation. Without an additional power conversion stage, it can stage, it can only perform
only
in voltage-buck mode operation. To overcome this limitation, a buck–boost
perform in voltage-buck mode operation. To overcome this limitation, a buck–boost Z-source NPC Z-source NPC inverter is
proposed in [29], where two additional X-shaped impedance networks are added
inverter is proposed in [29], where two additional X-shaped impedance networks are added between between two isolated
DC
twosources
isolated andDC traditional
sourcesNPCand circuitry.
traditionalTheNPCaddedcircuitry.
impedance networks
The added are responsible
impedance for balanced
networks are
inductive
responsible for balanced inductive voltage boosting upon shooting through any of the invertercausing
voltage boosting upon shooting through any of the inverter phase-legs without phase-
damage
legs withoutto their semiconductor
causing damage toswitches. This protection
their semiconductor from sudden
switches. current from
This protection surgesudden
is provided by
current
the
surgeinductors
is provided foundby within the Z-source
the inductors impedance
found within networks.
the Z-source Theimpedance
network consists
networks.of a split-inductor
The network
(L and
consists
1 Lof ) and two capacitors
2 a split-inductor (L1 and (C and C
1 L2) and ), connected between the input DC source
2 two capacitors (C1 and C2), connected between and a traditional
the input
NPC inverter
DC source andcircuitry. TheNPC
a traditional inputinverter
source circuitry.
can be a split-DC
The inputsource
sourceformed
can be aby two series-connected
split-DC source formed
capacitors, rather than two
by two series-connected isolated sources.
capacitors, rather thanOn two
the other hand,
isolated the rear-end
sources. On the NPCothercircuitry
hand, theallows the
rear-end
inverter to assume three distinct voltage levels per phase leg, whose expressions
NPC circuitry allows the inverter to assume three distinct voltage levels per phase leg, whose and corresponding
gating signalsand
expressions arecorresponding
shown in Tablegating
1. Compared
signals with the traditional
are shown in TableNPC inverter, Table
1. Compared with 1the includes also
traditional
four non-traditional states.
NPC inverter, Table 1 includes also four non-traditional states.
Table 1. Switching states and output values, summarized only for phase A.
Table 1. Switching states and output values, summarized only for phase A.
State Conducting Switches Conducting Diodes VA (Phase Voltage)
State Conducting Switches Conducting Diodes 𝑽𝑨 (Phase Voltage)
NST (1) Sa1 , Sa2 D1 , D2 + V2dc𝑉
NST (1) 𝑆 ,𝑆 𝐷 ,𝐷 +
NST (2) Sa2 , Sa3 D1 , D2 , {Da1 or Da2 } 0 2
−Vdc
𝑆 ,𝑆
NST (2) NST (3) Sa3 , Sa4 𝐷 , 𝐷 , {𝐷
D1 , D𝑜𝑟
2 𝐷 } 20
FST (1) Sa1 , Sa2 , Sa3 , Sa4 − 0
−𝑉
NST (3) 𝑆 ,𝑆 Sa1 , Sa2 , Sa3 𝐷 ,𝐷
FST (2) Da2 , Dc1 02
Sc1 , Sc2 , Sc3
FST (1) 𝑆 ,𝑆 ,𝑆 ,𝑆 − Vdc 0
UST Sa1 , Sa2 , Sa3 Da2 , D1 2
− 1−D
𝑆 ,𝑆 ,𝑆 Vdc
FST (2) DST Sa2 , Sa3 , Sa4 𝐷 , 𝐷 Da1 , D2 20
+ 1−D
𝑆 ,𝑆 ,𝑆
𝑉
Since 𝑆 , 𝑆 considerations
USTthe economic ,𝑆 and loss𝐷analysis
,𝐷 − 2
restrict us from constructing such a topology
1 − 𝐷
as that shown in Figure 5a, the structure represented in Figure 5b has been taken into account to
evaluate the performance analysis. 𝑉
DST 𝑆 ,𝑆 ,𝑆 𝐷 ,𝐷 + 2
1−𝐷

Since the economic considerations and loss analysis restrict us from constructing such a topology
as that shown in Figure 5a, the structure represented in Figure 5b has been taken into account to
evaluate the performance analysis.
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VL 1 ii
i
L1
L1
i dc D 1 C1 C2
Vdc
2
VC 1 VC 2 Vi ( U )
i VL 2 i
C2 C1
L2
i
L2 VL 1
i ii
L1
L1
i dc
C1 C2
Vdc
VC 1 VC 2 V
2 VL 2 i( D )
D 2 iC 2 i
C1
i L2
L2

(a)
VL 1 ii
i
L1
L1
i dc D 1
Vdc C1 C2
2
VC 1 VC 2

Vi

i dc
Vdc
2 VL 2
D2
i L2
L2

(b)
Figure 5. Impedance source multi-level network: (a) Two network utilization; (b) integrated
Figure 5. Impedance source multi-level network: (a) Two network utilization; (b) integrated network
network utilization.
utilization.Like the two-level Z-source inverter, these non-traditional states are for boosting
voltages carried byZ-source
Like the two-level the Z-source NPCthese
inverter, inverter. In particular,
non-traditional the two
states fullboosting
are for shoot-through (ST)
voltages carried
states help to short circuit the DC-link fully, and can be used together with
by the Z-source NPC inverter. In particular, the two full shoot-through (ST) states help to shortother non-shoot-
through
circuit (NST)fully,
the DC-link active
andandcannull statestogether
be used in a typical
withmodulation state sequence
other non-shoot-through for aactive
(NST) Z-source
and null
NPC inverter. For distinctly representing the non-shoot-through and shoot-through
states in a typical modulation state sequence for a Z-source NPC inverter. For distinctly representing states,
Figure 6 shows their
the non-shoot-through andsimplified
shoot-throughequivalent circuits6 for
states, Figure showsanalysis, where in Figure
their simplified 6a the
equivalent circuits
inverter circuitry and external load have been represented by a simplified
for analysis, where in Figure 6a the inverter circuitry and external load have been represented current source in by a
the NST state. Using this equivalent representation with input diodes D 1 and D
simplified current source in the NST state. Using this equivalent representation with input diodes D12 conducting,
and Dthe inductive voltage of the single symmetrical Z-source network ( 𝑉 = 𝑉 = 𝑉 and
2 conducting, the inductive voltage of the single symmetrical Z-source network (VL1 = VL2 = VL
and VC1 = 𝑉VC2==𝑉V)Cand
𝑉 = ) andallall
the voltage
the voltagegains
gainsofof
Z-source
Z-source inverter
inverter(ZSI) are
(ZSI) areexpressed
expressedasasbelow:
below:

𝑉 dc 11 −
V − t𝑡ST
V𝑉C = 2 (6)
(6)
2 11 − 2𝑡ST
− 2t

V𝑉C =
V𝑉 dc 1 −
− t𝑡ST
= 22 2 1 − 2t (7)
(7)
1 − 2𝑡ST
V
Vx = M.B. 𝑉dc ; x{a, b, c} (8)
𝑉 = 𝑀. 𝐵. 2 ; 𝑥𝜖 𝑎, 𝑏, 𝑐 (8)
2
where VC , Vdc and Vx are the capacitor voltage, DC link voltage and output ZSI voltage of each phase,
where 𝑉 , 𝑉 Theand
respectively. 𝑉 are the
parameters tSTcapacitor voltage,time
is shoot-through DCinterval,
link voltage andmodulation
M is the output ZSIindex
voltage
and of
B iseach
the
phase, respectively.
ZSI voltage gain. AnThe parameters
alternative 𝑡 isequivalent
simplified shoot-through
circuittime 𝑀 Figure
interval, in
is presented is the modulation index
7 for investigating
and
the up𝐵 shoot-through
is the ZSI voltage gain.
(UST) andAn alternative
down simplified
shoot-through (DST)equivalent circuit is presented in Figure 7
conditions.
for investigating the up shoot-through (UST) and down shoot-through (DST) conditions.
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VL 1 L1 i
i dc D 1 i
L1 ii vu i dc L1 ii vu
VL 1 L1 i
i dc D 1 L1
i ii vu i dc L1 L1 ii vu
Vdc L1 Vdc
C1 L1 C2 V2dc C1 L1 C2
V2dc
Vd VCC11 CV
2 Vi 2 Vd VCC11 CV
2 Vi
2 C2 C2
Vdc Vd Vi Vdc Vd
VC 1 VL 2 VC 2 VC 1 VL 2 VC 2 Vi
V2dc D2 V2dc
VL 2 VL 2
2 D2 i L2 vd 2
i L2 vd
L2 L2
i
L2
L2 vd i
L2
L2 vd

(a) (b)
(a) (b)
Figure 6. Simplified equivalent circuit for evaluating conditions: (a) NST state; (b) ST state.
Figure 6. Simplified equivalent circuit for evaluating conditions: (a) NST state; (b) ST state.
Figure 6. Simplified equivalent circuit for evaluating conditions: (a) NST state; (b) ST state.
L1
VL 1 i dc i
L1 ii vu
i dc D 1 i ii vu L1
VL 1 L1 i dc L1
i
L1 ii vu
i dc D 1 i Vdc
Vdc L1 L1 ii vu C1 L1 C2
C1 L1 C2 V2dc
V2dc Vd VCC11 CV
2 Vi
Vd CV Vi 2 C2
2 VCC1 1 2 Vdc Vd VL 2 Vi
Vdc C2 VC 1 VC 2
Vd VC 1 VL 2 VC 2 Vi V2dc D2
V2dc VL 2
VL 2 2 D2 i L2 vd
2 i
L2
L2 vd i
L2
L2 vd
i
L2
L2 vd L2

(a) (b)
(a) (b)
Figure 7. Simplified equivalent circuit for evaluating conditions: (a) Up shoot-through (UST); (b) down
Figure 7. Simplified equivalent circuit for evaluating conditions: (a) Up shoot-through (UST); (b)
shoot-through (DST).
Figure 7. Simplified equivalent circuit
down forshoot-through
evaluating conditions:
(DST). (a) Up shoot-through (UST); (b)
down shoot-through
As shown in Table 1, the false shoot-through condition (DST).
can happen, being originated from gate
Asthat
signals shown in Table
turn-on the 1, the false shoot-through
transistors. condition
These states led can happen,
the device being originated
to malfunction. from gate
For the proposed
As that
signals shown in Table
turn-on the 1,transistors.
the false shoot-through
These states condition
led the can happen,
device to being originated
malfunction. For the from gate
proposed
algorithm and due to the reliability constraints, they are neglected in this paper considering the
signals thatand
algorithm turn-on
due the
to the transistors.
reliability These states they
constraints, led the
aredevice to malfunction.
neglected in this paperFor the proposed
considering the
proposed switching algorithm. Table 2 represents all vectors that can be obtained by the switching
algorithm
proposed and due to the
switchinginalgorithm.reliability constraints, they are neglected in this paper considering the
vectors represented Figure 8. Table 2 represents all vectors that can be obtained by the switching
proposed
vectors switchingin
represented algorithm.
Figure 8. Table 2 represents all vectors that can be obtained by the switching
vectors represented in Figure 8. 2. CMV generation by Z-source converter.
Table
Table 2. CMV generation by Z-source converter.
Vectors StateTable 2. CMV
CMVgeneration
State CMV
by Z-source converter.State CMV
Vectors State CMV State CMV State CMV
Zero Vectors
[OOO] State 0 CMV [PPP] State CMV + Vdc State
[NNN]CMV − V2dc
𝑉 2 𝑉
Zero [OOO] Vdc 0 [PPP] + +Vdc [NNN] [OPO]− 𝑉2
Positive [POO] + [PPO] 𝑉2 + V6dc
Small Zero [OOO] 6 0 [PPP] + 3 [NNN] −
+ Vdc 𝑉 +𝑉+2 6dc [POP] 𝑉2
V
[OPP] [OPP] + V3dc
[POO] 3+ [PPO] [OPO] +
Vdc 𝑉6 +𝑉
Negative
Positive
[ONN] [POO]− 3+ [OON]
[PPO]
3− Vdc
6
[NON]+ 𝑉6
[OPO]
−Vdc
3
Small Positive Vdc 𝑉6 3
𝑉− Vdc 6
Small
[NOO] −
[OPP] 6+ [NOO]
[OPP] + 3 [ONO] 𝑉 − V6dc
𝑉3 𝑉6
[POP] +𝑉
Small 3
[PON] [OPP] 0 + [OPP] + 0
[OPN] [POP][NPO]+ 0
Medium
𝑉3 𝑉60 −𝑉3
[NOP] [ONN] 0 − [ONP]
[OON] − [NON] [PNO] 0
Negative 𝑉3 𝑉6 −𝑉3
[PNN] [ONN]− Vdc− [OON]
[PPN] − − Vdc [NON] [NPN] − V6dc
Large Negative 6
𝑉3 𝑉6 6 3
𝑉
Small [NOO]− Vdc−
[NPP] [NOO]
[NPP] − − V6dc [ONO] [PNP]− 𝑉 − V6dc
Small 6 𝑉6 𝑉3 6
[NOO] − [NOO] − [ONO] −
6
N: negative 3 6
[PON] 0 state,[OPN]
P: positive state.
0 [NPO] 0
Medium [PON] 0 [OPN] 0 [NPO] 0
Medium [NOP] 0 [ONP] 0 [PNO] 0
[NOP] 0 [ONP] 0 [PNO] 0
 Phase A B C
ST Sectors 𝑆 ,𝑆 ,𝑆 ,𝑆 𝑆 ,𝑆 ,𝑆 ,𝑆 𝑆 ,𝑆 ,𝑆 ,𝑆

To investigate the operation principles, it is supposed that the reference vector is positioned in
Electronics 2020, 9, 1639 8 of 18
sector 5, for instance.

S4 S3
S5 S2

S6 S1
θ

S7 S 12

β
S8 S 11
θ α S x : Sec torx
S9 S 10
Figure 8. Switching states of the proposed algorithm.

The switching
Then the large,areas shown
medium andinzero
Figure 8 are around
vectors sectionalized intohave
it should 12 sub-areas. According
been considered to Table 2,
to synthesize
there are four sections that
the reference voltage as: belong to each phase at ST states which are summarized in Table 3.

Table 3. Switching states of ST in each phase.

𝑉 ⃗𝑇 = 𝑉⃗𝑡 + 𝑉⃗𝑡 + 𝑉 ⃗𝑡 (9)
Phase A B C
ST Sectors S2 , S5 , S8 , S11 S3 , S6 , S9 , S12 S1 , S4 , S6 , S10
where 𝑡 = 𝑡 (L: stands for large) and 𝑡 = 𝑡 (M: stands for medium). The vectors 𝑉⃗, 𝑉⃗ and 𝑉 ⃗
are defined as:
To investigate the operation principles, it is supposed that the reference vector is positioned in
sector 5, for instance.
𝑉⃗ = 0 (10)
Then the large, medium and zero vectors around it should have been considered to synthesize the
reference voltage as:
√3 𝑉→ 5𝜋→
→ ⃗ →
Vre f Ts𝑉==V03t0 𝐵 ∡ (11)
+V 29 t9 +6V15 t15 (9)
→ → →
where t15 = tL (L: stands for large) and t9 =⃗ tM 2(M:𝑉stands2𝜋for medium). The vectors V0 , V9 and V15
𝑉 = 𝐵 ∡ (12)
are defined as: →
3 2 3
Since 𝑉 ⃗ = 𝑉 ∡𝜃, then the dwell times of = 0above-mentioned vectors could be calculated(10)
V0the as
√
follows: → 3 Vdc 5π
V9 = B ] (11)
3 2 6
→ 2 V 2π
V15 = B dc ] (12)
3 2 3
→
Since Vre f = Vre f ]θ, then the dwell times of the above-mentioned vectors could be calculated
as follows:
√ 
2π

tL = 3 M Ts sin −θ (13)
3
5π
 
tM = 2M Ts sin −θ (14)
6
t0 = Ts − tL − tM (15)
Electronics 2020, 9, 1639 9 of 18

The time interval Ts corresponds to the switching period, while tL , tM and t0 represent the dwell
times of the large vectors, medium vectors and the zero vector, respectively. The reference vector angle
is assumed to be in the range 2π3 ≤ θ ≤ 6 and the modulation index M is computed as:
5π

√ Vre f
M= 3 V (16)
B 2dc
→
While the modulation index is assumed as MMAX = 1, the maximum magnitude of Vre f and the
root mean square (RMS) value of phase to phase voltage (VLL ) are figured out as:
√
MAX 3 Vdc
Vre f
= B (17)
3 2
MAX √
√ Vre f 2 Vdc
MAX
VLL = 3 √ = B (18)
2 2 2
Therefore, according to Figure 8, since the small vectors are not considered in voltage analysis
calculations, the DC link voltage does not affect the phase to phase voltage. As a result, in the proposed
approach, the VLL is similar to the SVPWM switching pattern. All switching sequences in sector 5 are

[OOO] → [NPO] → [NPN ] → [NPO] → [OOO] . The transient interval for switching changing
in three phases is given by:
t0 t0 + tM t0
Ta = , Tb = , Tc = (19)
2 2 2
where Ta , Tb and Tc are the time interval of each phase vector. In the next section, when the reference
vector is located in Section 6, the reference voltage is synthesized as:

→ 1 →
 → → 
Vre f = V0 t0 + V16 t16 + V9 t9 (20)
Ts

where t15 = tL and t9 = tM . Then these triple vectors can be defined in (21), (22) and (23) and their
dwell times are expressed in (24), (25) and (26), where the permissible range of the reference vector
6 ≤θ≤
angle is considered as 5π

π. Then, the synthesis switching sequences in sector 6 are introduced

with the following statement: [OOO] → [NPO] → [NPP] → [NPO] → [OOO] .
→
V0 = 0 (21)
√
→ 3 Vdc 5π
V9 = B ] (22)
3 2 6
→ 2 V
V15 = B dc ]π (23)
3 2
√
tL = 3 M Ts sin(π − θ) (24)
5π
 
tM = 2M Ts sin −θ (25)
6
t0 = Ts − tL − tM (26)

The ST time interval in the ZSI topology is a key design parameter, which should be carefully
chosen. This means that in the proposed topology, the reference vector should be defined by ST states.
→
Therefore, the improved reference voltage Vre f and the sampling time Ts are determinate as:

→ → → → →
Vre f Ts = V0 t0 + VL tL + VM tM + VST tST (27)
Electronics 2020, 9, 1639 10 of 18

Ts = t0 + tL + tM + tST (28)
→
where VST is the ST voltage vector across ST time intervals (tST ) as presented in Table 1. As the ST and
NST states are described in Tables 2 and 3, it is worth-mentioning that the UST and DST states are
never generated if an appropriate sector and switching sequence are adopted. Moreover, the output
voltage waveform is not affected by the proposed ST states, because the ST states have the same effect
as the zero vectors have. Therefore, the ST time transitions are sectionalized into two equal parts which
are supposed to be inserted between medium vectors and zero ones, due to symmetrical characteristic
→
satisfaction, as shown in Figure 8. Assuming that Vre f is located in sector 5, then the ST interval
insertion is applied to phase A, according to Table 4. Formerly, the [SOO] (“S” denotes the ST state)
is going to be added to the reference frame vectors. Since the tST affects the zero vectors, the new
modified dwell time of these vectors (t00 ) is calculated as:

t00 = t0 − tST (29)

Table 4. Switching vectors during ST intervals.

Sector Switching Vectors During ST Intervals

S1 [OOO], [OOS], [PON ], [PNN ], [PON ], [OOS], [OOO]

S2 [OOO], [SOO], [PON ], [PPN ], [PON ], [SOO], [OOO]
S3 [OOO], [OSO], [OPN ], [PPN ], [OPN ], [OSO], [OOO]
S4 [OOO], [OOS], [OPN ], [PNN ], [OPN ], [OOS], [OOO]
S5 [OOO], [SOO], [NPO], [NPN ], [NPO], [SOO], [OOO]
S6 [OOO], [OSO], [NPO], [NPP], [NPO], [OSO], [OOO]
S7 [OOO], [OOS], [NOP], [NPP], [NOP], [OOS], [OOO]
S8 [OOO], [SOO], [NOP], [NNP], [NOP], [SOO], [OOO]
S9 [OOO], [OSO], [ONP], [NNP], [ONP], [OSO], [OOO]
S10 [OOO], [OOS], [ONP], [PNP], [ONP], [OOS], [OOO]
S11 [OOO], [SOO], [PNO], [PNP], [PNO], [SOO], [OOO]
S12 [OOO], [OSO], [PNO], [PNN ], [PNO], [OSO], [OOO]

As the new inserted intervals are symmetrically sectionalized, the improved transition times of
three phases (Ta0 , Tb0 , Tc0 ) are expressed as:

tST
Ta0 = Ta − (30)
2

Tb0 = Tb (31)

Tc0 = Tc (32)

It is obvious that the switching vector during ST interval insertion in sector 5 belongs to

[OOO] → [SOO] → [NPO] → [NPN ] → [NPO] → [FOO] → [OOO] . After that, as the reference vector
moves to sector 6, the ST interval is inserted into the phase B switching period and the modified time
intervals are expressed as:
Ta0 = Ta (33)
tST
Tb0 = Tb − (34)
2
Tc0 = Tc (35)
 𝑆 [𝑂𝑂𝑂], [𝑂𝑂𝑆], [𝑁𝑂𝑃], [𝑁𝑃𝑃], [𝑁𝑂𝑃], [𝑂𝑂𝑆], [𝑂𝑂𝑂]

𝑆 [𝑂𝑂𝑂], [𝑆𝑂𝑂], [𝑁𝑂𝑃], [𝑁𝑁𝑃], [𝑁𝑂𝑃], [𝑆𝑂𝑂], [𝑂𝑂𝑂]

𝑆 [𝑂𝑂𝑂], [𝑂𝑆𝑂], [𝑂𝑁𝑃], [𝑁𝑁𝑃], [𝑂𝑁𝑃], [𝑂𝑆𝑂], [𝑂𝑂𝑂]

Electronics 2020, 9, 1639 11 of 18
𝑆 [𝑂𝑂𝑂], [𝑂𝑂𝑆], [𝑂𝑁𝑃], [𝑃𝑁𝑃], [𝑂𝑁𝑃], [𝑂𝑂𝑆], [𝑂𝑂𝑂]

The switching 𝑆vector[𝑂𝑂𝑂], [𝑆𝑂𝑂],ST

during [𝑃𝑁𝑂], [𝑃𝑁𝑃], [𝑃𝑁𝑂],
interval [𝑆𝑂𝑂],
insertion in[𝑂𝑂𝑂]
sector 6 belongs to

[OOO] → [OSO] → [NPO 𝑆 ] → [ NPP ] → [ NPO ] → [ OSO ] → [ OOO ]
[𝑂𝑂𝑂], [𝑂𝑆𝑂], [𝑃𝑁𝑂], [𝑃𝑁𝑁], [𝑃𝑁𝑂], [𝑂𝑆𝑂], [𝑂𝑂𝑂] complete sequence
. The
selections at all ST sites are represented in Table 4.

Dead Time
4. Dead Time Impact
Impact on CMV Cancelation
The dead time
time (𝑡(td ) effects on CMV elimination are documented in [29]. As power switches such
insulated gate
as insulated gate bipolar
bipolar transistors
transistors (IGBTs)
(IGBTs) and metal oxide semiconductor
semiconductor fieldfield effect transistors
(MOSFETs) do
(MOSFETs) donotnotturn
turnon on
instantaneously, an adverse
instantaneously, effect on
an adverse CMV
effect onsuppression is expected.
CMV suppression Figure 9a
is expected.
represents
Figure the ideal scenario
9a represents the idealwhere the where
scenario dead time requirement
the dead is not necessary.
time requirement However, real
is not necessary. power
However,
switches
real powerrequire finiterequire
switches time tofinite
turn-on.
timeIntoorder to prevent
turn-on. In orderthetoshoot-through condition, the condition,
prevent the shoot-through dead time
condition
the will condition
dead time force the CMV not bethe
will force zero,
CMVas can
not be
be verified
zero, as in Figure
can 9b. Considering
be verified in Figure 9b.thatConsidering
the value of
td is taking
that the value of 𝑡 isthe
into account trigger
taking intoswitch gate pulses
account according
the trigger gatesign
to the
switch (I ). dv/dt
pulses < 0 condition,
according to the
𝑠𝑖𝑔𝑛(𝐼). 𝑑𝑣/𝑑𝑡 < 0 condition,
CMV high-frequency pulses can CMVbe high-frequency
eliminated. pulses can be eliminated.

(a) (b)
Figure 9. CMV mitigation: (a) The CMV in ideal condition [2]; (b) the CMV in real condition
Figure 9. CMV mitigation: (a) The CMV in ideal condition [2]; (b) the CMV in real condition (needs
(needs compensation).
compensation).
In order to reduce the dead time contribution on CMV generation, it is proposed that the dead
In order tointerval
time transition reduce is
theincorporated
dead time contribution on CMV
into the reference generation,
voltage it is
equation as:proposed that the dead
time transition interval is incorporated into the reference voltage equation as:
→ → → → → →
Vre f Ts = V0 t0 + VL tL + VM tM + VST tST + Vd td (36)
𝑉 ⃗𝑇 = 𝑉⃗𝑡 + 𝑉⃗𝑡 + 𝑉 ⃗𝑡 + 𝑉 ⃗𝑡 + 𝑉⃗𝑡 (36)
Ts = t0 + tL + tM + tST + td (37)
→
where Vd is the dead time voltage vector. The changes of the switches in this mode are visible in
Figure 10a. The CMV is zero at all instants of simulation. Currently, in phase “A”, for instance,
these principle operations, transient states and the impact of dead time are investigated. There are
two analysis sub-sections: The first one represents the positive current (sign(Ia ) > 0) and the second
one will discuss about the negative current flow through the load (sign(Ia ) < 0). These switching
transitions are depicted in Figures 10 and 11, respectively. For better realization, the Figure 10a is
explained as below: In this case, S3 and S4 are switched on and voltage Va0 is equal to −Vdc /2. The final
state is to reach the condition shown in Figure 5; that switches S2 and S3 are turned on and voltage Va0
is zero. In this transient mode, switch S2 starts to turn on, but due to the dead time, until this switch is
completely turned on, current Ia still passes through the two previous switches. In the next section,
the proposed constructed laboratory prototype would be tested in the power electronics and drive
laboratory of our university.
Va0 is zero. In this transient mode, switch S2 starts to turn on, but due to the dead time, until this
switch is completely turned on, current Ia still passes through the two previous switches. In the next
section, the proposed constructed laboratory prototype would be tested in the power electronics and
Electronics 2020, 9, 1639 12 of 18
drive laboratory of our university.

S a1 S a1 S a1
C1 Vdc C1 Vdc C1 Vdc
2 S a2 2 S a2 2 S a2
Ia > 0 Ia > 0 Ia > 0
0 a 0 a 0 a
S a3 S a3 S a3
C2 Vdc C2 Vdc C2 Vdc
2 2 2
S a4 S a4 S a4

(a)

S a1 S a1 S a1
C1
Vdc C1 Vdc C1 Vdc
2 S a2 2 S a2 2 S a2
Ia > 0 Ia > 0 Ia > 0
0 a 0 a 0 a
S a3 S a3 S a3
C2 Vdc C2 Vdc C2 Vdc
2 2 2
S a4 S a4 S a4

(b)

S a1 S a1 S a1
C1 Vdc C1 Vdc C1 Vdc
2 S a2 2 S a2 2 S a2
Ia > 0 Ia > 0 Ia > 0
0 a 0 a 0 a
S a3 S a3 S a3
C2 Vdc C2 Vdc C2 Vdc
2 2 2
S a4 S a4 S a4

(c)

S a1 S a1 S a1
C1 Vdc C1 Vdc C1 Vdc
2 S a2 2 S a2 2 S a2
Ia > 0 Ia > 0 Ia > 0
0 a 0 a 0 a
S a3 S a3 S a3
Vdc C2 Vdc C2 Vdc
C2
2 2 2
S a4 S a4 S a4

(d)
Figure 10. Transient state of switching at positive current: (a) From −Vdc /2 to 0; (b) from 0 to +Vdc /2;
Figure 10. (c) from +Vstate
Transient dc /2 to 0;
of(d)
switching dc /2
from 0 to −Vat positive
[2]. current: (a) From -Vdc/2 to 0; (b) from 0 to +Vdc/2;
(c) from +Vdc/2 to 0; (d) from 0 to -Vdc/2 [2].
 Electronics 2020, 9, 1639 13 of 18
Electronics 2020, 9, x FOR PEER REVIEW 13 of 18

S a1 S a1 S a1
Vdc C1 Vdc C1 Vdc
C1
2 S a2 2 S a2 2 S a2
Ia < 0 Ia < 0 Ia < 0
0 a 0 a 0 a
S a3 S a3 S a3
C2 Vdc C2 Vdc C2 Vdc
2 2 2
S a4 S a4 S a4

(a)

S a1 S a1 S a1
C1 Vdc C1 Vdc C1 Vdc
2 S a2 2 S a2 2 S a2
Ia < 0 Ia < 0 Ia < 0
0 a 0 a 0 a
S a3 S a3 S a3
C2 Vdc C2 Vdc C2 Vdc
2 2 2
S a4 S a4 S a4

(b)

S a1 S a1 S a1
C1 Vdc C1 Vdc C1 Vdc
2 S a2 2 S a2 2 S a2
Ia < 0 Ia < 0 Ia < 0
0 a 0 a 0 a
S a3 S a3 S a3
C2 Vdc C2 Vdc C2 Vdc
2 2 2
S a4 S a4 S a4

(c)

S a1 S a1 S a1
C1 Vdc C1 Vdc C1 Vdc
2 S a2 2 S a2 2 S a2
Ia < 0 Ia < 0 Ia < 0
0 a 0 a 0 a
S a3 S a3 S a3
Vdc Vdc Vdc
C2 C2 C2
2 2 2
S a4 S a4 S a4

(d)
Figure 11. Transient state of switching at negative current: (a) From −Vdc /2 to 0; (b) from 0 to +Vdc /2;
Figure 11.(c)Transient
from +Vdc /2state of from
to 0; (d) switching at/2negative
0 to −Vdc [2]. current: (a) From -Vdc/2 to 0; (b) from 0 to +Vdc/2;
(c) from +Vdc/2 to 0; (d) from 0 to -Vdc/2 [2].
5. Verification of CMC Cancelation through Experimental Evaluation
The prototype was built according to the specifications shown in Table 5. A general view of the
5. Verification of CMC Cancelation through Experimental Evaluation
test bench can be seen in Figure 12. A base switching frequency of 12 kHz was used for synthesizing
The prototype was built according to the specifications shown in Table 5. A general view of the
test bench can be seen in Figure 12. A base switching frequency of 12 kHz was used for synthesizing
three-phase voltage waveforms at 50 Hz. Available laboratory resources are restricted to low power
tests. Hence, load maximum rated power is 300 W and fixed at unity power factor. The SVPWM
Electronics 2020, 9, 1639 14 of 18

three-phase voltage waveforms at 50 Hz. Available laboratory resources are restricted to low power
Electronics 2020, 9, x FOR
Electronics PEERPEER
REVIEW 14 of 14
18 of 18
tests. Hence,2020,load9, xmaximum
FOR REVIEW
rated poweris 300 W and fixed at unity power factor. The SVPWM
variant presented in this paper is compared to the SPWM switching scheme. Figure 13 depicts CMV
voltage and and
voltage capacitor voltages
capacitor jointly,
voltages which
jointly, imply
which implythat that
the dead timetime
the dead compensation doesdoes
compensation not have
not have
output regarding the two PWM switching schemes. In conventional SPWM CMV cancellation is not
any any
bad bad
effect on the capacitor voltage.
effect on the capacitor voltage.
possible. In addition, it can generate high-frequency pulses associated with the CMV pattern. As for
the proposed SVPWM variant, the CMV
Table profile is virtually
5. Prototype MainMain null thanks to the dead time compensation
Specifications.
Table 5. Prototype Specifications.
algorithm implemented in the novel switching scheme. The three-phase load current with a semi-pure
sinusoidal waveform is represented inParameter Parameter
Figure 14a. The current ValueValue
total harmonic distortion (THD) is
computed as 1.12%, which is inDC thevoltage
standard range.
(𝑽𝒅𝒄(𝑽
) 𝒅𝒄 ) Figure 14b shows
𝑉 𝑉 input voltage and capacitor
150 150 the
DC voltage
voltages jointly, which imply that the dead time compensation does not have any bad effect on the
capacitor voltage. LineLine
frequency (𝒇𝒍𝒊𝒏𝒆(𝒇) 𝒍𝒊𝒏𝒆 )
frequency 50 𝐻𝑧50 𝐻𝑧
Switching frequency
Switching ) 𝒔𝒘 ) 12 𝑘𝐻𝑧
(𝒇𝒔𝒘(𝒇
frequency 12 𝑘𝐻𝑧
Table 5. Prototype Main Specifications.
Output power
Output power ) 𝒐𝒖𝒕 )
(𝑷𝒐𝒖𝒕(𝑷 300 300
𝑊 𝑊
Parameter Value
FilterFilter
inductance (𝑳𝒇 ) (𝑳𝒇 )
inductance 2 𝑚𝐻
DC voltage (Vdc ) 150 V2 𝑚𝐻
Line frequency
Filter ( fline(𝑪
capacitance ) ) 50 Hz
Filter capacitance 220 220
𝜇𝐹 𝜇𝐹
) 𝒇)
( fsw(𝑪
𝒇
Switching frequency 12 kHz
) 1.5 𝑚𝐻
Output power (Pout
ZSI inductance (𝑳𝒁) (𝑳 300 W
ZSI inductance 𝑺𝒐𝒖𝒓𝒄𝒆 ) 1.5 𝑚𝐻
Filter inductance (L f ) 𝒁 𝑺𝒐𝒖𝒓𝒄𝒆 2 mH
ZSI capacitance
Filter ZSI (𝑪𝒁f ) (𝑪
capacitance
capacitance (C )
𝒁 𝒔𝒐𝒖𝒓𝒄𝒆 )
𝒔𝒐𝒖𝒓𝒄𝒆 670µF
220 𝜇𝐹 𝜇𝐹
670
ZSI inductance (LZ−Source ) 1.5 mH
𝑰𝑮𝑩𝑻
ZSI 𝑰𝑮𝑩𝑻
capacitance (CZ−source ) BUP314
670 µFBUP314
IGBT BUP314
𝑫𝒊𝒐𝒅𝒆
Diode 𝑫𝒊𝒐𝒅𝒆 DSEI8-06
DSEI8-06
DSEI8-06

Figure
Figure 12.
12. Laboratory
Figure Laboratory implementation
implementation
12. Laboratory setup.
setup.
implementation setup.

𝑉 𝑉 𝑉 𝑉

𝑉 𝑉 𝑉
𝑉

𝑉 𝑉
𝑉 𝑉

𝑉 𝑉
𝑉 𝑉

(a) (a) (b) (b)

13. Threephase
Figure 13.
Figure phaseoutput
outputvoltage
voltage and CMV waveforms (100 volts/div
andand 10 time/div):
µs time/div):
FigureThree
13. Three phase and
output voltage CMV
and waveforms
CMV (100
waveforms volts/div
(100 volts/div 10 μs
and (a) (a)
10 μs time/div):
(a) SPWM method; (b) proposed approach.
SPWM method; (b) proposed approach.
SPWM method; (b) proposed approach.
Electronics 2020, 9, 1639 15 of 18
Electronics 2020, 9, x FOR PEER REVIEW 15 of 18

Electronics 2020, 9, x FOR PEER REVIEW 15 of 18

Electronics 2020, 9, x FOR PEER REVIEW 15 of 18
𝐼 𝐼 𝐼 𝑉

𝐼 𝐼 𝐼 𝑉
𝐼 𝐼 𝐼 𝑉 𝑉

𝑉
𝑉
4 [𝑚𝑠]
↔

↔
↔
4 [𝑚𝑠] 1 [𝐴] 60 [𝑉]
↔ 4 [𝑚𝑠]
↔

↔↔
4 [𝑚𝑠] ↔↔ 1 [𝐴] 4 [𝑚𝑠] 60 [𝑉]
↔
4 [𝑚𝑠] 1 [𝐴] ↔ 60 [𝑉]
↔ (a) (b)
(a) (b)
Figure 14. Three phase load current and input voltages: (a) Three phase load current; (b) input voltage
(a) phase load current and input voltages: (a)(b)
Figure 14. Three Three phase load current; (b) input voltage
and capacitors’
Figure 14.
voltages.
Three phase load current and input voltages: (a) Three phase load current; (b) input voltage
and capacitors’ voltages.
and capacitors’
Figure 14. Three voltages.
phase load current and input voltages: (a) Three phase load current; (b) input voltage
As theAs proposed
the proposedmethod is to resolve
method the impact
is to resolve of the of
the impact deadthetime
deadintime the in
CMV cancellation,
the CMV cancellation,it can it can
and capacitors’ voltages.
be observed As the
in proposed
Figure 15b method
that theis V
to resolve
waveformthe impact
has of the dead
higher THD time in thebecause
content CMV cancellation,
V and V it canremain
be observed in Figure 15b that the 𝑉 waveform has higher THD content because 𝑉 and 𝑉
AB a0 an
𝑉 the 𝑉 and 𝑉
equal.be observed
InAs
the
remain
thesame
equal.
in Figure
proposed
Figure,
In
15b that
method
the DCis totheresolve
input waveform
impact
voltage hasthehigher
of
of the PWM THDincontent
deadinverter
time the CMV
running because
cancellation,
the SVPWM it canvariant
remain
be equal.
observed thethe
inInFigure samesame
15b Figure,
Figure,
that thethe
the DC input
𝑉 DCwaveform
input voltage voltage
of the PWM
has higher
of theinverter
THD content
PWM inverter
running
because
running
𝑉the SVPWM
and 𝑉
the SVPWM
revealsvariant
a high reveals
voltagearipplehigh that goesripple
voltage downthat to 0V.
goesNevertheless,
down to 0V. itNevertheless,
does not compromise it does thecompromise
not inverter’s the
variantequal.
remain revealsIna thehighsame
voltage ripple
Figure, thethat
DCgoesinput down to 0V.
voltage of Nevertheless,
the PWM inverter it does not compromise
running the SVPWM the
maininverter’s
function,
inverter’s which
main
main
is to drive
function,
function, which
the
which AC motor.
to isdrive
is that to drive The
the AC the THDAC profile
motor. was
The measured
THDnot andwas
profile comparedmeasured to and
variant reveals a high voltage ripple goes down to motor.
0V. The THD
Nevertheless, itprofile
does was measured
compromise and
the
the results
compared
compared
inverter’s of [6,16]
to to
main in
thethe Figure
results
results
function, 16.
ofand
of which
[6] The
[6] isand
[16] figure
toin[16]
Figure
drive shows
inthe
Figure
16.AC a
The16. slight
TheThe
figure
motor. increase
figure
shows THDashowsin
slight
profilethis quantity,
a slight
increase
was in increase which in
this quantity,
measured and is not
this quantity,
significant
which over
is not the switching
significant frequency
over the
and switching
[16] inrange
Figure under
frequency
16. Thestudy.
range
figure This
under
shows small increase
study.
which is not significant over the switching frequency range under study. This small increase is due
compared to the results of [6] a slight This is
small
increase due
in to
increase
this the algorithm
is
quantity, due
implemented
totothe
which theis to minimize
algorithm
not significant
algorithm dead
implemented time
over the
implemented interval.
toswitching
minimize
to minimize It is time
dead
frequencyworth
dead mentioning
interval.
range
time under
interval. that
It isstudy.
worth the THDmentioning
ismentioning
It This small
worth value is isstill
that the
increase THD
due within
that the THD
value
the acceptable
tovalue is still
the algorithm
is stillwithin
range the acceptable
according
implemented
within range
totointernational
minimize
the acceptable according
rangedead to international
standards.
time interval.
according standards.
It is worth mentioning
to international standards.that the THD
value is still within the acceptable range according to international standards.

↑𝑉
↑𝑉
↑𝑉 ↑𝑉
𝑉 𝑉 ↑𝑉 ↑𝑉
𝑉 𝑉 𝑉 𝑉
↔↔

4 [𝑚𝑠]
↔↔

100 [𝑉] 100 [𝑉]

↔
4 [𝑚𝑠]
4 [𝑚𝑠]
↔
↔

4 [𝑚𝑠] 100 [𝑉] 100 [𝑉]

↔

100 [𝑉]
↔↔ 4 [𝑚𝑠] 4 [𝑚𝑠]
↔ ↔
100 [𝑉]
(a) (b)
(a) (b)
Figure 15. DC link voltage
(a)and line-to-line voltage waveforms: (a) SPWM method; (b)(b) proposed
approach.
Figure
Figure 15. DC15.
linkDC link voltage
voltage and line-to-line
and line-to-line voltage
voltage waveforms:
waveforms: (a) SPWM
(a) SPWM method;
method; (b)(b) proposed
proposed approach.
Figure 15. DC link voltage and line-to-line voltage waveforms: (a) SPWM method; (b) proposed
approach.
approach. 3% [6]
[%] [%]

3% [6]
[16]
THDTHD

2% 3% [16]
Proposed [6]
Ooutput Current THD [%]
Current

2% Proposed [16]
Current

1% 2% Proposed
Ooutput

1%
Ooutput

0% 1%
30 50 80 100 150 220 400 500
0%
30 50 80RMS Output
100 Voltage
150 [V]
220 400 500
RMS Output Voltage [V]
Figure
Figure 16. 16.
Output 0%
Output currentTHD
current THDcomparison
comparison as
asaafunction
functionofof
output ACAC
output voltage.
voltage.
30 50 80 100 150 220 400 500
Figure 16. Output current THD comparison as a function of output AC voltage.
RMS Output Voltage [V]

Figure 16. Output current THD comparison as a function of output AC voltage.

 Electronics2020,
Electronics 2020,9,9,1639
x FOR PEER REVIEW 16ofof18
16 18
Electronics 2020, 9, x FOR PEER REVIEW 16 of 18
In Figures 17 and 18, the effectiveness of applying the dead time compensation is evaluated from
In In Figures
Figures
an electrical 17 17
andand
18,18,
efficiency the the effectiveness
effectiveness
viewpoint. This of of applying
applying
implies thethe
a need fordead
dead time
time
better compensation
compensation
performance is evaluated
is evaluated
evaluation to fromfrom
feed the
an electrical
an electrical efficiency
inductiveefficiency viewpoint.
dynamic viewpoint.
loads in low This
This implies
implies
voltage a need for better
a need fornetworks.
distribution performance
better performance evaluation
evaluation
All efficiencies to
to feed
calculated feed
arethethe
more
inductive
inductive
than 90%, dynamic
dynamic
whichloads loadsin in
represents lowlow voltage
voltage
the distribution
usefuldistribution
performance. networks.
networks.
The AllAll efficiencies
efficiencies
experimental calculated
calculated
efficiency analysis are
areis more
more
realized
than
than 90%,
in90%, which
which
Figure represents
18 represents
in terms of the useful
theinput performance.
usefulvoltage
performance. The experimental
The experimental
variations. efficiency
As a result,efficiency analysis is realized inis
is realized
analysiscomparison
comprehensive
Figure
in Figure 18 in terms
18 ininterms
represented of input voltage
Table 6oftoinput variations.
voltage
show the As a
variations.
effectiveness result, comprehensive
As proposed
of the a result, switching comparison
comprehensive is represented
comparison
algorithm. is
in Table 6 in
represented to show
Table the
6 toeffectiveness of the proposed
show the effectiveness of theswitching
proposed algorithm.
switching algorithm.
100%
Percentage of transmitted active
[6]
100%
Percentage of transmitted active

96% [6] Proposed

96% Proposed
[16]
92%
power

[16]
92%
power

88%
88%
84%
84%
80%
80% 6 kHz 12 kHz 20 kHz 30 kHz
6 kHz 12 kHz 20 kHz
Switching 30 kHz
frequency
Switching frequency

Figure17.
Figure 17.Transmitted
Transmittedactive
activepower
powervs.
vs.switching
switchingfrequency.
frequency.
Figure 17. Transmitted active power vs. switching frequency.
100%
Theoretical
100%
Experimental
96% Theoretical
96% Experimental
Efficiency

92%
Efficiency

92%
88%
88%
84%
84%
80%
80% 4 kHz 6 kHz 12 kHz 20 kHz
4 kHz Switching
6 kHz 12frequency
kHz 20 kHz
Switching frequency
Figure 18.Efficiency
Figure18. Efficiencyanalysis
analysisin
interms
termsof
ofswitching
switchingfrequency.
frequency.
Figure 18. Efficiency analysis in terms of switching frequency.
Table 6. Measured maximum CMV.
Table 6. Measured maximum CMV.
Table 6. Measured maximum Max{CMV}
Methods CMV.
Max{CMV} Methods
[6]
Methods
Max{CMV}
[6]Vdc dc /6
V/6
[8] Vdc /2
[6]
Vdc/6
[9] [8]Vdc dc /6
V/2
√
Vdc/2Vdc / 3
[16] [8]
[17] [9]Vdc dc /2
V/6
Proposed approach
[9]
Vdc/6 Zero
[16] Vdc/√3
[16] V dc/√3
6. Conclusions [17] Vdc/2
This paper has presented a variant [17]
of the SVPWM Valgorithm
dc/2 for CMV cancellation in a PWM
Proposed approach Zero
inverter-driven three-phase motor. The dead time requirement for the proper operation of power
Proposed approach Zero
switches in a bridge configuration is also a source of high frequency noise, contributing to the sharp
6. Conclusions
edged CMV transitions as well as to an increase in its amplitude. The proposed SVPWM variant is
6. Conclusions
able to eliminate the dead time impact on the CMV level while providing a complete cancellation of it.
This paper has presented a variant of the SVPWM algorithm for CMV cancellation in a PWM
The pulsating
This paper hasoutput of the impedance
presented amotor.
variantThe ofsource
the modulealgorithm
SVPWM is correlated with the shoot-through interval
inverter-driven three-phase dead time requirementfor forCMV cancellation
the proper in a of
operation PWMpower
without changing
inverter-driven the sinusoidal-shaped waveform of the three-phase output. The impedance source
switches in athree-phase motor. The
bridge configuration dead
is also time requirement
a source for the noise,
of high frequency proper operation
contributing of
to power
the sharp
topology
switches provided in the DC power sideaofsource
structure makes it possible to control the output ACsharp
voltage
edgedinCMVa bridge configuration
transitions as well isasalso
to an increase of in
high
its frequency
amplitude.noise, contributing
The proposed to the
SVPWM variant is
edged CMV transitions as well as to an increase in its amplitude. The proposed SVPWM variant is
Electronics 2020, 9, 1639 17 of 18

in both the stepping-up/down modes. The experimental results have shown a slight increase of 0.2%
in the output current THD calculation.

Author Contributions: Conceptualization and methodology, M.M.; investigation and software, M.F.; validation
and review, E.M.G.R.; editing, E.P. All authors have read and agreed to the published version of the manuscript.
Funding: The authors declare no funding.
Conflicts of Interest: The authors declare no conflict of interest.

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