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VHDL Programs

This document contains VHDL code that defines an 8-to-3 encoder and a 3-to-8 decoder. The encoder entity takes in 8 bits of input and outputs 3 bits by performing OR logic on combinations of the inputs. The decoder entity takes in 3 bits of input and outputs 8 bits by performing AND logic on combinations of the inputs to uniquely determine the input combination.

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Anuradha Khalkho
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© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
31 views

VHDL Programs

This document contains VHDL code that defines an 8-to-3 encoder and a 3-to-8 decoder. The encoder entity takes in 8 bits of input and outputs 3 bits by performing OR logic on combinations of the inputs. The decoder entity takes in 3 bits of input and outputs 8 bits by performing AND logic on combinations of the inputs to uniquely determine the input combination.

Uploaded by

Anuradha Khalkho
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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8:3 Encoder

library ieee;
use ieee.std_logic_1164.all;

entity enc is
port(i0,i1,i2,i3,i4,i5,i6,i7:in bit; o0,o1,o2: out bit);
end enc;

architecture vcgandhi of enc is


begin
o0<=i4 or i5 or i6 or i7;
o1<=i2 or i3 or i6 or i7;
o2<=i1 or i3 or i5 or i7;
end vcgandhi;

3:8 decoder

library ieee;
use ieee.std_logic_1164.all;

entity dec is
port(i0,i1,i2:in bit; o0,o1,o2,o3,o4,o5,o6,o7: out bit);
end dec;

architecture vcgandhi of dec is


begin
o0<=(not i0) and (not i1) and (not i2);
o1<=(not i0) and (not i1) and i2;
o2<=(not i0) and i1 and (not i2);
o3<=(not i0) and i1 and i2;
o4<=i0 and (not i1) and (not i2);
o5<=i0 and (not i1) and i2;
o6<=i0 and i1 and (not i2);
o7<=i0 and i1 and i2;
end vcgandhi;

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