EVALUATION KIT AVAILABLE

MAX5214/MAX5216 14-/16-Bit, Low-Power, Buffered Output,

Rail-to-Rail DACs with SPI Interface

General Description Benefits and Features

The MAX5214/MAX5216 are pin-compatible, 14-bit and ●● Low Power Consumption (80µA max)
16-bit digital-to-analog converters (DACs). The MAX5214/ ●● 14-/16-Bit Resolution in a 3mm x 5mm, 8-Pin μMAX
MAX5216 are single-channel, low-power, buffered volt- Package
age-output DACs. The devices use a precision external
reference applied through the high resistance input for ●● Relative Accuracy
rail-to-rail operation and low system power consumption. • ±0.40 LSB INL (MAX5214, 14-Bit typ, ±1 LSB max)
The MAX5214/MAX5216 accept a wide 2.7V to 5.5V sup- • ±1.2 LSB INL (MAX5216, 16-Bit typ, ±4 LSB max)
ply voltage range. Power consumption is extremely low ●● Guaranteed Monotonic Over All Operating Ranges
to accommodate most low-power and low-voltage appli- ●● Low Gain and Offset Error
cations. These devices feature a 3-wire SPI-/QSPI™-/
●● Wide 2.7V to 5.5V Supply Range
MICROWIRE-/DSP-compatible serial interface to save
board space and to reduce the complexity in isolated ●● Rail-to-Rail Buffered Output Operation
applications. The MAX5214/MAX5216 minimize the digi- ●● Safe Power-On Reset (POR) to Zero DAC Output
tal noise feedthrough from input to output with SCLK and
●● Fast 50MHz, 3-Wire, SPI/QSPI/MICROWIRE
DIN input buffers powered down after completion of each
Compatible Serial Interface
serial input frame. On power-up, the MAX5214/MAX5216
reset the DAC output to zero, providing additional safety ●● Schmitt-Trigger Inputs for Direct Optocoupler
for applications that drive valves or other transducers that Interface
need to be off on power-up. The DAC output is buffered ●● Asynchronous CLR Clears DAC Output to Code 0
resulting in a low supply current of 80µA (max) and a low
●● High Reference Input Resistance for Power
offset error of ±0.25mV. A zero level applied to the CLR
Reduction
pin asynchronously clears the contents of the input and
DAC registers and sets the DAC output to zero indepen- ●● Buffered Voltage Output Directly Drives 10kΩ Loads
dent of the serial interface. The MAX5214/MAX5216 are
available in an ultra-small (3mm x 5mm), 8-pin µMAX®
package and are specified over the -40°C to +105°C
extended industrial temperature range.
Functional Diagram
Applications
●● 2-Wire Sensors
VDD REF
●● Communication Systems
●● Automatic Tuning
●● Gain and Offset Adjustment POR MAX5214
●● Power Amplifier Control CS MAX5216
●● Process Control and Servo Loops SERIAL-TO-
SCLK PARALLEL
●● Portable Instrumentation INPUT DAC 14-/16-BIT OUT
CONVERTER REGISTER REGISTER
●● Programmable Voltage and Current Sources DIN DAC BUFFER
●● Automatic Test Equipment

Ordering Information appears at end of data sheet.

CLR GND
QSPI is a trademark of Motorola, Inc.
µMAX is a registered trademark of Maxim Integrated Products, Inc.

19-5651; Rev 2; 7/13

MAX5214/MAX5216 14-/16-Bit, Low-Power, Buffered Output,
Rail-to-Rail DACs with SPI Interface

Absolute Maximum Ratings

VDD to GND..............................................................-0.3V to +6V Maximum Current into Any Input or Output..................... Q50mA
REF, OUT, CLR to GND............................... -0.3V to the lower of Operating Temperature Range......................... -40NC to +105NC
(VDD + 0.3V) and +6V Storage Temperature Range............................. -65NC to +150NC
SCLK, DIN, CS to GND............................................-0.3V to +6V Lead Temperature (soldering, 10s).................................+300NC
Continuous Power Dissipation (TA = +70NC) Soldering Temperature (reflow).......................................+260NC
FMAX (derate at 4.8mW/NC above +70NC)..................387mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.

Package Thermal Characteristics (Note 1)

FMAX
Junction-to-Ambient Thermal Resistance (BJA).........206NC/W
Junction-to-Case Thermal Resistance (BJC)................42NC/W
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.

Electrical Characteristics
(VDD = 2.7V to 5.5V, VREF = 2.5V to VDD, CL = 60pF, RL = 10kI, TA = -40NC to +105NC, unless otherwise noted. Typical values are
at TA = +25NC.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
STATIC ACCURACY (Note 3)
MAX5214 14
Resolution N Bits
MAX5216 16
MAX5214 (14-bit) (Note 4) -1 ±0.4 +1
Integral Nonlinearity INL MAX5216 (16-bit) (Note 4) -4 ±1.2 +4 LSB
MAX5216B (16-bit) (Note 4) -8 ±3 +8
MAX5214 (14-bit) (Note 4) -1 ±0.1 +1
Differential Nonlinearity DNL LSB
MAX5216 (16-bit) (Note 4) -1 ±0.25 +1
Offset Error OE (Note 5) -1.25 ±0.25 +1.25 mV
Offset-Error Drift ±1.6 µV/°C
Gain Error GE (Note 5) -0.06 -0.04 0 %FS
ppmFS/
Gain Temperature Coefficient ±2
°C
REFERENCE INPUT
Reference-Input Voltage Range VREF 2 VDD V
Reference-Input Impedance RREF 200 256 kΩ
DAC OUTPUT
No load (typical) VDD
VDD -
10kΩ load to GND 0
Output Voltage Range (Note 6) 0.2 V
VDD -
10kΩ load to VDD 0.2
0.2
DC Output Impedance 0.1 Ω
Capacitive Load (No Sustained Series resistance = 0Ω 0.1 nF
CL
Oscillations) Series resistance = 1kΩ 15 µF

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MAX5214/MAX5216 14-/16-Bit, Low-Power, Buffered Output,
Rail-to-Rail DACs with SPI Interface

Electrical Characteristics (continued)

(VDD = 2.7V to 5.5V, VREF = 2.5V to VDD, CL = 60pF, RL = 10kI, TA = -40NC to +105NC, unless otherwise noted. Typical values are
at TA = +25NC.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Resistive Load (Note 6) RL 5 kΩ
Short-Circuit Current VDD = 5.5V -25 ±6 +25 mA
Power-Up Time From power-down mode 25 µs
DIGITAL INPUTS (SCLK, DIN, CS, CLR)
0.7 x
Input High Voltage VIH V
VDD
0.3 x
Input Low Voltage VIL V
VDD
Input Leakage Current IIN VIN = 0V or VDD ±0.1 ±1 µA
Input Capacitance CIN 10 pF
Hysteresis Voltage VHYS 0.15 V
DYNAMIC PERFORMANCE (Note 7)
Voltage-Output Slew Rate SR Positive and negative 0.5 V/µs
Voltage-Output Settling Time 1/4 scale to 3/4 scale, to P 0.5 LSB, 14-bit 18 µs
Hex code = 2000 (MAX5214),
Reference -3dB Bandwidth BW 100 kHz
Hex code = 8000 (MAX5216)
Code = 0, all digital inputs from 0V to VDD,
Digital Feedthrough 0.5 nV·s
SCLK < 50MHz
DAC Glitch Impulse Major code transition 2 nV·s
1kHz 73
Output Noise nV/√Hz
10kHz 70
Integrated Output Noise 0.1Hz to 10Hz 3.5 µVP-P
POWER REQUIREMENTS
Supply Voltage VDD 2.7 5.5 V
No load; all digital inputs at 0V or VDD,
Supply Current IDD supply current only; excludes reference 70 80 µA
input current, midscale
Power-Down Supply Current PDIDD No load, all digital inputs at 0V or VDD 0.4 2 µA
TIMING CHARACTERISTICS (Notes 7 and 8) (Figures 1 and 2)
Serial Clock Frequency fSCLK 0 50 MHz
SCLK Pulse-Width High tCH 8 ns
SCLK Pulse-Width Low tCL 8 ns
CS Fall to SCLK Fall Setup Time tCSS0 8 ns
CS Fall to SCLK Fall Hold Time tCSH0 0 ns
CS Rise to SCLK Fall Hold Time tCSH1 0 ns
CS Rise to SCLK Fall tCSA 12 ns
SCLK Fall to CS Fall tCSF 100 ns
DIN to SCLK Fall Setup Time tDS 5 ns
DIN to SCLK Fall Hold Time tDH 4.5 ns
CS Pulse-Width High tCSPW 20 ns

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MAX5214/MAX5216 14-/16-Bit, Low-Power, Buffered Output,
Rail-to-Rail DACs with SPI Interface

Electrical Characteristics (continued)

(VDD = 2.7V to 5.5V, VREF = 2.5V to VDD, CL = 60pF, RL = 10kI, TA = -40NC to +105NC, unless otherwise noted. Typical values are
at TA = +25NC.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

CLR Pulse-Width Low tCLPW 20 ns
CLR Rise to CS Fall tCSC 20 ns

Note 2: Electrical specifications are production tested at TA = +25NC and TA = +105NC. Specifications over the entire operating
temperature range are guaranteed by design and characterization. Typical specifications are at TA = +25NC and are not
guaranteed.
Note 3: Static accuracy tested without load.
Note 4: Linearity is tested within 20mV of GND and VDD.
Note 5: Gain and offset is tested within 100mV of GND and VDD.
Note 6: Subject to offset and gain error limits and VREF settings.
Note 7: Guaranteed by design; not production tested.
Note 8: All timing specifications measured with VIL = VGND, VIH = VDD.

DIN DIN15 DIN14 DIN13 DIN12 DIN11 DIN10 DIN9 DIN8 DIN2 DIN1 DIN0 DIN15
tDS tCP
tDH

SCLK 1 2 3 4 5 6 7 8 14 15 16 1

tCSH0 tCSA
tCH
tCSS0 tCSH1
tCL
CS
tCSPW tCSF

CLR

tCLPW tCSC

Figure 1. 16-Bit Serial-Interface Timing Diagram (MAX5214)

DIN DIN23 DIN22 DIN21 DIN20 DIN19 DIN18 DIN17 DIN16 DIN2 DIN1 DIN0 DIN23
tDS tCP
tDH

SCLK 1 2 3 4 5 6 7 8 22 23 24 1
tCSH0 tCH tCSH1
tCSA
tCSS0
tCL
CS
tCSPW tCSF

CLR

tCLPW tCSC

Figure 2. 24-Bit Serial-Interface Timing Diagram (MAX5216)

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MAX5214/MAX5216 14-/16-Bit, Low-Power, Buffered Output,
Rail-to-Rail DACs with SPI Interface

Typical Operating Characteristics

(TA = +25°C, unless otherwise noted.)

INTEGRAL NONLINEARITY INTEGRAL NONLINEARITY INTEGRAL NONLINEARITY

vs. DIGITAL INPUT CODE vs. DIGITAL INPUT CODE vs. DIGITAL INPUT CODE
1.0 1.0 3

MAX5214 toc02a
MAX5214 toc01b
MAX5214 toc01a

MAX5214 MAX5214 MAX5216

0.8 VREF = 5V 0.8 VREF = 2.5V VREF = 5V
2
0.6 0.6
0.4 0.4 1
0.2 0.2

INL (LSB)
INL (LSB)
INL (LSB)

0 0 0

-0.2 -0.2
-1
-0.4 -0.4
-0.6 -0.6 -2
-0.8 -0.8
-1.0 -1.0 -3
0 4096 8192 12288 16384 0 4096 8192 12288 16384 0 16384 32768 49152 65536
DIGITAL INPUT CODE (LSB) DIGITAL INPUT CODE (LSB) DIGITAL INPUT CODE (LSB)

INTEGRAL NONLINEARITY INL MIN/MAX INTEGRAL NONLINEARITY

vs. DIGITAL INPUT CODE (VREF = 5.0V/2.5V) vs. SUPPLY VOLTAGE
3 3.0 1.00
MAX5214 toc03

MAX5214 toc04a
MAX5214 toc02b

MAX5216 VREF = 5.0V MAX5216 MAX5214

2.5
VREF = 2.5V VREF = 2.5V 0.75
2 2.0 VREF = 5.0V
1.5 VREF = 2.5V 0.50
INL MIN/MAX (LSB)

1 1.0 MAX
0.25
0.5
INL (LSB)

INL (LSB)

0 0 0
-0.5 MIN
-0.25
-1 -1.0
-1.5 -0.50
-2 -2.0
-0.75
-2.5
-3 -3.0 -1.00
0 16384 32768 49152 65536 1 3 5 7 9 11 13 15 17 19 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
DIGITAL INPUT CODE (LSB) DEVICE NUMBER SUPPLY VOLTAGE (V)

INTEGRAL NONLINEARITY INTEGRAL NONLINEARITY INTEGRAL NONLINEARITY

vs. SUPPLY VOLTAGE vs. TEMPERATURE vs. TEMPERATURE
3 1.00 3
MAX5214 toc05a
MAX5214 toc04b

MAX5214 toc05b

MAX5216 MAX5214 MAX5216

0.75
2 2
MAX 0.50
MAX
1 1
0.25 MAX
INL (LSB)

INL (LSB)
INL (LSB)

0 0 0
MIN MIN
-0.25 MIN
-1 -1
-0.50
-2 -2
-0.75

-3 -1.00 -3
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 -40 -20 0 20 40 60 80 100 -40 -20 0 20 40 60 80 100
SUPPLY VOLTAGE (V) TEMPERATURE (°C) TEMPERATURE (°C)

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MAX5214/MAX5216 14-/16-Bit, Low-Power, Buffered Output,
Rail-to-Rail DACs with SPI Interface

Typical Operating Characteristics (continued)

(TA = +25°C, unless otherwise noted.)

MAX(ABS(INL)) DISTRIBUTION MAX(ABS(INL)) DISTRIBUTION DIFFERENTIAL NONLINEARITY

vs. TEMPERATURE vs. TEMPERATURE vs. DIGITAL INPUT CODE
80 80 0.5

MAX5214 toc07a
MAX5214 toc06b
MAX5214
MAX5214 toc06a

MAX5214 MAX5216
70 70 VREF = 5V
-40°C -40°C 0.3
60 +25°C 60 +25°C
+105°C +105°C
COUNT (units)

50
COUNT (units)

50 0.1

DNL (LSB)
40 40
-0.1
30 30

20 20
-0.3
10 10

0 -0.5
0
0 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 0 4096 8192 12288 16384
LSB LSB DIGITAL INPUT CODE (LSB)

DIFFERENTIAL NONLINEARITY DIFFERENTIAL NONLINEARITY DIFFERENTIAL NONLINEARITY

vs. DIGITAL INPUT CODE vs. DIGITAL INPUT CODE vs. DIGITAL INPUT CODE
0.5 0.5 0.5
MAX5214 toc07b

MAX5214 toc07d
MAX5214 toc07c

MAX5214 MAX5216 MAX5216

VREF = 2.5V 0.4 VREF = 5V 0.4 VREF = 2.5V
0.3 0.3 0.3
0.2 0.2
0.1 0.1 0.1
DNL (LSB)

DNL (LSB)
DNL (LSB)

0 0
-0.1 -0.1 -0.1
-0.2 -0.2
-0.3 -0.3 -0.3
-0.4 -0.4
-0.5 -0.5 -0.5
0 4096 8192 12288 16384 0 16384 32768 49152 65536 0 16384 32768 49152 65536
DIGITAL INPUT CODE (LSB) DIGITAL INPUT CODE (LSB) DIGITAL INPUT CODE (LSB)

DNL MIN/MAX DIFFERENTIAL NONLINEARITY DIFFERENTIAL NONLINEARITY

(VREF = 5.0V/2.5V) vs. SUPPLY VOLTAGE vs. SUPPLY VOLTAGE
1.0 0.5 0.5
MAX5214 toc09b
MAX5214 toc08

MAX5214 toc09a

VREF = 5.0V MAX5216 MAX5214 MAX5216

0.8 VREF = 2.5V 0.4 0.4
VREF = 5.0V
0.6 VREF = 2.5V 0.3 0.3
0.4 0.2 0.2
MAX
0.2 0.1 0.1
DNL (LSB)
DNL (LSB)

DNL (LSB)

MAX
0 0 0
-0.2 -0.1 MIN -0.1
-0.4 -0.2 -0.2 MIN
-0.6 -0.3 -0.3
-0.8 -0.4 -0.4
-1.0 -0.5 -0.5
1 3 5 7 9 11 13 15 17 19 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
DEVICE NUMBER SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V)

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MAX5214/MAX5216 14-/16-Bit, Low-Power, Buffered Output,
Rail-to-Rail DACs with SPI Interface

Typical Operating Characteristics (continued)

(TA = +25°C, unless otherwise noted.)

DIFFERENTIAL NONLINEARITY DIFFERENTIAL NONLINEARITY

vs. TEMPERATURE vs. TEMPERATURE
0.5 0.5

MAX5214 toc10a

MAX5214 toc10b
MAX5214 MAX5216
0.4 0.4
0.3 0.3
0.2 0.2
MAX
0.1 0.1
DNL (LSB)

DNL (LSB)
MAX
0 0
-0.1 -0.1
MIN MIN
-0.2 -0.2
-0.3 -0.3
-0.4 -0.4
-0.5 -0.5
-40 -20 0 20 40 60 80 100 -40 -20 0 20 40 60 80 100
TEMPERATURE (°C) TEMPERATURE (°C)

OFFSET ERROR vs. SUPPLY VOLTAGE OFFSET ERROR vs. TEMPERATURE

1.0 1.25
MAX5214 toc11

MAX5214 toc12
VREF = 2.5V

0.8 1.00
OFFSET ERROR (mV)

OFFSET ERROR (mV)

0.6 0.75

0.4 MAX5216 MAX5214 0.50

MAX5214
MAX5216
0.2 0.25

0 0
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 -40 -20 0 20 40 60 80 100
SUPPLY VOLTAGE (V) TEMPERATURE (°C)

OFFSET ERROR DRIFT

vs. TEMPERATURE DISTRIBUTION GAIN ERROR vs. SUPPLY
14 0
MAX5214 toc14
MAX5214 toc13

-40°C TO +105°C VREF = 2.5V

12 BOX METHOD
-0.01

10
GAIN ERROR (%FS)

-0.02
COUNT (UNITS)

8
-0.03
6 MAX5214

-0.04
4

2 -0.05
MAX5216
0 -0.06
0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
DRIFT (µV/°C) SUPPLY VOLTAGE (V)

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MAX5214/MAX5216 14-/16-Bit, Low-Power, Buffered Output,
Rail-to-Rail DACs with SPI Interface

Typical Operating Characteristics (continued)

(TA = +25°C, unless otherwise noted.)

GAIN ERROR DRIFT

GAIN ERROR vs. TEMPERATURE vs. TEMPERATURE DISTRIBUTION
0 14

MAX5214 toc15

MAX5214 toc16
VREF = 2.5V -40°C TO +105°C
12 BOX METHOD
-0.01

10
GAIN ERROR (%FS)

-0.02

COUNT (UNITS)
8
-0.03
MAX5214 6
-0.04
4

-0.05 2
MAX5216
-0.06 0
-40 -20 0 20 40 60 80 100 0 0.10 0.20 0.30 0.40 0.50
TEMPERATURE (°C) DRIFT (ppmFS/°C)

FULL-SCALE OUTPUT FULL-SCALE OUTPUT

vs. SUPPLY VOLTAGE vs. TEMPERATURE
2.500 2.500
MAX5214 toc17

MAX5214 toc18
2.498 2.498
MAX5216 MAX5214 MAX5216 MAX5214
OUTPUT VOLTAGE (V)

OUTPUT VOLTAGE (V)

2.496 2.496

2.494 2.494

2.492 2.492

VREF = 2.5V VREF = 2.5V

2.490 2.490
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 -40 -20 0 20 40 60 80 100
SUPPLY VOLTAGE (V) TEMPERATURE (°C)

SUPPLY CURRENT vs. TEMPERATURE SUPPLY CURRENT vs. TEMPERATURE

80 80
MAX5214 toc19b
MAX5214 toc19a

78 75
76 VDD = 5V VDD = 5.25V
70 VDD = 5.25V
SUPPLY CURRENT (µA)
SUPPLY CURRENT (µA)

74 VDD = 5V
65 VDD = 4V
72
70 60
68 55
VDD = 2.7V VDD = 4V
66 MAX5214/MAX5216
MAX5214/MAX5216 50
64 NO LOAD
NO LOAD VDD = 2.7V
VDD = VREF 45 VDD = VREF
62
VOUT = MIDSCALE VOUT = ZEROSCALE
60 40
-40 -20 0 20 40 60 80 100 -40 -20 0 20 40 60 80 100
TEMPERATURE (°C) TEMPERATURE (°C)

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MAX5214/MAX5216 14-/16-Bit, Low-Power, Buffered Output,
Rail-to-Rail DACs with SPI Interface

Typical Operating Characteristics (continued)

(TA = +25°C, unless otherwise noted.)

SUPPLY CURRENT SUPPLY CURRENT

vs. SUPPLY VOLTAGE vs. SUPPLY VOLTAGE
80 80

MAX5214 toc20a

MAX5214 toc20b
NO LOAD NO LOAD
78
VDD = VREF 75 VDD = VREF
76 VOUT = MIDSCALE VOUT = ZERO SCALE
70

SUPPLY CURRENT (µA)

SUPPLY CURRENT (µA)

74
MAX5216 65
72
MAX5214
70 60
68
MAX5214 55
66
50 MAX5216
64
62 45

60 40
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V)

SUPPLY CURRENT vs. SUPPLY VOLTAGE

(POWER-DOWN MODE) SUPPLY CURRENT vs. DAC CODE
0.6 80
MAX5214 toc21

MAX5214 toc22a
NO LOAD MAX5214
-40°C
75 VDD = VREF
0.5 0°C
+25°C
SUPPLY CURRENT (µA)

SUPPLY CURRENT (µA)

+85°C 70
0.4
+105°C
65
0.3 VREF = 5.0V VREF = 2.5V
60
0.2
55
0.1
50

0 45
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 0 2500 5000 7500 10,000 12,500 15,000
SUPPLY VOLTAGE (V) CODE

VOUT vs. TIME

SUPPLY CURRENT vs. DAC CODE (EXITING POWER-DOWN MODE)
MAX5214 toc23
80
MAX5214 toc22b

NO LOAD MAX5216 MAX5214/MAX5216

75 VDD = VREF RL = 10kI
VREF = 5V
SUPPLY CURRENT (µA)

70

65 VREF = 5.0V VREF = 2.5V OUT = MIDSCALE

1V/div
60

55 0V

50

45
0 10,000 20,000 30,000 40,000 50,000 60,000 10µs/div
CODE

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MAX5214/MAX5216 14-/16-Bit, Low-Power, Buffered Output,
Rail-to-Rail DACs with SPI Interface

Typical Operating Characteristics (continued)

(TA = +25°C, unless otherwise noted.)

MAJOR CODE TRANSITION MAJOR CODE TRANSITION

(0x8000 TO 0x7FFF) (0x7FFF TO 0x8000)
MAX5214 toc24a MAX5214 toc24b

MAX5216 MAX5216
VDD = 5V VDD = 5V
NO LOAD REF = 5V
REF = 5V NO LOAD

OUT = MIDSCALE
OUT = MIDSCALE AC-COUPLED
AC-COUPLED
1mV/div
1mV/div

4µs/div 4µs/div

MAJOR CODE TRANSITION MAJOR CODE TRANSITION

(0x2000 TO 0x1FFF) (0x1FFF TO 0x2000)
MAX5214 toc24c MAX5214 toc24d

MAX5214 MAX5214
VDD = 5V VDD = 5V
REF = 5V REF = 5V
NO LOAD NO LOAD

OUT = MIDSCALE
OUT = MIDSCALE AC-COUPLED
AC-COUPLED 1mV/div
1mV/div

4µs/div 4µs/div

SETTLING TO ±0.5 LSB 14 BIT SETTLING TO ±0.5 LSB 14 BIT

(VDD = VREF = 5V, CL = 100pF) (VDD = VREF = 5V, CL = 100pF)
MAX5214 toc25a MAX5214 toc25b

MAX5214/MAX5216
3/4 SCALE TO 1/4 SCALE

18µs

17µs
MAX5214/MAX5216
1/4 SCALE TO 3/4 SCALE

4µs/div 4µs/div

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MAX5214/MAX5216 14-/16-Bit, Low-Power, Buffered Output,
Rail-to-Rail DACs with SPI Interface

Typical Operating Characteristics (continued)

(TA = +25°C, unless otherwise noted.)

OUTPUT VOLTAGE
DIGITAL FEEDTHROUGH vs. OUTPUT CURRENT
MAX5214 toc26
2.55

MAX5214 toc27
VOUT 2.50
AC-COUPLED
1mV/div

OUTPUT VOLTAGE (V)

2.45

2.40

2.35

2.30 VDD = 5V
VSCLK
5V/div VREF = 5V
2.25
40ns/div 0 1 2 3 4 5 6
OUTPUT CURRENT (mA)

SUPPLY CURRENT REFERENCE INPUT BANDWIDTH

vs. DIGITAL INPUT VOLTAGE vs. FREQUENCY
3500 5
MAX5214 toc28

MAX5214 toc29
3000
DIGITAL SUPPLY CURRENT (µA)

VDD = 5V 0
2500 LOW T0 HIGH
ATTENUATION (dB)

2000 VDDI = 5V -5
HIGH T0 LOW VDDI = 2.7V
1500 LOW T0 HIGH
-10
VDDI = 2.7V
1000 HIGH T0 LOW
-15
500

0 -20
0 1 2 3 4 5 1 10 100 1000
DIGITAL INPUT VOLTAGE (V) INPUT FREQUENCY (kHz)

INTEGRATED OUTPUT NOISE DAC OUPUT NOISE DENSITY

(0.1Hz TO 10Hz) vs. FREQUENCY
MAX5214 toc30
200
MAX5214 toc31

MAX5214/MAX5216
175
FULL-SCALE (CODE 0XFF00)
NOISE (nVRMS /√Hz)

150
ZERO-SCALE (CODE 0x00FF)
OUT
125
1µV/div
MIDSCALE (CODE 0x8000)
100

75

50
1s/div 10 100 1k 10k 100k
FREQUENCY (Hz)

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MAX5214/MAX5216 14-/16-Bit, Low-Power, Buffered Output,
Rail-to-Rail DACs with SPI Interface

Pin Configuration

TOP VIEW

+
REF 1 8 GND

CS 2 7 VDD
MAX5214
SCLK 3 MAX5216 6 OUT

DIN 4 5 CLR

µMAX

Pin Description
PIN NAME FUNCTION
1 REF Reference Voltage Input. Bypass REF with a 0.1µF capacitor to GND.
2 CS Active-Low Chip-Select Input
3 SCLK Serial-Clock Input
4 DIN Data In
Active-Low Asynchronous Digital-Clear Input. Drive CLR low to clear the contents of the input and
5 CLR
DAC registers and set the DAC output to zero.
6 OUT Buffered DAC Voltage Output
7 VDD Supply Voltage. Bypass VDD with a 0.1µF capacitor to GND.
8 GND Ground

Detailed Description Output Amplifier (OUT)

The MAX5214/MAX5216 are pin-compatible and soft- The MAX5214/MAX5216 include an internal buffer on the
ware-compatible 14-bit and 16-bit DACs. The MAX5214/ DAC output. The internal buffer provides improved load
MAX5216 are single-channel, low-power, high-refer- regulation and transition glitch suppression for the DAC
ence input resistance, and buffered voltage-output output. The output buffer slews at 0.5V/Fs and drives
DACs. The MAX5214/MAX5216 minimize the digital up to 10kI in parallel with 100pF. The analog supply
noise feedthrough from their inputs to their outputs by voltage (VDD) determines the maximum output voltage
powering down the SCLK and DIN input buffers after range of the device as VDD powers the output buffer.
completion of each data frame. The data frames are
16-bit for the MAX5214 and 24-bit for the MAX5216. On
DAC Reference (REF)
power-up, the MAX5214/MAX5216 reset the DAC output The external reference input features a typical input
to zero, providing additional safety for applications that impedance of 256kI and accepts an input voltage
drive valves or other transducers which need to be off on from +2V to VDD. Connect an external voltage supply
power-up. The MAX5214/MAX5216 contain a segmented between REF and GND to apply an external reference.
resistor string-type DAC, a serial-in/parallel-out shift reg- Visit www.maximintegrated.com/products/references
ister, a DAC register, power-on-reset (POR) circuit, CLR for a list of available voltage-reference devices.
to asynchronously clear the device independent of the
serial interface, and control logic. On the falling edge
of the clock (SCLK) pulse, the serial input (DIN) data is
shifted into the device, MSB first.

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MAX5214/MAX5216 14-/16-Bit, Low-Power, Buffered Output,
Rail-to-Rail DACs with SPI Interface

Serial Interface transfers its contents to the input registers after loading
The MAX5214/MAX5216 3-wire serial interface is com- 16/24 bits of data and updates the DAC output immedi-
patible with MICROWIRE, SPI, QSPI, and DSP. The ately after the data is received on the 16-/24-bit falling
interface provides three inputs: SCLK, CS, and DIN. The edge of the clock. To initiate a new data transfer, drive
chip-select input (CS) frames the serial data loading at CS high and keep CS high for a minimum of 20ns before
DIN. Following a chip-select input high-to-low transition, the next write sequence. The SCLK can be either high or
the data is shifted synchronously and latched into the low between CS write pulses. Figure 1 and Figure 2 show
input register on each falling edge of the serial-clock the timing diagram for the complete 3-wire serial inter-
input (SCLK). Each serial word is 16-bit for the MAX5214 face transmission. The MAX5216 DAC code is unipolar
and 24-bit for the MAX5216. The first 2 bits are the binary with VOUT = (code/65,535) x VREF. The MAX5214
control bits followed by 14 data bits (MSB first) for the DAC code is unipolar binary with VOUT = (code/16,383)
MAX5214 and 22 data bits (MSB first) for the MAX5216 x VREF. See Table 1 and Table 2.
as shown in Table 1 and Table 2. The serial input register

Table 1. Operating Mode Truth Table (MAX5214)

16-BIT WORD
CONTROL
DATA BITS
BITS FUNCTION
MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 0 X X X X X X X X X X X X X X No operation
Power-down
1 0 0 X A1 A0 X X X X X X X X X X
(see Table 3)
0 1 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Write through
1 1 Reserved, Do Not Use

Table 2. Operating Mode Truth Table (MAX5216)

24-BIT WORD
CONTROL
DATA BITS
BITS
FUNCTION
MSB LSB
D5–
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6
D0
0 0 X X X X X X X X X X X X X X X X X No operation
Power-down
1 0 0 X A1 A0 X X X X X X X X X X X X X
(see Table 3)
0 1 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 X Write through
1 1 Reserved, Do Not Use

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MAX5214/MAX5216 14-/16-Bit, Low-Power, Buffered Output,
Rail-to-Rail DACs with SPI Interface

Writing to the Devices Power-Down Mode

1) Drive CS low, enabling the shift register. The MAX5214/MAX5216 feature a software-controlled
2) Clock 16/24 bits of data into DIN (MSB first and LSB power-down mode. In power-down, the output discon-
last), observing the specified setup and hold times. nects from the buffer and is grounded with one of the
three selectable internal resistors. See Table 3 for the
3) After clocking in the last data bit, drive CS high. CS selectable internal resistor values in power-down mode.
must remain high for 20ns before the next transmis- The selected mode takes effect on the 16th SCLK falling
sion is started. edge of the MAX5214 and 24th SCLK falling edge of the
Figure 1 shows a write operation for the transmission of MAX5216. The serial interface remains active in power-
16 bits. If CS is driven high at any point prior to receiving down mode. In order to abort the power-down mode
16 bits, the transmission is discarded. selection, pull CS high prior to the 16th (MAX5214) or
Figure 2 shows a write operation for the transmission of 24th (MAX5216) SCLK falling edge. The contents of the
24 bits. If CS is driven high at any point prior to receiving DAC register remain valid while in power-down mode,
24 bits, the transmission is discarded. allowing for the DAC to return to previous code by writing
0x8000 for the MAX5214 or 0x800000 for the MAX5216
Clear (CLR) (Table 3). A write to the write-through register causes the
The MAX5214/MAX5216 feature an asynchronous active- device to immediately exit power-down mode and transi-
low CLR logic input that sets the DAC output to zero. tion to the requested code (see Table 1 and Table 2).
Driving CLR low clears the contents of both the input and
DAC registers and also aborts the on-going SPI com-
mand. To allow a new SPI command, drive CLR high.

Table 3. Power-Down Modes

DAC OPERATION
A1 A0 DESCRIPTION
CONDITION
0 0 DAC powers up and returns to its previous code setting. Normal operation
0 1 DAC powers down; OUT is high impedance.
1 0 DAC powers down; OUT connects to ground through an internal 100kI resistor. Power-down
1 1 DAC powers down; OUT connects to ground through an internal 1kI resistor.

Table 4. MAX5216 Input Code vs. Output Voltage

DAC LATCH CONTENTS
ANALOG OUTPUT (VOUT)
MSB g LSB
1111 1111 1111 1111 VREF x (65,535/65,535)
1000 0000 0000 0000 VREF x (32,768/65,535) = 1/2 VREF
0000 0000 0000 0001 VREF x (1/65,535)
0000 0000 0000 0000 0V

Table 5. MAX5214 Input Code vs. Output Voltage

DAC LATCH CONTENTS
ANALOG OUTPUT (VOUT)
MSB g LSB
1111 1111 1111 11XX VREF x (16,383/16,383)
1000 0000 0000 00XX VREF x (8,192/16,383) = 1/2 VREF
0000 0000 0000 01XX VREF x (1/16,383)
0000 0000 0000 00XX 0V

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MAX5214/MAX5216 14-/16-Bit, Low-Power, Buffered Output,
Rail-to-Rail DACs with SPI Interface

Applications Information Offset Error

Power-On Reset (POR) Offset error indicates how well the actual transfer func-
tion matches the ideal transfer function at a single point.
When first power is applied to VDD, the input registers
are set to zero so the DAC output is set to code zero. Typically, the point at which the offset error is specified
To optimize DAC linearity, wait until the supplies have is at or near the zero-scale point of the transfer function.
settled. The MAX5214/MAX5216 output voltage range is Gain Error
0 to VREF.
Gain error is the difference between the ideal and the
Power Supplies and actual full-scale output voltage on the transfer curve,
Bypassing Considerations after nullifying the offset error. This error alters the slope
Bypass VDD with high-quality 0.1µF ceramic capacitors to a of the transfer function and corresponds to the same
low-impedance ground as close as possible to the device. percentage error in each step.
Minimize lead lengths to reduce lead inductance. Settling Time
Connect the GND to the analog ground plane. The settling time is the amount of time required from
Layout Considerations the start of a transition, until the DAC output settles to
the new output value within the converter’s specified
Digital and AC transient signals on GND can create noise
accuracy.
at the output. Connect GND to the star ground for the
DAC system. Refer the remote DAC loads to this system Digital Feedthrough
ground for the best possible performance. Use proper Digital feedthrough is the amount of noise that appears
grounding techniques, such as a multilayer board with a on the DAC output when the DAC digital control lines
low-inductance ground plane, or star connect all ground are toggled.
return paths back to the MAX5214/MAX5216 GND.
Carefully lay out the traces between channels to reduce Digital-to-Analog Glitch Impulse
AC cross-coupling. Do not use wire-wrapped boards A major carry transition occurs at the midscale point
and sockets. Use shielding to improve noise immunity. where the MSB changes from low to high and all other
Do not run analog and digital signals parallel to one bits change from high to low, or where the MSB changes
another, especially clock signals. Avoid routing digital from high to low and all other bits change from low to
lines underneath the MAX5214/MAX5216 package. high. The duration of the magnitude of the switching
glitch during a major carry transition is referred to as the
Definitions digital-to-analog glitch impulse.
Integral Nonlinearity (INL) Digital-to-Analog Power-Up Glitch Impulse
INL is the deviation of the measured transfer function The digital-to-analog power-up glitch is the duration of
from a straight line drawn between two codes once offset the magnitude of the switching glitch that occurs as the
and gain errors have been nullified. device exits power-down mode.
Differential Nonlinearity (DNL)
DNL is the difference between an actual step height and
the ideal value of 1 LSB. If the magnitude of the DNL is
greater than -1 LSB, the DAC guarantees no missing
codes and is monotonic.

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MAX5214/MAX5216 14-/16-Bit, Low-Power, Buffered Output,
Rail-to-Rail DACs with SPI Interface

Typical Operating Circuit

POWER SUPPLY

IN MAX6029 OUT

100pF 100nF 4.7µF

VDD

OUT
DAC OUTPUT

CLR
µC

CS MAX5214
MAX5216 REF
SCLK

DIN

GND

Chip Information Package Information

PROCESS: BiCMOS For the latest package outline information and land patterns, go
to www.maximintegrated.com/packages. Note that a “+”, “#”,
or “-” in the package code indicates RoHS status only. Package
drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Ordering Information
PACKAGE PACKAGE OUTLINE LAND
PIN- RESOLUTION INL MAX TYPE CODE NO. PATTERN NO.
PART
PACKAGE (BITS) (LSB) 8 FMAX U8+3 21-0036 90-0092
MAX5214GUA+ 8 FMAX 14 ±1
MAX5216GUA+ 8 FMAX 16 ±4
MAX5216BGUA+ 8 FMAX 16 ±8
Note: All devices are specified over the -40°C to +105°C oper-
ating temperature range.
+Denotes a lead(Pb)-free/RoHS-compliant package.

www.maximintegrated.com Maxim Integrated │  16

MAX5214/MAX5216 14-/16-Bit, Low-Power, Buffered Output,
Rail-to-Rail DACs with SPI Interface

Revision History
REVISION REVISION PAGES
DESCRIPTION
NUMBER DATE CHANGED
0 12/10 Initial release —
Added an additional electrical grade for MAX5216. Made multiple text edits and
1 6/13 1–17
updated the Typical Operating Characteristics.
2 7/13 Updated General Description, Features, and the Electrical Characteristics. 1, 3

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

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