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Format of Lab Report

This document describes Experiment 1 which aimed to design and simulate a CMOS inverter using the SymicaDE tool. It provides the circuit diagram and truth table of the CMOS inverter. The experiment details the schematic design using 130nm PTM technology and specifies the device widths and lengths. It then shows the transient result of the inverter output for an input signal pulse between 1.8V and 0V with a 100ns period and 50ns pulse width. The simulated propagation delay is also measured.

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Huzaifa Ahmed
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19 views

Format of Lab Report

This document describes Experiment 1 which aimed to design and simulate a CMOS inverter using the SymicaDE tool. It provides the circuit diagram and truth table of the CMOS inverter. The experiment details the schematic design using 130nm PTM technology and specifies the device widths and lengths. It then shows the transient result of the inverter output for an input signal pulse between 1.8V and 0V with a 100ns period and 50ns pulse width. The simulated propagation delay is also measured.

Uploaded by

Huzaifa Ahmed
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Index

Exp Experiment Exp. Sub. Remarks


. Date Date
No.
Date: 24/08/2020

Experiment No. 1
Aim: To design and Simulate CMOS Inverter using SymicaDE Tool .

Tool & Apparatus Used: SymicaDE

Theory:

Fig.1.1 Circuit diagram of CMOS Inverter

Table 1.1 Truth Table of CMOS Inverter

Design and Simulation:

Figure 1.2 Schematic of CMOS Inverter

Table 1.2 Design specifications of CMOS Inverter

Parameters Values
CMOS Technology PTM 130nm
NMOS: W/L 360nm/180nm
PMOS: W/L 720nm/180nm
VDD 1.8V
Input signal (Pulse) V1=1.8V, V2=0, Time
Period=100ns, Pulse Width=50ns
Observation:

Figure 1.3 Transient result of CMOS Inverter output

Simulated propagation delay:

Result:

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