HCC/HCF4067B

HCC/HCF4097B

ANALOG MULTIPLEXER/DEMULTIPLEXER

4067B–SINGLE 16-CHANNEL

.
4097B–DIFFERENTIAL 8-CHANNEL
LOW ON RESISTANCE: 125Ω (typ.) OVER 15
Vp-p SIGNAL INPUT RANGE FOR

. VDD - VSS = 15V

HIGH OFF RESISTANCE: CHANNEL LEAK-

. AGE OF ±10pA (typ.) @ VDD - VSS = 10V

MATCHED SWITCH CHARACTERISTICS:

. ∆RON = 5Ω (typ.) FOR VDD - VSS = 15V

VERY LOW QUIESCENT POWER DISSIPA-
TION UNDER A DIGITAL CONTROL INPUT
EY
(Plastic Package)
F
(Ceramic Package)

AND SUPPLY CONDITIONS: 0.2µW (typ.) @

.. VDD -VSS = 10V

BINARY ADDRESS DECODING ON CHIP
QUIESCENT CURRENT SPECIFIED TO 20V

. FOR HCC DEVICE

STANDARDIZED SYMMETRICAL OUTPUT

.. CHARACTERISTICS
5V, 10V AND 15V PARAMETRIC RATINGS
INPUT CURRENT OF 100nA AT 18V AND 25 C
o
M1
(Micro Package)
C1
(Chip Carrier)

.. FOR HCC DEVICE

100% TESTED FOR QUIESCENT CURRENT
MEETS ALL REQUIREMENTS OF JEDEC TEN-
ORDER CODES :
HCC40XXBF
HCF40XXBEY
HCF40XXBM1
HCF40XXBC1
TATIVE STANDARD No 13A, ”STANDARD
SPECIFICATIONS FOR DESCRIPTION OF B
SERIE CMOS DEVICES”

PIN CONNECTIONS

4067B 4097B

September 1988 1/16

HCC/HCF4067B HCC/HCF4097B

DESCRIPTION
The HCC4067B, HCC4097B (extended tempera- address decoding. in addition, the ON resistance is
ture range) and HCF4067B, HCF4097B (intermedi- relatively constant over the full input-signal range.
ate temperature range) are monolithic integrated The HCC/HCF4067B ia a 16-channel multiplexer
circuits available in 24-lead dual in line plastic or ce- with four binary control inputs A, B, C, D, and an in-
ramic package. hibit input, arranged so that any combination of the
The HCC/HCF4067B and HCC/HCF4097B inputs selects one switch.
COS/MOS analog multiplexers/demultiplexers are The HCC/HCF4097 is a differential 8-channel multi-
digitally controlled analog switches having low ON plexer having three binary control inputs A, B, C, and
impedance, low OFF leakage current and internal an inhibit input. The inputs permit selection of one

FUNCTIONAL DIAGRAM

For 4067B For 4097B

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 HCC/HCF4067B HCC/HCF4097B

LOGIC DIAGRAM

For 4067B

3/16
HCC/HCF4067B HCC/HCF4097B

LOGIC DIAGRAM

For 4097B

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 HCC/HCF4067B HCC/HCF4097B

TRUTH TABLES FOR HCC/HCF4067B TRUTH TABLE FOR HCC/HCF4097B

SELECTED SELECTED
A B C D INH A B C INH
CHANNEL CHANNEL
X X X X 1 None X X X 1 None
0 0 0 0 0 0 0 0 0 0 0X 0Y
1 0 0 0 0 1 1 0 0 0 1X 1Y
0 1 0 0 0 2 0 1 0 0 2X 2Y
1 1 0 0 0 3 1 1 0 0 3X 3Y
0 0 1 0 0 4 0 0 1 0 4X 4Y
1 0 1 0 0 5 1 0 1 0 5X 5Y
0 1 1 0 0 6 0 1 1 0 6X 6Y
1 1 1 0 0 7 1 1 1 0 7X 7Y
0 0 0 1 0 8
1 0 0 1 0 9
0 1 0 1 0 10
1 1 0 1 0 11
0 0 1 1 0 12
1 0 1 1 0 13
0 1 1 1 0 14
1 1 1 1 0 15

ABSOLUTE MAXIMUM RATING

Symbol Parameter Value Unit
VDD * Supply Voltage: HCC Types -0.5 to +20 V
HCF Types -0.5 to +18 V
Vi Input Voltage -0.5 to VDD + 0.5 V
II DC Input Current (any one input) ± 10 mA
Ptot Total Power Dissipation (per package) 200 mW
Dissipation per Output Transistor
for Top = Full Package Temperature Range 100 mW
o
Top Operating Temperature: HCC Types -55 to +125 C
o
HCF Types -40 to +85 C
o
Tstg Storage Temperature -65 to +150 C
Stresses above those listed under ”Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress ratingonly and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for external periods may affect device reliability.
* All voltage values are referred to VSS pin voltage.

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Value Unit
VDD Supply Voltage: HCC Types 3 to 18 V
HCF Types 3 to 15 V
VI Input Voltage 0 to VDD V
o
Top Operating Temperature: HCC Types -55 to +125 C
o
HCF Types -40 to +85 C

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HCC/HCF4067B HCC/HCF4097B

STATIC ELECTRICAL CHARACTERISTICS (over recommended operating conditions)

Test Conditios Value
Symbol Parameter VIS VEE VSS VDD TLOW * 25 oC THIGH * Unit
(V) (V) (V) (V) Min. Max. Min. Typ. Max. Min. Max.
IL Quiescent 5 5 0.04 5 150
Supply HCC 10 10 0.04 10 300
Current types 15 20 0.04 20 600
µA
20 100 0.08 100 3000
5 20 0.04 20 150
HCF
types 10 40 0.04 40 300
15 80 0.04 80 600
SWITCH
RON On 5 800 470 1050 1300
HCC 0 ≤ VI
Resistance 0 0 10 310 180 400 580
types ≤ VDD
15 200 125 240 320 Ω
5 850 470 1050 1200
HCF 0 ≤ VI
0 0 10 330 180 400 520
types ≤ VDD
15 210 125 240 300
∆ON Resistance ∆RON 5 10
(Between any two 0 0 10 10 Ω
channels) 15 5
OFF (•)
Any HCC
0 0 18 100 ±0.1 100 1000
Channel
Channel OFF types
Leakage
All Channel
Current
OFF HCC
0 0 18 100 ±0.1 100 1000
(common types
OUT/IN) µA
Any HCF
0 0 15 300 ±0.1 300 1000
Channel OFF types
All Channel
OFF HCF
0 0 15 300 ±0.1 300 1000
(common types
OUT/IN)
C Capacitance
Input 5
Output for 4067 -5 5 55 pF
Output for 4097 35
Feedthrough 0.2
CONTROL
V IL Input Low = VDD V EE=VSS 5 1.5 1.5 1.5
Voltage thru RL =1KΩ 10 3 3 3 V
1KΩ to VSS 15 4 4 4
VIH Input High IIS < 2µA 5 3.5 3.5 3.5
Voltage (on all OFF
10 7 7 7 V
channels)
15 11 11 11
IIH IIL Input HCC
VI = 0/18V 18 ±0.1 ±10-3 ±0.1 ±1
Leackage types
µA
Current HCF
VI = 0/15V 15 ±0.3 ±10-3 ±0.3 ±1
types
CI Input Capacitance Any Address or 5 7.5
pF
Inhibit Input
• Determined by minimum feasible leakage measurement for automatic testing
* TLOW = -55 oC for HCC device: -40 oC for HCF device.
* THIGH = +125 oC for HCC device: +85 oC for HCF device.
The Noise Margin for both ”1” and ”0” level is: 1V min. with VDD = 5 V, 2 V min. with VDD = 10 V, 2.5 V min. with VDD = 15 V

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 HCC/HCF4067B HCC/HCF4097B

DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25 o C, C L = 50 pF, RL = 200 KΩ,

o
typical temperature coefficent for all VDD values is 03 %/ C, all input rise and fall times= 20 ns)
Test Conditions Value
Symbol Parameter VC RL fi VI VSS VDD Unit
Typ. Max.
(V) (KΩ) (KHz) (V) (V) (V)
SWITCH
tpd Propagation Delay 5 30 60
Time (Signal Input to = VDD 200 0 10 15 30 ns
Output)
15 11 20
Frequency Response V O at 4067B 14
Channel ”ON” (Sine Common 4097B 20
Wave Input) at = VDD 1 5 (•) 0 10 OUT/IN ns
VO
20 Log = − 3 dB V O at Any Channel 60
VI

Feedthrough (All V O at 4067B 20

Channels OFF) at Common 4097B 12
VO = VSS 1 5 (•) 0 10 OUT/IN MHz
20 Log = − 40 dB
VI V O at Any Channel 8

Frequency Signal Between Any two (A 1

Crosstalk at and B) Channels
VO(B) VC(A)=VDD Between Measured 10
20Log = −40dB
VI(A) 1 5 (•) 0 10 Sections on MHz
VC(B)=VSS (A and B) common
4097B Measured 18
only on Any
Channel
tW Sine Wave Distortion 5 10 1 2 (•) 0 5 0.3
(fis = 1KHz sine 10 10 1 3 (•) 0 10 0.2 %
wave)
15 10 1 5 (•) 0 15 0.12
CONTROL (address or Inhibit)
tPLH Propagation Delay 0 5 325 650
tPHL Time: Address or 0 10 135 270
1 ns
Inhibit to Signal OUT
0 15 95 190
(Channel Turning ON)

tPLH Propagation Delay 0 5 220 440

tPHL Time: Address or 0 10 90 180
Inhibit to Signal OUT 0.3 0 15 65 130 ns
(Channel Turning
OFF)

Address or Inhibit to 75 mV
10* 0 10
Signal Crosstalk peak
VDD − VSS
(•) Peak to peak voltage symmetrical about
2
(*) Both ends of channel

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HCC/HCF4067B HCC/HCF4097B

Typical ON Resistance vs Input Signal Voltage Typical ON Resistance vs Input Signal Voltage
(All Types) (All Types)

Typical ON Resistance vs Input Signal Voltage Typical ON Resistance vs Input Signal Voltage
(All Types) (All Types)

TEST CIRCUITS
OFF Channel Leakage Current Any Channel OFF

For 4067B For 4097B

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 HCC/HCF4067B HCC/HCF4097B

OFF Channel Leakage Current All Channels OFF

For 4067B For 4097B

Input Voltage Measure < 2 µA an All OFF Channels (e.g. Channel 12)

For 4067B For 4097B

Quiescent Device Current

For 4067B For 4097B

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HCC/HCF4067B HCC/HCF4097B

Turn-on and Turn-off Propagation Delay Address Select Input to Signal Output (e. g. Channel 0)

For 4067B For 4097B

Turn-on and Turn-off Propagation Delay-Inhibit Input to Signal Output (e. g. Channel 1)

For 4067B For 4097B

Channel ON Resistance Measurement Circuit

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 HCC/HCF4067B HCC/HCF4097B

Propagation Delay Waveform Channel Being Propagation Delay Waveform Channel Being
Turned ON (RL = 10 KΩ, CL = 50 pF) Turned OFF (RL = 300 Ω, CL = 50 pF)

APPLICATIONS INFORMATION
In applications where separate power sources are lose 3-4% of its voltage at the moment the channel
used to drive VDD and the signal inputs, the VDD cur- turns ON or OFF. This loss of voltage is essentially
rent capability should exceed VDD/RL (RL = effective independent of the address or inhibit signal trnasi-
external load). This provision avoids permanent cur- tion time, if the transition time is less than 1- 2 µs.
rent flow or clamp action on the VDD supply when When the inhibit signal turns a channel off, there is
power is applied or removed from the no change dumping of VSS. Rather, there is a slight
HCC/HCF4067B or HCC/HCF4097B. rise in the channel voltage level (65 mV typ.) due to
When switching from one address to another, some the capacitance coupling from inhibit input to chan-
of the ON periods of the channels of the multiplexers nel input or output. Address input also couple some
will overlap momentarily, which may be objection- voltage steps onto the channel signal levels.
able in certain applications. Also when a channel is In certain applications, the external load-resistor
turned ON or OFF by an address input, there is a current may include both VDD and signal line com-
momentary conductive path from the channel to ponents. To avoid drawing VDD current when switch
VSS, which will drump some charge from any capa- current flows into the transmission gate inputs, the
citor connected to the input or output of the channel. voltage drop across the bidirectional switch must not
The inhibit input turning on a channel will similarly exceed 0.8 V (calculated from RON values shown in
drump some charge to VSS. ELECTRICAL CHARACTERISTICS CHART). No
The amount of charge dumped is mostly a function VDD current will flow through RL if the switch current
of the signal level above VSS. flows into terminal 1 on the HCC/HCF4067B, termi-
Typically, ay VDD - VSS = 10V, a 100 pF capacitor nals 1 and 17 on the HCC/HCF4097B.
connected to the input or output of the channel will

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HCC/HCF4067B HCC/HCF4097B

Plastic DIP24 (0.25) MECHANICAL DATA

mm inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.

a1 0.63 0.025

b 0.45 0.018

b1 0.23 0.31 0.009 0.012

b2 1.27 0.050

D 32.2 1.268

E 15.2 16.68 0.598 0.657

e 2.54 0.100

e3 27.94 1.100

F 14.1 0.555

I 4.445 0.175

L 3.3 0.130

P043A

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 HCC/HCF4067B HCC/HCF4097B

Ceramic DIP24 MECHANICAL DATA

mm inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
A 32.3 1.272

B 13.05 13.36 0.514 0.526

C 3.9 5.08 0.154 0.200

D 3 0.118
E 0.5 1.78 0.020 0.070
e3 27.94 1.100

F 2.29 2.79 0.090 0.110

G 0.4 0.55 0.016 0.022
I 1.17 1.52 0.046 0.060

L 0.22 0.31 0.009 0.012

M 1.52 2.49 0.060 0.098

N1 4° (min.), 15° (max.)

P 15.4 15.8 0.606 0.622
Q 5.71 0.225

P058C

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HCC/HCF4067B HCC/HCF4097B

SO24 MECHANICAL DATA

mm inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.

A 2.65 0.104

a1 0.10 0.20 0.004 0.007

a2 2.45 0.096

b 0.35 0.49 0.013 0.019

b1 0.23 0.32 0.009 0.012

C 0.50 0.020

c1 45° (typ.)

D 15.20 15.60 0.598 0.614

E 10.00 10.65 0.393 0.420

e 1.27 0.05

e3 13.97 0.55

F 7.40 7.60 0.291 0.299

L 0.50 1.27 0.19 0.050

S 8° (max.)

L
c1
C
a2

b1

b e s
a1

e3 E

24 13
F

1 12

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 HCC/HCF4067B HCC/HCF4097B

PLCC20 MECHANICAL DATA

mm inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.

A 9.78 10.03 0.385 0.395

B 8.89 9.04 0.350 0.356

D 4.2 4.57 0.165 0.180

d1 2.54 0.100

d2 0.56 0.022

E 7.37 8.38 0.290 0.330

e 1.27 0.050

e3 5.08 0.200

F 0.38 0.015

G 0.101 0.004

M 1.27 0.050

M1 1.14 0.045

P027A

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HCC/HCF4067B HCC/HCF4097B

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use ascritical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectonics.

 1994 SGS-THOMSON Microelectronics - All Rights Reserved

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