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Vin

Analog Engineer’s
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Circuit Cookbook: Data Converters

DAC VDAC
Analog Engineer’s Circuit Cookbook:
Data Converters

Second Edition
SLYY138 - 03/2019

Special thanks for technical contribution:

Manuel Chavez
Luis Chioye
Kevin Duke
Aaron Estrada
Paul Frost
Abhijeet Godbole
Reed Kaczmarek
Art Kay
Dale Li
Peggy Liska
Bryan McKay
Garrett Satterfield
Uttama Kumar Satu
Evan Sawyer
Alex Smith
Cynthia Sosa
Collin Wells
 Analog Engineer’s
Circuit Cookbook: Data Converters
(Second Edition)

Message from the editors:

The Analog Engineer’s Circuit Cookbook: Data Converters provides analog-to-digital converter (ADC) and digital-to-analog converter
(DAC) sub-circuit ideas that can be quickly adapted to meet your specific system needs. Each circuit is presented as a “definition-by-
example.” They include step-by-step instructions, like a recipe, with formulas enabling you to adapt the circuit to meet your design
goals. Additionally, all circuits are verified with SPICE simulations and include links to the corresponding TINA-TITM SPICE circuits.

We’ve provided at least one recommended data converter for each circuit, but you can swap it with another device if you’ve found one
that’s a better fit for your design. You can search our large portfolio of data converters at www.ti.com/DC.

Our circuits require a basic understanding of amplifier and data converter concepts. If you’re new to data converter design, we highly
recommend completing our TI Precision Labs (TIPL) training series. TIPL includes courses on introductory topics, such as device
architecture, as well as advanced, application-specific problem-solving, using both theory and practical knowledge. Check out our
curriculum for Amplifiers, Data Converters and more at: www.ti.com/precisionlabs.

We plan to update this e-book with new ADC and DAC circuit building blocks and encourage you to see if your version is the latest at
www.ti.com/circuitcookbooks. If you have feedback on any of our existing circuits or would like to request additional data converter
circuits for the next edition of this e-book, please contact us at [email protected].

We hope you find our collection of data converter circuits helpful in developing your designs!

Additional resources to explore

TI Precision Labs Data Converter Parametric Quick Search

ti.com/precisionlabs • Find your next precision or high-speed ADC, ti.com/ADC-search
• On-demand courses and tutorials ranging from introductory to • Find your next precision or high-speed DAC, ti.com/DAC-search
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• Hands-on labs and evaluation modules (EVM) available DIY Amplifier Circuit Evaluation Module (DIYAMP-EVM)
- TIPL Op Amps experimentation platform, ti.com/TIPL-amp-evm ti.com/DIYAMP-EVM
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and SOIC package options in 12 popular amplifier configurations
Analog Engineer’s Pocket Reference
ti.com/analogrefguide Dual-Channel DIY Amplifier Circuit Evaluation Module
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tables and equations ti.com/dual-diyamp-evm
• e-book, iTunes and Android apps and hardcopy available • Dual-channel circuit evaluation module in an SOIC-8 package with
10 popular amplifier configurations
The Signal e-book
ti.com/signalbook TINA-TI simulation software
• Short, bite-sized lessons on on op-amp design topics, such as offset ti.com/tool/tina-ti
voltage, input bias current, stability, noise and more • Complete SPICE simulator for DC, AC, transient and noise analysis
• Includes schematic entry and post-processor for waveform math
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ti.com/analogwire Analog Engineer’s Calculator
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ti.com/tidesigns TI E2E™ Community
• Ready-to-use reference designs with theory, calculations, ti.com/e2e
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 Table of Contents

Analog-to-digital converter (ADC) Four-wire PT100 RTD measurement circuit with low-side reference ...168
Low-Power/Cost-Optimized Circuits Two-channel, K-type thermocouple measurement circuit with internal
Driving a SAR ADC directly without a front-end buffer circuit (low-power, temperature sensor CJC ......................................................................174
low-sampling-speed DAQ) ..........................................................................5
Input Protection, Filtering and Isolation Circuits
Low-power sensor measurements: 3.3-V, 1-ksps, 12-bit, single-ended,
±12-V voltage sensing circuit with an isolated amplifier and pseudo-
dual-supply circuit ....................................................................................10
differential input SAR ADC ...................................................................181
Low-power sensor measurements: 3.3-V, 1-ksps, 12-bit, single-ended,
±12-V voltage sensing circuit with an isolated amplifier and differential
single-supply circuit ...............................................................................16
input SAR ADC .....................................................................................188
Level Translation Input Drive Circuits Anti-aliasing filter circuit design for single-ended ADC input using fixed
Circuit for driving a high-voltage SAR with an instrumentation amplifier ....23 cutoff frequency ...................................................................................195
Circuit for driving high-voltage SAR ADC with a buffered instrumentation Circuit showing overstress protection on ADC with integrated analog
amplifier .....................................................................................................29 front end ............................................................................................... 204
Circuit for driving high-voltage SAR ADCs for high-voltage, true differential Digitally-isolated ADS8689 circuit design ............................................ 213
signal acquisition ......................................................................................36 Reducing effects of external RC filter circuit on gain and drift error for
Circuit to increase input range on an integrated analog front end (AFE) integrated analog front ends (AFEs): ±10 V .......................................... 217
SAR ADC ...................................................................................................45
Commonly Used Auxiliary Circuits
High common-mode differential input voltage to ±10-V ADC input circuit......50
Isolated power supply, low-noise circuit: 5 V, 100 mA ......................... 223
High-current battery monitor circuit: 0−10 A, 0−10 kHz, 18 bit ...............57
Powering a dual-supply op-amp circuit with one LDO......................... 228
High-input impedance, true differential, analog front end (AFE) attenuator
circuit for SAR ADCs .................................................................................63 Digital-to-analog converter (DAC)
High-voltage battery monitor circuit: ±20 V, 0-10 kHz, 18-bit fully
Audio Outputs
differential .................................................................................................. 71 Active-filtering circuit for audio DAC .................................................... 232

Single-ended to differential signal conversion using an op amp and FDA Auxiliary circuits for high-performance audio .......................................237
for unipolar signals ................................................................................... 78 Current-to-voltage converter circuit for audio DACs ........................... 243
Single-ended-to-differential circuit using an op amp and fully-differential
Auxiliary and Biasing Circuits
amplifier (FDA) for bipolar signals..............................................................85
Circuit for offset adjustment of input signals using precision DAC for
Single-ended to differential using a two op-amp circuit ..........................92 measurement equipment ..................................................................... 248
True differential, 4 × 2 MUX, analog front end, simultaneous-sampling DAC force and sense reference drive circuit ........................................ 252
ADC circuit ...............................................................................................100
Power-supply margining circuit for LDOs using a precision DAC ........ 256
Low-Level Sensor Input Circuits Power-supply margining circuit for SMPS using a precision DAC ....... 261
Circuit for driving a switched-capacitor SAR ADC with a buffered
instrumentation amplifier ......................................................................109 Current Sources
Loop-powered 4- to 20-mA transmitter circuit .................................... 266
Circuit for driving a switched-capacitor SAR ADC with an
instrumentation amplifier ......................................................................117 Programmable low-side current sink circuit ......................................... 270
Circuit for driving an ADC with an instrumentation amplifier in high gain ..124 Programmable, two-stage, high-side current source circuit .................275
Low-input bias-current front end SAR ADC circuit ..............................131 Voltage Sources
High-side current shunt monitor circuit to 3-V single-ended ADC .......136 Circuit for differential output from a single-ended precision DAC ....... 280
Two-wire PT100 RTD measurement circuit with low-side reference ....142 High-current voltage output circuit using a precision DAC .. ................ 286
Three-wire PT100 RTD measurement circuit with high-side reference Progammable voltage output with sense connections circuit ............ 290
and two IDAC current sources .............................................................148
Unipolar negative voltage source from unipolar DAC circuit ............... 295
Three-wire PT100 RTD measurement circuit with low-side reference
Unipolar voltage output DAC to bipolar voltage output circuit ............ 299
and one IDAC current source ...............................................................155
Three-wire PT100 RTD measurement circuit with low-side reference
and two IDAC current sources .............................................................161
 Analog Engineer's Circuit: Data
Converters
SBAA256A – January 2018 – Revised March 2019

Driving a SAR ADC directly without a front-end buffer

circuit (low-power, low-sampling-speed DAQ)

Abhijeet Godbole

Design Description
This design explains how sensor outputs can be directly interfaced with a SAR ADC input. In applications
such as Environmental Sensors, Gas Detectors, and Smoke or Fire Detectors, the input is very slow-
moving and the sensor output voltage is sampled at fairly slower speeds (10ksps or so). In such or similar
systems, the sensor output can be directly interfaced with the SAR ADC input without the need for a driver
amplifier to achieve a small form-factor, low-cost design.
Interfacing Sensor Output Directly to a SAR ADC
The following figure shows a typical application diagram for interfacing a sensor directly to a SAR ADC
input without the use of a driver amplifier. The sensor block highlights the Thevenin equivalent of a sensor
output. Voltage source, VTH, is the Thevenin-equivalent voltage and source resistance RTH is the Thevenin-
equivalent impedance. Most sensor data sheets provide the Thevenin model of the sensor from which the
value of the series impedance can be easily calculated.

VTH
½ LSB

VCSH(t)
SENSOR
V0 SAR ADC
t0 tACQ RSW
RTH SW

+ CSH
VTH
±
CFLT

SBAA256A – January 2018 – Revised March 2019 Driving a SAR ADC directly without a front-end buffer
Submit Documentation Feedback 5 circuit (low-power, low-sampling-speed DAQ)
Copyright © 2018–2019, Texas Instruments Incorporated
 www.ti.com

Specifications

Parameter Calculated Simulated Measured

Transient ADC Input Settling < 0.5LSB 36.24µV N/A
Error < 100.5µV
Step Input Full Scale Range 3.15V 3.15V 3.14978
Input Source Impedance (RTH) 10kΩ 10kΩ 10.01kΩ
Filter Capacitor Value (CFLT) 680pF 680pF N/A
ADC Sampling Speed 10ksps 10ksps 10ksps

Design Note
1. Determine source impedance of input signal. Calculate the RC time constant of the input source
impedance and filter capacitor (known value).
2. Determine the minimum acquisition time required for the input signal to settle for a given source
impedance and the filter capacitor combination.
3. Select COG capacitors to minimize distortion.
4. Use 0.1% 20ppm/°C film resistors or better for good gain drift and to minimize distortion.

Driving a SAR ADC directly without a front-end buffer circuit SBAA256A – January 2018 – Revised March 2019
6 Submit Documentation Feedback
(low-power, low-sampling-speed DAQ)
Copyright © 2018–2019, Texas Instruments Incorporated
www.ti.com

Component Selection for ADC Input Settling

SAR ADCs can be directly interfaced with sensors when the analog input source is capable of driving the
switched capacitor load of a SAR ADC and settling the analog input signal to within ½ of an LSB within
the acquisition time of the SAR ADC. To achieve this, the external RC filter (RTH and CFLT) must settle
within the acquisition time (tACQ) of the ADC. The relationship between the ADC acquisition time and RC
time constant of the external filter is:
tACQ ≥ k · ԎFLT
where
• ԎFLT = RTH · CFLT
• k is the single pole time constant for N bit ADC
The following design example values are given in the table on page 1:
RTH = 10kΩ
CFLT = 680pF
K = 11 (Single pole time constant multiplier for 14-bit ADC) – More information is found on page 96 and
page 97 of the Analog Engineer’s Pocket Reference.
Minimum acquisition time required for proper settling is calculated using this equation:
tACQ ≥ 11 · 10kΩ · 680pF = 74.80µs
For more information on SAR ADCs and front end design for SAR ADCs, refer to Introduction to SAR
ADC Front-End Component Selection.
Transient Input Settling Simulation using TI-TINA
The following figure shows the settling of an ADS7056 ADC given a 3.15-V DC input signal. This type of
simulation shows that the sample and hold kickback circuit is properly selected. Refer to Refine the Rfilt
and Cfilt Values in the TI Precision Labs - ADCs training video series for detailed theory on this subject.

SBAA256A – January 2018 – Revised March 2019 Driving a SAR ADC directly without a front-end buffer
Submit Documentation Feedback 7 circuit (low-power, low-sampling-speed DAQ)
Copyright © 2018–2019, Texas Instruments Incorporated
 www.ti.com

Increasing Acquisition Time of SAR ADC for Input Signal Settling

The acquisition time of a SAR ADC can be increased by reducing the throughput in the following ways:
1. Reducing the SCLK frequency to reduce the throughput.
2. Keeping the SCLK fixed at the highest permissible value and increasing the CS high time.
The following table lists the acquisition time for the previous two cases for the ADS7056 SAR ADC
operating at 10ksps throughput (tcycle = 100µs). Case 2 provides a longer acquisition time for the input
signal to settle because of the increased frequency of the SCLK given a fixed conversion and cycle time.

Acquisition Time
Case SCLK tcycle Conversion Time (18 · tSCLK )
(tcycle – tconv )
1 0.24MHz 100µs 74.988µs 25.01µs
2 60MHz 100µs 0.3µs 99.70µs

The following table shows a performance comparison between an 8-, 10-, 12-, and 14-bit ADC with
respect to sampling speed and effective number of bits (ENOB) when a sensor output with an output
impedance of 10kΩ is directly interfaced with the ADC input. As expected, the ENOB degrades with higher
sampling rates because the acquisition time decreases.

ADS7040 (8-bit ADC) ADS7041 (10-bit ADC) ADS7042 (12-bit ADC)

Sampling ADS7056 (14-bit ADC)
ENOB (RTH = 10kΩ, ENOB (RTH = 10kΩ, ENOB (RTH = 10kΩ,
Speed (ksps) ENOB (RTH = 10kΩ, CFLT = 680pF)
CFLT = 1.5nF) CFLT = 1.5nF) CFLT = 1.5nF)
10 7.93 9.87 10 12.05
100 7.92 9.85 9.97 10.99
500 7.88 9.68 9.95 8.00

Performance Achieved at Different Throughput Rates with Different Source impedance

The following figure provides the ENOB achieved from the ADS7056 at different throughout with different
input impedances. Note that all the results for the following graph were taken with a 100-Hz analog input
signal and without an ADC driver amplifier.
12.5

12

11.5
ENOB (Bits)

11

10.5
33Ohm, 680pF
330Ohm, 680pF
10 3.3kOhm, 680pF
10kOhm, 680pF
20kOhm, 680pF
9.5
2 22 42 62 82 100
Sampling Speed(kSPS) D039

Driving a SAR ADC directly without a front-end buffer circuit SBAA256A – January 2018 – Revised March 2019
8 Submit Documentation Feedback
(low-power, low-sampling-speed DAQ)
Copyright © 2018–2019, Texas Instruments Incorporated
www.ti.com

Design Featured Devices:

Device Key Features Link Similar Devices

8-bit resolution, SPI, 1-Msps sample rate, single-
ADS7040 www.ti.com/product/ADS7040 www.ti.com/adcs
ended input, AVDD/Vref input range 1.6V to 3.6V.
10-bit resolution, SPI, 1Msps sample rate, single-
ADS7041 www.ti.com/product/ADS7041 www.ti.com/adcs
ended input, AVDD/Vref input range 1.6V to 3.6V.
12-bit resolution, SPI, 1-Msps sample rate, single-
ADS7042 www.ti.com/product/ADS7042 www.ti.com/adcs
ended input, AVDD/Vref input range 1.6V to 3.6V.
14-bit resolution, SPI, 2.5-Msps sample rate, single-
ADS7056 www.ti.com/product/ADS7056 www.ti.com/adcs
ended input, AVDD/Vref input range 1.6V to 3.6V.

NOTE: The ADS7042 and ADS7056 use the AVDD as the reference input. A high-PSRR LDO, such
as the TPS7A47, should be used as the power supply.

Design References
See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.
Link to Key file
Source files for interfacing sensor output directly with SAR ADCs – http://www.ti.com/lit/zip/sbac178.

Revision History
Revision Date Change
A March 2019 Downstyle the title and changed title role to 'Data Converters.
Added link to circuit cookbook landing page.

SBAA256A – January 2018 – Revised March 2019 Driving a SAR ADC directly without a front-end buffer
Submit Documentation Feedback 9 circuit (low-power, low-sampling-speed DAQ)
Copyright © 2018–2019, Texas Instruments Incorporated
 Analog Engineer's Circuit: Data
Converters
SBAA251A – November 2017 – Revised March 2019

Low-power sensor measurements: 3.3-V, 1-ksps, 12-bit,

single-ended, dual-supply circuit

Reed Kaczmarek

Input ADC Input Digital Output ADS7042

VinMin = 0V AIN_P = 0V, AIN_M = 0V 000H or 010
VinMax = 3.3V AIN_P = 3.3V, AIN_M = 0V FFFH or 409610

Power Supplies
AVDD Vee Vdd
3.3V –0.3V 4.5V

Design Description
This design shows an low-power amplifier being used to drive a SAR ADC that consumes only nW of
power during operation. This design is intended for systems collecting sensor data and require a low-
power signal chain which only burns single-digit µW of power. PIR sensors, gas sensors, and glucose
monitors are a few examples of power-sensitive systems that benefit from this SAR ADC design. The
values in the component selection section can be adjusted to allow for different data throughput rates and
different bandwidth amplifiers. Low-Power Sensor Measurements: 3.3 V, 1 ksps, 12-bit Single-Ended,
Single Supply shows a simplified version of this circuit where the negative supply is grounded. The –0.3-V
negative supply in this example is used to achieve the best possible linear input signal range. See SAR
ADC Power Scaling for a detailed description of trade-offs in low-power SAR design.

AVDD 3.3V
Vdd 4.5V

0.1 F
0.1 F
Rfilt
-+ 200kŸ AVDD
LPV811 AinP

+ Cfilt ADS7042
+

AinM
510pF
VSENSOR Vee -0.3V

Copyright © 2017, Texas Instruments Incorporated

SBAA251A – November 2017 – Revised March 2019 Low-power sensor measurements: 3.3-V, 1-ksps,
Submit Documentation Feedback 10 12-bit, single-ended, dual-supply circuit
Copyright © 2017–2019, Texas Instruments Incorporated
 www.ti.com

Specifications

Specification Calculated Simulated Measured

Transient ADC Input Settling (1ksps) < 0.5 × LSB = 402µV 41.6µV N/A
AVDD Supply Current (1ksps) 230nA N/A 214.8nA
AVDD Supply Power (1ksps) 759nW N/A 709nW
VDD OPAMP Supply Current 450nA N/A 431.6nA
VDD OPAMP Supply Power 2.025µW N/A 1.942µW
AVDD + VDD System Power (1ksps) 2.784µW N/A 2.651µW

Design Notes
1. Determine the linear range of the op amp based on common mode, output swing, and linear open loop
gain specification. This is covered in the component selection section.
2. Select a COG (NPO) capacitor for Cfilt to minimize distortion.
3. The TI Precision Labs – ADCs training video series covers methods for selecting the charge bucket
circuit Rfilt and Cfilt (see Introduction to SAR ADC Front-End Component Selection). These component
values are dependent on the amplifier bandwidth, data converter sampling rate, and data converter
design. The values shown here will give good settling and AC performance for the amplifier and data
converter in this example. If you modify the design you will need to select a different RC filter.

Low-power sensor measurements: 3.3-V, 1-ksps, SBAA251A – November 2017 – Revised March 2019
12-bit, single-ended, dual-supply circuit 11 Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com

Component Selection
1. Select a low-power op amp:
• Supply current < 0.5µA
• Gain bandwidth product > 5kHz (5 times the sampling rate)
• Unity gain stable
• LPV811 – 450-nA supply current, 8-kHz gain bandwidth product, unity gain stable
2. Find op amp maximum and minimum output for linear operation:

3. Typical power calculations (at 1ksps) with expected values. See SAR ADC Power Scaling for a
detailed description of trade-offs in low-power SAR design:

4. Typical power calculations (at 1ksps) with measured values:

5. Find Rfilt and Cfilt to allow for settling at 1ksps. Refer to Refine the Rfilt and Cfilt Values (a Precision
Labs video) for the algorithm to select Rfilt and Cfilt. The final value of 200kΩ and 510pF proved to
settle to well below ½ of a least significant bit (LSB).

SBAA251A – November 2017 – Revised March 2019 Low-power sensor measurements: 3.3-V, 1-ksps,
Submit Documentation Feedback 12 12-bit, single-ended, dual-supply circuit
Copyright © 2017–2019, Texas Instruments Incorporated
 www.ti.com

DC Transfer Characteristics
The following graph shows a linear output response for inputs from 0 to 3.3V. The full-scale range (FSR)
of the ADC falls within the linear range of the op amp. Refer to Determining a SAR ADC’s Linear Range
when using Operational Amplifiers for detailed theory on this subject.

5.0
Op Amp Output (V)

4.0

3.0
Vin=3.3V
2.0 Vout=3.3V
Vin=0V
1.0 Vout=55uV

0.0

-1.0
-1.0 0.0 1.0 2.0 3.0 4.0 5.0
Op Amp Input VSENSOR (V)
AC Transfer Characteristics
The bandwidth simulation includes the effects of the amplifier output impedance and the RC charge
bucket circuit (Rfilt and Cfilt).The bandwidth of the RC circuit is shown in the following equation to be
1.56kHz. The simulated bandwidth of 2kHz includes effects from the output impedance interacting with the
impedance of the load. See TI Precision Labs - Op Amps: Bandwidth 1 for more details on this subject.

T 0.00

fc = 2kHz
Gain (dB)

-24.60

-49.21
0.00
Phase [deg]

-207.14

-413.84
10 100 1k 10k 100k
Frequency (Hz)

Low-power sensor measurements: 3.3-V, 1-ksps, SBAA251A – November 2017 – Revised March 2019
12-bit, single-ended, dual-supply circuit 13 Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com

Transient ADC Input Settling Simulation

The following simulation shows settling to a 3-V DC input signal. This type of simulation shows that the
sample and hold kickback circuit is properly selected to within ½ of an LSB (402µV). Refer to Introduction
to SAR ADC Front-End Component Selection for detailed theory on this subject.

T 1.00

Vacq

0.00
0.00

Verror
Verror 41.6µV

-10.00m
2.00m 2.55m 3.10m
Time (s)

Noise Simulation
This section walks through a simplified noise calculation for a rough estimate. We neglect resistor noise in
this calculation as it is attenuated for frequencies greater than 10kHz.

Note that the calculated and simulated values match well. Refer to Calculating the Total Noise for ADC
Systems for detailed theory on this subject.

T 16.84u

Vn = 16.84uV rms
Total noise (V)

8.42u

0.00
1 10 100 1k 10k 100k 1MEG 10MEG
Frequency (Hz)

SBAA251A – November 2017 – Revised March 2019 Low-power sensor measurements: 3.3-V, 1-ksps,
Submit Documentation Feedback 14 12-bit, single-ended, dual-supply circuit
Copyright © 2017–2019, Texas Instruments Incorporated
 www.ti.com

Measure FFT
This performance was measured on a modified version of the ADS7042EVM with a 10-Hz input sine
wave. The AC performance indicates SNR = 71.0dB, THD = –82.4dB, and ENOB (effective number of
bits) = 11.51, which matches well with the specified performance of the ADC, SNR = 70dB and THD =
–80dB. This test was performed at room temperature. See Introduction to Frequency Domain for more
details on this subject.

Measured FFT and AC Performance for ADS7042 and LPV811 Dual Supply

Fundamental at 2kHz SNR = 71.0 dB

THD = -82.4 dB
ENOB = 11.51
Signal Power = -0.05 dBFS

Design Featured Devices

Device Key Features Link Similar Devices

ADS7042 (1) 12-bit resolution, SPI, 1-Msps sample rate, single-ended input, www.ti.com/product/ADS7042 www.ti.com/adcs
AVDD reference input range 1.6 V to 3.6 V.
LPV811 (2) 8-kHz bandwidth, rail-to-rail output, 450-nA supply current, unity www.ti.com/product/LPV811 www.ti.com/opamp
gain stable
(1)
The ADS7042 uses the AVDD as the reference input. A high-PSRR LDO, such as the TPS7A47, should be used as the power
supply.
(2)
The LPV811 is also commonly used in low-speed applications for sensors. Furthermore, the rail-to-rail output allows for linear
swing across the entire ADC input range.

Design References
See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.
Link to Key Files (TINA)
Design files for this circuit – http://www.ti.com/lit/zip/sbam342.

Revision History
Revision Date Change
A March 2019 Downstyle the title and changed title role to 'Data Converters'.
Added link to circuit cookbook landing page.

Low-power sensor measurements: 3.3-V, 1-ksps, SBAA251A – November 2017 – Revised March 2019
12-bit, single-ended, dual-supply circuit 15 Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
 Analog Engineer's Circuit: Data
Converters
SBAA253A – February 2018 – Revised March 2019

Low-power sensor measurements: 3.3-V, 1-ksps, 12-bit,

single-ended, single-supply circuit

Reed Kaczmarek

Input ADC Input Digital Output ADS7042

VinMin = 0 V AIN_P = 0V, AIN_M = 0V 000H or 010
VinMax = 3.3V AIN_P = 3.3V, AIN_M = 0V FFFH or 409610

Power Supplies
AVDD Vee Vdd
3.3V 0V 4.5V

Design Description
This design shows an ultra-low power amplifier being used to drive a SAR ADC that consumes only
nanoWatts of power during operation. This design is intended for collecting sensor data by providing
overall system-level power consumption on the order of single-digit microWatts. PIR sensors, gas sensors,
and glucose monitors are a few examples of possible implementations of this SAR ADC design. The
values in the component selection section can be adjusted to allow for different data throughput rates and
different bandwidth amplifiers. Low-Power Sensor Measurements: 3.3V, 1ksps, 12-bit Single-Ended, Dual
Supply shows a more sophisticated version of this circuit where the negative supply is connected to a
small negative voltage (–0.3V). The single-supply version has degraded performance when the amplifier
output is near zero volts. However, in most cases the single-supply configuration is preferred for its
simplicity.
AVDD 3.3V
Vdd 4.5V

0.1uF
0.1uF
-+ 200kOhm AVDD
LPV811 AinP

+ ADS7042
+

510pF AinM
VSENSOR

Copyright © 2018, Texas Instruments Incorporated

SBAA253A – February 2018 – Revised March 2019 Low-power sensor measurements: 3.3-V, 1-ksps,
Submit Documentation Feedback 16 12-bit, single-ended, single-supply circuit
Copyright © 2018–2019, Texas Instruments Incorporated
 www.ti.com

Specifications

Specification Calculated Simulated Measured

Transient ADC Input Settling < 0.5·LSB = 402µV 41.6µV N/A
(1ksps)
AVDD Supply Current (1ksps) 230nA N/A 214.8nA
AVDD Supply Power (1ksps) 759nW N/A 709nW
VDD OPAMP Supply Current 450nA N/A 431.6nA
VDD OPAMP Supply Power 2.025µW N/A 1.942µW
AVDD + VDD System Power 2.784µW N/A 2.651µW
(1ksps)

Design Notes
1. Determine the linear range of the op amp based on common mode, output swing, and linear open loop
gain specification. This is covered in the component selection section.
2. Select COG capacitors to minimize distortion.
3. Use 0.1% 20ppm/°C film resistors or better to minimize distortion.
4. The TI Precision Labs – ADCs training video series covers methods for selecting the charge bucket
circuit Rfilt and Cfilt. These component values are dependent on the amplifier bandwidth, data
converter sampling rate, and data converter design. The values shown here will give good settling and
AC performance for the amplifier and data converter in this example. If you modify this design you will
need to select a different RC filter. Refer to the Introduction to SAR ADC Front-End Component
Selection training video for an explanation of how to select the RC filter for best settling and AC
performance.

Low-power sensor measurements: 3.3-V, 1-ksps, SBAA253A – February 2018 – Revised March 2019
12-bit, single-ended, single-supply circuit 17 Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
www.ti.com

Component Selection
1. Select a low-power operational amp:
• Supply current < 0.5µA
• Gain bandwidth product > 5kHz (5 times the sampling rate)
• Unity gain stable
• For this cookbook, the LPV811 was selected. It has a 450-nA supply current, 8-kHz gain
bandwidth product, and is unity gain stable.
2. Find op amp maximum and minimum output for linear operation

NOTE: The linear range of the LPV811 is 300mV above ground. This means to design a
system to guarantee a full linear range from 0V to 3.3V (full-scale range (FSR) of
ADS7042), then a negative supply is required. This design shows that full-
measured SNR and THD specifications of the ADS7042 are met without using a
negative supply voltage. This testing was only at room temperature and for a more
robust system; Low-Power Sensor Measurements: 3.3V, 1ksps, 12-bit Single-
Ended, Dual Supply shows this design using a negative supply instead of ground.
3. Typical power calculations (at 1ksps) with expected values:

4. Typical power calculations (at 1ksps) with measured values:

5. Find Rfilt and Cfilt to allow for settling at 1ksps. Refine the Rfilt and Cfilt Values (a Precision Labs
video) showing the algorithm for selecting Rfilt and Cfilt. The final value of 200kΩ and 510pF proved to
settle to well below ½ of a least significant bit (LSB).

SBAA253A – February 2018 – Revised March 2019 Low-power sensor measurements: 3.3-V, 1-ksps,
Submit Documentation Feedback 18 12-bit, single-ended, single-supply circuit
Copyright © 2018–2019, Texas Instruments Incorporated
 www.ti.com

DC Transfer Characteristics
The following graph shows a linear output response for inputs from 0 to 3.3V. The FSR of the ADC
falls within the linear range of the op amp.

T 5.00

4.00

3.00
Vin = 0V
Voltage (V)

Vout = 55µV Vin = 3.3V

2.00 Vout = 3.3V

1.00

0.00

-1.00
-1.00 0.00 1.00 2.00 3.00 4.00 5.00
Input voltage (V)

AC Transfer Characteristics
The bandwidth is simulated to be 7.02kHz at the gain of 0dB which is a linear gain of 1. This bandwidth
will allow for settling at 1ksps.

T 0.00

fc = 2kHz
Gain (dB)

-24.60

-49.21
0.00
Phase [deg]

-207.14

-413.84
10 100 1k 10k 100k
Frequency (Hz)

Low-power sensor measurements: 3.3-V, 1-ksps, SBAA253A – February 2018 – Revised March 2019
12-bit, single-ended, single-supply circuit 19 Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
www.ti.com

Transient ADC Input Settling Simulation

The following simulation shows settling to a 3-V DC input signal. This type of simulation shows that the
sample and hold kickback circuit is properly selected to within ½ of a LSB (402µV). Refer to
Introduction to SAR ADC Front-End Component Selection for detailed theory on this subject.

T 1.00

Vacq

0.00
0.00

Verror
Verror 41.6µV

-10.00m
2.00m 2.55m 3.10m
Time (s)

Noise Simulation
This section details a simplified noise calculation for a rough estimate. We neglect resistor noise in this
calculation as it is attenuated for frequencies greater than 10kHz.

Note that calculated and simulated match well. Refer to Calculating the Total Noise for ADC Systems for
detailed theory on this subject.
T 16.84u

Vn = 16.84uV rms
Total noise (V)

8.42u

0.00
1 10 100 1k 10k 100k 1MEG 10MEG
Frequency (Hz)

SBAA253A – February 2018 – Revised March 2019 Low-power sensor measurements: 3.3-V, 1-ksps,
Submit Documentation Feedback 20 12-bit, single-ended, single-supply circuit
Copyright © 2018–2019, Texas Instruments Incorporated
 www.ti.com

Measure FFT
This performance was measured on a modified version of the ADS7042EVM-PDK. The AC performance
indicates SNR = 70.8dB, THD = –82.7dB, and ENOB (effective number of bits) = 11.43, which matches
well with the specified performance of the ADC of SNR = 70dB.

Measured FFT and AC Performance for ADS7042 and LPV811 Single Supply

Fundamental at 2kHz SNR = 70.8 dB

THD = -82.7 dB
ENOB = 11.43
Signal Power = -0.05 dBFS

Low-power sensor measurements: 3.3-V, 1-ksps, SBAA253A – February 2018 – Revised March 2019
12-bit, single-ended, single-supply circuit 21 Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
www.ti.com

Design Featured Devices

Device Key Features Link Similar Devices

ADS7042 (1) 12-bit resolution, SPI, 1-Msps sample rate, single-ended input, AVDD, www.ti.com/product/ADS7042 www.ti.com/adcs
Vref input range 1.6 V to 3.6 V.
LPV811 (2) 8 kHz bandwidth, Rail-to-Rail output, 450 nA supply current, unity www.ti.com/product/LPV811 www.ti.com/opamp
gain stable

(1)
The ADS7042 uses the AVDD as the reference input. A high-PSRR LDO, such as the TPS7A47, should be used as the power supply.
(2)
The LPV811 is also commonly used in low speed applications for sensors. Furthermore, the rail-to-rail output allows for linear swing
across all of the ADC input range.

Design References
See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.
Link to Key Files
Tina files for low-power sensor measurements - http://www.ti.com/lit/zip/sbam341.

Revision History
Revision Date Change
A March 2019 Downstyle the title and changed title role to 'Data Converters'.
Added link to circuit cookbook landing page.

SBAA253A – February 2018 – Revised March 2019 Low-power sensor measurements: 3.3-V, 1-ksps,
Submit Documentation Feedback 22 12-bit, single-ended, single-supply circuit
Copyright © 2018–2019, Texas Instruments Incorporated
 Analog Engineer's Circuit: Data
Converters
SBAA316 – October 2018

Circuit for driving a high-voltage SAR with an

instrumentation amplifier

Dale Li

Input ADC Input Digital Output ADS7042

–10V –10V 8000H
+10V +10V 7FFFH

Power Supplies
AVDD DVDD Vref Vcc Vee
5.0V 3.0V 5.0V +15V –15V

Design Description
Instrumentation amplifiers are optimized for low noise, low offset, low drift, high CMRR and high accuracy.
The INA828 instrumentation amplifier preforms a differential to single-ended conversion for a ±10-V range.
The INA828 has excellent DC performance (that is, offset, drift), as well as good bandwidth. The ADS8568
is ideally suited to work with the INA828 as the ADC can be configured for a ±10-V single-ended input. To
achieve the best settling, limit the sampling rate to 200kSPS or lower. For higher sampling rates see
Driving High-Voltage SAR ADC with a Buffered Instrumentation Amplifier. Also, this design example uses
unity gain (G=1) to translate a ±10-V differential input signal to a ±10-V single-ended output. For smaller
input signals or higher gains, see Circuit for Driving an ADC with an Instrumentation Amplifier in High
Gain. This circuit implementation is applicable to Industrial Transportation and Analog Input Modules that
require precision signal-processing and data-conversion.
+15V
C2 100n

±10V +15V -15V 5V 3.3V

+
Rg+ HVDD HVSS AVDD DVDD
Rg Rflt 715
±10V open Ref
CH_xx
U1 Data Bus
Rg
- INA828
Cflt ADS8568
+

Vdif/ Vdif/ 370p Control Bus

2 2 C1 100n
AGND

Vcm -15V

SBAA316 – October 2018 Circuit for driving a high-voltage SAR

Submit Documentation Feedback 23 with an instrumentation amplifier
Copyright © 2018, Texas Instruments Incorporated
 www.ti.com

Specifications

Specification Goal Calculated Simulated

Transient Settling Error < 1/2 LSB (±152µV) NA –105µV
Noise < 20µV 103µV 86.6µV

Design Notes
1. The bandwidth of instrumentation amplifiers is typically not enough to drive SAR data converters at
higher data rate. In this example, the sampling rate is reduced from 510kSPS to 200kSPS to achieve
good settling. For full sampling rate see Driving High-Voltage SAR ADC with a Buffered
Instrumentation Amplifier.
2. Check the common mode and output range of the instrumentation amplifier using the Common-Mode
Input Range Calculator for Instrumentation Amplifiers software tool.
3. Use a COG type capacitor for Cfilt to minimize distortion.
4. The Precision Labs video series covers methods for selecting the charge bucket circuit Cflt and Rflt. See
the Introduction to SAR ADC Front-End Component Selection for details on this subject.

Circuit for driving a high-voltage SAR SBAA316 – October 2018

with an instrumentation amplifier 24 Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
www.ti.com

Component Selection
1. The ADS8568 can accept a ±10-V single-ended input signal. The INA828 is used to translate a ±10-V
differential signal to a ±10-V single-ended signal. So the INA828 is in unity gain for this example, and
no external gain set resistor Rg is needed. See Circuit for Driving an ADC with an Instrumentation
Amplifier in High Gain in cases where the input signal range is small and gain is required.
2. The INA826 reference voltage (Vref) input is used to shift asymmetrical input ranges to match the input
range of the ADC. In this case the input range is symmetrical so the Vref pin is grounded (Vref = 0V).
See Circuit for Driving an ADC with an Instrumentation Amplifier in High Gain for an example where
the Vref pin is used to adjust asymmetrical input signals.
3. Use the Common-Mode Input Range Calculator for Instrumentation Amplifiers to determine if the
INA828 is violating the common-mode range. The common-mode calculator in the following figure
indicates that the output swing is ±14.9V for a 0-V common mode input.

4. Find the value for Cfilt, and Rfilt using TINA SPICE and the methods described in Introduction to SAR
ADC Front-End Component Selection. The value of Rfilt and Cfilt shown in this document will work for
these circuits; however, if you use different amplifiers you will have to use TINA SPICE to find new
values.

SBAA316 – October 2018 Circuit for driving a high-voltage SAR

Submit Documentation Feedback 25 with an instrumentation amplifier
Copyright © 2018, Texas Instruments Incorporated
 www.ti.com

DC Transfer Characteristics
The following graph shows a linear output response for inputs from differential –14.9V to +14.9V. The
input range of the ADC is ±10V, so the amplifiers are linear well beyond the required range. See
Determining a SAR ADC’s Linear Range when using Instrumentation Amplifiers for detailed theory on
this subject. The full-scale range (FSR) of the ADC falls within the linear range of the instrumentation
amplifier.
18
15 (10V, 10V)
12
9 14.9V
6
Output

3
0
-3
-6
-9 -14.9V
-12 (-10V, -10V)
-15
-18
-18 -15 -12 -9 -6 -3 0 3 6 9 12 15 18
Input voltage (V)
AC Transfer Characteristics
The bandwidth for this circuit is simulated to be 446.75kHz and the gain is 0dB.
10
0
-10
-20 fC_ADC_IN = 1.08MHz
-30
Gain (dB)

-40 fC_INA = 1.7MHz

-50
-60
-70
-80
-90
-100
-110
1k 10k 100k 1MEG 10MEG
Frequency (Hz)

Circuit for driving a high-voltage SAR SBAA316 – October 2018

26 Submit Documentation Feedback
with an instrumentation amplifier
Copyright © 2018, Texas Instruments Incorporated
www.ti.com

Transient ADC Input Settling Simulation (200kSPS)

The following simulation shows settling to a 10-V DC input signal with INA828 and ADS8568. This type of
simulation shows that the sample and hold kickback circuit is properly selected to within ½ of a LSB
(152µV) at 200kSPS sampling rate on ADS8568. See the ADC Front End Component Selection video
series for detailed theory on this subject.

305.0u
Verror 152.5u
0.0
Error = -105…V
-152.5u
-305.0u
10.04
Vout

9.86
1.00
tacq

0.00
5.00u 7.50u 10.00u
Time (s)
Noise
This section shows a simplified noise calculation for a rough estimate. The bandwidth estimate was taken
from the TINA simulation, and the noise density values are from the INA828 50-μV Offset, 7-nV/√Hz
Noise, Low-Power, Precision Instrumentation Amplifier data sheet. The Kn factor of 1.22 is used because
the filter is second order (the INA and output filter both have a pole).
2
§ eno ·
En ADC Gain ˜ eni 2 ¨ Gain ¸ ˜ K n ˜ fc
© ¹
2
2 § 90 nV Hz ·
En ADC 1˜ 7 nV Hz ¨¨ ¸¸ ˜ 1.22 ˜ 1.08MHz 103 PVrms
© 1 ¹
Note that simulated and calculated are close but not exact (simulated = 86.6µV, calculated = 103µV). The
difference is because the INA has gain peaking and the filter order is approximated as two but in reality
the INA and filter poles are not exactly aligned.
140.5u

VINA =
140.5µV
Total noise (V)

70.3u VADC =
86.6µV

0.0
100 1k 10k 100k 1MEG 10MEG
Frequency (Hz)

SBAA316 – October 2018 Circuit for driving a high-voltage SAR

Submit Documentation Feedback 27 with an instrumentation amplifier
Copyright © 2018, Texas Instruments Incorporated
 www.ti.com

Design Featured Devices

Device Key Features Link Other Possible Devices

ADS8860 16-bit resolution, SPI, 1MSPS sample rate, single-ended input, http://www.ti.com/product/ADS8860 http://www.ti.com/adcs
Vref input range 2.5 V to 5.0 V
INA826 Bandwidth 1MHz (G=1), low noise 18nV/√Hz, low offset ±40µV, http://www.ti.com/product/INA826 http://www.ti.com/inas
low offset drift ±0.4µV/ºC, low gain drift 0.1ppm/ºC. (Typical
values)

Design References
See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.
Link to Key Files
Source files for this circuit - http://www.ti.com/lit/zip/SBAC217.

Circuit for driving a high-voltage SAR SBAA316 – October 2018

28 Submit Documentation Feedback
with an instrumentation amplifier
Copyright © 2018, Texas Instruments Incorporated
 Analog Engineer's Circuit: Data
Converters
SBAA286 – October 2018

Circuit for driving high-voltage SAR ADC with a buffered

instrumentation amplifier

Dale Li

Input ADC Input Digital Output ADS7042

VinDiffMin = –10V CH_x = –10V 8000H
VinDiffMax = +10V CH_x = +10V 7FFFH

Power Supplies
AVDD DVDD HVDD (VCC) HVSS(VEE)
5.0V 3.3V +15V –15V

Design Description
Instrumentation amplifiers are optimized for low noise, low offset, low drift, high CMRR and high accuracy
but these instrument amplifiers may not be able to drive a precision ADC to settle the signal properly
during the acquisition time of ADC. This design will show how a wide bandwidth buffer (OPA827) can be
used with an instrumentation amplifier to achieve good settling at higher sampling rate. This INA828
instrumentation amplifier with the buffer drives the ADS8568 SAR ADC to implement data capture for a
high voltage fully differential signal which may have a wide common-mode voltage range or a bipolar
single-ended signal up to ±10V. A related cookbook circuit shows a simplified approach that does not
include the wide bandwidth buffer (Driving High Voltage SAR ADC with an Instrumentation Amplifier), this
simplified approach has limited sampling rate as compared to the buffered design in this document. This
circuit implementation is applicable to Industrial Transportation and Analog Input Modules that require
Precision Signal-Processing and Data-Conversion.

+15V
-15V
+15V -15V 5V 3.3V
U1 +10V
+
+
INA828 +10V - Rflt 42.2 HVDD HVSS AVDD DVDD
Rg
+ R1 1k CH_xx
Rg Data Bus
10V ++ U2
open Ref
- OPA827 ADS8568
Rg Cflt 370p
-
C1 1n Control Bus
+15V AGND
+

-4.67V
VG1 VG2
-15V
Driving at the highest sampling rate
Vcm

SBAA286 – October 2018 Circuit for Driving High-Voltage SAR ADC

Submit Documentation Feedback 29 with a Buffered Instrumentation Amplifier
Copyright © 2018, Texas Instruments Incorporated
 www.ti.com

Specifications

Specification Goal Calculated Simulated

Transient Settling Error < 1/2LSB (< 152µV) NA –346nV
Noise (at ADC Input) <20µVRMS 47.2µVRMS 46µVRMS

Design Notes
1. The bandwidth of instrumentation amplifiers is typically not enough to drive SAR data converters at
higher data rate, so a wide bandwidth driver is needed because the SAR ADC with switched-capacitor
input structure has an input capacitor that needs to be fully charged during each acquisition time. The
OPA827 buffer is added to allow the ADC to run at full sampling rate (ADS8568 510kSPS for parallel
interface).
2. The ADS8568 can accept a ±10-V single-ended input signal. The INA828 is used to translate a ±10-V
differential signal to a ±10-V single-ended signal. So the INA282 is in unity gain for this example, and
no external gain set resistor Rg is needed. Refer to Circuit for Driving an ADC with an Instrumentation
Amplifier in High Gain in cases where the input signal range is small and gain is required.
3. Check the common mode range of the amplifier using the Common-Mode Input Range Calculator for
Instrumentation Amplifiers software tool.
4. Select COG capacitors for C1 and Cfilt to minimize distortion.
5. Precision labs video series covers the method for selecting driver amplifier and the charge bucket
circuit Rfilt and Cfilt. For details, see the Selecting and Verifying the Driver Amplifier and Introduction of
SAR ADC Front-End Component Selection videos.
6. Set the cutoff of the filter between the op amp and instrumentation amplifier for anti aliasing and to
minimize noise. See Aliasing and Anti-aliasing Filters for more details on aliasing and anti-aliasing
filters.

Circuit for Driving High-Voltage SAR ADC SBAA286 – October 2018

with a Buffered Instrumentation Amplifier 30 Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
www.ti.com

Component Selection
1. Find the gain based on differential input signal and ADC full-scale input range. The input signal in this
design is ±10-V high voltage signal, so the Gain of INA828 should be set to 1 and no gain resistor (Rg)
is needed.
2. Use the Common-Mode Input Range Calculator for Instrumentation Amplifiers to determine if the
INA828 is violating the common mode range. The common mode calculator in the following figure
indicates that the output swing is ±14.9V for a 0-V common-mode input.

3. Find the value for Cfilt, and Rfilt using TINA SPICE and the methods described in SAR ADC Front-End
Component Selection. The value of Rfilt and Cfilt shown in this document will work for these circuits;
however, if you use different amplifiers you will have to use TINA SPICE to find new values.
4. Select the RC filter between the INA828 and OPA827 based on your system requirements
(fcRC = 15.9kHz in this example). Set the cutoff of this filter for anti aliasing and to minimize noise.

1 1
fcRC 159kHz
2S ˜ R1 ˜ C1 2S ˜ (1k :) ˜ 1pF

SBAA286 – October 2018 Circuit for Driving High-Voltage SAR ADC

Submit Documentation Feedback 31 with a Buffered Instrumentation Amplifier
Copyright © 2018, Texas Instruments Incorporated
 www.ti.com

DC Transfer Characteristics
The following graph shows a linear output response for inputs from differential –12.2V to +12.2V. The
input range of the ADC is ±10V, so the amplifiers are linear well beyond the required range. Refer to
Determining a SAR ADC’s Linear Range when using Instrumentation Amplifiers for detailed theory on this
subject. The full-scale range (FSR) of the ADC falls within the linear range of the Instrumentation
Amplifier.
18.0
12.2V
12.0

6.0
Output

0.0
-12.2V
-6.0 Vadc

-12.0
VINA
-18.0
-18.0 -12.0 -6.0 0.0 6.0 12.0 18.0
Input voltage (V)
AC Transfer Characteristics
The bandwidth for this system is simulated to be 167kHz and the gain is 0dB. The filter between the
OPA827 and INA828 limits the bandwidth to about 167kHz.
T 10
0
VINA
-10
fc = 167kHz
-20
Gain (dB)

-30
Vadc
-40
-50
-60
-70
-80
-90
100 1k 10k 100k 1MEG 10MEG
Frequency (Hz)

Circuit for Driving High-Voltage SAR ADC SBAA286 – October 2018

with a Buffered Instrumentation Amplifier 32 Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
www.ti.com

Transient ADC Input Settling Simulation (510kSPS)

The OPA827 buffer (22MHz GBW) is used because it is capable of responding to the rapid transients from
the ADS8568’s charge kickback. The op amp buffer allows the system to achieve the ADS8568 maximum
sampling rate of 510kSPS. The following simulation shows settling to a full scale DC input signal with
INA828 and OPA827 buffer, and ADS8568. This type of simulation shows that the sample and hold
kickback circuit is properly selected to meet desired ½ of a LSB (152µV). Refer to the Introduction to SAR
ADC Front-End Component Selection training video series for detailed theory on this subject.
T 50.0u Verror = 285uV
Verror

-50.0u
1.00
tacq

0.00
7.84u 8.02u 8.20u
Time (s)

SBAA286 – October 2018 Circuit for Driving High-Voltage SAR ADC

Submit Documentation Feedback 33 with a Buffered Instrumentation Amplifier
Copyright © 2018, Texas Instruments Incorporated
 www.ti.com

Noise Simulation
The section walks through a simplified noise calculation for a rough estimate. We include both the INA828,
and OPA827 noise. Note that the RC filter between the instrumentation amplifier and op amp significantly
reduces the total noise. The output filter pole is estimated as a second order filter because the OPA827
(22MHz) bandwidth limit and charge bucket filter cutoff frequency (10.2MHz) is close.
2
§ en out ·
¨ G ¸ ˜ K n ˜ fcRC
2
En INA G en in
© ¹
2
2 § 90 nV Hz ·
En INA 1 4 nV Hz ¨¨ ¸¸ ˜ 1.57 ˜ 159kHz 45.1PVrms
© 1 ¹
1 1
fc 10.2MHz
2S ˜ Rfilt ˜ Cfilt 2S ˜ 42.2: ˜ 370 pF
adcFilter

Eopa en opa K n ˜ fc 4 nV Hz 1.22 ˜ 10.2MHz 14.1PVrms

2 2
En total En INA
2
Eopa 2 45.1PV 14.1PV 47.2PVrms
Note that calculated and simulated match well (calculated = 47.2µV, Simulated = 46µV). See TI Precision
Labs - Noise 4 for detailed theory on amplifier noise calculations, and Calculating Total Noise for ADC
Systems for data converter noise.
133.08u
VINA
Total noise (V)

66.54u 46uVrms

Vadc

0.00
1 10 100 1k 10k 100k 1MEG 10MEG
Frequency (Hz)

Circuit for Driving High-Voltage SAR ADC SBAA286 – October 2018

with a Buffered Instrumentation Amplifier 34 Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
www.ti.com

Design Featured Devices

Device Key Features Link Similar Devices

ADS8568 16-bit, 8 Channel Simultaneous-Sampling, Bipolar-Input SAR ADC http://www.ti.com/product/ADS8568 www/ti.com/adcs
INA828 Bandwidth 1MHz (G=1), low noise 18nV/rtHz, low offset ±40μV, low http://www.ti.com/product/INA828 www.ti.com/inas
offset drift ±0.4μV/ºC, low gain drift 0.1ppm/ºC. (Typical values)
OPA827 Gain bandwidth 22MHz, low noise 4nV/rtHz, low offset ±75μV, low http://www.ti.com/product/OPA827 www.ti.com/opamp
offset drift ±0.1μV/ºC (Typical values)

Design References
See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.
Links to Key Files
Source files for this circuit - http://www.ti.com/lit/zip/SBAC216.

SBAA286 – October 2018 Circuit for Driving High-Voltage SAR ADC

Submit Documentation Feedback 35 with a Buffered Instrumentation Amplifier
Copyright © 2018, Texas Instruments Incorporated
 Analog Engineer's Circuit: Data
Converters
SBAA247A – January 2018 – Revised March 2019

Circuit for driving high-voltage SAR ADCs for high-

voltage, true differential signal acquisition

Dale Li

Input ADC Input Digital Output ADS7042

VinDiffMin = –20V CH_x = +10V 7FFF H, or 32767 10
VinDiffMax = +20V CH_x = –10V 8000 H , or 32768 10

Power Supplies
AVDD DVDD VCC (HVDD) VSS (HVSS)
5.0V 3.3V +15V –15V

Design Description
This design shows a solution to drive high-voltage SAR ADC to implement data capture for high-voltage
fully differential signal which may have a wide common-mode voltage range depended on amplifier’s
power supply and input signal’s amplitude. A general high-voltage precision amplifier performs the
differential to single-ended conversion and drives high-voltage SAR ADC single-ended input scale of ±10V
at highest throughput. This type of application is popular in end equipment such as: Multi-Function Relays,
AC Analog Input Modules, and Control Units for Rail Transport. The values in the component selection
section can be adjusted to allow for different level differential input signal, different ADC data throughput
rates, and different bandwidth amplifiers.
Cf1 3n

Rf1 5.05k

-15V 15V 5V 3.3V

+15V
Rg1 10.1k
- + Rflt 49.9
HVDD

DVDD
AVDD
HVSS

+ Vopa_cm CH_xx
Vdif + REFIO
OPA827
- Cflt
Rg2 10.1k Vsamp
370p
-15V tacq
-
+

Vdif Vdif AGND ADS8568 tconv

Rf2
Cf2
2 2 5.05k
- 3n
+

VInputCM
Copyright © 2018, Texas Instruments Incorporated

SBAA247A – January 2018 – Revised March 2019 Circuit for driving high-voltage SAR ADCs for
Submit Documentation Feedback 36 high-voltage, true differential signal acquisition
Copyright © 2018–2019, Texas Instruments Incorporated
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Specifications

Specification OPA827 Calculated OPA827 Simulated OPA192 Calculated OPA192 Simulated

Common Mode Input Range ±26V ±26V ±35V ±35V
(with Vdif = ±20V)
Transient ADC Input Settling < 1/2LSB (< 152µV) 0.002 LSB (0.568µV) < 1/2LSB (< 152µV) 0.006 LSB (1.86µV)
Error
Phase Margin of driver > 45° 67.1° > 45° 68.6°
Noise (at ADC Input) 14.128µVrms 15.88µVrms 5.699µVrms 6.44µVrms

Design Notes
1. Determine the amplifier gain based on the differential input signal level, the ADC’s configuration for
input range. This is covered in the component selection section.
2. Determine amplifier’s linear range based on common mode voltage, input swing, and power supplies.
This is covered in the component selection section.
3. In this design circuit, the common-mode voltage of the input signal can be any value in the range of
VInputCM . The derivation of this range is provided in the component selection section for the OPA827
and OPA192.
4. Select COG capacitors to minimize distortion.
5. Use 0.1% 20ppm/°C film resistors or better for good accuracy, low gain drift, and to minimize distortion.
Review Statistics Behind Error Analysis for methods to minimize gain, offset, drift, and noise errors.
6. Refer to Introduction to SAR ADC Front-End Component Selection for an explanation of how to select
Rfilt and Cfilt for best settling and AC performance. These component values are dependent on the
amplifier bandwidth, data converter sampling rate, and data converter design. The values shown here
provide good settling and AC performance for the amplifier and data converter in this example. If the
design is modified, select a different RC filter.

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Component Selection
1. Find the gain based on differential input signal and ADC full-scale input range.

2. Find standard resistor values for differential gain. Use the Analog Engineer's Calculator ("Amplifier and
Comparator\Find Amplifier Gain" section) to find standard values for Rf/Rg ratio.

3. Find the amplifier’s maximum and minimum input for linear operation (that is, the common mode range
of the amplifier, Vcm_amp). For this example, the OPA827 is used.

4. Calculate the maximum common-mode voltage range based on amplifier’s input range and previously
shown configuration. Refer to the schematic diagram on the first page for better understanding of how
Vcm_opa, VInputCM, and Vdif relate to the circuit.

5. Solve the equation for the input common-mode range VInputCM for the amplifier. For this example
(OPA827), the common mode input can be ±26V with a ±20-V differential input. Using the same
method on OPA192 shows a common mode range of ±35V with a ±20-V differential input. Exceeding
this common-mode range will distort the signal. Note that this common-mode range was calculated
using ±15-V power supplies. The common mode range could be extended by increasing the supply
(maximum ±18V).

6. Find the value for Cf that will achieve the desired closed-loop bandwidth. In this example we want
approximately 10-kHz bandwidth. Note: if you adjust the bandwidth you will need to verify the charge
bucket filter settling (Cfilt and Rfilt) as the closed-loop bandwidth effects settling.

7. Find the value for Cfilt and Rfilt using TINA SPICE and the methods described in Introduction to SAR
ADC Front-End Component Selection. The value of Rfilt and Cfilt shown in this document will work for
these circuits; however, if you use different amplifiers or different gain settings you must use TINA
SPICE to find new values.

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Submit Documentation Feedback 38 high-voltage, true differential signal acquisition
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DC Transfer Characteristics
The following graph shows a linear output response for inputs from differential –20V to +20V. The full-
scale range (FSR) of the ADC falls within the linear range of the op amp. Refer to Determining a SAR
ADC's Linear Range when using Operational Amplifiers for detailed theory on this subject.

T 15.00
Vin(dif)= -20V
10.00 Vout = 10V

5.00
Voltage (V)

Vin(dif)= 20V
0.00 Vout = -10V
-5.00

-10.00

-15.00
-30.0 -20.0 -10.0 0.0 10.0 20.0 30.0
Input voltage (V)
AC Transfer Characteristics
The bandwidth is simulated to be 10.58kHz and the gain is –6.038dB which is a linear gain of 0.5V/V. See
the Op Amps: Bandwidth 1 video for more details on this subject.
0.0

-20.0 -6.038dB
Gain (dB)

Vin(dif)= -20V
-40.0 Vout = 10.0V

-60.0

-80.0
10 100 1k 10k 100k 1MEG 10MEG
Frequency (Hz)

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Transient ADC Input Settling Simulation Highest Sampling rate – 510ksps on ADS8568+OPA827
The following simulation shows settling to a 20-V DC input signal with OPA827. This type of simulation
shows that the sample and hold kickback circuit is properly selected to within ½ of a LSB (152µV). Refer
to Introduction to SAR ADC Front-End Component Selection for detailed theory on this subject.

T 1.0m
Verror 0.0

-1.0m Verror = 568nV

1.00
tacq

0.00
1.00
tconv

0.00
98.00u 98.50u 99.00u
Time (s)
Transient ADC Input Settling Simulation Lower Sampling rate – 200ksps on ADS8568+OPA192
The following simulation shows settling to a 20-V DC input signal with OPA192. This type of simulation
shows that the sample and hold kickback circuit is properly selected to within ½ of a LSB (152µV).
1.00m
Verror

-1.00m Verror = 1.86uV

1.00
tacq

0.00
1.00
tconv

0.00
95.0u 97.5u 100.0u
Time (s)

SBAA247A – January 2018 – Revised March 2019 Circuit for driving high-voltage SAR ADCs for
Submit Documentation Feedback 40 high-voltage, true differential signal acquisition
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Noise Calculation
This section demonstrates a full-noise analysis including resistor noise. Also, we look at the noise below fc
(Noise Gain = 1.5), and the noise above fc (noise Gain = 1). In this example, the noise is dominated by
wide band amplifier noise so the resistors do not contribute significantly. However, in many cases the
resistor noise may be important, so the full noise calculation is provided. Refer to Calculating the Total
Noise for ADC Systems and Op Amps: Noise 1 for more detailed theory on this subject.
Bandwidth for feedback loop:

Noise from OPA827: 3.8nV/rtHz

Thermal noise density from feedback loop (Rf1 and Rg1 ) and RC non-inverting input (Rf2 and Rg2 ):

Noise from resistors on the non-inverting input is the same as noise from the feedback resistors.

Total noise (in gain) referred to output of amplifier:

Noise above fc is limited by the output filter (cutoff given below):

Total noise applied to input of the ADC:

Circuit for driving high-voltage SAR ADCs for SBAA247A – January 2018 – Revised March 2019
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Noise Simulation
The simulated results compare well with the calculated results (that is, simulated = 15.88µVrms,
calculated = 14.128µVrms).
T 15.88u
Total noise (V)

7.94u

0.00
1 10 100 1k 10k 100k 1M 10M 100M 1G
Frequency (Hz)

31.68n
Output noise (V/Hz½)

en_below_fc
fc
15.84n

en_above_fc
foutput

0.00
1 10 100 1k 10k 100k 1M 10M 100M 1G
Frequency (Hz)

SBAA247A – January 2018 – Revised March 2019 Circuit for driving high-voltage SAR ADCs for
Submit Documentation Feedback 42 high-voltage, true differential signal acquisition
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Stability Test
The phase margin for this OPA827 driving circuit is 67.1°, which meets the >45° requirement and is
stable. Refer to Op Amps: Stability 1 for detailed theory explaining stability analysis.

T 140
120
100 AOL
Gain (dB)

80
60
40 1/E
20
0
-20
180
Phase Margin = 67o
Phase [deg]

135
90
45
0
1 10 100 1k 10k 100k 1MEG 10MEG 100MEG
Frequency (Hz)

Cf1 3n

Vfb
Rf1 5.05k C4 1T

Vss 15
+

VG1
C2 100n L1 1T

Rg1 10.1k
- U1 OPA827 R3 49.9 Vout
++
C1 100n
Rg2 10.1k C3 370p
Vo
Cf2 3n

Vcc 15
Rf2 5.05k

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Design Featured Devices

Device Key Features Link Similar Devices

ADS8568 (1) 16-bit, 8 Channel Simultaneous-Sampling, Bipolar- www.ti.com/product/ADS8568 www.ti.com/adcs
Input SAR ADC
OPA827 Low-Noise, High-Precision, JFET-Input Operational www.ti.com/product/OPA827 www.ti.com/opamp
Amplifier
OPA192 High-Voltage, Rail-to-Rail Input/Output, 5µV, www.ti.com/product/OPA192 www.ti.com/opamp
0.2µV/˚C, Precision operational amplifier

(1)
The ADS8568 has integrated a precision voltage reference which can meet most design requirements, but an external REF5050 can be
directly connected to the ADS8568 without any additional buffer because the ADS8568 has a built in internal reference buffer for every
ADC channel pair. Also, REF5050 has the required low noise and drift for precision SAR applications. C1 is added to balance CMRR
(common-mode rejection ratio). Clean analog power supplies are required to achieve best performance specified in the data sheet of the
ADC.

Design References
See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.
Link to Key Files (TINA)
Design files for this circuit – http://www.ti.com/lit/zip/sbac180.

Revision History
Revision Date Change
A March 2019 Downstyle the title and changed title role to 'Data Converters'.
Added link to circuit cookbook landing page.

SBAA247A – January 2018 – Revised March 2019 Circuit for driving high-voltage SAR ADCs for
Submit Documentation Feedback 44 high-voltage, true differential signal acquisition
Copyright © 2018–2019, Texas Instruments Incorporated
 Analog Engineer's Circuit: Data
Converters
SBAA244A – February 2018 – Revised March 2019

Circuit to increase input range on an integrated analog

front end (AFE) SAR ADC

Cynthia Sosa

Input ADC Input Digital Output

VinMin = –40V AIN-xP = –10V, AIN-xGND = 0V –13107210 or 20000H
VinMax = 40V AIN-xP = 10V, AIN-xGND = 0V 13107110 or 1FFFFH

Power Supplies
AVDD DVDD
5V 3.3V

Design Description
This cookbook design describes how to expand the input range of a SAR ADC with an integrated analog
front end (AFE) and decrease the loss of accuracy by implementing a two-point calibration method. This
design uses the ADS8598H at the full scale range of ±10V and expands the accessible input range to
±40V. This allows for a wider input range to be used without extra analog circuitry to step down the
voltage; instead a simple voltage divider is used to interact with the AFE of the device to step down the
voltage near the device input. A calibration method can be implemented to eliminate any error that could
occur.
A similar cookbook design, Reducing Effects of External RC Filter on Gain and Drift Error for Integrated
AFE: ±10 V, up to 200kHz, 16 bit, explaining how to measure introduced drift from external components
can prove to also be helpful in this application. Increasing the input range that the ADC can measure
proves useful in end equipment such as: Data Acquisition Modules, Multi Function Relays, AC Analog
Input Modules, and Control Units for Rail Transport.
±40V 3M ADS8598H
1M
Rext
GND
Vin_ADC Rin
Vin 1M
3M Rin
Rext
GND

SBAA244A – February 2018 – Revised March 2019 Circuit to increase input range on an integrated
Submit Documentation Feedback 45 analog front end (AFE) SAR ADC
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Specifications

Specification Measured Accuracy Without Calibration Measured Accuracy With Calibration

±40V 0.726318% 0. 008237%

Design Notes
1. Use low-drift resistors to decrease any error introduced due to temperature drift, such as 50 ppm/°C
with 1% tolerance or better. Note that as resistor values increase to 1MΩ and beyond, low-drift
precision resistors can become more expensive.
2. An input filter is frequently required for this configuration. Placing it directly after the large input
impedance can cause errors because of the capacitor leakage. If an input filtering capacitor is needed,
an alternate schematic is shown in this design.

Component Selection
The internal impedance of the device is 1MΩ, the external resistor is selected based on the desired
extended input range (Vin), in this case ±40V. This external resistor forms a voltage divider with the
internal impedance of the device, stepping down the input voltage at the ADC input pins (VinADC) within the
device input range of ±10V.
1. Rearrange the voltage divider equation to solve for the external resistor value. This same equation can
later be used to calculate the expected VinADC value from the input voltage.
R in
Vin ADC Vin ˜
R in R ext
Vin ˜ R in
R ext R in
Vin ADC
2. Solve for the external resistor value for the desired extended input voltage. Vin = ±40V, Rin = 1M Ω
40 V ˜ 1M:
R ext 1M:
10 V
The input can be extended to a variety of ranges, depending on what external resistor value is used.

Vin Rext
±40 3MΩ
±30 2MΩ
±20 1MΩ
±12 200kΩ

Circuit to increase input range on an integrated SBAA244A – February 2018 – Revised March 2019
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Non-Calibrated Measurements
Different DC input values ranging through the full ±40-V scale were used to measure the ADC voltage
input and the accuracy of the measurement. The following equation shows how to calculate the analog
voltage read by the ADC. Here the FSR is the system full scale range which is 40V in this case. The factor
of 2 is included because this is a bipolar input where the input range is actually ±40V which is a range of
80V. VoutADC for this equation will range ±40V, which corresponds to the system input.
2 ˜ FSR
Vout ADC Code out
2N
The percent error of the value is calculated using the next equation:
VinADC Vout ADC
Error(%) ˜ 100
VinADC

Two-Point Calibration
Calibration can be applied in order to eliminate the reading error introduced by the external resistor. The
two-point calibration applies and samples two test signals at 0.25V from the full scale input range within
the linear range of the ADC. These sample measurements are then used to calculate the slope and offset
of the linear transfer function. Calibration will eliminate both the gain error introduced by the external
resistor and the internal device gain error.
1. Apply test signal at –39 V:

Vmin Measured Code

–39 V –128689

2. Apply test signal at 39 V:

Vmax Measured Code

39 V 128701

SBAA244A – February 2018 – Revised March 2019 Circuit to increase input range on an integrated
Submit Documentation Feedback 47 analog front end (AFE) SAR ADC
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3. Calculate slope and offset calibration coefficients:

Code max Code min 128701 128689
m 3299.872
V max V min 39V 39V
b Codemin m ˜ Vmin 128689 3299.872 ˜ 39V 6.008
4. Apply calibration coefficients to all subsequent measurements:
Code b 128701 6.008
Vin Calibrate 38.999
m 3299.872
Two-Point Calibration Measurements
Calibration Coefficients
m = 3299.872; b = 6.008
When calibration is applied the readings error is dramatically reduced.

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Alternate Schematic With Filter Capacitor

Due to the high-value resistors used, introducing a capacitor would lead to significant impact in readings,
such as increase drift experienced. This is because of the capacitor leakage. This leakage will vary over
time and temperature and will generate errors that are difficult to calibrate out. If an input filter is needed,
the alternate schematic can be used to implement it. The capacitor is placed with a balanced resistor-
capacitor filter before the external resistors in relation to the input signal.
±40V
10 k 3M ADS8595H
1M
R Rext
GND
CFIL Rin
Vin Vin_ADC
24 nF 1M
10 k 3M Rin
R Rext
GND

Alternate Schematic With Filter Capacitor - Component Selection

External anti-aliasing RC filters reduce noise and protect from electrical overstress. A balanced RC filter
configuration is required for better common-mode noise rejection; matching external resistors are added to
both the negative and positive input paths. These external resistors should also be low-drift resistors as
stated in the Design Notes.
1. Choose a value of R based on the desired cutoff frequency. This example uses a cutoff frequency of
320Hz, and a resistor value of 10kΩ.
R = 10kΩ
2. Select CFIL
1 1
CFIL 24.8nF
2 ˜ S ˜ fc ˜ 2 ˜ R 2 ˜ S ˜ 320Hz ˜ 2 ˜ 10k:
Nearest standard capacitor value available, CFIL= 24 nF
Design Featured Devices

Device Key Features Link Similar Devices

ADS8598H 18-bit high-speed 8-channel simultaneous-sampling ADC With www.ti.com/product/ADS8598H www.ti.com/adcs
bipolar inputs on a single supply

Design References
See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.

Revision History
Revision Date Change
A March 2019 Downstyle the title and changed title role to 'Data Converters'.
Added link to circuit cookbook landing page.

SBAA244A – February 2018 – Revised March 2019 Circuit to increase input range on an integrated
Submit Documentation Feedback 49 analog front end (AFE) SAR ADC
Copyright © 2018–2019, Texas Instruments Incorporated
 Analog Engineer's Circuit: Data
Converters
SBAA337 – December 2018

High common-mode differential input voltage to ±10-V

ADC input circuit

Aaron Estrada

Input ADC Input Digital Output ADS8688

VinDiffMin = –10.24V CH_x = –10.24V 0000H
VinDiffMax = +10.24V CH_x = +10.24V FFFFH

Power Supplies
AVDD DVDD AGND DGND
5.0V 3.3V GND GND

Design Description
The purpose of this cookbook is to demonstrate the advantages and disadvantages of using difference
amplifiers or instrumentation amplifiers to translate a signal with a high common mode voltage (Vcm) to a
level that the ADS86XX family can accept. The ADS86XX family cannot support a high Vcm so using a
difference or instrumentation amplifier to drive the ADC solves this issue. The INA828 device is an
instrumentation amplifier with very high input impedance (100GΩ), excellent DC precision, and low noise.
The INA828 can accept common-mode signals in the range of its supply voltage (±15V). The INA149
device is a unity-gain difference amplifier with a high input common-mode voltage range of up to ±275V,
but the input impedance is lower than the INA828 device (differential = 800kΩ, common mode = 200kΩ).
The ADS86XX family of ADCs has an integrated analog front end (AFE) and multiplexer which makes it
an ideal candidate for a PLC (analog input module), protection relay, grid automation, and other various
industrial applications.
-15V
5.0V 3.3V
- U1 VoutP
Rg INA149
± 10V
Vdif AVDD DVDD
INP
± 10V Ref
Rg +
+ ADS8688
+

-Vdif/2 +Vdif/2 +15V INM GND

VCM
200V

SBAA337 – December 2018 High common-mode differential input

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Specifications

Specification Calculated Simulated Measured

INA149 Common-Mode 275V 275V 275V
Voltage (VCM)
INA828 Common-Mode 8.38V 8.38V 7.5V
Voltage (VCM)
INA149 Integrated Noise 487µV 487.3µV 488µV
INA828 Integrated Noise 150µV 150µV 154µV

Design Notes
1. The ADS86XX family of HV SAR ADCs was selected because of the integrated analog front end and
multiplexer. The integrated AFE eliminates the use of extra components to drive the ADC.
2. The INA149 device was selected to provide a very high common-mode voltage (Vcm = ±275V).
3. Comparing the INA828 device to the INA149 shows that the INA828 device has high input impedance
(100GΩ), and the INA149 device has lower input impedance (differential = 800kΩ, common mode =
200kΩ). Also, the INA149 device has very wide common mode (Vcm = ±275V) but the INA828
common mode range is limited to the supply range (for example, ±15V). In cases where high input
impedance is required, the INA828 device can be used, but be careful to not violate common-mode
range. Note that high input impedance is important when the sensor output impedance is high as this
will create a voltage divider effect and introduce error.
4. In this example, the input signal is ±10.24V. Therefore, resistor Rg is not needed in order to set the
Gain = 1 for the INA828 device. If the input signal is smaller, use the appropriate resistor value to set
the gain with a proper reference voltage on reference pin to achieve an input swing that matches the
input range of the ADC.
5. Check the common mode range of the instrumentation amplifier using the Common-Mode Input Range
Calculator for Instrumentation Amplifiers software tool.
6. If gain is required, use 0.1% 20ppm/°C film resistors or better for the gain setting resistor (Rg) to
achieve best gain accuracy and low gain drift.

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Component Selection
1. The ADS86XX can accept a single-ended input signal of ±10.24V. In this example, the input signal is
±10.24V so no external gain set resistor is required for the INA828 device. The INA149 device is a
unity gain difference amplifier so no extra components are necessary.
2. The INA828 reference voltage input is used to shift inputs to match the input range of the ADC. In this
example, the ADC input range is symmetrical so the reference pin is grounded.
3. Determine if the INA828 device is violating the common-mode range by using the Common-Mode Input
Range Calculator for Instrumentation amplifiers. In this example, the INA828 device shows that you
can achieve a maximum VCM of 8.38V with ±15V supplies, Gain = 1, and Vref = 0V.

SBAA337 – December 2018 High common-mode differential input

Submit Documentation Feedback 52 voltage to ±10-V ADC input circuit
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DC Transfer Characteristics
The following graphs show a linear output response for the INA149 device. The input range of the ADC is
±10.24V so the amplifier is linear well beyond the range the ADC requires. Refer to Determining a SAR
ADC’s Linear Range when using instrumentation amplifiers for detailed theory on this subject.
15.00

10.00
Voltage (V)

5.00 (10.24, 10.24)

0.00

-5.00 (-10.24, -10.24)

-10.00

-15.00
-18.00 -12.00 -6.00 0.00 6.00 12.00 18.00
Input voltage (V)
AC Transfer Characteristics
The simulated bandwidth for the INA149 device is 505kHz at gain = 1V/V, or 0dB. The simulated
bandwidth for the INA828 device is 1.78MHz at a gain of 0dB. Both of the simulated bandwidths closely
match their respective data sheets. See Amplifier Bandwidth Video Series for more details on this subject.

20 Bandwidth
fcINA828 = 1.78MHz
0
Gain (dB)

-20 Gain = 0dB Bandwidth

Gain=1V/V fcINA149 = 505kHz
-40

-60

-80
10 100 1k 10k 100k 1MEG 10MEG 100MEG
Frequency (Hz)

High common-mode differential input SBAA337 – December 2018

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Transient ADC Input Settling Simulation

The INA149 device was simulated with a ±10.24-V differential input and a 275-V common-mode voltage.
The following TINA simulation shows the differential input as well as the single-ended output for the
INA149 device. The device has no issue with a common-mode voltage of 200V.
10.24

Vin 0.00

-10.24
10.24

Vout 0.00

-10.24
0.00 5.00m 10.00m
Time (s)
The INA828 device was simulated with a ±10.24-V differential input and a 7.75-V common-mode voltage.
The following TINA simulation shows the differential input as well as the single-ended output for the
INA828 device.
T 10.24

Vdif 0.00

-10.24
10.22

Vout 0.00

-10.22
0.00 5.00m 10.00m
Time (s)

SBAA337 – December 2018 High common-mode differential input

Submit Documentation Feedback 54 voltage to ±10-V ADC input circuit
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Noise Simulation
The section provides simplified noise calculations for the INA149 and INA828 devices. The simulated
results closely match the calculated results. Refer to Op Amps: Noise 4 for detailed theory on amplifier
noise calculations, and Calculating Total Noise for ADC Systems for data converter noise.
INA149 integrated noise:
EnINA149 eni fc ˜ K n 550 nV Hz 505kHz ˜ 1.57 489PVrms

INA828 integrated noise:

2
EnINA828 Gain eni 2 eno 2 fc ˜ K n (1) (7 nV Hz )2 90 nV Hz 1.78MHz ˜ 1.57 151PVrms

The ADS8688 device has an internal second-order 15-kHz LPF. This filter will reduce the noise from the
instrumentation amplifiers significantly.
INA149 integrated noise:
EnINA149 eni fc ˜ K n 550 nV Hz 15kHz ˜ 1.22 74.4 PVrms

INA828 integrated noise:

2
EnINA828 Gain eni 2 eno 2 fc ˜ K n (1) (7 nV Hz )2 90 nV Hz 15kHz ˜ 1.22 12.2PVrms

500u

400u
Total noise (V)

En-INA828 = 488µV rms

300u

200u

100u
En-INA828 = 149µV rms
0
1 10 100 1k 10k 100k 1M 10M 100M
Frequency (Hz)

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Design Featured Devices

Device Key Features Link Other Possible Devices

ADS86XX 16-Bit Resolution, 4-,8-Channel MUX, SPI, 500ksps sample http://www.ti.com/product/ADS8688 http://www.ti.com/adcs
rate, on-chip 4.096V Reference
INA149 500kHz BW, Very High VCM, excellent nonlinearity http://www.ti.com/product/INA149 http://www.ti.com/amplifier-circuit/op-
amps/fully-differential/overview.html
INA828 2MHz BW, Low Power12nV/√Hz noise http://www.ti.com/product/INA828 http://www.ti.com/inas

Design References
See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.
Link to Key Files
TINA source files – http://www.ti.com/lit/zip/sbac224.

SBAA337 – December 2018 High common-mode differential input

Submit Documentation Feedback 56 voltage to ±10-V ADC input circuit
Copyright © 2018, Texas Instruments Incorporated
 Analog Engineer's Circuit: Data
Converters
SBAA243 – December 2017

High-current battery monitor circuit: 0–10 A,

0–10 kHz, 18 bit

Luis Chioye

Sense Resistor Current INA Out, Amplifier Input ADC Input Digital Output ADS8910B
MinCurrent = ±50mA Out = ±10mV VoutDif = ±21.3mV 233H 56310, 3FDCBH -5640
MaxCurrent = +10A Out = ±2V VoutDif = ± 4.3V 1B851H 11272210 247AEH -11272210

Supply and Reference

Vs Vee Vref Vcm
5.3 V <Vs <5.5V 0V 5V 2.5V

Design Description
This single-supply current sensing solution can measure a current signal in the range of ±50 mA to ±10 A
across a shunt resistor. The current sense amplifier can measure shunt resistors over a wide common-
mode voltage range from 0V to 75V. A fully differential amplifier (FDA) performs the single-ended to
differential conversion and drives the SAR ADC differential input scale of ±5V at full data rate of 1MSPS.
The values in the component selection section can be adjusted to allow for different current levels.
This circuit implementation is applicable in accurate voltage measurement applications such as Battery
Maintenance Systems, Battery Analyzers, Battery Testing Equipment, ATE, and Remote Radio Units
(RRU) in wireless base stations.
VS

RfINA 10k
INP VS OUT

Rsense CfINA 1.5n

+ 10PŸ INA240A1
VCM
0V to 75V REF2
INN GND REF1

±50mA to VREF/2
±10A
Current Sense Amplifier
G= 20 V/V

Cf1 10n

- Rg1 1k
Rf1 2.150k Rfil1 2.2

+
+ Vs THS4551
OPA320 VREF/2
Vs + R8 10
+ - INM
Vocm Cfil 10n ADS8910B
+
- INP
-
R9 10
- Rg2 1k Vs

VREF/2
+ Rf2 2.150k Rfil2 2.2
+ OPA320
Vs
Cf2 10n

SBAA243 – December 2017 High-current battery monitor

Submit Documentation Feedback 57 circuit: 0–10 A, 0–10 kHz, 18 bit
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Specifications:

Error Analysis Calculated Simulated Measured

Transient ADC Input Settling > 1LSB > 38µV 6.6µV N/A
Noise (at ADC Input) 221.8µV rms 207.3µV rms 227µV rms
Bandwidth 10.6kHz 10.71kHz 10.71kHz

Design Notes
1. Determine the shunt sense resistor value and select the current sense amplifier based on the input
current range and input common mode voltage requirements. This is covered in the component
selection section.
2. Determine the fully differential amplifier gain based on the current sense amplifier output, the ADC full-
scale range input and the output swing specifications of the fully differential amplifier. This is covered in
the component selection section.
3. Select COG capacitors to minimize distortion.
4. Use 0.1% 20ppm/°C film resistors or better for good accuracy, low gain drift, and to minimize distortion.
5. The TI Precision Labs training video series covers methods for error analysis. Review the following
links for methods to minimize gain, offset, drift, and noise errors: Error and Noise.
6. The TI Precision Labs – ADCs training video series covers methods for selecting the charge bucket
circuit Rfilt and Cfilt. These component values are dependent on the amplifier bandwidth, data converter
sampling rate, and data converter design. The values shown here will give good settling and ac
performance for the amplifier, gain settings, and data converter in this example. If the design is
modified, select a different RC filter. Refer to Introduction to SAR ADC Front-End Component Selection
for an explanation of how to select the RC filter for best settling and ac performance.

High-current battery monitor SBAA243 – December 2017

circuit: 0–10 A, 0–10 kHz, 18 bit 58 Submit Documentation Feedback
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Component Selection for Current Sense Circuit

1. Choose the Rsense resistor and find the gain for the current sense amplifier (bidirectional current).

2. Calculate the current sense amplifier output range.

3. Find ADC full-scale input range and results from step 3.

4. Find FDA maximum and minimum output for linear operation.

5. Find differential gain based on ADC full-scale input range, FDA output range and results from step 3.

6. Find standard resistor values for differential gain.

7. Find RfINA, CfINA for cutoff frequency.

SBAA243 – December 2017 High-current battery monitor

Submit Documentation Feedback 59 circuit: 0–10 A, 0–10 kHz, 18 bit
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Fully Differential DC Transfer Characteristics

The following graph shows a linear output response for inputs from –10A to +10A.
T 5.00
Iin = 10A
VoutDif = 4.299918V
2.50
Voltage (V)

Iin = -10A
0.00 VoutDif = -4.299955V

-2.50

-5.00
-10.00 -7.50 -5.00 -2.50 0.00 2.50 5.00 7.50 10.00
Input current (A)
AC Transfer Characteristics
The bandwidth is simulated to be 10.5kHz and the gain is 32.66dB which is a linear gain of 43V/V (G =
20·2.15V/V).
50.0

35.0

20.0 Vout_dif = 33.59dB Vout_dif

Gain (dB)

G=47.8V/V fc=10.59kHz
5.0 (G=20Â2.39)

-10.0

-25.0

-40.0
10 100 1k 10k 100k 1MEG
Frequency (Hz)

High-current battery monitor SBAA243 – December 2017

circuit: 0–10 A, 0–10 kHz, 18 bit 60 Submit Documentation Feedback
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Noise Simulation
The following simplified noise calculation is provided for a rough estimate. Since the current sense
amplifier INA240 is the dominant source of noise, the noise contribution of the OPA320 buffers and
THS4521 is omitted in the noise estimate. We neglect resistor noise in this calculation as it is attenuated
for frequencies greater than 10.6kHz.

Note that calculated and simulated match well. Refer to Op Amps: Noise 4 for detailed theory on amplifier
noise calculations, and Calculating Total Noise for ADC Systems for data converter noise.

T 207.48u
Total noise (V)

138.32u

69.16u

0.00
1 10 100 1k 10k 100k 1MEG 10MEG
Frequency (Hz)

Transient ADC Input Settling Simulation

The following simulation shows settling to a 10-A DC input signal (ADC differential input signal +4.3V).
This type of simulation shows that the sample and hold kickback circuit is properly selected. Refer to Final
SAR ADC Drive Simulations for detailed theory on this subject.
a
4.30
VADC_IN

4.29
1.00
Vacq

0.00
1.00
Vconv

0.00
2.00m
Verror 6.567uV<<1LSB
Verror

-2.00m
1.00u 1.50u 2.00u
Time (s)

SBAA243 – December 2017 High-current battery monitor

Submit Documentation Feedback 61 circuit: 0–10 A, 0–10 kHz, 18 bit
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Design Featured Devices:

Device Key Features Link Similar Devices

(1) 18-bit resolution, 1-Msps sample rate, integrated reference buffer, fully www.ti.com/product/ADS8910
ADS8910B www.ti.com/adcs
differential input, Vref input range 2.5V to 5V B
High- and low-Side, bi-directional, zero-drift current sense amp,
INA240 www.ti.com/product/INA240 www.ti.com/inas
GainError = 0.20%, Gain = 20V/V, wide common-mode = –4V to 80V
Fully differential amplifier (FDA), 150-MHz bandwidth, Rail-to-Rail output,
THS4551 www.ti.com/product/THS4551 www.ti.com/opamp
VosDriftMax = 1.8 µV/°C, en = 3.3 nV/rtHz
20-MHz bandwidth, Rail-to-Rail with zero crossover distortion, VosMax =
OPA320 www.ti.com/product/OPA320 www.ti.com/opamp
150 µV, VosDriftMax = 5 µV/C, en = 7 nV/rtHz
REF5050 3 ppm/°C drift, 0.05% initial accuracy, 4 µVpp/V noise www.ti.com/product/REF5050 www.ti.com/vref
(1)
The REF5050 can be directly connected to the ADS8910B without any buffer because the ADS8910B has a built in internal
reference buffer. Also, the REF5050 has the required low noise and drift for precision SAR applications. The INA240 offers high
common-mode range and low gain error in current sensing solutions. The THS4551 is commonly used in high-speed precision
fully differential SAR applications as it has sufficient bandwidth to settle to charge kickback transients from the ADC input
sampling. The OPA320 is required to isolate the INA240 from any residual charge kickback at the inputs of the FDA..

Design References
See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.
Link to Key Files
ADS8900B Design File – http://www.ti.com/lit/zip/sbam340.

High-current battery monitor SBAA243 – December 2017

circuit: 0–10 A, 0–10 kHz, 18 bit 62 Submit Documentation Feedback
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 Analog Engineer's Circuit: Data
Converters
SBAA267A – February 2018 – Revised March 2019

High-input impedance, true differential, analog front end

(AFE) attenuator circuit for SAR ADCs

Luis Chioye

Input Voltage (OPA197 Buffers) THS4551 Output, ADC Input ADS8912B Digital Output
VinP = –12V, VinN = +12V, VinMin (Dif) = –24V VoutDif = –4.00V, VoutP = 0.25V, VoutN = 4.25V 238E3H -11650910
VinP = +12V, VinN = –12V, VinMax (Dif) = +24V VoutDif = +4.0V, VoutP = 4.25V, VoutN = 0.25V 1C71CH +11650810

Supplies and Reference

HVDD HVSS Vcc Vee Vref Vcm
+15V –15V +5.0V 0V +4.5V 2.5V

Design Description
This analog front end (AFE) and SAR ADC data acquisition solution can measure true differential voltage
signals in the range of ±24V (or absolute input range VinP = ±12V, VinN = ±12V) offering high-input
impedance supporting data rates up to 500ksps with 18-bit resolution. A precision, 36-V rail-to-rail
amplifier with low-input bias current is used to buffer the inputs of a fully-differential amplifier (FDA). The
FDA attenuates and shifts the signal to the differential voltage and common-mode voltage range of the
SAR ADC. The values in the component selection section can be adjusted to allow for different input
voltage levels.
This circuit implementation is used in accurate measurement of true differential voltage in Application-
Specific Test Equipment, Data Acquisition (DAQ) cards, and Analog Input Modules used in Programmable
Automation Control (PAC), Discrete Control System (DCS), and Programmable Logic Control (PLC)
applications.
Cf1 120pF
HVSS Ccm1
750pF
VinN - Rg1 6.04kŸ
Rf1 1kŸ Rfil1 4.99Ÿ

+V
+ Vcc
OPA197 INP
THS4551
VREF/2
HVDD - Riso1 10Ÿ
+ ADS8910B
+ Cdiff
Vocm - - 7.5n
HVSS +
Riso2 10Ÿ INM

VinP - Vcc Rfil2 4.99Ÿ

+V
+ Rf2 1kŸ
OPA197 Rg2 6.04kŸ
Ccm2
Cf2 120pF
750pF
HVDD

Copyright © 2017, Texas Instruments Incorporated

SBAA267A – February 2018 – Revised March 2019 High-input impedance, true differential, analog front end (AFE)
Submit Documentation Feedback 63
attenuator circuit for SAR ADCs
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 www.ti.com

Specifications

Specification Goal Calculated Simulated

Transient ADC Input Settling << 1 LSB; << 34µV N/A 0.5µV
(500ksps)
Noise (at ADC Input) 10µVRMS 9.28µVRMS 9.76µVRMS
Bandwidth 1.25MHz 1.25MHz 1.1MHz

Design Notes
1. Verify the linear range of the op amp (buffer) based on the common mode, output swing specification
for linear operation. This is covered in the component selection section. Select an amplifier with low
input bias current.
2. Find ADC full-scale range and common-mode range specifications. This is covered in the component
selection.
3. Determine the required attenuation for the FDA based on the input signal amplitude, the ADC full-scale
range and the output swing specifications of the FDA. This is covered in the component selection
section.
4. Select COG capacitors to minimize distortion.
5. Use 0.1% 20ppm/°C film resistors or better for good accuracy, low gain drift, and to minimize distortion.
6. Understanding and Calibrating the Offset and Gain for ADC Systems covers methods for error
analysis. Review the link for methods to minimize gain, offset, drift, and noise errors
7. Introduction to SAR ADC Front-End Component Selection covers methods for selecting the charge
bucket circuit Rfilt and Cfilt. These component values are dependent on the amplifier bandwidth, data
converter sampling rate, and data converter design. The values shown here will give good settling and
AC performance for the amplifier, gain settings, and data converter in this example. If the design is
modified, a different RC filter must be selected. Refer to the Precision Labs videos for an explanation
of how to select the RC filter for best settling and AC performance.

High-input impedance, true differential, analog front end (AFE) SBAA267A – February 2018 – Revised March 2019
64 Submit Documentation Feedback
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Component Selection and Settings for Buffer Amplifier and FDA

1. Verify the buffer amplifier input range for linear operation:

Select Supplies  (V - ) = - 15V, (V+ ) = +15V to allow VinP = ±12V VinN = ±12V range
(V - ) - 0.1V < Vcm < (V+ ) - 3V from OPA197 common-mode voltage specification
-15.1V < Vcm < +12V allows required ±12V input voltage ra nge 
2. Verify the buffer amplifier output range for linear operation:
V- +0.6V<Vout < V+ -0.6V from OPA197 Aol specification for linear operation
-14.4V<Vout <14.4V allows required±12Voutput voltage range
3. Find ADC full-scale input range. In this circuit, VREF = 4.5V:
ADC Full-Scale Range =± VREF =±4.5V from ADS8910B datasheet
4. Find the required ADC common-mode voltage:
VREF
VCM 2.25V from ADS8910B datasheet, therefore set FDA VCOM = 2.25V
2
5. Find FDA absolute output voltage range for linear operation:
0.23 <Vout < 4.77V from THS4551 output low/high specification for linear operation
However, the positive range is limited by ADCFull Scale Range r4.5V , therefore
0.23V < Vout < 4.5V where VoutMin = 0.23V, VoutMax = 4.5V
6. Find FDA differential output voltage range for linear operation. The general output voltage equations
for this circuit follow:
VoutDifMin VoutDifMax
VoutMin Vcm and VoutMax Vcm
2 2
Re-arrange the equations and solve for VoutDifMin and VoutDifMax .
Find maximum differential output voltage range based on worst case:
VoutDifMax 2 ˜ VoutMax 2 ˜ Vcm 2 ˜ 4.5V 2 ˜ 2.25V 4.5V
VoutDifMin 2 ˜ VoutMin 2 ˜ Vcm 2 ˜ 0.23V 2 ˜ 2.5V 4.04V
Based on combined worst case, choose VoutDifMin = -4.04V and VoutDifMax = +4.04V
7. Find the FDA differential input voltage range:
VinDifmax VinPmax VinNmin 12V 12V 24V
VinDifmin VinPmin VinNmax 12V 12V 24V
8. Find FDA required attenuation ratio:
VoutDifMax VoutDifMin 4.04V 4.04V V 1V
GainFDA 0.166 |
VinDifMax VinDifMin 24V 24V V 6V
9. Find standard resistor values to set the attenuation:
Rf 1 R 1.00k
GainFDA V /V Ÿ g V /V
Rg 6 R f 6.04k
10. Find Cƒ for cutoff frequency ƒc, RfINA = 1kΩ:
1 1
Cf 127 pF or 120 pF standard value
2 ˜ S ˜ f c ˜ R fINA 2 ˜ S ˜ 1.25MHz ˜ 1k

SBAA267A – February 2018 – Revised March 2019 High-input impedance, true differential, analog front end (AFE)
Submit Documentation Feedback 65
attenuator circuit for SAR ADCs
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DC Transfer Characteristics
The following graph shows a linear output response for differential inputs from +24V to –24V.
4
3
2
1
Output

VoutDif = -3.973443V
0 VinDiff = -24V VoutDif = +3.973543V
VinDiff = +24V
-1
-2
-3
-4
-24 -16 -8 0 8 16 24
Input voltage (V)
AC Transfer Characteristics
The simulated bandwidth is approximately 1.1MHz and the gain is –15.62dB which is a linear gain of
approximately 0.166V/V (attenuation ratio 6.04V/V).

-20
Gain (dB)

-40 VoutDiff f(>3dB) = 1.1MHz

Gain = >15.62dB
-60 Attenuation = 6.04V/V

-80

-100
10 100 1k 10k 100k 1M 10M 100M
Frequency (Hz)

High-input impedance, true differential, analog front end (AFE) SBAA267A – February 2018 – Revised March 2019
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Noise Simulation
Simplified Noise calculation for rough estimate:
1 1
fc 1.33MHz
2 ˜S ˜ Rf ˜ C f 2 ˜ S ˜ 1k ˜ pF
Noise contribution of OPA197 buffer referred to ADC input
EnOPA197 enOPA197 ˜ K n ˜ f c ˜ GainFDA
EnOPA197 5.5nV / Hz ˜ 1.57 ˜ 1.33MHz ˜ 0.166V / V 1.319µVRMS
Noise of THS 4551 FDA referred to ADC input
1.00k
Noise gain : NG 1 R f / Rg 1 1.166V / V
6.04k
2 2
enoFDA enFDA ˜ NG 2 inFDA ˜ R f 2 4kTR f ˜ NG
2 2
18
enoFDA 3.4nV / Hz ˜ 1.166V / V 2 0.5 pA / Hz ˜ 1k ˜ 0 ˜ 1.166V / V

enoFDA 7.40nV / Hz
EnFDA enoFDA ˜ K n ˜ f c 7.40nV / Hz ˜ 1.57 ˜ 1.33MHz 9.28µVRMS
2 2
Total Noise EnFDA2 EnOPA197 2 9.28µVRMS 1.32 µVRMS 9.37 µVRMS
Note that calculated and simulated match well. Refer to Calculating the Total Noise for ADC Systems for
detailed theory on this subject.
9.76u
Total noise (V)

4.88u

0.00
1 10 100 1k 10k 100k 1M 10M 100M
Frequency (Hz)

SBAA267A – February 2018 – Revised March 2019 High-input impedance, true differential, analog front end (AFE)
Submit Documentation Feedback 67
attenuator circuit for SAR ADCs
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Stability Simulation
The following circuit is used in TINA to measure loop gain and verify phase margin using AC transfer
analysis in TINA. Resistors RISO = 10Ω are used inside the feedback loop to increase phase margin. The
circuit has 45 degrees of phase margin. Refer to TI Precision Labs - Op Amps: Stability 4 for detailed
theory on this subject.

Vin-
Cf1 120p
Rg1 6.04k

Rf1 1k

L1 1MEG
R4 1G
R8 4.99
U1 THS4551
VCVS1 500m C1 1MEG
+ + Ccm1 750p

Vocm
Vcc Riso1 10
- -
-+
+

Vocm +
- Riso1 10 Cdiff 7.5n
VG1
- - +-
C2 1MEG PD
+ +
Ccm2 750p
R9 4.99
R6 1G

L2 1MEG

VCVS2 500m

Rg2 6.04k
Vin+ Rf2 1k
Cf2 120p
Vocm

Vin-
Vcc

R1 1G
PD

Loop_Gain

C3 1.2p

R5 100k

-
V1 5 V4 2.25 V3 5
+ R2 1G

Vin+

140
120
100
Gain (dB)

80
60
40
20
0
-20
Loop Gain
45
Phase Margin = 180ö- 135ö
Phase [deg]

0
-45 Phase Margin = 45ö
-90
-135
-180
10 100 1k 10k 100k 1M 10M 100M
Frequency (Hz)

High-input impedance, true differential, analog front end (AFE) SBAA267A – February 2018 – Revised March 2019
68 Submit Documentation Feedback
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Transient ADC Input Settling Simulation

The following simulation shows settling to a 24-V DC differential input signal with the OPA197 buffers
inputs set at +12V and –12V. This type of simulation shows that the sample and hold kickback circuit is
properly selected. Refer to Refine the Rfilt and Cfilt Values for detailed theory on this subject.
1.00

Vacq

0.00
100u
Verror = 168nV
Verror 0

-100u
3.90u 4.95u 6.00u
Time (s)

SBAA267A – February 2018 – Revised March 2019 High-input impedance, true differential, analog front end (AFE)
Submit Documentation Feedback 69
attenuator circuit for SAR ADCs
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Design Featured Devices

Device Key Features Link Similar Devices

ADS8912B (1) 18-bit resolution, 500-ksps sample rate, integrated reference buffer, fully- www.ti.com/product/ADS8912B www.ti.com/adcs
differential input, Vref input range 2.5V to 5V.
THS4551 FDA, 150-MHz bandwidth, Rail-to-Rail Output, VosDriftMax = 1.8µV/°C, en www.ti.com/product/THS4551 www.ti.com/opamp
= 3.3nV/rtHz
OPA197 36V, 10-MHz bandwidth, Rail-to-Rail Input/Output, VosMax = ±250µV, www.ti.com/product/OPA197 www.ti.com/opamp
VosDriftMax = ±2.5µV/°C, bias current = ±5pA
REF5045 VREF = 4.5V, 3 ppm/°C drift, 0.05% initial accuracy, 4µVpp/V noise www.ti.com/product/REF5045 www.ti.com/voltageref

(1)
The REF5045 can be directly connected to the ADS8912B without any buffer because the ADS8912B has a built in internal reference
buffer. Also, the REF5045 has the required low noise and drift for precision SAR applications. The THS4551 provides the attenuation and
common-mode level shifting to the voltage range of the SAR ADC. In addition, this FDA is commonly used in high-speed precision fully-
differential SAR applications as it has sufficient bandwidth to settle to charge kickback transients from the ADC input sampling. The
OPA197 is a 36-V operational amplifier that provides a very high input impedance front end, buffering the FDA inputs

Design References
See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.
Link to Key Files
Source files for this design – http://www.ti.com/lit/zip/sbac183.

Revision History
Revision Date Change
A March 2019 Downstyle the title and changed title role to 'Data Converters'.
Added link to circuit cookbook landing page.

High-input impedance, true differential, analog front end (AFE) SBAA267A – February 2018 – Revised March 2019
70 Submit Documentation Feedback
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 Analog Engineer's Circuit: Data
Converters
SBAA242A – December 2017 – Revised January 2019

High-voltage battery monitor circuit: ±20V, 0–10kHz,

18-bit fully differential

Bryan McKay, Arthur Kay

Input ADC Input Digital Output ADS8910

VinMin = –20V VoutDif = 4.8V, VoutP = 4.9V, VoutN = 0.1V 1EB85 H or 125829 10
VinMax = 20V VoutDif = –4.8V, VoutP = 0.1V, VoutN = 4.9V 2147B H or –125829 10
Power Supplies
Vcc Vee Vref Vcm
5.3 V 0V 5V 2.5 V

Design Description
This design translates an input bipolar signal of ±20V into a fully differential ADC differential input scale of
±4.8V, which is within the output linear operation of amplifiers. The values in the component selection
section can be adjusted to allow for different input voltage levels.
This circuit implementation is applicable in accurate voltage measurement applications such as Battery
Maintenance Systems, Battery Analyzers, Battery Testing Equipment, ATE, and Remote Radio Units
(RRU) in wireless base stations.
Cf1 1.3n

Rg1 100k Rf1 12k

Vcc Vref
Cfilt1 1.2n
5.4V 5.0V
VinMax 20 +
20V VoutP
- Rfilt1 47.5
- +0.1V
Rg2 100k INP RVDD VREF
+ +
U3
Rf2 12k OPA320 - ADS8910B
VoutDif
Vs
4.8V
Vcm 5V
+ INM
2.5V GND

Cf2 1.3n VoutN

+4.9V
Cf3 1.3n
Vs
5V

Rf3 12k
Rfilt2
+ 47.5
+
Rg3 100k
- -
20V U1
+ OPA320 Cfilt2 1.2n

Rf4 12k
Rg4 100k

Cf4 1.3n
Copyright © 2017, Texas Instruments Incorporated

SBAA242A – December 2017 – Revised January 2019 High-voltage battery monitor circuit:
Submit Documentation Feedback 71 ±20V, 0–10kHz,18-bit fully differential
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 www.ti.com

Specifications

Specification Calculated Simulated Measured

Transient ADC Input Settling < 0.5LSB or 19µV 6.6µV N/A
Noise 20.7µV rms 20.65µV rms 30.8µV rms
Bandwidth 10.2kHz 10.4kHz 10.4kHz

Design Notes
1. Determine the linear range of the op amp based on common mode, output swing, and linear open-loop
gain specification. This is covered in the component selection section.
2. For capacitors in the signal path, select COG type to minimize distortion. In this circuit Cf1, Cf2, Cf3,
Cf4, Cfilt1, and Cfilt2 need to be COG type.
3. Use 0.1% 20ppm/°C film resistors or better for good gain drift and to minimize distortion.
4. Precision labs video series covers methods for error analysis. Review the Statistics Behind Error
Analysis for methods to minimize gain, offset, drift, and noise errors.
5. The TI Precision Labs – ADCs training video series covers methods for selecting the charge bucket
circuit Rfilt and Cfilt. These component values are dependent on the amplifier bandwidth, data converter
sampling rate, and data converter design. The values shown here will give good settling and AC
performance for the amplifier, gain settings, and data converter in this example. If the design is
modified, select a different RC filter. Refer to Introduction to SAR ADC Front-End Component Selection
for an explanation of how to select the RC filter for best settling and AC performance.

High-voltage battery monitor circuit: SBAA242A – December 2017 – Revised January 2019
±20V, 0–10kHz,18-bit fully differential 72 Submit Documentation Feedback
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Component Selection
1. The general equation for this circuit.

2. Find op amp maximum and minimum output for linear operation.

3. Rearrange the equation from part 1 and solve for VoutDifMin and VoutDifMax. Find maximum and
minimum differential output voltage based on combined worst case from step 2.

4. Find differential gain based on results from step 3.

5. Find standard resistor values for differential gain. Use Analog Engineer's Calculator ("Amplifier and
Comparator\Find Amplifier Gain" section) to find standard values for Rf/Rg ratio.

6. Find Cf for cutoff frequency.

SBAA242A – December 2017 – Revised January 2019 High-voltage battery monitor circuit:
Submit Documentation Feedback 73 ±20V, 0–10kHz,18-bit fully differential
Copyright © 2017–2019, Texas Instruments Incorporated
 www.ti.com

DC Transfer Characteristics
The following graph shows a linear output response for inputs from –20V to +20V. Refer to Determining a
SAR ADC's Linear Range when using Operational Amplifiers for detailed theory on this subject.

T 5.00

2.50
Vin = 20V
Voltage (V)

VoutDif = 4.8V
0.00
Vin = -20V
VoutDif = -4.5V

-2.50

-5.00
-25 -20 -15 -10 -5 0 5 10 15 20 25
Input voltage (V)
AC Transfer Characteristics
The bandwidth is simulated to be 10.4 kHz, and the gain is –12.4dB which is a linear gain of 0.12. See Op
Amps: Bandwidth 1 for more details on this subject.

T -10.00

-20.00
Vdif
Gain (dB)

-30.00 fc = 10.4kHz

-40.00

-50.00

-60.00
10 100 1k 10k 100k 1MEG
Frequency (Hz)

High-voltage battery monitor circuit: SBAA242A – December 2017 – Revised January 2019
±20V, 0–10kHz,18-bit fully differential 74 Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com

Transient ADC Input Settling Simulation

The following simulation shows settling to a –20V dc input signal. This type of simulation shows that the
sample and hold kickback circuit is properly selected. Refer to Introduction to SAR ADC Front-End
Component Selection for detailed theory on this subject.
T
1.00
Vacq
0.00
1.00
Vconv
0.00
-2.29
Vdif
-2.40
1.00m
Verror Verror
4.6uV
-1.00m
2.00u 2.50u 3.00u
Time (s)
Noise Simulation
The following simplified noise calculation is provided for a rough estimate. We neglect resistor noise in this
calculation as it is attenuated for frequencies greater than 10kHz.

Note that calculated and simulated match well. Refer to Calculating the Total Noise for ADC Systems for
detailed theory on this subject.

T 20.65u
Total noise (V)

10.32u

0.00
10 100 1k 10k 100k 1MEG 10MEG 100MEG
Frequency (Hz)

SBAA242A – December 2017 – Revised January 2019 High-voltage battery monitor circuit:
Submit Documentation Feedback 75 ±20V, 0–10kHz,18-bit fully differential
Copyright © 2017–2019, Texas Instruments Incorporated
 www.ti.com

Measure FFT
This performance was measured on a modified version of the ADS8910BEVM. The AC performance
indicates SNR = 99.4dB, and THD = –116.4dB. See Introduction to Frequency Domain for more details on
this subject.

Noise Measurement
The following measured result is for both inputs connected to ground. The histogram shows the system
offset and noise. The standard deviation in codes is given by the EVM GUI (0.81), and this can be used to
calculate the RMS noise (30.9µV rms) as shown in the following equation.

High-voltage battery monitor circuit: SBAA242A – December 2017 – Revised January 2019
±20V, 0–10kHz,18-bit fully differential 76 Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com

Design Featured Devices

Device Key Features Link Similar Devices

ADS8900B (1) 18-bit resolution, 1-Msps sample rate, Integrated reference buffer, fully www.ti.com/product/ADS8900B www.ti.com/adcs
differential input, Vref input range 2.5V to 5V.
OPA320 (2) 20-MHz bandwidth, Rail-to-Rail with Zero Crossover Distortion, www.ti.com/product/OPA320 www.ti.com/opamp
VosMax = 150 µV, VosDriftMax = 5uV/°C, en = 7nV/rtHz
REF5050 (3) 3 ppm/°C drift, 0.05% initial accuracy, 4µVpp/V noise www.ti.com/product/REF5050 www.ti.com/vref

(1)
The REF5050 can be directly connected to the ADS8910B without any buffer because the ADS8910B has a built in internal reference
buffer. Also, the REF5050 has the required low noise and drift for precision SAR ADC applications. The OPA320 is also commonly used
in 1Msps SAR applications as it has sufficient bandwidth to settle to charge kickback transients from the ADC input sampling.
Furthermore, the zero crossover distortion rail-to-rail input allows for linear swing across most of the ADC input range.
(2)
The REF5050 can be directly connected to the ADS8910B without any buffer because the ADS8910B has a built in internal reference
buffer. Also, the REF5050 has the required low noise and drift for precision SAR ADC applications. The OPA320 is also commonly used
in 1Msps SAR applications as it has sufficient bandwidth.
(3)
The REF5050 can be directly connected to the ADS8910B without any buffer because the ADS8910B has a built in internal reference
buffer. Also, the REF5050 has the required low noise and drift for precision SAR ADC applications. The OPA320 is also commonly used
in 1Msps SAR applications as it has sufficient bandwidth.

Link to Key Files for High Voltage Battery Monitor

See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.
Design files for this circuit – http://www.ti.com/lit/zip/sbac171.

Revision History
Revision Date Change
A January 2019 Downstyle title, update title role content, added link to circuit cookbook library page.

SBAA242A – December 2017 – Revised January 2019 High-voltage battery monitor circuit:
Submit Documentation Feedback 77 ±20V, 0–10kHz,18-bit fully differential
Copyright © 2017–2019, Texas Instruments Incorporated
 Analog Engineer's Circuit: Data
Converters
SBAA264A – January 2018 – Revised March 2019

Single-ended to differential signal conversion using an op

amp and FDA for unipolar signals

Evan Sawyer

Input ADC Input Digital Output ADS7057

AINP = 0V 2000H
Vin Min = –3.3V
AINM = 3.3V 819210
AINP = 3.3V 1FFFH
Vin Max = 3.3V
AINM = 0V 819110

Power Supplies
AVDD GND DVDD
3.3V 0V 1.8V

Design Description
This design is intended to demonstrate how to convert a unipolar, single-ended signal into a unipolar, fully-
differential signal and drive a differential ADC (for more information on these and other signal types,
please refer to the TI Precision Labs training titled SAR ADC Input Types). Compared to a single-ended
device, a fully-differential ADC has twice the dynamic range which improves the AC performance of the
converter. Many common systems, for example Sonar Receivers, Flow Meters, and Motor Controls,
benefit from the higher performance of a differential ADC. The equations and explanation of component
selection in this design can be customized based on system specifications and needs. For more
information on a similar design using a bipolar input, see the cookbook circuit titled Single-Ended to
Differential Using an Op Amp and FDA for Bipolar Signals.
Cf1 30pF

Rg1 1kŸ Rf1 2kŸ

AVDD 3.3V
(Vs+) 5V
Vocm Rs1 10Ÿ Rfilt1 18.2Ÿ AVDD
1.65V -+ AINP

THS4551 Cfilt 330pF ADS7057

(V+) 5V + AINM
Rs2 10Ÿ Rfilt2 18.2Ÿ GND
-+ (Vs-) -0.3V

OPA320
Rg2 1kŸ Rf2 2kŸ
+
+

VSENSOR (V-) -0.3V Cf2 30pF

0 ± 3.3V
Copyright © 2018, Texas Instruments Incorporated

SBAA264A – January 2018 – Revised March 2019 Single-ended to differential signal conversion using
Submit Documentation Feedback 78 an op amp and FDA for unipolar signals
Copyright © 2018–2019, Texas Instruments Incorporated
 www.ti.com

Specifications

Specification Calculated Simulated

Transient ADC Input Settling (at 250ksps) < 0.5 · LSB = 201µV 144.8µV
Conditioned Signal Range (at 250ksps) > 99% ADC FSR = > 6.53V 6.60V
Noise 43.8µV / √Hz 44.3µV / √Hz

Design Notes
1. The ADS7057 was selected because of its throughput (2.5Msps), size (2.25mm²), and low-latency
(successive approximation register, or SAR, architecture).
2. Determine the linear range of the fully-differential amplifier (ADC driver) based on common mode,
output swing, and linear open-loop gain specification. This is covered in the component selection
section.
3. Determine the linear range of the op amp (signal conditioning) based on common mode, output swing,
and linear open-loop gain specification. This is covered in the component selection section.
4. Select COG (NPO) capacitors for Cfilt, to minimize distortion.
5. For best performance, consider using a 0.1% 20ppm/°C film resistor, or better, to minimize distortion.
6. The TI Precision Labs - ADCs training video series covers methods for selecting the charge bucket
circuit Rfiltx and Cfilt. These component values are dependent on the amplifier bandwidth, data converter
sampling rate, and data converter design. The values shown here will give good settling and AC
performance for the amplifier and data converter in this example. If you modify the design you will need
to select a different RC filter. Refer to Introduction to SAR ADC Front-end Component Selection (a TI
Precision Labs training video) for an explanation of how to select the RC filter for best settling and AC
performance.

Single-ended to differential signal conversion using SBAA264A – January 2018 – Revised March 2019
an op amp and FDA for unipolar signals 79 Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
www.ti.com

Component Selection
1. Select a fully-differential amplifier capable of driving the ADC:
THS4551 – Low noise, precision, 150MHz, fully-differential amplifier
• Wide input common-mode voltage:
Vs 0.1 V Vcm Vs 1.3V
• Linear output (requirement: 0V to 3.3V at each output):
Vs 0.22V Vout Vs 0.22V
2. Select a wide bandwidth operational amplifier:
OPA320 – Precision, zero-crossover, 20MHz, RRIO, operational amplifier
• Gain bandwidth product >12.5MHz (>5 times the sampling rate)
• Input common-mode voltage (requirement: 0 - 3.3V):
V 0.1V Vcm V 0.1V
• Linear output:
V 0.03V Vout V 0.03V
V 0.2V Vout V 0.2V
• Combined worst-case linear range (calculated from supplies used with OPA320):
0.1V Vout 4.8V

NOTE: The operational amplifier is used to protect the sensor from any charge kickbacks that occur
when the ADC connects or disconnects the sampling capacitor. This amplifier may not be
needed if the sensor has a high-output impedance. A negative rail is used for both the
OPA320 and THS4551 based on the assumption that the sensor is operating with a negative
rail. This also ensures the highest performance from the ADC by providing the full scale input
range.

3. Select Rfx and Rgx

• The combination of Rfx and Rgx sets the gain of the system. With an input range of 0V - 3.3V and
an ADC full scale of ±3.3V, a gain of 2 was selected for this system.
• The values of Rfx = 2k and Rgx = 1k were selected to both provide the desired gain as well as limit
the current through the feedback network, thus minimizing power consumption of the system.
4. Select Rsx
• It is important to connect small resistors at the output of the amplifier, in this case 10Ω, to flatten
the output impedance and improve stability of the system.
5. Select Rfiltx and Cfilt values for settling of 250-kHz input signal and sample rate of 2.5Msps:
• Refine the Rfilt and Cfilt Values is a Precision Labs Video showing the methodology for selecting Rfiltx
and Cfilt. The final value of 18.2Ω and 330pF proved to settle to well below ½ of a least significant
bit (LSB) within the acquisition window.

SBAA264A – January 2018 – Revised March 2019 Single-ended to differential signal conversion using
Submit Documentation Feedback 80 an op amp and FDA for unipolar signals
Copyright © 2018–2019, Texas Instruments Incorporated
 www.ti.com

DC Transfer Characteristics
The following graph shows the simulated output for a 0 - 3.3V input. The analog front end has a linear
output of ±3.3V which matches the full-scale range (FSR) of the ADC (with AVDD = 3.3V).

AC Transfer Characteristics
The bandwidth of the analog front end is simulated to be 4.12MHz at the gain of 0dB which is a linear gain
of 1. This bandwidth will allow the inputs of the ADC to adequately settle for a 250-ksps input signal.
T
10

0
fc = 2.45 MHz
-10

-20 BW = 4.12 MHz

Gain (dB)

-30

-40

-50

-60

-70
10 100 1k 10k 100k 1M 10M 100M
Frequency (Hz)

Single-ended to differential signal conversion using SBAA264A – January 2018 – Revised March 2019
an op amp and FDA for unipolar signals 81 Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
www.ti.com

Transient ADC Input Settling Simulation

The following simulation shows the ADC sample and hold capacitor settling for a 3.3-V DC input signal.
This simulation shows that the analog front end is able to drive the ADC with a large step input (from 0V to
3.3V) so it settles to within ½ of an LSB (approximately 200µV) in the allotted acquisition time (95ns).
Refer to Introduction to SAR ADC Front-End Component Selection for detailed theory on this subject, and
follow the link at the end of this design to download these simulation files.
T
1.00

Vacq

0.00
500u

|Verror| =
144.8µV
Verror (V) 0

-500u
0.00 400n 800n 1.20u 1.60u 2.00u
Time (s)

SBAA264A – January 2018 – Revised March 2019 Single-ended to differential signal conversion using
Submit Documentation Feedback 82 an op amp and FDA for unipolar signals
Copyright © 2018–2019, Texas Instruments Incorporated
 www.ti.com

Noise Simulation
This section walks through a simplified noise calculation, providing a rough estimate to compare with the
simulated result. The resistor noise is included in this calculation as it is a significant portion of the overall
noise of the system. Note that the resistor noise can be reduced by using smaller value resistors, but at
the expense of increased power consumption through the feedback network.
1 1
fc 2.65MHz
2 u Πu 5 filt u & filt u Πu k: u pF
En eOPA320 u 2 u K n u f c 7nV / Hz u 2 u 1.57 u 2.65MHz 20.2 PV / Hz

E n _ OPA320 E n u Gain 20.2 PV / Hz u 2 40.4 PV / Hz

E n _ THS 4551 e nTHS4551 u 2 u K n u f c 3.3nV / Hz u 2 u 1.57 u 2.65MHz 9.52 PV / Hz
23
4 u k u T u Rg R 4 u 1.38 u 10 u 273.15 25 u 1000 2000
ERg 9
u f u 2 9
u u 2 11.47 PV / Hz
1 u 10 Rg 1 u 10 1000

4 u k u T u Rf 4 u 1.38 u 10 23 u 273.15 25 u 2000

E Rf u 2 u 2 8.11PV / Hz
1 u 10 9 1 u 10 9
Total noise at output equation:
En E nOPA320 2 E n _ THS 45512 ERg 2 E Rf 2 40.42 9.522 11.472 8.112 43.8PV / Hz

Note that calculated and simulated match well. Refer to the TI Precision Labs - ADCs training video series
for detailed theory on this subject.
T
50u

40u
Total noise (V)

30u Noise =
44.3µV/O,Ì
20u

10u

0
1 10 100 1k 10k 100k 1M 10M 100M 1G
Frequency (Hz)

Single-ended to differential signal conversion using SBAA264A – January 2018 – Revised March 2019
an op amp and FDA for unipolar signals 83 Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
www.ti.com

Design Featured Devices

Device Key Features Link Similar Devices

ADS7057 14 bit, 2.5 Msps, fully-differential input, SPI, 2.25mm2 package www.ti.com/product/ADS7057 www.ti.com/adcs
THS4551 150MHz, 3.3nV/√Hz input voltage noise, fully-differential www.ti.com/product/THS4551 www.ti.com/opamp
amplifier
OPA320 Precision, zero-crossover, 20MHz, 0.9pA Ib, RRIO, operational www.ti.com/product/OPA320 www.ti.com/opamp
amplifier

NOTE: The ADS7057 uses the AVDD as the reference input. A high-PSRR LDO, such as the
TPS7A47, should be used as the power supply.

Design References
See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.
Link to Key files (TINA):
Design files for this circuit – http://www.ti.com/lit/zip/sbac188.
Link to Related Cookbooks:
Single-Ended to Differential Signal Conversion for Bipolar Input

Revision History
Revision Date Change
A March 2019 Downstyle the title and changed title role to 'Data Converters'.
Added link to circuit cookbook landing page.

SBAA264A – January 2018 – Revised March 2019 Single-ended to differential signal conversion using
Submit Documentation Feedback 84 an op amp and FDA for unipolar signals
Copyright © 2018–2019, Texas Instruments Incorporated
 Analog Engineer's Circuit: Data
Converters
SBAA246A – January 2018 – Revised March 2019

Single-ended-to-differential circuit using an op amp and

fully differential amplifier (FDA) for bipolar signals

Evan Sawyer

Input ADC Input Digital Output ADS7057

AINP = 0V 2000H
Vin Min = –3.3V
AINM = 3.3V 819210
AINP = 3.3V 1FFFH
Vin Max = 3.3V
AINM = 0V 819110

Power Supplies
AVDD GND DVDD
3.3V 0V 1.8V

Design Description
This design is intended to demonstrate how to convert a bipolar, single-ended signal into a unipolar, fully-
differential signal and drive a differential ADC (for more information on these and other signal types,
please refer to the TI Precision Labs training titled SAR ADC Input Types). Compared to a single-ended
device, a fully-differential ADC has twice the dynamic range which improves the AC performance of the
converter. Many common systems, for example Sonar Receivers, Flow Meters, and Motor Controls,
benefit from the higher performance of a differential ADC. The equations and explanation of component
selection in this design can be customized based on system specifications and needs. For more
information on a similar design using a unipolar input signal, see the cookbook circuit titled Single-Ended
to Differential Signal Conversion for Unipolar Inputs.
Cf1 30pF

Rg1 1kŸ Rf1 2kŸ

AVDD 3.3V
(Vs+) 5V
Rs1 10Ÿ Rfilt1 18.2Ÿ
AVDD
-+ AINP
Vocm
THS4551 Cfilt 330pF ADS7057
1.65V
(V+) 2.5V AINM
+ Rs2 10Ÿ GND
Rfilt2 18.2Ÿ
-+ (Vs-) -0.3V

OPA320
Rg2 1kŸ Rf2 2kŸ
+
+

VSENSOR (V-) -2.5V

Cf2 30pF
±1.65V
Copyright © 2018, Texas Instruments Incorporated

SBAA246A – January 2018 – Revised March 2019 Single-ended-to-differential circuit using an op amp
Submit Documentation Feedback 85 and fully differential amplifier (FDA) for bipolar signals
Copyright © 2018–2019, Texas Instruments Incorporated
 www.ti.com

Specifications

Specification Calculated Simulated

Transient ADC Input Settling (at 250ksps) < 0.5 · LSB = 201µV 134.7µV
Conditioned Signal Range (at 250ksps) > 99% ADC FSR = > 6.60V
6.53V
Noise 43.8µV / √Hz 44.3µV / √Hz

Design Notes
1. The ADS7057 was selected because of its throughput (2.5Msps), size (2.25mm²) and low-latency
(successive approximation register, or SAR, architecture).
2. Determine the linear range of the fully-differential amplifier (ADC driver) based on common mode,
output swing, and linear open-loop gain specification. This is covered in the component selection
section.
3. Determine the linear range of the op amp (signal conditioning) based on common mode, output swing,
and linear open-loop gain specification. This is covered in the component selection section.
4. Select COG (NPO) capacitors for Cfilt, to minimize distortion.
5. For best performance, consider using a 0.1% 20ppm/°C film resistor, or better, to minimize distortion.
6. The TI Precision Labs - ADCs training video series covers methods for selecting the charge bucket
circuit Rfiltx and Cfilt. These component values are dependent on the amplifier bandwidth, data converter
sampling rate, and data converter design. The values shown here will give good settling and AC
performance for the amplifier and data converter in this example. If the design is modified, a different
RC filter must be selected. Refer to Introduction to SAR ADC Front-end Component Selection (a TI
Precision Labs training video) for an explanation of how to select the RC filter for best settling and AC
performance.

Single-ended-to-differential circuit using an op amp SBAA246A – January 2018 – Revised March 2019
and fully differential amplifier (FDA) for bipolar signals 86 Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
www.ti.com

Component Selection
1. Select a fully-differential amplifier capable of driving the ADC:
THS4551 – Low noise, precision, 150MHz, fully-differential amplifier
• Wide input common-mode voltage:
Vs 0.1 V Vcm Vs 1.3V
• Linear output (requirement: 0V to 3.3V at each output):
Vs 0.22V Vout Vs 0.22V
2. Select a wide bandwidth operational amplifier:
OPA320 – Precision, zero-crossover, 20MHz, RRIO, operational amplifier
• Gain bandwidth product > 12.5MHz (> 5 times the sampling rate)
• Input common-mode voltage (requirement: ±1.65V):
V 0.1V Vcm V 0.1V
• Linear output:
V 0.03V Vout V 0.03V
V 0.2V Vout V 0.2V
• Combined worst-case linear range (calculated from supplies used with OPA320):
2.3V Vout 2.3V

NOTE: The operational amplifier is used to protect the sensor from any charge kickbacks that occur
when the ADC connects or disconnects the sampling capacitor. This amplifier may not be
needed if the sensor has a high output impedance. A negative rail is used for both the
OPA320 and THS4551 based on the assumption that the sensor is operating with a negative
rail. This also ensures the highest performance from the ADC by providing the full scale input
range.

3. Select Rfx and Rgx

• The combination of Rfx and Rgx sets the gain of the system. With an input range of ±1.65V and an
ADC full scale of ±3.3V, a gain of 2 was selected for this system.
• The values of Rfx = 2k and Rgx = 1k were selected to both provide the desired gain as well as limit
the current through the feedback network, thus minimizing power consumption of the system.
4. Select Rsx
• It is important to connect small resistors at the output of the amplifier, in this case 10Ω, to flatten
the output impedance and improve stability of the system.
5. Select Rfiltx and Cfilt values for settling of 250-kHz input signal and sample rate of 2.5Msps:
• Refine the Rfilt and Cfilt Values is a TI Precision Labs video showing the methodology for selecting
Rfiltx and Cfilt. The final value of 18.2Ω and 330pF proved to settle to well below ½ of a least
significant bit (LSB) within the acquisition window.

SBAA246A – January 2018 – Revised March 2019 Single-ended-to-differential circuit using an op amp
Submit Documentation Feedback 87 and fully differential amplifier (FDA) for bipolar signals
Copyright © 2018–2019, Texas Instruments Incorporated
 www.ti.com

DC Transfer Characteristics
The following graph shows the simulated output for a ±1.65-V input. The analog front end has a linear
output of ±3.3V which matches the full-scale range (FSR) of the ADC (with AVDD = 3.3V).
3.5

2.5

1.5 Vin = 1.65V

Output Voltage (V)

Vout = 3.30V
500.0m

-500.0m Vin = -1.65V

Vout = -3.30V
-1.5

-2.5

-3.5
-1.70 0.00 1.70
Input Voltage (V)
AC Transfer Characteristics
The bandwidth of the analog front end is simulated to be 4.12MHz at the gain of 0dB which is a linear gain
of 1. This bandwidth will allow the inputs of the ADC to adequately settle for a 250-ksps input signal.
10

0
fc = 2.45 MHz
-10
BW = 4.12 MHz
-20
Gain (dB)

-30

-40

-50

-60

-70
10 100 1k 10k 100k 1M 10M 100M
Frequency (Hz)

Single-ended-to-differential circuit using an op amp SBAA246A – January 2018 – Revised March 2019
and fully differential amplifier (FDA) for bipolar signals 88 Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
www.ti.com

Transient ADC Input Settling Simulation

The following simulation shows the ADC sample and hold capacitor settling for a 3.3-V DC input signal.
This simulation shows that the analog front end is able to drive the ADC with a large step input (from 0V to
3.3V) so it settles to within ½ of an LSB (approximately 200µV) in the allotted acquisition time (95ns).
Refer to Introduction to SAR ADC Front-End Component Selection for detailed theory on this subject, and
follow the link at the end of this design to download these simulation files.
1.00

Vacq

0.00
500u

|Verror| =
134.7µV
Verror (V) 0.00

-500u
0.00 400n 800n 1.20u 1.60u 2.00u
Time (s)

SBAA246A – January 2018 – Revised March 2019 Single-ended-to-differential circuit using an op amp
Submit Documentation Feedback 89 and fully differential amplifier (FDA) for bipolar signals
Copyright © 2018–2019, Texas Instruments Incorporated
 www.ti.com

Noise Simulation
This section walks through a simplified noise calculation, providing a rough estimate to compare with the
simulated result. The resistor noise is included in this calculation as it is a significant portion of the overall
noise of the system. Note that the resistor noise can be reduced by using smaller value resistors, but at
the expense of increased power consumption through the feedback network.
1 1
fc 2.65MHz
2 u Πu 5 filt u & filt u Πu k: u pF
En eOPA320 u 2 u K n u f c 7nV / Hz u 2 u 1.57 u 2.65MHz 20.2 PV / Hz

E n _ OPA320 E n u Gain 20.2 PV / Hz u 2 40.4 PV / Hz

E n _ THS 4551 e nTHS4551 u 2 u K n u f c 3.3nV / Hz u 2 u 1.57 u 2.65MHz 9.52 PV / Hz
23
4 u k u T u Rg R 4 u 1.38 u 10 u 273.15 25 u 1000 2000
ERg 9
u f u 2 9
u u 2 11.47 PV / Hz
1 u 10 Rg 1 u 10 1000

4 u k u T u Rf 4 u 1.38 u 10 23 u 273.15 25 u 2000

E Rf u 2 u 2 8.11PV / Hz
1 u 10 9 1 u 10 9
Total noise at output equation:
En E nOPA320 2 E n _ THS 45512 ERg 2 E Rf 2 40.42 9.522 11.472 8.112 43.8PV / Hz

Note that calculated and simulated match well. Refer to the TI Precision Labs - ADCs training video series
for detailed theory on this subject.

50u

40u
Total noise (V)

30u Noise =
44.3µV/O,Ì

20u

10u

0
1 10 100 1k 10k 100k 1M 10M 100M 1G
Frequency (Hz)

Single-ended-to-differential circuit using an op amp SBAA246A – January 2018 – Revised March 2019
and fully differential amplifier (FDA) for bipolar signals 90 Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
www.ti.com

Design Featured Devices

Device Key Features Link Similar Devices

ADS7057 14 bit, 2.5 Msps, fully-differential input, SPI, 2.25mm2 package www.ti.com/product/ADS7057 www.ti.com/adcs
THS4551 150-MHz, 3.3-nV/√Hz input voltage noise, fully-differential amplifier www.ti.com/product/THS4551 www.ti.com/opamp
OPA320 Precision, zero-crossover, 20-MHz, 0.9-pA Ib, RRIO, operational amplifier www.ti.com/product/OPA320 www.ti.com/opamp

NOTE: The ADS7057 uses the AVDD as the reference input. Use a high-PSRR LDO, such as the
TPS7A47, as the power supply.

Design References
See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.
Link to key files (TINA):
Design files for this circuit – http://www.ti.com/lit/zip/sbac181.
Link to Related Cookbooks
Single-Ended to Differential Signal Conversion for Unipolar Input

Revision History
Revision Date Change
A March 2019 Downstyle the title and changed title role to 'Data Converters'.
Added link to circuit cookbook landing page.

SBAA246A – January 2018 – Revised March 2019 Single-ended-to-differential circuit using an op amp
Submit Documentation Feedback 91 and fully differential amplifier (FDA) for bipolar signals
Copyright © 2018–2019, Texas Instruments Incorporated
 Analog Engineer's Circuit: Data
Converters
SBAA265 – October 2018

Single-ended to differential using a two op-amp circuit

Bryan McKay, Art Kay

Input ADC Differential Input (Vdif) ADC Common-Mode Input Digital Output ADS9110
(Vcm)
0V –5V 2.5V 20000H
5V +5V 2.5V 1FFFFH

Power Supplies
V+ (op amp) AVDD DVDD REFP
5V 5V 3V 5V

Design Description
This circuit uses two OPA320 op amps to perform a single-ended to differential conversion for driving the
ADS8912B fully-differential ADC. Another approach to solve this problem uses a fully-differential amplifier
(FDA). See Single-Ended to Differential Conversion Using an Op Amp and FDA for Unipolar Signals for
the FDA example. Since there are many thousands of different types of op amps available, finding an op
amp the meets your specific requirements may be easer than finding an fully-differential amplifier. Most
FDAs, for example, do not have as good swing to the rail, offset, bias current, and drift as many precision
op amps have. On the other hand, the op-amp approach has an asymmetrical group delay in the inverting
and non-inverting paths. Furthermore, FDA amplifiers often have better distortion and ADC drive
characteristics. In general, the FDA approach will achieve best SNR and THD, and the op-amp approach
will achieve best DC characteristics. Nevertheless, the specific op amp or FDA will impact the comparison
of the two typologies.

Cflt1
120p 5V 5V 3V
Rflt1 0V
- 47.5 REFP AVDD DVDD
+5V
AIN_P
++ U1
OPA320 Cflt2 ADS8912B
+

Vin
0V 1.2n
+5V Rg Rf
+5V AIN_M
1k 1k +5V
0V
Rfilt2
47.5
Cflt3
120p
Vcm
2.5V -

++
U2 OPA320

+5V

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Specifications

Specification Goal Calculated Simulated

Transient ADC Input Settling < 0.5LSB = 19.1µV NA 5µV
(1MSPS)
Input Output Range NA NA 0.1 < VIN < 4.9V
–4.8V < VOUT < 4.8V
Noise NA 30.5µVRMS 28.4µVRMS

Design Notes
1. Use 0.1% resistors for R1 and Rg to minimize gain error and drift on U2.
2. Select COG (NPO) capacitors for Cfilt1, Cfilt2, and Cfilt3 to minimize distortion.
3. The TI Precision Labs – ADCstraining video series covers methods for selecting the charge bucket
circuit Rfilt and Cfilt. These component values are dependent on the amplifier bandwidth, data converter
sampling rate, and data converter design. The values shown here will give good settling and AC
performance for the amplifier and data converter in this example. If you modify this design you will
need to select a different RC filter. See the Introduction to SAR ADC Front-End Component Selection
training video for an explanation of how to select the RC filter for best settling and AC performance.

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Component Selection
1. Select an op amp to meet the system requirements. Key specifications to consider follow:
• Swing to rail - For 5-V supply rails it is common to use a rail-to-rail zero crossover distortion device
(for example, OPA320, OPA325, and OPA365).
• Offset voltage and Drift - One of the advantages of this circuit over the FDA approach is that some
op-amps can have very good DC performance.
• Bandwidth and quiescent current - Another advantage of this circuit over the FDA approach is that
a wide range of op-amp bandwidth and related quiescent currents are available. For lower
sampling rate a low bandwidth low current op amp may be a good choice.
2. Choose Rg and Rf to minimize noise. The gain of this circuit is always 1, so Rg = Rf. The main
consideration here is to minimize noise while keeping the load resistance reasonable. Set the resistor
noise to be roughly ⅓ of the amplifier noise. In this example Rf = Rg = 1kΩ gives a noise of 2.8nV/√Hz
which is approximately ⅓ of the 7nV/√Hz op-amp noise. Also, the maximum load current is 2.5mA (5V
/ 2kΩ = 2.5mA) which is low compared to the op-amp short-circuit limit (65mA).
3. Find Rfilt and Cfilt to allow for settling at 1kSPS. See Refine the Rfilt and Cfilt Values for the algorithm to
select Rfilt and Cfilt. The final value of 200kΩ and 510pF proved to settle to well below ½ of a least
significant bit (LSB).

SBAA265 – October 2018 Single-ended to differential using a two op-amp circuit

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DC Transfer Characteristics
The following graph shows the DC transfer characteristics for this circuit (0-V to 5-V single-ended input,
–5-V to +5-V fully-differential output). Note that the linear range is limited to about 0.1V from both supply
rails (Vin linear range approximately 0.1V to 4.9V). The limitation is from the amplifier output swing limit.
For improved linear swing the negative and positive supply on the amplifiers would need to be adjusted.
See Low-Power Sensor Measurements: 3.3-V, 1-ksps, 12-bit, Single-Ended, Dual-Supply Circuit for an
example on how to do this.
5.00

2.50 (4.89, 4.78)

Vdif 0.00

-2.50 (0.1, -4.77)

-5.00
-1.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0
Input voltage (V)
AC Transfer Characteristics
In this case the bandwidth limitation is primary set by the Rfilt, Cfilt values. The amplifier closed loop
bandwidth can also impact the overall bandwidth. Note the bandwidth of U2 is half the bandwidth of U1 as
its noise gain is two (BWU2 = GBW/Gn = 20MHz/2 = 10MHz).

1 1
fc 1.4MHz
2S R ˜ C 2S (2 ˜ 47.5:) ˜ 1.2nF
6.02

fc = 1.58MHz
Gain (dB)

-25.72

-57.46
1k 10k 100k 1M 10M 100M
Frequency (Hz)

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Group Delay (Frequency Domain)

Group delay is the time delay between the applied input signal and the output signal. All amplifiers and
filters will have a group delay. Group delay is highlighted for this circuit because the inverting and non-
inverting path both have different group delays. This can create distortion for higher frequency signals.
See the group delay in time domain plot for additional detail.
144n

Voutp Voutn
delay = 128ns
Time (s)

delay = 143ns
72n

0.00
1k 10k 100k 1M 10M
Frequency (Hz)
Group Delay (Time Domain)
The following graph shows qualitatively how group delay can effect time domain signals. The errors in this
plot are exaggerated to emphasize the effect of group delay. The green signal represents the output on
AIN_P and the blue signal represents the inverted output on AIN_N. Ideally, the two signals should track,
but the group delay shifts the blue signal to the right. Notice that when signals are moving slowly the error
is relatively small and when they are moving rapidly the error is larger. Thus, low frequency signals will
have good distortion, and higher frequency signals will have degraded distortion. SPICE does not simulate
THD, so for quantitative values measurement is required. However, if the input signal period more than
1,000 times larger than the group delay between the channels than this effect can generally be neglected.
Large Error for fast
moving signals AIN_N
(inverted)

Small Error for slow

moving signals
Voltage

AIN_P

Time
Group
Delay

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Noise Simulation
The following noise calculation considers the amplifier and resistor noise. Note that the noise from U1 is
inverted by U2 and added at the differential output. Since this noise is directly correlated, it adds directly
as opposed to root sum square addition usually used for noise sources. Also note that the output filter is
approximated as first order but it is a more complex filter. The calculated noise compares well to the
simulated noise (calculated = 30.5µVRMS, simulated = 28.4µVRMS).

enU 1 en 320 en 320 7 nV Hz 7 nV Hz 14 nV Hz Note these two sources are correlated

Rf ˜ Rg 1k : ˜ 1k :
Req 500:
Rf Rg 1k : 1k :
23
en Re q 4K n ˜ TK ˜ Req 4(1.38 ˜ 10 J K ) ˜ (298.15) ˜ (500:) 2.87 nV Hz
2 2 2 2
enU 2 en Re q ˜ Gn en 320 ˜ Gn 2.87 nV Hz ˜ 2 7 nV Hz ˜ 2 15.1nV Hz

2 2 2 2
enT enU 1 enU 2 14 nV Hz 15.1nV Hz 20.6 nV Hz
1 1
fc 1.4MHz
2S R ˜ C 2S (2 ˜ 47.5:) ˜ 1.2nF
EnT enT ˜ 1.57 ˜ fc 20.6 nV Hz ˜ 1.57 ˜ 1.4MHz 30.5 PVRMS
The calculated noise compares well to the simulated noise (calculated = 30.5µVRMS, simulated =
28.4µVRMS). See Calculating the Total Noise for ADC Systems for detailed theory on this subject.
28.42u

28.42µV
Total noise (V)

14.21u

0.00
100 1k 10k 100k 1M 10M 100M
Frequency (Hz)

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Transient ADC Input Settling Simulation

The following simulation shows settling to a full scale DC input signal at 500kSPS. This type of simulation
shows that the sample and hold kickback circuit is properly selected. See Introduction to SAR ADC Front-
End Component Selection for detailed theory on this subject.
1.00
Vacq

0.00
1.00
Vconv

0.00
20u
Verror 0
Verror = 5uV
-20u
2.00u 3.00u 4.00u
Time (s)

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Design Featured Devices

Device Key Features Link Other Possible Devices

ADS8912 18-bit resolution, 500-kSPS sample rate, integrated reference http://www.ti.com/product/ADS8912 http://www.ti.com/adcs
buffer, fully-differential input, Vref input range 2.5V to 5V. B
OPA320 20-MHz bandwidth, Rail-to-Rail with zero crossover distortion, http://www.ti.com/product/OPA320 http://www.ti.com/opamps
VosMax = 150 μV, VosDriftMax = 5μV/C, en = 7 nV/√Hz

Design References
See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.
Link to Key Files
Source files for this circuit - http://www.ti.com/lit/zip/SBAC193.

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 Analog Engineer's Circuit: Data
Converters
SBAA315A – October 2018 – Revised November 2018

True differential, 4 × 2 MUX, analog front end,

simultaneous-sampling ADC circuit

Luis Chioye

Input (THS4551 Inputs) ADC Input (THS4551 Output) Digital Output ADS7042
VinP = +0.23V, VinN =+3.866V, VoutP = +0.23V, VoutN = 3.866V, 8E60H -2908810
VinMin(Dif) = -3.636V Vout(Dif) = -3.636V
VinP = +3.866V, VinN =0.23V, VoutP = 3.866V, VoutN = +0.23V, 71A0H +2908810
VinMax(Dif) = +3.636V Vout(Dif) = +3.636V

Power Supplies
Vcc Vee Vref Vocm
5 0V 4.096V 2.048V

Design Description
This dual simultaneous-sampling SAR ADC and 4 × 2 channel multiplexed analog front end data
acquisition solution can measure differential voltage signals in the range of ±3.866V supporting ADC
sampling rates up to 3-MSPS (or effective sampling rate of 750-kSPS per channel) with 16-B resolution.
The circuit consists of a dual simultaneous sampling SAR ADC, with each SAR ADC connected to two 4:1
(2x) multiplexers, providing 4 differential input channels per ADC. Eight Fully Differential Amplifiers (FDAs)
drive the multiplexed SAR ADC inputs. This circuit is applicable in the accurate measurement of dual
simultaneous signals in applications such as Optical Modules and Analog Input Modules. It also can be
used in motor drive applications such as Servo Drive Control Module, Servo Drive Position Feedback, and
Servo Drive Position Sensor.
REFby2

4 Channels per ADC 1µF

REFby2
INN_x Rg1 1NŸ Cf1 3pF (2.048V output)
Rfil1 30.1Ÿ
SxA
Rf1 1NŸ
REFby2
2.048V +5V Riso1 15pF DA AINP_A
- 10Ÿ
Vocm + Cfil
+
- 150pF 4:1 MUX ADC_A
100nF Riso2
10Ÿ DB AINM_A
15pF
Rfil2 30.1Ÿ
Rf2 1NŸ SxB
INP_x Rg2 1NŸ Cf2 3pF
THS4551 (4x)
TMUX1109 ADS9224R
Dual,
Simultaneous-Sampling
Low-Latency
INN_x SAR ADC
Rg1 1NŸ Cf1 3pF
Rfil1 30.1Ÿ
Rf1 1NŸ SxA
REFby2
2.048V +5V Riso1 15pF DA AINP_B
- 10Ÿ
Cfil
Vocm +
- 150pF
4:1
+ ADC_B
100nF Riso2 MUX
10Ÿ DB AINM_B
15pF
Rfil2 30.1Ÿ
Rf2 1NŸ
SxB
INP_x Rg2 1NŸ Cf2 3pF TMUX1109
THS4551 (4x)

4 Channels per ADC

SBAA315A – October 2018 – Revised November 2018 True differential, 4 × 2 MUX, analog front end,
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Specifications

Specification Goal Calculated Simulated

Dual ADC Sampling Speed 3-MSPS 3-MSPS 3-MSPS
Sampling Rate per Channel 750-kSPS 750-kSPS 750-kSPS
(dual, simultaneous) (3-MSPS / 4) (3-MSPS / 4) (3-MSPS / 4)
Transient ADC Input Settling << 1 LSB NA 20 µV
<< 125 µV
Noise (at ADC Input) 50µVrms 55.9µVrms 51.1µVrms

Design Notes
1. The ADS9224R was selected because of the dual simultaneous sampling and high throughput (3-
MSPS) requirements.
2. The TMUX1109 4:1 (2x) multiplexer was selected to support 4-channel differential inputs for each
ADC.
3. Find ADC full-scale range, resolution and common-mode range specifications. This is covered in the
component selection.
4. Determine the linear range of the FDA (THS4551) based on common-mode and output swing
specification. This is covered in the component selection section.
5. Select COG capacitors for all filter capacitors at the ADC input to minimize distortion.
6. Select the FDA gain resistors RF1,2 , RG1,2. Use 0.1% 20ppm/°C film resistors or better for good
accuracy, low gain drift and to minimize distortion.
7. Introduction to SAR ADC Front-End Component Selection covers the methods for selecting the charge
bucket circuit Rfil1, Rfil1 and Cfil. These component values are dependent on the amplifier bandwidth,
data converter sampling rare, and data converter design. The values shown here will give good settling
and AC performance for the amplifier and data converter in this example. If the design is modified, a
different RC filter must be selected.
8. The THS4551 is commonly used in high-speed precision fully differential SAR applications as it has
sufficient bandwidth to settle to charge kickback transients from the ADC input sampling, and
multiplexer charge injection and provides the common-mode level shifting to the voltage range of the
SAR ADC.

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Component Selection

1. Find ADC full-scale input range. In this circuit, ADS9224 internal V_REF= 2.5V
ADCFull Scale Range r 1.6384V V ˜ VREF r4.096V from ADS9224R datasheet
2. Find required ADC common-mode voltage 2.
ADCFull Scale Range
VCM 2.048V from ADS9224R datasheet
2
Use REFby2 Output pin of ADS9224R to connect to FDA THS4551 VCOM = 2.048V
3. Find FDA absolute output voltage range for linear operation:
0.23V Vout 4.77V from THS4551 output low/high specification for linear operation
4. Find FDA differential output voltage range for linear operation. The general output voltage
equations for this circuit:
VoutDifMin
VoutMin Vcm
2
VoutDifMax
VoutMax Vcm
2
Rearrange the equations and solve for VoutDifMinand VoutDifMax . Find maximum differential output
voltage range based on worst case:
VoutDifMax 2 ˜ VoutMax 2 ˜ Vcm 2 ˜ 4.096V 2 ˜ 2.048V 4.096V
VoutDifMin 2 ˜ VoutMin 2 ˜ Vcm 2 ˜ 0.23V 2 ˜ 2.048V 3.636V
Based on combined worst case, chooseVoutDifMin = -3.636V and VoutDifMax = +3.636V
5. Set FDA gain to 1 V/V
Rf 1.00k
GainFDA 1V V
Rg 1.00k
6. Select the minimum charge kickback capacitor filter to optimize circuit for fastest settling.
Csh 16 pF internal sample-and-hold capacitor from ADS9224R datasheet
Select a capacitor 10x larger than Cfil 150 pF
7. Optimize RC charge kickback filter resistors Rfil 1,Rfil 2 and feedback capacitors Cf 1,Cf 2 for both
settling and stability using TINA simulations. This is covered in the transient settling optimization
and stability simulation sections.

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Transient Settling Optimization

TINA simulation is used to optimize the RC kickback filter for stability and transient settling. The transient
simulation incorporates two adjacent channels of the multiplexer (TMUX1109). To simulate worst case
transient settling during the multiplexer scanning sequence, the two adjacent channels are set to a voltage
close to positive full-scale and negative full-scale respectively. The multiplexer drain capacitance and
series resistance are modeled in the multiplexer simulation circuit. The sample and hold capacitor of the
SAR ADC must settle within the 16-Bit resolution of the SAR ADC during the acquisition period. A
simplified schematic of the simulation circuit follows:

Cf1 3p
Rfil1 Ron SW-S1A
INN_CH1 Rg 1k 49.9 S1A 4Ÿ

+5V Rf1 1k
± Riso1 Cs
- 10 9pF
Voltage Close to + Cdiff
- 82p
Positive Full-Scale + Rs1
Riso2 SW1
THS4551 120Ÿ
10 DA AINP
+ Rfil2 Ron SW-S2A
Rf2 1k 49.9 S2A 4Ÿ
Cs1
Cd 1pF 16 pF
INP_CH1 Rg 1k
Cs 35pF
Cf2 3p 9pF
Cs2
SW2 16 pF
Cf1 3p DB AINM
Rfil1 Ron SW-S1B
INN_CH1 Rg 1k 4Ÿ Rs2
49.9 S1B
120Ÿ
Cd 1pF
+5V Rf1 1k
Riso1 Cs 35pF
± 9pF
- 10
Cdiff
Voltage Close to +
- 82p ADS9224R
Negative Full-Scale + Riso2
THS4551 10 Simplified SAR ADC
Rfil2 Ron SW-S2B
+ Rf2 1k 4Ÿ
Model
49.9 S2B
INP_CH2 Rg 1k
Cs
Cf2 3p 9pF TMUX1109

Simplified Mux Model

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Multiplexer and ADC Control Timing

The following plot shows the ADC conversion control (CONVST) and multiplexer channel control timing.
The ADS9224R supports a maximum sampling rate of 3-MSPS or a minimum cycle time of 333ns. To
avoid switching channels prior to the rising edge of the CONVST signal, a small delay is implemented in
the MUX channel control timing after the CONVST rising edge. Refer to TI design 16-Bit, 400-kSPS, Four-
Channel MUX Data Acquisition System for High-Voltage Inputs Reference Design for detailed theory in
the subject.
tcycle > 333ns (3-MSPS)

CONVST
tdelay > 10ns (to avoid overlap)

MUX
Channel N ± 1 Channel N Channel N+1
CONTROL

Acquisition Conversion Acquisition Channel Conversion Channel

ADC STATE Channel N ± 1 Channel N ± 1 N N

Settling Time for Settling Time for Settling Time for

FDA SETTLING Channel N ± 1 Channel N Channel N + 1

Available settling time for channel #N

333ns t 10ns = ~323ns

Transient Settling Results

The following TINA transient simulation shows settling of the FDA, multiplexer, and SAR ADC sample and
hold after a full-scale step change between adjacent MUX channels. This type of simulation shows that
the sample and hold kickback circuit, and AFE amplifier circuit is properly selected. See Introduction to
SAR ADC Front-end Component Selection for an explanation of how to select the RC filter for best settling
and AC performance.
1.00
S1_MUX Ch1
Selected
0.00

1.00
S2_MUX Ch2
0.00 Selected

125u
VError_ch1 0
-125u Settling Error Ch1 Settling Error Ch2
2.6µV < ½ LSB 20µV < ½ LSB
125u
VError_ch2 0
-125u

1.00
Vacquisition
ADC
0.00 Acquisition
Period
1.00
Vconversion

0.00 ADC
Conversion
835n Period
0.00 1.67u
Time (s)

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AC Transfer Characteristics
The circuit has a gain of 0-dB (1-V/V) and a simulated frequency bandwidth of 16.45-MHz. Notice that the
calculated and simulated bandwidth compare well (calculated = 17.62MHz, simulated = 16.45MHz). See
Op Amp Bandwidth for a general overview of bandwidth calculations and simulations.
The system bandwidth is set by the output filter:
1 1
fc 17.62MHz
2S (Rfil 1 Rfil 2 )Cdiff 2S 30.1 pF

0.0

Gain = 0dB Bandwidth

Gain=1V/V fc = 16.45MHz
Gain (dB)

-20

-40
1k 10k 100k 1M 10M 100M
Frequency (Hz)

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Stability Simulation Graph

The following circuit is used in TINA to measure loop gain and verify phase margin using AC analysis in
TINA. Resistors RISO = 10Ω are used inside the feedback loop to increase phase margin. The circuit has
good stability (approximately 45 degrees of phase margin). See Op Amp Stability for detailed theory on
this subject.
Cf1 3p
Vin-

Rg1 1k Rf1 1k

L1 1MEG
R4 1G
Rfil1 30.1
U1 THS4551
VCVS1 500m C1 1MEG

+ + Ccm1 15p

Vocm
Riso1 10
- - Vcc
-
+ +
+

Vocm

VG1 - - Riso1 10 Cdiff 150p

+
- -
C2 1MEG PD
+ +
Ccm2 15p
Rfil2 30.1
R6 1G

L2 1MEG

VCVS2 500m

Rg2 1k

Vin+ Rf2 1k
Cf2 3p

Vin-
Vocm

R1 1G
Vcc

PD

R5 100k

-
C3 1.2p

V1 5 V4 2.25 V3 5
Loop_Gain
+
R2 1G

Vin+

120
a

100
80
Gain (dB)

60
40
20
0
-20
90 Phase :
Phase [deg]

45 Loop_Gain A:(60.08MEG; -130.79)

0
Phase Margin = 180 ± 135.2 = 44.8 degrees
-45
-90
-135
-180
10 100 1k 10k 100k 1M 10M 100M
Frequency (Hz)

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Noise Simulation
Simplified noise calculation estimate:
The dominant pole in this data acquisition circuit is in the RC kickback filter:
1 1
fc 17.62MHz
2S (Rfil 1 Rfil 2 )Cdiff 2S 30.1 pF

Noise of THS4551 FDA referred to ADC input

1k :
Noise Gain: NG 1 Rf / R g 1 2V V
1k :
2 2
enoFDA enFDA ˜ NG 2 i nFDA ˜ Rf 2 4kTRf ˜ NG
2 2
18
enoFDA 3.4nV / Hz ˜ 2.00V / V 2 0.5 pA / Hz ˜ 1k ˜ ˜ V V

enoFDA 10.629nV / Hz
EnFDA enoFDA ˜ K n ˜ fc 10.629nV / Hz 1.57 ˜17.62MHz 55.90 PVrms

The following figure shows the TINA simulated total noise for the FDA circuit. See Calculating the Total
Noise for ADC systems for detailed theory on this subject. Note that the calculated and simulated noise
compare well (calculated = 55.9µVrms, simulated = 51.5µVrms).
51.55u

Total Noise
Total noise (V)

51.5µVrms

25.78u

0.00
100 1k 10k 100k 1M 10M 100M 1G
Frequency (Hz)

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Design Featured Devices

Device Key Features Link Other Possible Devices

ADS9224R 16-bit resolution, SPI, 3-MSPS sample rate, fully-differential input, http://www.ti.com/product/ADS9224R http://www.ti.com/adcs
integrated 2.5-V reference, dual, simultaneous sampling, low-latency
THS4551 150-MHz, 3.3-nV / √Hz input voltage noise, fully-differential amplifier http://www.ti.com/product/THS4551 http://www.ti.com/opamps

Design References
See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.
Link to Key Files
See the Tina files for low-power sensor measurements - http://www.ti.com/lit/zip/SBAC219.

Revision History
Revision Date Change
A November 2018 Downscale title.
Updated the schematic in the Transient Settling Optimization section.

SBAA315A – October 2018 – Revised November 2018 True differential, 4 × 2 MUX, analog front end,
Submit Documentation Feedback 108 simultaneous-sampling ADC circuit
Copyright © 2018, Texas Instruments Incorporated
 Analog Engineer's Circuit: Data
Converters
SBAA277A – February 2018 – Revised March 2019

Circuit for driving a switched-capacitor SAR ADC with a

buffered instrumentation amplifier

Art Kay

Input ADC Input Digital Output ADS8860

–10mV Out = 0.2V 0A3D H or 262110
5mV Out = 4.8V F5C3H or 6291510

Power Supplies
AVDD DVDD Vref_INA V ref V cc V ee
5.0V 3V 3.277V 5.0V 15V –15V

Design Description
Instrumentation amplifiers are a common way of translating low-level sensor outputs to high-level signals
to drive an ADC. Typically, instrumentation amplifiers are optimized for low noise, low offset, and low drift.
Unfortunately, the bandwidth of many instrumentation amplifiers may not be sufficient to achieve good
settling to ADC charge kickback at maximum sampling rates. This document shows how a wide-bandwidth
buffer can be used with an instrumentation amplifier to achieve good settling at high sampling rates.
Furthermore, many instrumentation amplifiers are optimized for high voltage supplies and it may be
required to interface the high voltage output (that is, ±15V) to a lower voltage amplifier (for example, 5V).
This design shows how a current-limiting resistor can protect the amplifier from electrical overstress in
cases where the instrumentation amplifier is outside the input range of the op amp. A related cookbook
circuit shows a simplified approach that does not include the wide-bandwidth buffer (Driving a Switched-
Capacitor SAR With an Instrumentation Amplifier). The simplified approach has limited sampling rate as
compared to the buffered design. Note that the following circuit shows a bridge sensor, but this method
could be used for a wide range of different sensors.
This circuit implementation is applicable in applications such as Analog Input Modules, Electrocardiogram
(ECG), Pulse Oximeters, Lab Instrumentation, and Control Units for Rail Transport.

+15V

-15V
5V 5.0V 5.0V 3.0V
Rfilt
- INA826 - 25.5
Rg Vref AVDD DVDD
R3 10k INP
Rg 162

++ Cfilt
Ref OPA320
1.1n ADS8860
Rg +
+ C1 1n
-15V
INM
GND
+15V
+5.0V

R1
11.3k -15V

-
R2
21.5k ++ OPA192

+15V Copyright © 2018, Texas Instruments Incorporated

SBAA277A – February 2018 – Revised March 2019 Circuit for driving a switched-capacitor SAR ADC
Submit Documentation Feedback 109
with a buffered instrumentation amplifier
Copyright © 2018–2019, Texas Instruments Incorporated
 www.ti.com

Specifications

Specification Calculated Simulated

Sampling rate 1Msps 1Msps, settling to –44µV
Offset (ADC Input) 40μV · 306.7 = 12.27mV 16mV
Offset Drift (0.4μV/ºC) · 306.7 = 123μV/ºC N/A
Noise 978μV 586μVRMS

Design Notes
1. The bandwidth of instrumentation amplifiers is typically too low to drive SAR data converters at high
data rates (the INA826 bandwidth is 10.4kHz for a gain of 305V/V in this example). Wide bandwidth is
needed because the SAR has a switched capacitor input that needs to be charged during each
conversion cycle. The OPA320 buffer was added to allow the ADC to run at full data rate (ADS8860
1Msps).
2. Select the gain to achieve an input swing that matches the input range of the ADC. Use the
instrumentation amplifier reference pin to shift the signal offset to match the input range. This is
covered in the component selection section.
3. The INA826 gain is scaled so that the op amp input voltage levels are inside the normal operating
range of the amplifier. However, during power up or when a sensor is disconnected the output may
drive to either power supply rail (±15V). The resistor R3 is used to limit the current . This is covered in
the Overvoltage Protection Filter Between Instrumentation Amplifier and Op Amp section of this
document.
4. The buffer amplifier following the voltage divider is required for driving the reference input of most
instrumentation amplifiers. Choose precision resistors and a precision low offset amplifier as the buffer.
Refer to Selecting the right op amp for more details on this subject.
5. Check the common mode range of the amplifier using the Common-Mode Input Range Calculator for
Instrumentation Amplifiers software tool.
6. Select COG capacitors for C1, and Cfilt to minimize distortion.
7. Use 0.1% 20ppm/°C film resistors or better for the gain set resistor Rg. The error and drift of this
resistor will directly translate into gain error and gain drift.
8. The TI Precision Labs – ADCs training video series methods for selecting the charge bucket circuit Rfilt
and Cfilt. Refer to Introduction to SAR ADC Front-End Component Selection for details on this subject.

Circuit for driving a switched-capacitor SAR ADC SBAA277A – February 2018 – Revised March 2019
110 Submit Documentation Feedback
with a buffered instrumentation amplifier
Copyright © 2018–2019, Texas Instruments Incorporated
www.ti.com

Component Selection
1. Find the gain set resistor for the instrumentation amplifier to set the output swing to 0.2V to 4.8V.
.
Vout _ max Vout _ min 4.9V 0.2V
Gain 306.7
Vin _ max Vin _ min 5mV ( 10mV )
49.4k :
Gain 1
Rg
49.4k : 49.4k :
Rg 151.6: or 162: for standard 0.1% resistor
Gain 1.0 (306.7) 1.0
2. Find the INA826 reference voltage (Vref) to shift the output swing to the proper voltage level
.
Vout Gain ˜Vin Vref _ INA
§ 49.4k : ·
Vref _ INA Vout Gain ˜ Vin 4.8V ¨1 ¸· 5mV 3.27V
© 162: ¹
3. Select standard value resistors to set the INA826 reference voltage (Vref_INA = 3.27V). Use the Analog
Engineer's Calculator ("Passive\Find Voltage Divider" section) to find standard values for the voltage
divider.
R2 21.5k :
Vref _ INA ·Vin _ div · 5V 3.277V
R1 R2 11.3k : 21.5k :

The resistors given are

Enter the input and standard value
output for the resistors and can be
voltage divider. scaled by factors of 10.

4. Use the Common-Mode Input Range Calculator for Instrumentation Amplifiers to determine if the
INA826 is violating the common mode range.

Enter the common The linear output range

Enter supply voltage, gain, mode input to the INA is given here.
Select INA826. (Vcm = 0V here) -14.9V < Vout < 14.85V
and INA reference input.

SBAA277A – February 2018 – Revised March 2019 Circuit for driving a switched-capacitor SAR ADC
Submit Documentation Feedback 111
with a buffered instrumentation amplifier
Copyright © 2018–2019, Texas Instruments Incorporated
 www.ti.com

DC Transfer Characteristics
The following graph shows a linear output response for inputs from –5mV to +15mV. Refer to Determining
a SAR ADC’s Linear Range when using Instrumentation Amplifiers for detailed theory on this subject. In
cases where the INA826 output exceeds the op amp input range, the ESD diodes turn on and limit the
input. The resistor R3 protects the amplifier from damage by limiting the input current (see the
Overvoltage Protection Filter Between Instrumentation Amplifier and Op Amp section). The op amp output
is inside the absolute maximum rating of the ADS8860 (–0.3V < VIN < REF +0.3V).
5.19

(5mV, 4.8227V)
Output

2.50
(-10mV, 0.235V)

Vadc

-189m
-15m -10m -5m 0 5m 10m
AC Transfer Characteristics
The bandwidth is simulated to be 11.45 kHz in this configuration. In this bandwidth it is not possible to
drive the SAR converter at full speed. See the TI Precision Labs video series Op Amps: Bandwidth 1 for
more details on this subject.
60

40
Gain(dB) = 49.7dB
Gain (dB)

Gain(V/V) = 305.8 V/V fc = 11.45kHz

20

-20
10 100 1k 10k 100k 1MEG
Frequency (Hz)

Circuit for driving a switched-capacitor SAR ADC SBAA277A – February 2018 – Revised March 2019
112 Submit Documentation Feedback
with a buffered instrumentation amplifier
Copyright © 2018–2019, Texas Instruments Incorporated
www.ti.com

Transient ADC Input Settling Simulation

The OPA320 buffer (20MHz) is used because it is capable of responding to the rapid transients from the
ADC8860 charge kickback. This type of simulation shows that the sample and hold kickback circuit is
properly selected. Refer to Introduction to SAR ADC Front-End Component Selection for detailed theory
on this subject.
Output 1.00m

0.00

Error = -44µV

-1.00m
1.00u 1.25u 1.50u
Time (s)

Noise Simulation
Use a simplified noise calculation for a rough estimate. We neglect the noise from the OPA192 as the
instrumentation amplifier is in high gain so its noise is dominant.
.
2
§ eNO ·
En Gain· eNI 2 ¨ ¸ · Kn· f c
© Gain ¹
2
2 § 110nV / Hz ·
En 305.8 · 18nV / Hz ¨ ¸ · 1.57· 11.45kHz 738 PV / Hz
© 305.8 ¹
Note that the calculated and simulated match well. Refer to TI Precision Labs - Op Amps: Noise 4 for
detailed theory on amplifier noise calculations, and Calculating the Total Noise for ADC Systems for data
converter noise.

T 586.63u
Total noise (V)

293.31u

0.00
1 10 100 1k 10k 100k 1MEG
Frequency (Hz)

SBAA277A – February 2018 – Revised March 2019 Circuit for driving a switched-capacitor SAR ADC
Submit Documentation Feedback 113
with a buffered instrumentation amplifier
Copyright © 2018–2019, Texas Instruments Incorporated
 www.ti.com

Overvoltage Protection Filter Between Instrumentation Amplifier and Op Amp

The filter between the INA826 and OPA320 serves two purposes. It protects the OPA320 from
overvoltage, and acts as a noise or anti-aliasing filter. The INA826 gain should be scaled so that under
normal circumstances, the output is inside the range of the OPA320 (that is, 0V to 5V). Thus, normally the
overvoltage signals applied to the input of the OPA320 is not seen. However, during power up or in cases
where the sensor is disconnected, the INA826 output may be at either power supply rail (that is, ±15V). In
overvoltage cases, the resistor (R3) will limit current into the OPA320 for protection. The internal ESD
diodes on the OPA320 will turn on during overvoltage events and direct the overvoltage signal to the
positive or negative supply. In the following example, the overvoltage signal is directed to the positive
supply and the transient voltage suppressor (D1, SMAJ5.0A) turns on to sink the current. Note that the
resistor is scaled to limit the current to the OPA320 absolute maximum input current (10mA). See TI
Precision Labs - Op Amps: Electrical Overstress (EOS) for detailed theory on this subject.
.
VINA VOpaSupply 0.7V 15V 5.0V 0.7V
R3 ! 9.3k : choose 10k: for margin.
I ABS _ MAX _ OPA 10mA
1 1
C1 1.06nF or 1nF standard value
2 ˜ S ˜ R3 ˜ f c 2 ˜ S ˜ (10k :) ˜ (15kHz )

-15V 5V

0.93mA
- INA826 +9.3V- D1
Rg
+15V R3 10k

Ref
Rg + C1 5.7V OPA320
+ 1n
Ref

+15V
Copyright © 2018, Texas Instruments Incorporated

Circuit for driving a switched-capacitor SAR ADC SBAA277A – February 2018 – Revised March 2019
114 Submit Documentation Feedback
with a buffered instrumentation amplifier
Copyright © 2018–2019, Texas Instruments Incorporated
www.ti.com

Optional Input Filter

The following figure shows a commonly used instrumentation amplifier input filter. The differential noise is
filtered with Cdif, and the common mode noise is filtered with Ccm1 and Ccm2. Note that it is recommended
that Cdif ≥ 10Ccm. This prevents conversion of common mode noise to differential noise due to component
tolerances. The following filter was designed for a differential cutoff frequency of 15kHz.
.
Let Cdif 1nF and f dif 15kHz
1 1
Rin 5.305k : or 5.23k: for 1% standard value
4 ˜ S ˜ f dif ˜ Cdif 4 ˜ S ˜ (15kHz ) ˜ (1nF )
1
Ccm ˜ Cdif 100 pF
10
1 1
f cm 304kHz
2 ˜ S ˜ Rin ˜ Ccm 2 ˜ S ˜ ( 5.23k:) ˜ (100 pF )
1 1
f dif 14.5kHz
§ 1 · § 1 ·
4 ˜ S ˜ Rin ˜ ¨ Cdif Ccm ¸ 4 ˜ S ˜ ( 5.23k:) ˜ ¨1nF ˜ 100 pF ¸
© 2 ¹ © 2 ¹
+15V

CCM1 1n -15V

Rin1 5.23k
- INA826
Rg
R1 162

Cdif 10n
Ref
Rin2 5.23k Rg +
-15V +
Vref_INA
CCM2 1n
+15V

Copyright © 2018, Texas Instruments Incorporated

SBAA277A – February 2018 – Revised March 2019 Circuit for driving a switched-capacitor SAR ADC
Submit Documentation Feedback 115
with a buffered instrumentation amplifier
Copyright © 2018–2019, Texas Instruments Incorporated
 www.ti.com

Design Featured Devices

Device Key Features Link Similar Devices

ADS8860 16-bit resolution, SPI, 1-Msps sample rate, single-ended input, www.ti.com/product/ADS8860 www.ti.com/adcs
Vref input range 2.5V to 5.0V.
OPA192 8-kHz bandwidth, Rail-to-Rail output, 450-nA supply current, unity www.ti.com/product/OPA192 www.ti.com/opamp
gain stable
INA826 Bandwidth 1MHz (G=1), low noise 18nV/rtHz, low offset ±40µV, www.ti.com/product/INA826 www.ti.com/inas
low offset drift ±0.4µV/ºC, low gain drift 0.1ppm/ºC. (typical
values)

Design References
See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.
Link to Key Files
Source Files for this circuit – http://www.ti.com/lit/zip/SBAC184.

Revision History
Revision Date Change
A March 2019 Downstyle the title and changed title role to 'Data Converters'.
Added link to circuit cookbook landing page.

Circuit for driving a switched-capacitor SAR ADC SBAA277A – February 2018 – Revised March 2019
116 Submit Documentation Feedback
with a buffered instrumentation amplifier
Copyright © 2018–2019, Texas Instruments Incorporated
 Analog Engineer's Circuit: Data
Converters
SBAA245A – December 2017 – Revised March 2019

Circuit for driving a switched-capacitor SAR ADC with an

instrumentation amplifier

Art Kay, Bryan McKay

Input ADC Input Digital Output ADS8860

–5mV Out = 0.2V 0A3D H or 2621 10
15mV Out = 4.8V F5C3 H or 62915 10

Power Supplies
AVDD DVDD V ref_INA Vref Vcc Vee
5.0V 3.0V 3.277V 5.0V +15V –15V

Design Description
Instrumentation amplifiers are a common way of translating low level sensor outputs to high level signals
to drive an ADC. Typically, instrumentation amplifiers are optimized for low noise, low offset, and low drift.
Unfortunately, the bandwidth of many instrumentation amplifiers may not be sufficient to achieve good
settling to ADC charge kickback at maximum sampling rates. This document shows how sampling rate
can be adjusted to achieve good settling. Furthermore, many instrumentation amplifiers are optimized for
high-voltage supplies and it may be required to interface the high-voltage output (that is, ±15V) to a lower
voltage ADC (for example, 5V). This design shows how to use Schottky diodes and a series resistor to
protect the ADC input from an overvoltage condition. Note that the following circuit shows a bridge sensor,
but this method could be used for a wide range of different sensors. A modified version of this circuit,
Driving a Switched-Capacitor SAR With a Buffered Instrumentation Amplifier shows how a wide bandwidth
buffer can be used to achieve higher sampling rate.
This circuit implementation is applicable to all Bridge Transducers in PLC’s and Analog Input Modules that
require Precision Signal-Processing and Data-Conversion.

+15V

5V

-15V

5.0V 5.0V 3.0V

D1
- INA826
Rg R3 100
Vref AVDD DVDD
Rfilt 160
Rg 162

INP
Ref
Rg + ADS8860
-15V +
Cfilt 1.1n D2

INM
GND
+15V

+5.0V

R1 11.3k -15V

R2 21.5k
+ + OPA192

+15V

Copyright © 2017, Texas Instruments Incorporated

SBAA245A – December 2017 – Revised March 2019 Circuit for driving a switched-capacitor SAR ADC
Submit Documentation Feedback 117 with an instrumentation amplifier
Copyright © 2017–2019, Texas Instruments Incorporated
 www.ti.com

Specifications

Specification Calculated Simulated

Sampling rate 200ksps 200ksps, settling to –6µV
Offset (ADC Input) 40µV · 306.7 = 12.27mV 16mV
Offset Drift (0.4µV/ºC) · 306.7 = 123µV/ºC NA
Noise 978µV 874µV

Design Notes
1. Select the gain to achieve an input swing that matches the input range of the ADC. Use the
instrumentation amplifier reference pin to shift the signal offset to match the input range. This is
covered in the component selection section.
2. The input Schottky diode configuration is used to prevent driving the input voltage outside of the
absolute maximum specifications. The BAT54S Schottky is a good option for design as this device
integrates both diodes into one package and the diodes are low leakage and have a low forward
voltage. This is covered in the component selection section.
3. The buffer amplifier following the voltage divider is required for driving the reference input of most
instrumentation amplifiers. Choose precision resistors and a precision low-offset amplifier as the buffer.
Refer to Selecting the right op amp for more details on this subject.
4. Check the common-mode range of the amplifier using the Common-Mode Input Range Calculator for
Instrumentation Amplifiers software tool.
5. Select C0G capacitors for CCM1, CCM2, CDIF, and Cfilt to minimize distortion.
6. Use 0.1% 20ppm/°C film resistors or better for the gain set resistor Rg. The error and drift of this
resistor will directly translate into gain error and gain drift.
7. The TI Precision Labs – ADCs training video series covers methods for selecting the charge bucket
circuit Rfilt and Cfilt. Although this method was designed for op amps, it can be modified for
instrumentation amplifiers. Refer to Introduction to SAR ADC Front-End Component Selection for
details on this subject.

Circuit for driving a switched-capacitor SAR ADC SBAA245A – December 2017 – Revised March 2019
118 Submit Documentation Feedback
with an instrumentation amplifier
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com

Component Selection
1. Find the gain set resistor for the instrumentation amplifier to set the output swing to 0.2V to 4.8V.
Vout _ max Vout _ min 4.9V 0.2V
Gain 306.7
Vin _ max Vin _ min 5mV ( 10mV)
49.4k:
Gain 1
Rg
49.4k: 49.4k:
Rg 151.6: or 162: for standard 0.1% resistor
Gain 1.0 (306.7) 1.0

2. Find the INA826 reference voltage (Vref) to shift the output swing to the proper voltage level.
Vout Gain ˜ Vin Vref _ INA
§ 49.4k: ·
Vref _ INA Vout Gain ˜ Vin 4.8V ¨1 ¸· 5mV 3.27V
© 162: ¹

3. Select standard value resistors to set the INA826 reference voltage (Vref = 3.27V). Use Analog
Engineer's Calculator ("Passive\Find Voltage Divider" section) to find standard values for the voltage
divider.
R2 21.5k:
Vref _ INA ·Vin _ div · 5V 3.277V
R1 R2 11.3k: 21.5k:

The resistors given are

Enter the input and standard value
output for the resistors and can be
voltage divider. scaled by factors of 10.

4. Use the Common-Mode Input Range Calculator for Instrumentation Amplifiers to determine if the
INA826 is violating the common-mode range.

Enter the common The linear output range

Enter supply voltage, gain, mode input to the INA is given here.
Select INA826. (Vcm = 0V here) -14.9V < Vout < 14.85V
and INA reference input.

SBAA245A – December 2017 – Revised March 2019 Circuit for driving a switched-capacitor SAR ADC
Submit Documentation Feedback 119
with an instrumentation amplifier
Copyright © 2017–2019, Texas Instruments Incorporated
 www.ti.com

DC Transfer Characteristics
The following graph shows a linear output response for inputs from –5mV to +15mV. Refer to Determining
a SAR ADC’s Linear Range when using Instrumentation Amplifiers for detailed theory on this subject.
Note that the output range is intentionally limited to –0.12V to 5.12V using Schottky diodes to protect the
ADS8860. Note that Schottky diodes are used because the low forward voltage drop (typically less than
0.3V) keeps the output limit very near the ADC supply voltages. The absolute maximum rating for the
ADS8860 is –0.3V < Vin < REF +0.3V.
5.12
Voltage (V)

(5mV, 4.82V)
2.50
(-10mV, 0.235V)

-124m
-15.0m -10.0m -5.0m 0.0 5.0m 10.0m
Input voltage (V)

AC Transfer Characteristics
The bandwidth is simulated to be 20.1kHz, and the gain is 49.7dB which is a linear gain of 305.8. See the
video series on Op Amps: Bandwidth 1 for more details on this subject.
60
Gain (dB)

40

Gain(dB) = 49.7dB
20 Gain(V/V) = 305.8 V/V fc = 20.1kHz

0
0
Phase [deg]

-90

-180

-270
10 100 1k 10k 100k 1MEG
Frequency (Hz)

Circuit for driving a switched-capacitor SAR ADC SBAA245A – December 2017 – Revised March 2019
120 Submit Documentation Feedback
with an instrumentation amplifier
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com

Transient ADC Input Settling Simulation

The following simulation shows settling to a +15mV dc input signal. This type of simulation shows that the
sample and hold kickback circuit is properly selected. Refer to Introduction to SAR ADC Front-End
Component Selection for detailed theory on this subject
T 1.00
Vacq

0.00
1.00
Vconv

0.00
1.00m
Verror
Verror 0.00 -6.1uV

-1.00m
5.00u 7.50u 10.00u
Time (s)
Noise Simulation
The following simplified noise calculation is provided for a rough estimate. We neglect noise from the
OPA192 as the instrumentation amplifier is in high gain, so its noise is dominant.
2
§ eNO ·
En Gain· eNI2 ¨ ¸ · Kn·fc
© Gain ¹
2
2 § 110nV / Hz ·
En 305.8 · 18nV / Hz ¨ ¸ · 1.57· 20.1kHz 978PV / Hz
¨ 305.8 ¸
© ¹

Note that calculated and simulated match well. Refer to TI Precision Labs - Op Amps: Noise 4 for detailed
theory on amplifier noise calculations, and Calculating the Total Noise for ADC Systems for data converter
noise.
874u
Total noise (V)

437u

0
1 10 100 1k 10k 100k 1MEG
Frequency (Hz)

SBAA245A – December 2017 – Revised March 2019 Circuit for driving a switched-capacitor SAR ADC
Submit Documentation Feedback 121
with an instrumentation amplifier
Copyright © 2017–2019, Texas Instruments Incorporated
 www.ti.com

Optional Input Filter

The following figure shows a commonly used instrumentation amplifier input filter. The differential noise is
filtered with Cdif, and the common-mode noise is filtered with Ccm1 and Ccm2. Note that it is recommended
that Cdif ≥ 10Ccm. This prevents conversion of common-mode noise to differential noise due to component
tolerances. The following filter was designed for a differential cutoff frequency of 15kHz.
Let Cdif 1nF and fdif 15kHz
1 1
Rin 5.305k: or 5.23k: for 1% standard value
4 ˜ S ˜ fdif ˜ Cdif 4 ˜ S ˜ (15kHz) ˜ (1nF)
1
Ccm ˜ Cdif 100pF
10
1 1
fcm 304kHz
2 ˜ S ˜ Rin ˜ Ccm 2 ˜ S ˜ ( 5.23k:) ˜ (100pF)
1 1
fdif 14.5kHz
§ 1 · § 1 ·
4 ˜ S ˜ Rin ˜ ¨ Cdif C ¸ 4 ˜ S ˜ ( 5.23k:) ˜ ¨ 1nF ˜ 100pF ¸
© 2 cm ¹ © 2 ¹ (1)

+15V

CCM1 1n -15V

Rin1 5.23k
- INA826
Rg

Cdif 10n R1 162

Ref
Rin2 5.23k Rg +
-15V +

Vref_INA

CCM2 1n
+15V

Copyright © 2017, Texas Instruments Incorporated

Circuit for driving a switched-capacitor SAR ADC SBAA245A – December 2017 – Revised March 2019
122 Submit Documentation Feedback
with an instrumentation amplifier
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com

Design Featured Devices

Device Key Features Link Similar Devices

ADS8860 16-bit resolution, SPI, 1Msps sample rate, single-ended input, Vref input www.ti.com/product/ADS8860 www.ti.com/adcs
range 2.5 V to 5.0 V.
OPA192 Bandwidth 10MHz, Rail-to-Rail input and output, low noise 5.5nV/rtHz, low www.ti.com/product/OPA192 www.ti.com/opamp
offset ±5µV, low offset drift ±0.2µV/ºC. (Typical values)
INA826 Bandwidth 1MHz (G = 1), low noise 18nV/rtHz, low offset ±40µV, low offset www.ti.com/product/INA826 www.ti.com/inas
drift ±0.4µV/ºC, low gain drift 0.1ppm/ºC. (Typical values)

Design References
See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.
Link to Key Files
Source files for this design - http://www.ti.com/lit/zip/sbac184.

Revision History
Revision Date Change
A March 2019 Downstyle the title and changed title role to 'Data Converters'.
Added link to circuit cookbook landing page.

SBAA245A – December 2017 – Revised March 2019 Circuit for driving a switched-capacitor SAR ADC
Submit Documentation Feedback 123
with an instrumentation amplifier
Copyright © 2017–2019, Texas Instruments Incorporated
 Analog Engineer's Circuit: Data
Converters
SBAA314 – October 2018

Circuit for driving an ADC with an instrumentation

amplifier in high gain

Dale Li, Art Kay

Input ADC Input Digital Output ADS8568

VinDiffMin = –8mV CH_x = –10V 8000H
VinDiffMax = +22mV CH_x = +10V 7FFFH

Power Supplies
AVDD Vee Vdd
5.0V 3.3V +15V –15V

Design Description
Instrumentation amplifiers are optimized for low noise, low offset, low drift, high CMRR and high accuracy
but these instrument amplifiers may not be able to drive a precision ADC to settle the signal properly
during the acquisition time of ADC. This design shows an example of how to set the gain and offset shift
to amplify a low level asymmetric input signal. Also, the high gain limits the INA828 instrumentation
amplifier bandwidth, so an OPA827 op amp is used as a buffer so that the ADS8568 full sampling rate can
be achieved. A related cookbook circuit shows a simplified approach that does not include the wide
bandwidth buffer (Driving High Voltage SAR ADC with an Instrumentation Amplifier), this simplified
approach has limited sampling rate as compared to the buffered design in this document. Also Driving
High Voltage SAR ADC with a Buffered Instrumentation Amplifier, analyzes this design in unity gain. This
circuit implementation is applicable to all Bridge Transducers in PLC’s and Analog Input Modules that
require precision signal-processing and data-conversion.

+15V
-15V
+15V -15V 5V 3.3V
U1 +10V
+
+
INA828 +10V - Rflt 42.2 HVDD HVSS AVDD DVDD
Rg
+ R1 10k CH_xx
Rg Data Bus
22mV ++ U2
75Ÿ Ref
- OPA827 ADS8568
Rg Cflt 370p
-
C1 1n Control Bus
+15V AGND
+

-4.67V
VG1 VG2
-15V
Driving at the highest sampling rate
Vcm

SBAA314 – October 2018 Circuit for driving an ADC with an

Submit Documentation Feedback 124 instrumentation amplifier in high gain
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Specifications

Specification Goal Calculated Simulated

Transient Settling Error >0.5 LSB (152µV) NA 0.36µV
Noise 1.1mV 1.14mV
System Offset Error 33.6mV NA
System Offset Drift 334µV/ºC NA
System Gain Error 0.53% NA
System Gain Drift 54.2ppm/ºC NA

Design Notes
1. The bandwidth of instrumentation amplifiers is typically not enough to drive SAR data converters at a
higher data rate. This is especially true when the instrumentation amplifier is in high gain. so a wide
bandwidth driver is needed because the SAR ADC with switched-capacitor input structure has an input
capacitor that needs to be fully charged during each acquisition time. The OPA827 buffer is added to
allow the ADC to run at full sampling rate (ADS8568 510kSPS for parallel interface).
2. Check the common-mode range of the amplifier using the Common-Mode Input Range Calculator for
Instrumentation Amplifiers software tool.
3. Select COG capacitors for C1 and Cfilt to minimize distortion.
4. The gain set resistor, Rg, should be a 0.1% 20ppm/°C film resistors or better for low gain error and low
gain drift.
5. The TI Precision Labs video series covers the method for selecting the driver amplifier and the charge
bucket circuit Rfilt and Cfilt. See Introduction of SAR ADC Front-End Component Selection for details.
6. Set the cutoff of the filter between the op amp and instrumentation amplifier for anti aliasing and to
minimize noise. See Aliasing and Anti-aliasing Filters for more details on aliasing and anti-aliasing
filters.
7. Because of the high instrumentation amplifier gain, the DC errors (offset, gain, and drift) are significant.
Calibration is a good approach to minimizing these errors. See Understanding and Calibrating the
Offset and Gain for ADC Systems for more details on calibration.

Circuit for driving an ADC with an SBAA314 – October 2018

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Component Selection
1. Find the gain based on differential input signal and the ADS8568 full-scale input range.

Vout Vout 10V ( 10V )

G 666.7
Vin Vin 22mV ( 8mV )
50k : 50k :
Rg 75.1:
G 1 666.7
Rg 75.1: standard value
50k :
G 1 667.7
Rg
2. The input signal in this design is ±10-V high voltage signal, so the gain of INA828 should be set to 1
and no gain resistor (Rg) is needed.
Vout G ˜ Vin Vref
Vref Vout G ˜ Vin 10V 667.7 ˜ 22mV 4.667V
3. Use the Common-Mode Input Range Calculator for Instrumentation Amplifiers to determine if the
INA826 is violating the common-mode range. The common-mode calculator in the following figure
indicates that the output swing is ±14.9V for a 0-V common-mode input.

4. Find the value for Cfilt, and Rfilt using TINA SPICE and the methods described in Introduction of SAR
ADC Front-End Component Selection videos. The value of Rfilt and Cfilt shown in this document will
work for these circuits; however, if you use different amplifiers you will have to use TINA SPICE to find
new values.
5. Select the RC filter between the INA828 and OPA827 based on your system requirements (fcRC =
15.9kHz in this example).

1 1
fcRC 15.9kHz
2S ˜ R1 ˜ C1 2S ˜ (10k :) ˜ 1pF

SBAA314 – October 2018 Circuit for driving an ADC with an

Submit Documentation Feedback 126 instrumentation amplifier in high gain
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DC Transfer Characteristics
The following graph shows a linear output response for inputs from differential –10V to +10V. See
Determining a SAR ADC’s Linear Range when using Instrumentation Amplifiers for detailed theory on this
subject. The full-scale range (FSR) of the ADC falls within the linear range of the Instrumentation
Amplifier.
T 20
V_INA
15
(22mV, 10V)
10
5 Vadc
Output

0
-5

-10
(-8mV, -10V)
-15
-20
-20m -15m -10m -5m 0 5m 10m 15m 20m 25m 30m 35m
Input voltage (V)
AC Transfer Characteristics
The bandwidth for this design is simulated to be 14.8kHz and the gain is 56.4dB (667.7V/V). The
bandwidth limit is set by a combination RC filter (fcRC = 15.9kHz) and the instrumentation amplifier
(fcINA=49.2kHz).
60

V_INA
56.5dB fc = 14.8kHz
40
Gain (dB)

fcINA = 49.2kHz

Vadc
20

0
100 1k 10k 100k 1MEG
Frequency (Hz)

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Transient ADC Input Settling Simulation (510kSPS)

The OPA827 buffer (22-MHz GBW) is used because it is capable of responding to the rapid transients
from the charge kickback of the ADS8568. The op-amp buffer allows the system to achieve the ADS8568
maximum sampling rate of 510kSPS. The following simulation shows settling to a full-scale DC input
signal with the INA828 and OPA827 buffer, and ADS8568. This type of simulation shows that the sample
and hold kickback circuit is properly selected to meet desired ½ of a LSB (152µV). See Introduction to
SAR ADC Front-End Component Selection for detailed theory on this subject.
50u
Verror = -346nV
Verror 0

-50u
1.00
tacq

0.00
7.84u 8.02u 8.20u
Time (s)
Noise Simulation
The section walks through a simplified noise calculation for a rough estimate. We neglect the noise from
the OPA827 as the noise of the INA828 is dominant also neglect resistor noise in this calculation as it is
attenuated for frequencies greater than 15.92kHz.
2
2 § eNO ·
En Gain · eNI ¨ Gain ¸ · K n ·fc
© ¹
2
2 § 90nV / Hz ·
En 667.7 · 7nV / Hz ¨¨ ¸¸ · 1.57·14.8kHz 595 PVrms
© 667.7 ¹
Note that calculated and simulated match well (simulated = 563µVRMS, calculated = 595µVRMS). See TI
Precision Labs - Op Amps: Noise 4 for detailed theory on amplifier noise calculations and Calculating
Total Noise for ADC Systems for data converter noise.

1.13m En-INA
1.14mVrms
Total noise (V)

564.41u
En-adc
563µ Vrms

0.00
1 10 100 1k 10k 100k 1MEG
Frequency (Hz)

SBAA314 – October 2018 Circuit for driving an ADC with an

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Gain Error and Offset Estimates:

The following offset and offset drift calculations will be dominated by the instrumentation amplifier since it
is in high gain. Gain error calculations include the gain error of the ADC and instrumentation amplifier. For
offset and gain error, the maximum room temperature value is used. See Statistics Behind Error Analysis
for details on system gain and offset error.

System Offset Calculation:

Vosi 50 PV , Voso 250 PV max at room temp
G 667.7V / V
Voso 250 PV
VosRTI Vosi 50 PV 50.4 PV
G 667.7
VosRTO G ˜ VosRTI 667.7 ˜ 50.4 PV 33.6mV
Vos (System ) | 33.6mV total system offset is dominated by INA828 offset

System Offset Drift Calculation:

o
VosDrift (INA828RTI ) 0.5 PV C
VosDrift (INA828RTO ) G ˜ VosDriftINA828RTI 667.7 ˜ 0.5 PV qC 334 PV qC
VosDrift (System ) | 334 PV qC the INA drift dominates because of the high gain.

System Gain Error Calculation:

GEina r0.15%, max room temp INA828
GERg r0.1%, Rg Tolerance
GE ADS 8568 r0.5%, max room temp ADS8568
2 2 2 2 2 2
GEtotal GEina GERg GE ADS 8568 0.15% 0.1% 0.5% 0.53%

System Gain Drift Calculation:

'GEINA
| 50 ppm / qC
'T
'GERg
| 20 ppm / qC
'T
'GEADC 8568
| 6 ppm / qC
'T
'GESystem 2 2 2
| 50 ppm / qC 20 ppm / qC 6 ppm / qC 54.2 ppm / qC
'T

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Design Featured Devices

Device Key Features Link Other Possible Devices

ADS8568 16-bit resolution, SPI, 500kSPS sample rate, single-ended input, http://www.ti.com/product/ADS8568 http://www.ti.com/adcs
simultaneous sampling, internal reference, programmable range up to
±12V.
INA828 Bandwidth 1MHz (G=1), low noise 18nV/√Hz, low offset ±40μV, low http://www.ti.com/product/INA828 http://www.ti.com/inas
offset drift ±0.4μV/ºC, low gain drift 0.1ppm/ºC. (Typical values)
OPA827 Gain bandwidth 22MHz, low noise 4nV/√Hz, low offset ±75μV, low http://www.ti.com/product/OPA827 http://www.ti.com/opamp
offset drift ±0.1μV/ºC (Typical values)

Link to Key Files

See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.
Source files for this circuit - http://www.ti.com/lit/zip/SBAC215.

SBAA314 – October 2018 Circuit for driving an ADC with an

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 Analog Engineer's Circuit: Data
Converters
SBAA266A – February 2018 – Revised March 2019

Low-input bias-current front end SAR ADC circuit

Mike Stout

Input ADC Input Digital Output ADC122S021

VinMin = 0.03V IN1 = 0.14 115 = 0x073
VinMax = 1.07V IN1 = 4.88 3998 = 0xF9E
VinMin = 0V IN2 = 0V 0 = 0x000
VinMax = 1V IN2 = 1V 819 = 0x333

Power Supplies
V+, VA V–
5V 0V

Design Description
This design shows a low Ibias amplifier being used to drive a SAR ADC. A sensor with high output
impedance requires an amplifier with a low input bias current to minimize errors. Examples of applications
where this type of sensor might be used include gas detectors, blood gas analyzers, and air quality
detectors. In this design, a pH probe is used for the sensor. The output impedance of a pH probe can be
from 10MΩ to 1000MΩ. If a pH probe is used that has an output impedance of 10MΩ with an op amp that
has 3nA of input bias current, the error due to the input bias current of the op amp will be 30mV. Using the
input signal amplitude and gain described in the component selection section, this 30mV equates to an
error of about 2.9%. If an op amp with an input bias current of 3fA is used, the error is decreased to 30nV.
The output of the pH sensor does not quickly change, so a lower speed ADC can be used. The value from
the pH sensor changes as the temperature changes so a two channel ADC was selected so that one
channel could be used to monitor the temperature. The ADC122S021 used in this design is a 2-channel,
12-bit, ADC that can sample up to 200ksps.

5V
C1

5V 0.1 µF R1 R2
GND 1.00k 3.57k
5

5V
R3 4 U1 GND C2
13.7k V+ 1 DIN
3 V-
LMP7715MF 0.1 µF U2 DOUT
6

R4 GND 6 7
DIN DOUT
2

1.69k 8 U3 5V CS
V+ 4 R5 5 2
IN1 VA
1 V- 20 4 IN2 SCLK
GND LMP7721MA C3 3 C4
GND
GND 330pF 8 0.1 µF
SCLK
3

1 CS
pH Sensor R6 GND GND
0 GND ADC122S021CIMM/NOPB
5V
GND LM35CZ/NOPB
2

LMP7715MF U4
U5 3 1 2 R7
R8 +VS VO
1 V-
20
V+ 4 C5 GND C6
100
0.1 µF 330pF
3
5

C7
GND GND
GND
0.1 µF
5V GND

SBAA266A – February 2018 – Revised March 2019 Low-input bias-current front end SAR ADC circuit
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Specifications

Specification Calculated Simulated Measured

Ibias 20fA 118fA 20fA

Design Notes
1. Use COG (NPO) capacitors for C3 and C6.
2. Each IC should have a bypass capacitor of 0.1μF.
3. PCB layout is very important. See the LMP7721 Multi-Function Evaluation Board Users’ Guide.
4. The PCB must be clean. See the LMP7721 Multi-Function Evaluation Board Users’ Guide.
5. For more information on low leakage design, see Design femtoampere circuits with low leakage.
Component Selection
1. The output voltage of a pH sensor changes as the temperature changes. At 0°C it outputs 54.2mV/pH,
at 25°C it outputs 59.16mV/pH, and at 100°C it outputs 74.04mV/pH. This means that the maximum
swing of the pH sensor around the bias point of the pH sensor will be ±518.3mV at 100°C. The
maximum output of the LMP7721 should be limited to ±2.4V to allow for headroom. That sets the gain
of the LMP7721 at:
2.4V / 0.5183V = 4.6V/V
Setting resistors R2 = 3.57kΩ and R1 = 1kΩ, will set this gain.
2. Since the input of the LMP7721 must be from 0V to 5V, the pH sensor needs to be biased above
ground. Resistors R3 = 13.7kΩ and R4 = 1.69kΩ in a voltage divider configuration will set the input of
U1 to:
5V · 1.69kΩ / (1.69kΩ + 13.7kΩ) = 549mV
U1 has a gain of 1V/V so the bias of the pH sensor will also be at 549mV. Since the pH sensor can
swing –518.3mV below the bias point, this keeps the input of the LMP7721 above ground. The output
of the LMP7721 will be centered at:
0.549V · 4.6V/V = 2.52V
and can swing ±2.4V above and below the center point.
3. U5 is used to set the voltage of the guard ring. It is set with a gain of 1V/V and the input is the signal
on the –IN pin of the LMP7721.
4. The output of the LMP7721 is connected to one of the inputs of the ADC122S021 SAR ADC. The
sampling capacitor of the ADC is 33pF and the external capacitor placed next to the pin of the ADC
should be 10 times larger, or 330pF. A small resistor of 20Ω is added in series to isolate the capacitor
from the LMP7721.
5. Because the output of the pH sensor changes as the temperature changes the LM35, a temperature
sensor, is connected to channel 2 of the ADC122S021. A 330-pF capacitor along with a 20-Ω series
resistor is used on the output of the temperature sensor.

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DC Transfer Characteristics
The following graph shows the pH sensor input to the LMP7721, the Guard voltage, and the LMP7721
output. This data is for 100°C, when the pH sensor output has the largest possible output swing.
T
2.00

Guard (V)

0.00
5.00

LMP7721
Output (V)

0.00
2.00

pH Sensor
Output (V)

0.00

0.00 100.00m 200.00m 300.00m 400.00m 500.00m

Time (s)

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Layout
The PCB layout is very important for a low Ibias circuit. Current leakage will occur between two traces
when there a voltage potential between the traces. This is the reason for the guard trace. The guard trace
is set to a voltage close to the input voltage to minimize the leakage between the input of the LMP7721
and the outside world. The LMP7721 includes two unused pins (pins 2 and 7) that can be used to simplify
the layout of a guard trace.
The following image shows a sample layout. The output of the pH sensor and the +IN input of the
LMP7721 are separated from the rest of the circuit by the guard trace, which is close to the input voltage.
This will minimize the leakage on the input of the LMP7721. The bias of the pH sensor is located outside
of the guard. Leakage between the bias point and the rest of the circuit is not important. Solder mask
should not cover the area inside the guard trace. If there is a ground plane on the bottom side of the board
or other internal planes, they should have a 'keep out' area underneath the guard area.

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Design Featured Devices

Device Key Features Link Similar Devices

ADC122S021 12 bit, SPI, 2 channel, 50ksps to 200ksps, single ended input www.ti.com/product/adc122s021 www.ti.com/adcs
LMP7721 Ultra-low input bias current of 3fA, with a specified limit of ±20fA at www.ti.com/product/lmp7721 www.ti.com/opamps
25°C, offset voltage ±26µV, GBW 17MHz
LMP7715 Input offset voltage ±150µV, input bias current 100fA, input voltage www.ti.com/product/lmp7715 www.ti.com/opamps
noise 5.8nV/√Hz, gain bandwidth product 17MHz
LM35 Calibrated directly in degrees Celsius, Linear + 10-mV/°C scale factor, www.ti.com/product/lm35 www.ti.com/temperature
0.5°C ensured accuracy (at 25°C), rated for full –55°C to 150°C range

Design References
See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.

Revision History
Revision Date Change
A March 2019 Downstyle the title and changed title role to 'Data Converters'.
Added link to circuit cookbook landing page.

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 Analog Engineer's Circuit: Data
Converters
SBAA340 – January 2018

High-side current shunt monitor circuit to

3-V single-ended ADC

Art Kay

Input ADC Input Digital Output ADS7042

–6A 0.3V 19AH, 410d
+6A 2.7V E66H, 3686d

Power Supplies
AVDD / VREF DVDD Vsup
3.0V 1.65V 40V

Design Description
Current shunt monitors are amplifiers that are optimized to read small shunt voltages over very wide
common mode ranges. This example application uses the INA190A4 to translate a ±6-A current into a 0-V
to 3-V range for the ADC. Note that this is a high sided current measurement with a 40V common mode
range. Detailed theory on current sensing is covered in Using current sense amplifiers to solve today’s
current sensing design challenges. Compared to other current shunt devices the INA190 has very low
offset voltage, bias current, and drift. This excellent DC performance allows smaller for smaller input
voltage ranges without compromising accuracy as the offset is small compared to the input signal. The
use of small shunt resistors is an advantage as the power dissipated in the shunt is smaller for smaller
resistors for a given current level. The ADS7042 is a 12 bit 1MSPS SAR ADC with a 3V analog input
range. The design shown in this document can be modified for other data converters and input ranges.
This design can be used a wide range of applications where current needs to be monitored such as
notebook computers, cell phones, and battery management.
40V +3V
U1 +3V +1.65V
- INA190A4
G=200 Rfilt 1k AVDD DVDD
1m

±6mV AINP
±6A Ref

+ Cfilt ADS7042
1.5V 510pF
AINN
Load GND
G|sin + Vref
200|(±6mV)+1.5V
0.3V to 2.7V

SBAA340 – January 2018 High-side current shunt monitor circuit to 3-V single-ended ADC
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Specifications

Specification Goal Calculated Simulated

Transient Settling < 0.5LSB = 366µV NA 0.94µV
Noise NA 3.5mVrms 3.16mV
Bandwidth NA 33kHz 35kHz

Design Notes
1. The tolerance in the shunt resistor, RSENSE, will translate into a gain error. Choose the tolerance
according to your error budget. Note that the maximum specified gain error for the INA190A4 is 0.3%
and a common tolerance 1-m resistor is 0.5% to 1.0%.
2. Selection of the shunt resistor is covered in the component selection section. The objective is to
minimize power dissipation while maintaining good accuracy.
3. Use a C0G capacitor for CFILT to minimize distortion.
4. The example design is for a bidirectional current source (for example, ±6A). A similar approach can be
followed for an unidirectional current source (for example, 0A to 12A). The main difference is that the
reference input pin would connect to ground as opposed to 1/2 VREF.

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Component Selection
1. Choose Rsense Resistor and find Gain for the current sense amplifier bidirectional current
Pmax 50mW
Rsh 2 2
1.38m:
Imax 6A
Choose Rsh 1m:
VREF 3V
r Vout range r r r1.5V
2 2
rVout range r1.5V
GINA 250V / V
Iload max ˜ Rsh 6 A ˜1mß
Select INA190 A4, G 200V / V , Common Mode Range : 0.2 V to 40 V
2. Calculate the current sense amplifier output range
VREF 3V
VINA _ outmax GINA ˜ Iload max ˜ Rsh 200V / V ˜ 6 A ˜ 1m: 2.7V
2 2
VREF 5V
VINA _ outmin GINA ˜ Iload min ˜ Rsh 200V / V ˜ 6 A ˜ 1m: 0.3V
2 2
3. Find the INA190 output swing from the data sheet.
Swing to Posative Rail = 3V - 40mV = 2.96V
Swing to Negative Rail = 1mV
The output is scaled for 0.3V to 2.7V, so this design has significant margin.
If desired, a larger shunt resistor could be used to expand the usable range.
4. Offset Error impact on system error.
OutputOffsetINA = Vos ˜ Gain 15 PV ˜ 200 3mV
OfsetADS7042 = 3LSB ˜ 366 PV LSB 1.1mV
2 2
TotalOffsetRSS 3mV 1.1mV 3.2mV
3.2mV
Error (%FSR ) ˜ 100 0.11% of FSR
3V

SBAA340 – January 2018 High-side current shunt monitor circuit to 3-V single-ended ADC
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DC Transfer Characteristics
The following graph shows a linear output response for inputs from –7.5A to +7.5A. The required linear
range is ±6A, so this circuit meets the requirement with design margin.
3.00
(6A, 2.7V)

2.25 (7.5A, 2.95V)

Output

1.50

0.75 (-7.5A, 0.05V)

(-6A, 0.3V)
0.00
-10.00 -5.00 0.00 5.00 10.00
Input current (A)
AC Transfer Characteristics
The data sheet specified bandwidth of 33kHz for the INA190A4 closely matches the simulated 35kHz
bandwidth. The input ADC filter is designed to minimize charge kickback and does not limit the bandwidth
( fc(ADC filter) = 312kHz ). See TI Precision Labs - Op Amps: Bandwidth 1 for more details on this subject.
0

-20
fc = 35kHz
Gain (dB)

-40

-60

-80

-100
100 1k 10k 100k 1M 10M
Frequency (Hz)

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Transient ADC Input Settling Simulation

The transient ADC simulation is performed for a near full scale input (VinADC = 2.3V), for a 100-kHz
sampling rate. Note that the sampling rate needed to be adjusted as the INA190 does not have sufficient
bandwidth to respond to the transient charge kickback from the ADC at full sampling rate. Refer to
Introduction to SAR ADC Front-End Component Selection for detailed theory on this subject.
1.00
Vacq
0.00
1.00
Vconv
0.00
400u Error = 0.94µV
Verror 0
-400u
2.30
VoutOPA
2.28
100u 150u 200u 250u 300u
Time (s)
Noise Simulation
The noise hand calculation follows. This calculation assumes that the filter is a first order but inspection of
the bandwidth simulation shows a more complex response.

En Gn ˜ en ˜ K n ˜ fc
En 200 ˜ 75 nV Hz ˜ 1.57 ˜ 35kHz 3.5mVrms

Note that the calculated and simulated match well. Refer to TI Precision Labs - Op Amps: Noise 4 for
detailed theory on amplifier noise calculations, and Calculating the Total Noise for ADC Systems for data
converter noise.
3.16m

En = 3.16mVrms
Total noise (V)

1.58m

0.00
1 10 100 1k 10k 100k 1M 10M
Frequency (Hz)

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Design Featured Devices

Device Key Features Link Other Possible Devices

ADS7042 12-bit resolution, SPI, 1MSPS sample rate, single-ended input, http://www.ti.com/product/ADS7042 http://www.ti.com/adcs
AVDD/Vref input range 1.6V to 3.6V.
INA190 Low Supply voltage (1.7 V to 5.5 V), Wide Common-Mode (-0.2V to http://www.ti.com/product/INA190 http://www.ti.com/amplifier-
40 V), Low Offset Voltage (Vos<15µV Max), Low Bias Current (500pA circuit/current-sense/analog-
typ). output/products.html

Design References
See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.
Link to Key Files
TINA source files – http://www.ti.com/lit/zip/sbac230.

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 Analog Engineer's Circuit: Data
Converters
SBAA329 – December 2018

Two-wire PT100 RTD measurement circuit

with low-side reference

Joseph Wu

Power Supplies
AVDD AVSS, DGND DVDD, IOVDD
3.3V 0V 3.3V

Design Description
This cookbook design describes a temperature measurement for a two-wire RTD using the ADS124S08.
This design uses a ratiometric measurement for a PT100 type RTD with a temperature measurement
range from –200°C to 850°C. Included in this design are ADC configuration register settings and pseudo
code to configure and read from the device. This circuit can be used in applications such as analog input
modules for PLCs, lab instrumentation, and factory automation. For more information about making
precision ADC measurements with a variety of RTD wiring configurations, see A Basic Guide to RTD
Measurements.

3.3 V 3.3 V

330 nF 0.1 F

AVDD DVDD IOVDD

1 mA
AIN0
IDAC1 ADS124S08

Lead 1 4.99 k AIN1

4.7 nF
VRTD = 20 mV to 400 mV RRTD 47 nF PGA ADC
Gain = 4
4.7 nF
AIN2
Lead 2
4.99 k

IDAC2
Mux

4.32 k REFP0

RREF 4.7 nF
VREF = 1.62 V 47 nF
1.62 k
4.7 nF
REFN0
4.32 k AVSS DGND

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Design Notes
1. Use supply decoupling capacitors for both the analog and digital supplies. AVDD must be decoupled
with at least a 330-nF capacitor to AVSS. DVDD and IOVDD (when not connected to DVDD) must be
decoupled with at least a 0.1-µF capacitor to DGND. See the ADS124S0x Low-Power, Low-Noise,
Highly Integrated, 6- and 12-Channel, 4-kSPS, 24-Bit, Delta-Sigma ADC with PGA and Voltage
Reference data sheet for details on power supply recommendations.
2. Do not route the excitation currents through input filter resistors, using the same pin as an ADC input
and as the output for an IDAC current source. Excitation currents reacting with series resistance adds
error to the measurement.
3. A 1-µF capacitor is required between REFOUT and REFCOM to enable the internal reference for the
IDAC current.
4. Use a precision reference resistor with high accuracy and low drift. Because the measurement is
ratiometric, accuracy is dependent on the error of this reference resistor. A 0.01% resistor contributes
a gain error similar to that as the ADC.
5. When possible, use C0G (NPO) ceramic capacitors for input filtering. The dielectric used in these
capacitors provides the most stable electrical properties over voltage, frequency, and temperature
changes.
6. Input filtering for the ADC inputs and the reference inputs are selected using standard capacitor values
and 1% resistor values. An example design and analysis of these filters is found in the RTD
Ratiometric Measurements and Filtering Using the ADS1148 and ADS1248 Family of Devices
application report.
7. This design shows connections to three input pins of the ADC multiplexer. Remaining analog inputs
may be used for RTD, thermocouple, or other measurements.
8. The two-wire RTD measurement is the least accurate of RTD measurements because the lead
resistance error cannot be removed. For measurements with more accurate RTD wiring configurations,
see A Basic Guide to RTD Measurements.

Component Selection
1. Identify the range of operation for the RTD.
As an example, a PT100 RTD has a range of approximately 20Ω to 400Ω if the temperature
measurement range is from −200°C to 850°C. The reference resistor must be larger than the maximum
RTD value. The reference resistance and PGA gain determines the positive full scale range of the
measurement.
2. Determine values for the IDAC excitation current and reference resistor.
The excitation current source in this design is selected to be 1mA. This maximizes the value of the
RTD voltage while keeping the self-heating of the RTD low. The typical range of RTD self-heating
coefficients is 2.5mW/°C for small, thin-film elements and 65mW/°C for larger, wire-wound elements.
With 1-mA excitation at the maximum RTD resistance value, the power dissipation in the RTD is less
than 0.4mW and keeps the measurement errors from self-heating to less than 0.01˚C.
After selecting the IDAC current magnitude, set RREF = 1620Ω. This sets the reference at 1.62V and
the maximum RTD voltage is 400mV. The reference voltage acts as a level shift to place the input
measurement to near mid-supply, putting the measurement in the PGA input operating range. With
these values, the PGA gain can be set to 4 so that the maximum RTD voltage is near the positive full
scale range without exceeding it.
The reference resistor, RREF must be a precision resistor with high accuracy and low drift. Any error in
RREF reflects the same error in the RTD measurement. The REFP0 and REFN0 pins are shown
connecting to the RREF resistor as a Kelvin connection to get the best measurement of the reference
voltage. This eliminates any series resistance as an error from the reference resistance measurement.
Using the maximum RTD resistance, the ADC input voltages are calculated in the following equations.
VAIN1 = IIDAC1 • (RRTD + RREF) = 1mA • (400Ω + 1620Ω) = 2.02V
VAIN2 = IIDAC1 • RREF = 1mA • 1620Ω = 1.62V
VINMAX = 1mA • 400Ω = 400mV
3. Verify that the design is within the range of operation of the ADC.
First, verify that VAIN1 and VAIN2 are within the input range of the PGA given that the gain is 4 and that

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AVDD is 3.3V and AVSS is 0V. As the ADS124S0x Low-Power, Low-Noise, Highly Integrated, 6- and
12-Channel, 4-kSPS, 24-Bit, Delta-Sigma ADC with PGA and Voltage Reference data sheet shows,
the absolute input voltage must satisfy the following:
AVSS + 0.15V + [|VINMAX| • (Gain − 1) / 2] < VAIN1, VAIN2 < AVDD − 0.15V − [|VINMAX| (Gain − 1) / 2]
0V + 0.15V + [|VINMAX| • (Gain − 1) / 2] < VAIN1, VAIN2 < 3.3V − 0.15V − [|VINMAX| (Gain − 1) / 2]
0.75 < VAIN1, VAIN2 < 2.55V
Because the maximum and minimum input voltages seen at AIN1 and AIN2 (2.02 V and 1.62 V) are
between 0.75V and 2.55V, the inputs are in the PGA operating range.
Second, verify that the voltage at the IDAC output pin is within the current source compliance voltage.
The IDAC pin is AIN0, which have the same voltage as AIN1. At the maximum voltage, VAIN0 is
2.02V. As shown in the Electrical Characteristics table in the ADS124S0x Low-Power, Low-Noise,
Highly Integrated, 6- and 12-Channel, 4-kSPS, 24-Bit, Delta-Sigma ADC with PGA and Voltage
Reference data sheet, the output voltage of the IDAC must be between AVSS and AVDD − 0.6V for an
IDAC current of 1mA. In this example, with AVDD = 3.3V, the IDAC output must be:
AVSS < VAIN0 = VAIN1 < AVDD − 0.6V
0V < VAIN0 < 2.7V
With the previous result, the output compliance of the IDAC is satisfied.
4. Select values for the differential and common-mode filtering for the ADC inputs and reference inputs.
This design includes differential and common-mode input RC filtering. The bandwidth of the differential
input filtering is set to be at least 10 × higher than the data rate of the ADC. The common-mode
capacitors are selected to be 1/10 of the value the differential capacitor. Because of capacitor
selection, the bandwidth of common-mode input filtering is approximately 20 × higher than the
differential input filtering. While series filter resistors offer some amount of input protection, keep the
input resistors lower than 10kΩ, to allow for proper input sampling for the ADC.
With input filtering, differential signals are attenuated at a lower frequency than the common-mode
signals, which are significantly rejected by the PGA of the device. Mismatches in common-mode
capacitors cause an asymmetric noise attenuation, appearing as a differential input noise. With a lower
bandwidth for differential signals, the effects from the mismatch of input common-mode capacitors be
reduced. Input filtering for the ADC inputs and reference inputs are designed for the same bandwidth.
In this design, the data rate is chosen to be 20SPS using the low-latency filter of the ADS124S08. This
filtering provides a low noise measurement with single-cycle settling and the ability to reject 50-Hz and
60-Hz line noise. For the ADC input filtering, the bandwidth frequency for the differential and common-
mode filtering is approximated in the following equations.
fIN_DIFF = 1 / [2 • π • CIN_DIFF (RRTD + 2 • RIN)]
fIN_CM = 1 / [2 • π • CIN_CM (RRTD + RIN + RREF)]
For the ADC input filtering, RIN = 4.99kΩ, CIN_DIFF = 47nF, and CIN_CM = 4.7nF. This sets the differential
filter bandwidth to 330 Hz and the common-mode filter bandwidth to 5kHz.
Similarly, the bandwidth for the reference input filtering is approximated in the following equations.
fREF_DIFF = 1 / [2 • π • CREF_DIFF • (RREF + 2 • RIN_REF)]
fREF_CM = 1 / [2 • π • CREF_CM • (RREF + RIN_REF)]
For the reference input filtering, RIN_REF = 4.32kΩ, CREF_DIFF = 47nF, and CREF_CM = 4.7nF. This sets the
differential filter bandwidth to 330 Hz and the common-mode filter bandwidth to 5.7kHz. Matching the
ADC input and reference input filtering may not be possible. However, keeping the bandwidths close
may reduce the noise in the measurement.
For an in-depth analysis of component selection for input filtering, see the RTD Ratiometric
Measurements and Filtering Using the ADS1148 and ADS1248 Family of Devices application report.

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Measurement Conversion
RTD measurements are typically ratiometric measurements. Using a ratiometric measurement, the ADC
output code does not need to be converted to a voltage. This means that the output code gives a
measurement only as a ratio of the value of the reference resistor and does not require a precise value for
the excitation current. The only requirement is that the current through the RTD and reference resistor are
the same.
Equations for the measurement conversion are shown for a 24-bit ADC:
Output Code = 223 • Gain • (VRTD / VREF) = 223 • Gain • (IIDAC1 • RRTD) / (IIDAC1 • RREF) = 223 • Gain • (RRTD / RREF) (1)
RRTD = RREF • [Output Code / (Gain • 223)] (2)
The ADC converts the measurement to the RTD equivalent resistance. Because of non-linearity in the
RTD response, the conversion of the resistance to temperature requires an calculation from equation or
lookup table. For more information about the conversion of RTD resistance to temperature, see A Basic
Guide to RTD Measurements.

Register Settings

Configuration Register Settings for a Two-Wire PT100 RTD Measurement Circuit with Low-Side
Reference Using the ADS124S08
Register Register Name Setting Description
Address
02h INPMUX 12h Select AINP = AIN1 and AINN = AIN2
03h PGA 0Ah PGA enabled, Gain = 4
04h DATARATE 14h Continuous conversion mode, low-latency filter, 20-SPS data rate
05h REF 02h Positive and negative reference buffers enabled, REFP0 and REFN0
reference inputs selected, internal reference always on
06h IDACMAG 07h IDAC magnitude set to 1mA
07h IDACMUX F0h IDAC1 set to AIN0, IDAC2 disabled
08h VBIAS 00h VBIAS not used for any input
09h SYS 10h Normal mode of operation

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Pseudo Code Example

The following shows a pseudo code sequence with the required steps to set up the device and the
microcontroller that interfaces to the ADC to take subsequent readings from the ADS124S0x in continuous
conversion mode. The dedicated DRDY pin indicates availability of new conversion data. Pseudo code is
shown without the use of the STATUS byte and CRC data verification. ADS124S08 firmware example
code is available from the ADS124S08 product folder.

Configure microcontroller for SPI mode 1 (CPOL = 0, CPHA = 1)

Configure microcontroller GPIO for /DRDY as a falling edge triggered interrupt input
Set CS low;
Send 06; // RESET command to make sure the device is properly reset after power-up
Set CS high;
Set CS low; // Configure the device
Send 42 // WREG starting at 02h address
05 // Write to 6 registers
12 // Select AINP = AIN1 and AINN = AIN2
0A // PGA enabled, Gain = 4
14 // Continuous conversion mode, low-latency filter, 20-SPS data rate
02 // Positive and negative reference buffers enabled,
// REFP0 and REFN0 reference selected, internal reference always on
07 // IDAC magnitude set to 1 mA
F0; // IDAC1 set to AIN0, IDAC2 disabled
Set CS high;
Set CS low; // For verification, read back configuration registers
Send 22 // RREG starting at 02h address
05 // Read from 6 registers
00 00 00 00 00 00; // Send 6 NOPs for the read
Set CS high;
Set CS low;
Send 08; // Send START command to start converting in continuous conversion mode;
Set CS high;
Loop
{
Wait for DRDY to transition low;
Set CS low;
Send 12 // Send RDATA command
00 00 00; // Send 3 NOPs (24 SCLKs) to clock out data
Set CS high;
}
Set CS low;
Send 0A; //STOP command stops conversions and puts the device in standby mode;
Set CS to high;

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RTD Circuit Comparison Table

RTD Circuit Topology Advantages Disadvantages

Two-wire RTD, low-side
Least expensive Least accurate, no lead-resistance cancellation
reference
Three-wire RTD, low-side Sensitive to IDAC current mismatch, mismatch can be
reference, two IDAC Allows for lead-resistance cancellation removed by swapping IDAC currents and averaging
current sources two measurements
Three-wire RTD, low-side
Requires two measurements, first for RTD
reference, one IDAC Allows for lead-resistance cancellation
measurement, second for lead-resistance cancellation
current source
Three-wire RTD, high-side
Allows for lead-resistance cancellation, less sensitive Requires extra resistor for biasing, added voltage may
reference, two IDAC
to IDAC mismatch than using low side reference not be compatible with low supply operation
current sources
Four-wire RTD, low-side
Most accurate, no lead-resistance error Most expensive
reference

Design Featured Devices

Other Possible
Device Key Features Link
Devices
24-Bit, 4kSPS, 12-Ch Delta-Sigma ADC With PGA and Voltage Reference
ADS124S08 www.ti.com/product/ADS124S08 Link to similar devices
for Precision Sensor Measurement
16-Bit, 4kSPS, 12-Ch Delta-Sigma ADC With PGA and Voltage Reference
ADS114S08 (1) www.ti.com/product/ADS114S08 Link to similar devices
for Precision Sensor Measurement

(1)
The ADS114S08 is a 16-bit version of the ADS124S08 and may be used in similar applications.

Design References
See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.
Additional Resources
• Texas Instruments, ADS124S08 Evaluation Module
• Texas Instruments, ADS1x4S08 Evaluation Module User's Guide
• Texas Instruments, ADS1x4S08 Firmware Example Code
• Texas Instruments, A Basic Guide to RTD Measurements Application Report
• Texas Instruments, RTD Ratiometric Measurements and Filtering Using the ADS1148 and ADS1248
Family of Devices Application Report
For direct support from TI Engineers use the E2E community
e2e.ti.com

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 Analog Engineer's Circuit: Data
Converters
SBAA310 – December 2018

Three-wire PT100 RTD measurement circuit with high-side

reference and two IDAC current sources

Joseph Wu, Chris Hall

Power Supplies
AVDD AVSS, DGND DVDD
5V 0V 3.3V

Design Description
This cookbook design describes a temperature measurement for a three-wire RTD using the ADS1261.
This design uses a ratiometric measurement with a high-side reference using two matched excitation
current sources for a PT100 type RTD with a temperature measurement range from –200°C to 850°C.
Included in this design are ADC configuration register settings and pseudo code to configure and read
from the device. This circuit can be used in applications such as analog input modules for PLCs, lab
instrumentation, and factory automation. For more information about making precision ADC
measurements with a variety of RTD wiring configurations, see A Basic Guide to RTD Measurements.
5V 3.3 V

0.1 F 10 F 1 F 1 F

AVDD DVDD BYPASS

500 A
AINCOM
IDAC1 ADS1261

3.32 k AIN0

4.7 nF (REFP0)
RREF
VREF = 1.76 V 47 nF
3.52 k
4.7 nF
AIN1
(REFN0)
3.32 k

Optional
protection

Lead 1 4.99 k AIN2

4.7 nF
VRTD = 10 mV to 200 mV RRTD 47 nF PGA ADC
4.7 nF
AIN3
Lead 2
4.99 k
Optional
protection
AIN4
IDAC2
Lead 3
Mux
500 A

RBIAS AVSS
VBIAS = 1.1 V
1.1 k

1 mA

SBAA310 – December 2018 Three-wire PT100 RTD measurement circuit with high-side
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Design Notes
1. Use supply decoupling capacitors for both the analog and digital supplies. Place 0.1-μF and 10-μF
capacitors between AVDD and AVSS (ground). Connect a 1-μF capacitor from DVDD to the ground
plane. Connect a 1-μF capacitor from BYPASS to the ground plane. See the ADS126x Precision, 5-
Channel and 10-Channel, 40-kSPS, 24-Bit, Delta-Sigma ADCs With PGA and Monitors data sheet for
details on power-supply recommendations.
2. Do not route the excitation currents through input filter resistors, using the same pin as an ADC input
and as the output for an IDAC current source. Excitation currents reacting with series resistance adds
error to the measurement.
3. A 10-µF capacitor is required between REFOUT and REFCOM to enable the internal reference for the
IDAC current.
4. Use a precision reference resistor with high accuracy and low drift. Because the measurement is
ratiometric, accuracy is dependent on the error of this reference resistor. A 0.01% resistor contributes
a gain error similar to that as the ADC.
5. When possible, use C0G (NPO) ceramic capacitors for input filtering. The dielectric used in these
capacitors provides the most stable electrical properties over voltage, frequency, and temperature
changes.
6. Input filtering for the ADC inputs and the reference inputs are selected using standard capacitor values
and 1% resistor values. An example design and analysis of these filters is found in RTD Ratiometric
Measurements and Filtering Using the ADS1148 and ADS1248 Family of Devices.
7. This design shows connections to six input pins of the ADC multiplexer. Remaining analog inputs may
be used for other measurements, such as bridge measurements with AC excitation.
8. Because of lead-resistance cancellation, the three-wire measurement offers more accuracy than
comparable two-wire RTD measurements. Using a high-side reference for this design significantly
reduces the error from IDAC current mismatch seen in three-wire RTD measurements using a low-side
reference. For measurements with other RTD wiring configurations, see A Basic Guide to RTD
Measurements.

Component Selection
1. Identify the range of operation for the RTD.
As an example, a PT100 RTD has a range of approximately 20Ω to 400Ω if the temperature
measurement range is from −200°C to 850°C. The reference resistor must be larger than the maximum
RTD value. The reference resistance and PGA gain determines the positive full scale range of the
measurement.
2. Use two matched IDAC current sources to cancel the lead-resistance error.
Two matched IDAC current sources are used for lead-resistance cancellation. Assuming the
resistances of lead 1 and lead 2 are the same, and the currents of IDAC1 and IDAC2 are the same,
then the lead-resistance error is cancelled. Cancellation can be shown through the measured voltages
at AIN2 and AIN3.
IDAC1 drives current into the reference resistor RREF and the RTD through lead 1. IDAC2 drives
current into lead 2. First, assume that the input protection shown in the circuit has no voltage drop. The
voltages at AIN2 and AIN3 are calculated with the following equations.
VAIN2 = IIDAC1 • (RLEAD1 + RRTD) + (IIDAC1 + IIDAC2) • (RLEAD3 + RBIAS)
VAIN3 = IIDAC2 • RLEAD2 + (IIDAC1 + IIDAC2) • (RLEAD3 + RBIAS)
The measurement of the ADC is the difference between AIN2 and AIN3, which is the subtraction of the
previous equations.
VAIN2 – VAIN3 = [IIDAC1 • (RLEAD1 + RRTD + RBIAS) + (IIDAC1 + IIDAC2) • (RLEAD3 + RBIAS)] – [IIDAC2 • RLEAD2 + (IIDAC1 + IIDAC2) •
(RLEAD3 + RBIAS)]
Then, the RLEAD3 and RBIAS terms drop out.
VAIN2 – VAIN3 = IIDAC1 • (RLEAD1 + RRTD) – IIDAC2 • RLEAD2
If RLEAD1 and RLEAD2 are equal and IIDAC1 and IIDAC2 are equal (to become IIDAC), then the lead resistance
errors cancel to leave the following equation:
VAIN2 – VAIN3 = IIDAC • RRTD

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3. Determine values for the IDAC excitation currents and reference resistor.
The excitation current source in this design is selected to be 500μA. This maximizes the value of the
RTD voltage while keeping the self-heating of the RTD low. The typical range of RTD self-heating
coefficients is 2.5mW/°C for small, thin-film elements and 65mW/°C for larger, wire wound elements.
With 500-μA excitation at the maximum RTD resistance value, the power dissipation in the RTD is less
than 0.4mW and keeps the measurement errors from self-heating to less than 0.005°C.
After selecting the IDAC current magnitude, set RREF = 3.52kΩ. Using a 500-μA excitation current sets
the reference at 1.76V and the maximum RTD voltage is 200mV. With these values, the PGA gain can
be set to 8 so that the maximum RTD voltage is near the positive full scale range without exceeding it.
The reference resistor, RREF must be a precision resistor with high accuracy and low drift. Any error in
RREF reflects the same error in the RTD measurement. The REFP and REFN pins (AIN0 and AIN1) are
shown connecting to the RREF resistor as a Kelvin connection to get the best measurement of the
reference voltage. This eliminates any series resistance as an error from the reference resistance
measurement.
Note that for a high-side reference, the current flowing through the reference resistor and the RTD are
the same. For a three-wire RTD measurement with a low-side reference, the IDAC current mismatch is
a large contributor to the error. In this design, the mismatch only leads to a smaller error in the lead-
resistor cancellation, rather than a larger gain error in the RTD measurement.
4. Set RBIAS and verify that the design is within the range of operation of the ADC.
Once the reference resistance, IDAC current magnitudes, and ADC gain are set, select the RBIAS
resistance to set the bias voltage of the input measurement. Normally, RBIAS is selected to set the input
to the mid-supply voltage. However, there is a large total sum of the voltage drop across the reference
resistor, the RTD resistance, the bias resistor, and any optional input protection used in the circuit. It is
important that the RBIAS input offset is high enough to keep the RTD measurement voltage in the PGA
input range, but not too high so that the excitation current output pin is within the compliance voltage of
the IDAC.
Setting RBIAS of 1.1kΩ meets this requirement. Using the maximum RTD resistance of 400Ω, the ADC
input voltages are calculated in the following equations. The small lead resistances can be ignored for
this calculation.
VAIN2 = (IIDAC1 • RRTD) + [(IIDAC1 + IIDAC2) • RBIAS] = 1.3V
VAIN3 = (IIDAC1 + IIDAC2) • RBIAS = 1mA • 1.1kΩ = 1.1V
VINMAX = 500µA • 400Ω = 200mV
First, verify that the voltage at AIN2 and AIN3 are within the input range of the PGA given that the gain
is 8 and that AVDD is 5V and AVSS is 0V. As shown in the ADS126x Precision, 5-Channel and 10-
Channel, 40-kSPS, 24-Bit, Delta-Sigma ADCs With PGA and Monitors data sheet, the absolute input
voltage must satisfy the following:
AVSS + 0.3V + [|VINMAX| • (Gain – 1) / 2] < VAIN2, VAIN3 < VAVDD – 0.3V – [|VINMAX| • (Gain – 1) / 2]
0.3V + [|0.2V| • (8 – 1) / 2] < VAIN2, VAIN3 < 5V– 0.3V – [|0.2V| • (8 – 1) / 2]
1V < VAIN2, VAIN3 < 4V
Because the maximum and minimum input voltage seen at AIN2 and AIN2 (1.1V and 1.3V) are
between 1V and 4V, the inputs are in the PGA operating range.
Second, verify that the IDAC output pin voltages are within the compliance voltage. The IDAC current
output voltage is highest and most limited by output compliance when the RTD voltage is at a
maximum as the following equation shows. As before, we can ignore the low voltage contribution of the
lead resistance.
VIDAC1 = VBIAS + VRTD + VD + VREF
VIDAC1 = 1V + 0.2V + 0.3V + 1.76V = 3.26V
The maximum RTD voltage is 200mV and a drop of 300mV is assumed for an input protection
Schottky diode (VD).
The IDAC current compliance range is listed in the Electrical Characteristics table under the Current
Sources section of the ADS126x Precision, 5-Channel and 10-Channel, 40-kSPS, 24-Bit, Delta-Sigma
ADCs With PGA and Monitors data sheet. The IDAC current compliance range is given by the
following equation.
AVSS < VIDAC1 < AVDD – 1.1V

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In this example design, AVDD is 5V and reduces the following:

0V < VIDAC1 < 3.9V
With the previous equation, the output compliance of the IDAC1 pin is satisfied. Because the IDAC2
pin is always at a lower voltage than IDAC1 voltage, both current sources are in the compliance range.
The schematic is shown with two optional input protection diodes. These low VF diodes provide input
fault protection for the IDAC current sources, and may be replaced with series resistances. If series
resistance is used, then the added diode voltage of 0.3V is replaced with the voltage from IIDAC across
the new series resistance for equations verifying the IDAC output pin compliance voltage.
Third, verify that the reference voltage is within the reference voltage input range for the ADC. For the
ADS1261, the differential reference input voltage range is shown in the Recommended Operating
Conditions of the ADS126x Precision, 5-Channel and 10-Channel, 40-kSPS, 24-Bit, Delta-Sigma ADCs
With PGA and Monitors data sheet as the following equation.
0.9V < VREFP – VREFN < AVDD – AVSS
0.9V < 1.76V < 5V
Also verify the absolute negative reference input voltage and verify the absolute positive reference
input voltage with the following equations. Calculations show that the reference voltages are within the
input range of the ADC reference.
AVSS – 0.05V < VREFN = VBIAS + VRTD + VD < VREFP – 0.9V
–0.05V < 1.5V < 4.1V
VREFN < VREFP = VBIAS + VRTD + VD + VREF < AVDD + 0.05V
1.5V < 3.26V < 5.05V
5. Select values for the differential and common-mode input filtering for the ADC inputs and reference
inputs.
This design includes differential and common-mode input RC filtering. The bandwidth of the differential
input filtering is set to be at least 10 × higher than the data rate of the ADC. The common-mode
capacitors are selected to be 1/10 of the value the differential capacitor. Because of capacitor
selection, the bandwidth of common-mode input filtering is approximately 20 × higher than the
differential input filtering. While series filter resistors offer some amount of input protection, keep the
input resistors lower than 10kΩ, to allow for proper input sampling for the ADC.
With input filtering, differential signals are attenuated at a lower frequency than the common-mode
signals, which are significantly rejected by the PGA of the device. Mismatches in common-mode
capacitors cause an asymmetric noise attenuation, appearing as a differential input noise. With a lower
bandwidth for differential signals, the effects from the mismatch of input common-mode capacitors be
reduced. Input filtering for the ADC inputs and reference inputs are designed for the same bandwidth.
In this design, the data rate is chosen to be 20SPS using the low-latency filter of the ADS1261. This
filtering provides a low noise measurement with single-cycle settling and the ability to reject 50-Hz and
60-Hz line noise. For the ADC input filtering, the bandwidth frequency for the differential and common-
mode filtering is approximated in the following equations.
fIN_DIFF = 1 / [2 • π • CIN_DIFF (RRTD + 2 • RIN)]
fIN_CM = 1 / [2 • π • CIN_CM (RRTD + RIN + RBIAS)]
For the ADC input filtering, RIN = 4.99kΩ, CIN_DIFF = 47nF, and CIN_CM = 4.7nF. This sets the differential
filter bandwidth to 330Hz and the common-mode filter bandwidth to 5.4kHz.
Similarly, the bandwidth for the reference input filtering is approximated in the following equations.
fREF_DIFF = 1 / [2 • π • CREF_DIFF • (RREF + 2 • RIN_REF)]
fREF_CM = 1 / {2 • π • CREF_CM • [RIN_REF + (½ • RREF) + RRTD + RBIAS]}
For the reference input filtering, RIN_REF = 3.32kΩ, CREF_DIFF = 47nF, and CREF_CM = 4.7nF. This sets the
differential filter bandwidth to 330Hz and the common-mode filter bandwidth to 5.3kHz. Matching the
ADC input and reference input filtering is not always possible in a design. However, keeping the
bandwidths close may reduce noise in the measurement.
For an in-depth analysis of component selection for input filtering, see RTD Ratiometric Measurements
and Filtering Using the ADS1148 and ADS1248 Family of Devices.

Three-wire PT100 RTD measurement circuit with high-side SBAA310 – December 2018
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Measurement Conversion
RTD measurements are typically ratiometric measurements. Using a ratiometric measurement, the ADC
output code does not need to be converted to a voltage. This means that the output code gives a
measurement only as a ratio of the value of the reference resistor and does not require a precise value for
the excitation current. The only requirement is that the current through the RTD and reference resistor are
the same.
Equations for the measurement conversion are shown for a 24-bit ADC:
Output Code = 223 • Gain • (VRTD / VREF) = 223 • Gain • (IIDAC1 • RRTD) / (IIDAC1 • RREF) = 223 • Gain • (RRTD / RREF)
RRTD = RREF • [Output Code / (Gain • 223)]
The ADC converts the measurement to the RTD equivalent resistance. Because of non-linearity in the
RTD response, the conversion of the resistance to temperature requires an calculation from equation or
lookup table. For more information about the conversion of RTD resistance to temperature, see A Basic
Guide to RTD Measurements.

Register Settings

Configuration Register Settings for a 3-Wire RTD Measurement

with High-Side Reference and Two IDAC Current Sources Using the ADS1261
Register Register Name Setting Description
Address
02h MODE0 24h 20SPS, FIR digital filter
03h MODE1 01h Normal mode, Continuous conversion, 50 μs delay between
conversions
04h MODE2 00h GPIOs disabled
05h MODE3 00h No power-down, no STATUS or CRC byte, timeout disabled
06h REF 1Ah Internal reference enabled, REFP = AIN0, REFN = AIN1
0Dh IMUX 4Ah IDAC2 = AIN4, IDAC1 = AINCOM
0Eh IMAG 44h IMAG2 = IMAG1 = 500μA
0Fh RESERVED 00h Reserved
10h PGA 03h PGA enabled, Gain = 8
11h INPMUX 34h Select AINP = AIN2 and AINN = AIN3
12h INPBIAS 00h VBIAS voltages and burnout current sources disabled

SBAA310 – December 2018 Three-wire PT100 RTD measurement circuit with high-side
Submit Documentation Feedback 152 reference and two IDAC current sources
Copyright © 2018, Texas Instruments Incorporated
 www.ti.com

Pseudo Code Example

The following shows a pseudo code sequence with the required steps to set up the device and the
microcontroller that interfaces to the ADC to take subsequent readings from the ADS1261 in continuous
conversion mode. The dedicated DRDY pin indicates availability of new conversion data. Pseudo code is
shown without the use of the STATUS byte and CRC data verification. ADS1261 example code is
available from the ADS1261 product folder.

Configure microcontroller for SPI mode 1 (CPOL = 0, CPHA = 1)

Configure microcontroller GPIO for /DRDY as a falling edge triggered interrupt input
Set CS low;
Send 06; //RESET command to make sure the device is properly reset after power-up
Set CS high;
Set CS low; // Configure the device
Send 42 // WREG starting at 02h address
04 // Write to 5 registers
24 // 20SPS, FIR digital filter
01 // Normal mode, Continuous conversion, 50µs delay between conversions
00 // GPIOs disabled
00 // No power-down, no STATUS or CRC byte, timeout disabled
1A; // Internal reference enabled, REFP = AIN0, REFN = AIN1
Set CS high;
Set CS low; // Configure the device, IDACs
Send 4D // WREG starting at 0Dh address
05 // Write to 6 registers
4A // IMUX2 = AIN4, IMUX1 = AINCOM
44 // IMAG2 = IMAG1 = 500µA
00 // RESERVED
03 // PGA enabled, Gain = 8
34 // Select AINP = AIN2 and AINN = AIN3
00; // VBIAS voltages and burn-out current sources disabled
Set CS high;
Set CS low; // For verification, read back configuration registers
Send 22 // RREG starting at 02h address
10 // Read from 17 registers
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00; // Send 17 NOPs for the read
Set CS high;
Set CS low;
Send 08; // Send START command to start converting in continuous conversion mode;
Set CS high;
Loop
{
Wait for DRDY to transition low;
Set CS low;
Send 12 // Send RDATA command
00 00 00; // Send 3 NOPs (24 SCLKs) to clock out data
Set CS high;
}
Set CS low;
Send 0A; //STOP command stops conversions and puts the device in standby mode;
Set CS to high;

Three-wire PT100 RTD measurement circuit with high-side SBAA310 – December 2018
reference and two IDAC current sources 153 Submit Documentation Feedback
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RTD Circuit Comparison Table

RTD Circuit Topology Advantages Disadvantages

Two-wire RTD, low-side
Least expensive Least accurate, no lead-resistance cancellation
reference
Three-wire RTD, low-side Sensitive to IDAC current mismatch, mismatch can be
reference, two IDAC current Allows for lead-resistance cancellation removed by swapping IDAC currents and averaging
sources two measurements
Three-wire RTD, low-side
Requires two measurements, first for RTD
reference, one IDAC Allows for lead-resistance cancellation
measurement, second for lead-resistance cancellation
current source
Three-wire RTD, high-side
Allows for lead-resistance cancellation, less sensitive Requires extra resistor for biasing, added voltage may
reference, two IDAC current
to IDAC mismatch than using low side reference not be compatible with low supply operation
sources
Four-wire RTD, low-side
Most accurate, no lead-resistance error Most expensive
reference

Design Featured Devices

Device Key Features Link Other Possible Devices

24-bit 40kSPS 10-ch delta-sigma ADC w/ PGA, Vref, 2 Link to similar devices
ADS1261 http://www.ti.com/product/ADS1261
× IDACs, and AC excitation for factory automation Link to similar 16-bit devices

Design References
See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.
Additional Resources
• Texas Instruments, ADS1261 Evaluation Module
• Texas Instruments, ADS1261 and ADS1235 Evaluation Module User's Guide
• Texas Instruments, ADS1261 Example C Code Software
• Texas Instruments, A Basic Guide to RTD Measurements
• Texas Instruments, RTD Ratiometric Measurements and Filtering Using the ADS1148 and ADS1248
Family of Devices
For direct support from TI Engineers use the E2E community:
e2e.ti.com

SBAA310 – December 2018 Three-wire PT100 RTD measurement circuit with high-side
Submit Documentation Feedback 154 reference and two IDAC current sources
Copyright © 2018, Texas Instruments Incorporated
 Analog Engineer's Circuit: Data
Converters
SBAA334 – December 2018

Three-wire PT100 RTD measurement circuit with low-side

reference and one IDAC current source

Joseph Wu

Power Supplies
AVDD AVSS, DGND DVDD, IOVDD
3.3V 0V 3.3V

Design Description
This cookbook design describes a temperature measurement for a three-wire RTD with a low-side
reference using the ADS124S08. In comparison to a Three-Wire PT100 RTD Measurement Circuit With
Low- Side Reference and Two IDAC Current Sources with a single measurement, this design uses a
single IDAC excitation current source and a second measurement to remove the lead resistance error.
This design uses a ratiometric measurement for a PT100 type RTD with a temperature measurement
range from –200°C to 850°C. Included in this design are ADC configuration register settings and pseudo
code to configure and read from the device. This circuit can be used in applications such as analog input
modules for PLCs, lab instrumentation, and factory automation. For more information about making
precision ADC measurements with a variety of RTD wiring configurations, see A Basic Guide to RTD
Measurements.

3.3 V 3.3 V

330 nF 0.1 F

AVDD DVDD IOVDD

1 mA
AIN0
IDAC1 ADS124S08

Lead 1 4.99 k AIN1

4.7 nF
PGA
VRTD = 20 mV to 400 mV RRTD 47 nF ADC
Gain = 4
AIN2
Lead 2 4.7 nF
4.99 k
47 nF
4.7 nF
AIN3
IDAC2
Lead 3 4.99 k Mux

4.32 k REFP0

RREF 4.7 nF
VREF = 1.62 V 47 nF
1.62 k
4.7 nF

4.32 k REFN0
AVSS DGND

SBAA334 – December 2018 Three-wire PT100 RTD measurement circuit with low-side
Submit Documentation Feedback 155
reference and one IDAC current source
Copyright © 2018, Texas Instruments Incorporated
 www.ti.com

Design Notes
1. Use supply decoupling capacitors for both the analog and digital supplies. AVDD must be decoupled
with at least a 330-nF capacitor to AVSS. DVDD and IOVDD (when not connected to DVDD) must be
decoupled with at least a 0.1-µF capacitor to DGND. See the ADS124S0x Low-Power, Low-Noise,
Highly Integrated, 6- and 12-Channel, 4-kSPS, 24-Bit, Delta-Sigma ADC with PGA and Voltage
Reference data sheet for details on power supply recommendations.
2. Do not route the excitation currents through input filter resistors, using the same pin as an ADC input
and as the output for an IDAC current source. Excitation currents reacting with series resistance adds
error to the measurement.
3. A 1-µF capacitor is required between REFOUT and REFCOM to enable the internal reference for the
IDAC current.
4. Use a precision reference resistor with high accuracy and low drift. Because the measurement is
ratiometric, accuracy is dependent on the error of this reference resistor. A 0.01% resistor contributes
a gain error similar to that as the ADC.
5. When possible, use C0G (NPO) ceramic capacitors for input filtering. The dielectric used in these
capacitors provides the most stable electrical properties over voltage, frequency, and temperature
changes.
6. Input filtering for the ADC inputs and the reference inputs are selected using standard capacitor values
and 1% resistor values. An example design and analysis of these filters is found in RTD Ratiometric
Measurements and Filtering Using the ADS1148 and ADS1248 Family of Devices.
7. This design shows connections to four input pins of the ADC multiplexer. Remaining analog inputs may
be used for RTD, thermocouple, or other measurements.
8. The three-wire RTD measurement offers more accuracy than comparable two-wire RTD
measurements but also gives better immunity from the IDAC current mismatch than with a three-wire
RTD measurement using matched IDAC current sources. For measurements with other RTD wiring
configurations, see A Basic Guide to RTD Measurements.

Component Selection
1. Identify the range of operation for the RTD.
As an example, a PT100 RTD has a range of approximately 20Ω to 400Ω if the temperature
measurement range is from −200°C to 850°C. The reference resistor must be larger than the maximum
RTD value. The reference resistance and PGA gain determines the positive full scale range of the
measurement.
2. Determine values for the IDAC excitation current and reference resistor.
Start with a design where the excitation current is driven into lead 1 of the RTD, flowing through the
RTD, and out the RTD through lead 3. At this point, ignore the lead resistance error, so that the
measurement from AIN1 to AIN2 only measures the RTD resistance.
The excitation current source in this design is selected to be 1mA. This maximizes the value of the
RTD voltage while keeping the self-heating of the RTD low. The typical range of RTD self-heating
coefficients is 2.5mW/°C for small, thin-film elements and 65mW/°C for larger, wire-wound elements.
With 1-mA excitation at the maximum RTD resistance value, the power dissipation in the RTD is less
than 0.4mW and keeps the measurement errors from self-heating to less than 0.01˚C.
After selecting the IDAC current magnitude, set RREF = 1620Ω. This sets the reference at 1.62V and
the maximum RTD voltage is 400mV. The reference voltage acts as a level shift to place the input
measurement to near mid-supply, putting the measurement in the PGA input operating range. With
these values, the PGA gain can be set to 4 so that the maximum RTD voltage is near the positive full
scale range without exceeding it.
The reference resistor, RREF must be a precision resistor with high accuracy and low drift. Any error in
RREF reflects the same error in the RTD measurement. The REFP0 and REFN0 pins are shown
connecting to the RREF resistor as a Kelvin connection to get the best measurement of the reference
voltage. This eliminates any series resistance as an error from the reference resistance measurement.
Using the maximum RTD resistance, the ADC input voltages are calculated in the following equations.
The small lead resistances can be ignored for this calculation.

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reference and two IDAC current sources 156 Submit Documentation Feedback
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VAIN1 = IIDAC1 • (RRTD + RREF) = 1mA • (400Ω + 1620Ω) = 2.02V

VAIN2 = IIDAC1 • RREF = 1mA • 1620Ω = 1.62V
VINMAX = 1mA • 400Ω = 400mV
3. Verify that the design is within the range of operation of the ADC.
First, verify that VAIN1 and VAIN2 are within the input range of the PGA given that the gain is 4 and that
AVDD is 3.3V and AVSS is 0V. As shown in the ADS124S0x Low-Power, Low-Noise, Highly
Integrated, 6- and 12-Channel, 4-kSPS, 24-Bit, Delta-Sigma ADC with PGA and Voltage Reference
data sheet, the absolute input voltage must satisfy the following:
AVSS + 0.15V + [|VINMAX| • (Gain − 1) / 2] < VAIN1, VAIN2 < AVDD − 0.15V − [|VINMAX| (Gain − 1) / 2]
0V + 0.15V + [|VINMAX| • (Gain − 1) / 2] < VAIN1, VAIN2 < 3.3V − 0.15V − [|VINMAX| (Gain − 1) / 2]
0.75V < VAIN1, VAIN2 < 2.55 V
Because the maximum and minimum input voltages seen at AIN1 and AIN2 (2.02V and 1.62V) are
between 0.75V and 2.55V, the inputs are in the PGA operating range.
Second, verify that the voltage at the IDAC output pin is within the current source compliance voltage.
The IDAC pin is AIN0, which have the same voltage as AIN1. At the maximum voltage, VAIN0 is 2.02V.
As shown in the Electrical Characteristics table in the ADS124S0x Low-Power, Low-Noise, Highly
Integrated, 6- and 12-Channel, 4-kSPS, 24-Bit, Delta-Sigma ADC with PGA and Voltage Reference
data sheet, the output voltage of the IDAC must be between AVSS and AVDD − 0.6V for an IDAC
current of 1mA. In this example, with AVDD = 3.3V, the IDAC output must be:
AVSS < VAIN0 = VAIN1 < AVDD − 0.6V
0V < VAIN0 < 2.7V
With the previous result, the output compliance of the IDAC is satisfied.
4. Use two different measurements to measure the RTD resistance and cancel the lead-resistance error.
The first measurement of the ADC is measured across AIN1 and AIN2, with the lead resistances
included.
Measurement 1 = VAIN1 – VAIN2 = IIDAC1 • (RRTD + RLEAD1)
Because the IDAC current does not pass through lead 2, its resistance is never part of the
measurement. The input multiplexer of the ADC is then set to make a second measurement across
AIN2 and AIN3. This measures the voltage drop across the resistance from lead 3.
Measurement 2 = VAIN2 – VAIN3 = IIDAC1 • RLEAD3
Measurement 2 is subtracted from measurement 1 to get the following result.
Measurement 1 – Measurement 2 = [IIDAC1 • (RRTD + RLEAD1)] – (IIDAC1 • RLEAD3)
If the lead resistances are equal, then the lead-resistance error drops out to get the final result.
Measurement 1 – Measurement 2 = IIDAC1 • RRTD
5. Select values for the differential and common-mode filtering for the ADC inputs and reference inputs.
This design includes differential and common-mode input RC filtering. The bandwidth of the differential
input filtering is set to be at least 10 × higher than the data rate of the ADC. The common-mode
capacitors are selected to be 1/10 of the value the differential capacitor. Because of capacitor
selection, the bandwidth of common-mode input filtering is approximately 20 × higher than the
differential input filtering. While series filter resistors offer some amount of input protection, keep the
input resistors lower than 10 kΩ, to allow for proper input sampling for the ADC.
With input filtering, differential signals are attenuated at a lower frequency than the common-mode
signals, which are significantly rejected by the PGA of the device. Mismatches in common-mode
capacitors cause an asymmetric noise attenuation, appearing as a differential input noise. With a lower
bandwidth for differential signals, the effects from the mismatch of input common-mode capacitors be
reduced. Input filtering for the ADC inputs and reference inputs are designed for the same bandwidth.
In this design, the data rate is chosen to be 20SPS using the low-latency filter of the ADS124S08. This
filtering provides a low noise measurement with single-cycle settling and the ability to reject 50-Hz and
60-Hz line noise. For the ADC input filtering, the bandwidth frequency for the differential and common-
mode filtering is approximated in the following equations.
fIN_DIFF = 1 / [2 • π • CIN_DIFF (RRTD + 2 • RIN)]
fIN_CM = 1 / [2 • π • CIN_CM (RRTD + RIN + RREF)]
For the ADC input filtering, RIN = 4.99kΩ, CIN_DIFF = 47nF, and CIN_CM = 4.7nF. This sets the differential

SBAA334 – December 2018 Three-wire PT100 RTD measurement circuit with high-side
Submit Documentation Feedback 157 reference and two IDAC current sources
Copyright © 2018, Texas Instruments Incorporated
 www.ti.com

filter bandwidth to 330Hz and the common-mode filter bandwidth to 5kHz.

Similarly, the bandwidth for the reference input filtering is approximated in the following equations.
fREF_DIFF = 1 / [2 • π • CREF_DIFF • (RREF + 2 • RIN_REF)]
fREF_CM = 1 / [2 • π • CREF_CM • (RREF + RIN_REF)]
For the reference input filtering, RIN_REF = 4.32kΩ, CREF_DIFF = 47nF, and CREF_CM = 4.7nF. This sets the
differential filter bandwidth to 330Hz and the common-mode filter bandwidth to 5.7kHz. Matching the
ADC input and reference input filtering may not be possible. However, keeping the bandwidths close
may reduce the noise in the measurement.
For an in-depth analysis of component selection for input filtering, see RTD Ratiometric Measurements
and Filtering Using the ADS1148 and ADS1248 Family of Devices.
Measurement Conversion
RTD measurements are typically ratiometric measurements. Using a ratiometric measurement, the ADC
output code does not need to be converted to a voltage. This means that the output code gives a
measurement only as a ratio of the value of the reference resistor and does not require a precise value for
the excitation current. The only requirement is that the current through the RTD and reference resistor are
the same.
Equations for the measurement conversion are shown for a 24-bit ADC. First, the result from
measurement 1 is shown.
Output Code 1 = 223 • Gain • [(VRTD + VLEAD1)/ VREF] = 223 • Gain • [IIDAC1 • (RRTD + RLEAD1)] / (IIDAC1 • RREF) = 223 •
Gain • [(RRTD + RLEAD1) / RREF]
RRTD + RLEAD1 = RREF • [Output Code / (Gain • 223)]
Then the result from measurement 2 is shown.
Output Code 2 = 223 • Gain • (VLEAD3 / VREF = 223 • Gain • (IIDAC1 • RLEAD3) / (IIDAC1 • RREF) = 223 • Gain • (RLEAD1 / RREF)
RLEAD3 = RREF • [Output Code / (Gain • 223)]
If the lead resistances are assumed to be equal, then the subtract the result of measurement 2 from
measurement 1 to get the equivalent RTD resistance.
RRTD = RREF • [(Output Code 1 - Output Code 2) / (Gain • 223)]
The ADC converts the measurement to the RTD equivalent resistance. Because of non-linearity in the
RTD response, the conversion of the resistance to temperature requires an calculation from equation or
lookup table. For more information about the conversion of RTD resistance to temperature, see A Basic
Guide to RTD Measurements.

Register Settings

Configuration Register Settings for a Three-Wire PT100 RTD Measurement Circuit with Low-Side
Reference and One IDAC Current Source Using the ADS124S08
Register Register Name Setting Description
Address
02h (1) INPMUX 12h Select AINP = AIN1 and AINN = AIN2
03h PGA 0Ah PGA enabled, Gain = 4
04h DATARATE 14h Continuous conversion mode, low-latency filter, 20-SPS data rate
05h REF 02h Positive and negative reference buffers enabled, REFP0 and REFN0
reference inputs selected, internal reference always on
06h IDACMAG 07h IDAC magnitude set to 1mA
07h IDACMUX F0h IDAC1 set to AIN0, IDAC2 disabled
08h VBIAS 00h VBIAS not used for any input
09h SYS 10h Normal mode of operation
(2)
02h INPMUX 23h Select AINP = AIN2 and AINN = AIN3
(1)
This input multiplexer setting is for measurement 1.
(2)
This input multiplexer setting is for measurement 2, as a measurement of the lead-resistance error.

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reference and two IDAC current sources 158 Submit Documentation Feedback
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Pseudo Code Example

The following shows a pseudo code sequence with the required steps to set up the device and the
microcontroller that interfaces to the ADC to take subsequent readings from the ADS124S0x in continuous
conversion mode. The dedicated DRDY pin indicates availability of new conversion data. Pseudo code is
shown without the use of the STATUS byte and CRC data verification. ADS124S08 firmware example
code is available from the ADS124S08 product folder.

Configure microcontroller for SPI mode 1 (CPOL = 0, CPHA = 1)

Configure microcontroller GPIO for /DRDY as a falling edge triggered interrupt input
Set CS low;
Send 06; // RESET command to make sure the device is properly reset after power-up
Set CS high;
Set CS low; // Configure the device
Send 42 // WREG starting at 02h address
05 // Write to 6 registers
12 // Select AINP = AIN1 and AINN = AIN2
0A // PGA enabled, Gain = 4
14 // Continuous conversion mode, low-latency filter, 20-SPS data rate
02 // Positive and negative reference buffers enabled,
// REFP0 and REFN0 reference selected, internal reference always on
07 // IDAC magnitude set to 1mA
F0; // IDAC1 set to AIN0, IDAC2 disabled
Set CS high;
Set CS low; // For verification, read back configuration registers
Send 22 // RREG starting at 02h address
05 // Read from 6 registers
00 00 00 00 00 00; // Send 6 NOPs for the read
Set CS high;
Set CS low;
Send 08; // Send START command to start converting in continuous conversion mode;
Set CS high;
Loop
{
Set CS low; // Configure the device for measurement 1
Send 42 // WREG starting at 02h address
00 // Write to 1 register
12; // Select AINP = AIN1 and AINN = AIN2
Set CS high;
Wait for DRDY to transition low;
Set CS low;
Send 12 // Send RDATA command
00 00 00; // Send 3 NOPs (24 SCLKs) to clock out data
Set CS high;
Set CS low; // Configure the device for measurement 2
Send 42 // WREG starting at 02h address
00 // Write to 1 register
23; // Select AINP = AIN2 and AINN = AIN3
Set CS high;
Wait for DRDY to transition low;
Set CS low;
Send 12 // Send RDATA command
00 00 00; // Send 3 NOPs (24 SCLKs) to clock out data
Set CS high;
Subtract measurement 2 from measurement 1; // Remove lead-resistance error
}
Set CS low;
Send 0A; //STOP command stops conversions and puts the device in standby mode;
Set CS to high;

SBAA334 – December 2018 Three-wire PT100 RTD measurement circuit with high-side
Submit Documentation Feedback 159 reference and two IDAC current sources
Copyright © 2018, Texas Instruments Incorporated
 www.ti.com

RTD Circuit Comparison Table

RTD Circuit Topology Advantages Disadvantages

Two-wire RTD, low-side
Least expensive Least accurate, no lead-resistance cancellation
reference
Three-wire RTD, low-side Sensitive to IDAC current mismatch, mismatch can be
reference, two IDAC Allows for lead-resistance cancellation removed by swapping IDAC currents and averaging
current sources two measurements
Three-wire RTD, low-side
Requires two measurements, first for RTD
reference, one IDAC Allows for lead-resistance cancellation
measurement, second for lead-resistance cancellation
current source
Three-wire RTD, high-side
Allows for lead-resistance cancellation, less sensitive Requires extra resistor for biasing, added voltage may
reference, two IDAC
to IDAC mismatch than using low side reference not be compatible with low supply operation
current sources
Four-wire RTD, low-side
Most accurate, no lead-resistance error Most expensive
reference

Design Featured Devices

Other Possible
Device Key Features Link
Devices
24-Bit, 4kSPS, 12-Ch Delta-Sigma ADC With PGA and Voltage Link to similar
ADS124S08 www.ti.com/product/ADS124S08
Reference for Precision Sensor Measurement devices
16-Bit, 4kSPS, 12-Ch Delta-Sigma ADC With PGA and Voltage Link to similar
ADS114S08 (1) www.ti.com/product/ADS114S08
Reference for Precision Sensor Measurement devices

(1)
The ADS114S08 is a 16-bit version of the ADS124S08 and may be used in similar applications.

Design References
See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.
Additional Resources
• Texas Instruments, ADS124S08 Evaluation Module
• Texas Instruments, ADS1x4S08 Evaluation Module User's Guide
• Texas Instruments, ADS1x4S08 Firmware Example Code
• Texas Instruments, A Basic Guide to RTD Measurements
• Texas Instruments, RTD Ratiometric Measurements and Filtering Using the ADS1148 and ADS1248
Family of Devices
For direct support from TI Engineers use the E2E community:
e2e.ti.com

Three-wire PT100 RTD measurement circuit with high-side SBAA334 – December 2018
reference and two IDAC current sources 160 Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
 Analog Engineer's Circuit: Data
Converters
SBAA330 – December 2018

Three-wire PT100 RTD measurement circuit with low-side

reference and two IDAC current sources

Joseph Wu

Power Supplies
AVDD AVSS DVDD, IOVDD
3.3V 0V 3.3V

Design Description
This cookbook design describes a temperature measurement for a three-wire RTD using the ADS124S08.
This design uses two matched IDAC excitation currents for lead-resistance cancellation. This topology
creates a ratiometric measurement for a PT100 type RTD with a temperature measurement range from
–200°C to 850°C. Included in this design are ADC register settings and pseudo code is provided to
configure and read from the device. This circuit can be used in applications such as analog input modules
for PLCs, lab instrumentation, and factory automation. For more information about making precision ADC
measurements with a variety of RTD wiring configurations, see A Basic Guide to RTD Measurements.

3.3 V 3.3 V

330 nF 0.1 F

AVDD DVDD IOVDD

1 mA

AIN0
IDAC1 ADS124S08

Lead 1 4.99 k AIN1

4.7 nF
PGA
VRTD = 0.02 V to 400 mV RRTD 47 nF ADC
Gain = 4
4.7 nF
AIN2
Lead 2
4.99 k

AIN3
IDAC2
Lead 3
1 mA Mux

4.75 k REFP0

RREF 4.7 nF
VREF = 1.64 V 47 nF
820
4.7 nF

4.75 k REFN0
AVSS DGND

SBAA330 – December 2018 Three-wire PT100 RTD measurement circuit with low-side
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Design Notes
1. Use supply decoupling capacitors for both the analog and digital supplies. AVDD must be decoupled
with at least a 330-nF capacitor to AVSS. DVDD and IOVDD (when not connected to DVDD) must be
decoupled with at least a 0.1-µF capacitor to DGND. See the ADS124S0x Low-Power, Low-Noise,
Highly Integrated, 6- and 12-Channel, 4-kSPS, 24-Bit, Delta-Sigma ADC with PGA and Voltage
Reference data sheet for details on power supply recommendations.
2. Do not route the excitation currents through input filter resistors, using the same pin as an ADC input
and as the output for an IDAC current source. Excitation currents reacting with series resistance adds
error to the measurement.
3. A 1-µF capacitor is required between REFOUT and REFCOM to enable the internal reference for the
IDAC current.
4. Use a precision reference resistor with high accuracy and low drift. Because the measurement is
ratiometric, accuracy is dependent on the error of this reference resistor. A 0.01% resistor contributes
a gain error similar to that as the ADC.
5. When possible, use C0G (NPO) ceramic capacitors for input filtering. The dielectric used in these
capacitors provides the most stable electrical properties over voltage, frequency, and temperature
changes.
6. Input filtering for the ADC inputs and the reference inputs are selected using standard capacitor values
and 1% resistor values. An example design and analysis of these filters is found in RTD Ratiometric
Measurements and Filtering Using the ADS1148 and ADS1248 Family of Devices.
7. This design shows connections to four input pins of the ADC multiplexer. Remaining analog inputs may
be used for RTD, thermocouple, or other measurements.
8. Because of lead-resistance cancellation, the three-wire measurement offers more accuracy than
comparable two-wire RTD measurements. For measurements with other RTD wiring configurations,
see A Basic Guide to RTD Measurements.

Component Selection
1. Identify the range of operation for the RTD.
As an example, a PT100 RTD has a range of approximately 20Ω to 400Ω if the temperature
measurement range is from −200°C to 850°C. The reference resistor must be larger than the maximum
RTD value. The reference resistance and PGA gain determines the positive full scale range of the
measurement.
2. Use two matched IDAC current sources to cancel the lead-resistance error.
Two matched IDAC current sources are used for lead-resistance cancellation. Assuming the
resistances of lead 1 and lead 2 are the same, and the currents of IDAC1 and IDAC2 are the same,
then the lead-resistance error may be cancelled. Cancellation can be shown through the measured
voltages at AIN1 and AIN2.
IDAC1 drives current into the RTD through lead 1. IDAC2 drives a matched current into lead 2. The
voltage at AIN1 is calculated with the following equation.
VAIN1 = IIDAC1 • (RLEAD1 + RRTD) + (IIDAC1 + IIDAC2) • (RLEAD3 + RREF)
At the same time, voltage at AIN2 is also calculated.
VAIN2 = IIDAC2 • RLEAD2 + (IIDAC1 + IIDAC2) • (RLEAD3 + RREF)
The measurement of the ADC is the difference between AIN1 and AIN2, which is the subtraction of the
first two equations to get the following.
VAIN1 – VAIN2 = [IIDAC1 • (RLEAD1 + RRTD) + (IIDAC1 + IIDAC2) • (RLEAD3 + RREF)] – [IIDAC2 • RLEAD2 + (IIDAC1 + IIDAC2) • (RLEAD3 +
RREF)]
The RLEAD3 and RREF terms drop out.
VAIN1 – VAIN2 = IIDAC1 • (RLEAD1 + RRTD) – IIDAC2 • RLEAD2
So if RLEAD1 and RLEAD2 are equal and IIDAC1 and IIDAC2 are equal (to become IIDAC), then the lead
resistance errors cancel.
VAIN1 – VAIN2 = IIDAC • RRTD

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3. Determine values for the IDAC excitation currents and reference resistor.
The excitation current source in this design is selected to be 1mA. This maximizes the value of the
RTD voltage while keeping the self-heating of the RTD low. The typical range of RTD self-heating
coefficients is 2.5mW/°C for small, thin-film elements and 65mW/°C for larger, wire-wound elements.
With 1-mA excitation at the maximum RTD resistance value, the power dissipation in the RTD is less
than 0.4mW and keeps the measurement errors from self-heating to less than 0.01˚C.
After selecting the IDAC current magnitude, set RREF = 820Ω. Using two matched 1-mA excitation
currents sets the reference at 1.64V and the maximum RTD voltage is 400mV. The reference voltage
acts as a level shift to place the input measurement to near mid-supply, putting the measurement in
the PGA input operating range. With these values, the PGA gain can be set to 4 so that the maximum
RTD voltage is near the positive full scale range without exceeding it.
The reference resistor, RREF must be a precision resistor with high accuracy and low drift. Any error in
RREF reflects the same error in the RTD measurement. The REFP0 and REFN0 pins are shown
connecting to the RREF resistor as a Kelvin connection to get the best measurement of the reference
voltage. This eliminates any series resistance as an error from the reference resistance measurement.
Using the maximum RTD resistance, the ADC input voltages are calculated in the following equations.
The small lead resistances can be ignored for this calculation.
VAIN1 = (IIDAC1 • RRTD) + [(IIDAC1 + IIDAC2) • RREF] = (1mA • 400Ω) + (2mA • 820Ω) = 2.04V
VAIN2 = (IIDAC1 + IIDAC2) • RREF = 2mA • 820Ω = 1.64V
VINMAX = 1mA • 400Ω = 400mV
4. Verify that the design is within the range of operation of the ADC.
First, verify that VAIN1 and VAIN2 are within the input range of the PGA given that the gain is 4 and that
AVDD is 3.3V and AVSS is 0V. As shown in the ADS124S0x Low-Power, Low-Noise, Highly
Integrated, 6- and 12-Channel, 4-kSPS, 24-Bit, Delta-Sigma ADC with PGA and Voltage Reference
data sheet, the absolute input voltage must satisfy the following:
AVSS + 0.15V + [|VINMAX| • (Gain − 1) / 2] < VAIN1, VAIN2 < AVDD − 0.15V − [|VINMAX| (Gain − 1) / 2]
0V + 0.15V + [|VINMAX| • (Gain − 1) / 2] < VAIN1, VAIN2 < 3.3V − 0.15V − [|VINMAX| (Gain − 1) / 2]
0.75V < VAIN1, VAIN2 < 2.55V
Because the maximum and minimum input voltages seen at AIN1 and AIN2 (2.04V and 1.64V) are
between 0.75V and 2.55V, the inputs are in the PGA operating range.
Second, verify that the voltage seen at the IDAC output is within the current source compliance
voltage. The IDAC1 pin is AIN0 which has the same voltage as AIN1. At the maximum voltage, VAIN0 is
2.04V. As shown in the Electrical Characteristics table in the ADS124S0x Low-Power, Low-Noise,
Highly Integrated, 6- and 12-Channel, 4-kSPS, 24-Bit, Delta-Sigma ADC with PGA and Voltage
Reference data sheet, the output voltage of the IDAC pin must be between AVSS and AVDD − 0.6V
for an IDAC current of 1mA. In this example, with AVDD = 3.3V, the IDAC output must be:
AVSS < VAIN0 = VAIN1 < AVDD − 0.6V
0V < VAIN0 < 2.7V
With the previous result, the output compliance of the IDAC1 is satisfied. Because the IDAC2 pin is
always at a lower voltage than the IDAC1 voltage, both current sources are in the compliance range.
5. Select values for the differential and common-mode input filtering for the ADC inputs and reference
inputs.
This design includes differential and common-mode input RC filtering. The bandwidth of the differential
input filtering is set to be at least 10 × higher than the data rate of the ADC. The common-mode
capacitors are selected to be 1/10 of the value the differential capacitor. Because of capacitor
selection, the bandwidth of common-mode input filtering is approximately 20 × higher than the
differential input filtering. While series filter resistors offer some amount of input protection, keep the
input resistors lower than 10kΩ, to allow for proper input sampling for the ADC.
With input filtering, differential signals are attenuated at a lower frequency than the common-mode
signals, which are significantly rejected by the PGA of the device. Mismatches in common-mode
capacitors cause an asymmetric noise attenuation, appearing as a differential input noise. With a lower
bandwidth for differential signals, the effects from the mismatch of input common-mode capacitors be
reduced. Input filtering for the ADC inputs and reference inputs are designed for the same bandwidth.

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In this design, the data rate is chosen to be 20SPS using the low-latency filter of the ADS124S08. This
filtering provides a low noise measurement with single-cycle settling and the ability to reject 50-Hz and
60-Hz line noise. For the ADC input filtering, the bandwidth frequency for the differential and common-
mode filtering is approximated in the following equations.
fIN_DIFF = 1 / [2 • π • CIN_DIFF (RRTD + 2 • RIN)]
fIN_CM = 1 / [2 • π • CIN_CM (RRTD + RIN + RREF)]
For the ADC input filtering, RIN = 4.99kΩ, CIN_DIFF = 47nF, and CIN_CM = 4.7nF. This sets the differential
filter bandwidth to 330Hz and the common-mode filter bandwidth to 5.6kHz.
Similarly, the bandwidth for the reference input filtering is approximated in the following equations.
fREF_DIFF = 1 / [2 • π • CREF_DIFF • (RREF + 2 • RIN_REF)]
fREF_CM = 1 / [2 • π • CREF_CM • (RREF + RIN_REF)]
For the reference input filtering, RIN_REF = 4.75kΩ, CREF_DIFF = 47nF, and CREF_CM = 4.7nF. This sets the
differential filter bandwidth to 330Hz and the common-mode filter bandwidth to 6.1kHz. Matching the
ADC input and reference input filtering may not be possible. However, keeping the bandwidths close
may reduce noise in the measurement.
For an in-depth analysis of component selection for input filtering, see RTD Ratiometric Measurements
and Filtering Using the ADS1148 and ADS1248 Family of Devices.
6. If IDAC current mismatch error is significant, use two measurements to chop the error (optional).
One of the original assumptions in the lead-resistance cancellation is that IDAC1 and IDAC2 match. If
the two IDAC currents do not match, the mismatch causes an error that appears as gain error. The
voltage across the RTD comes from the current of IDAC1, while the voltage across the reference
resistor comes from the current of IDAC1 + IDAC2. For the ADS124S08, the typical IDAC current
mismatch for a 1-mA IDAC current is 0.07%. This mismatch error leads to a gain error of 0.35% in the
measurement. To remove this current mismatch error, the IDAC excitation currents may be chopped.
This involves taking two measurements with the IDAC currents swapped.
For chopping, first take a measurement with IDAC1 set to AIN0 and IDAC2 set to AIN3. Then set
IDAC1 to AIN3 and IDAC2 to AIN0, swapping the current sources, and take a second measurement. In
the first case, IDAC1 drives the RTD, in the second case IDAC2 drives the RTD. In both cases, the
sum of IDAC1 and IDAC2 drive the reference resistor. By averaging the two chopped cases, the
mismatch error is removed from the measurement. For a more detailed analysis of chopping see the
IDAC Current Chopping section of the A Basic Guide to RTD Measurements application report.
Measurement Conversion
RTD measurements are typically ratiometric measurements. Using a ratiometric measurement, the ADC
output code does not need to be converted to a voltage. This means that the output code gives a
measurement only as a ratio of the value of the reference resistor and does not require a precise value for
the excitation current. The only requirement is that the current through the RTD and reference resistor are
the same.
Equations for the measurement conversion are shown for a 24-bit ADC (without IDAC current chopping):
Output Code = 223 • Gain • (VRTD / VREF) = 223 • Gain • (IIDAC1 • RRTD) / (IIDAC1 • RREF) = 223 • Gain • (RRTD / RREF)
RRTD = RREF • [Output Code / (Gain • 223)]
The ADC converts the measurement to the RTD equivalent resistance. Because of non-linearity in the
RTD response, the conversion of the resistance to temperature requires an calculation from equation or
lookup table. For more information about the conversion of RTD resistance to temperature, see A Basic
Guide to RTD Measurements.

Three-wire PT100 RTD measurement circuit with low-side SBAA330 – December 2018
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Register Settings

Configuration Register Settings for a Three-Wire PT100 RTD Measurement

with Low-Side Reference and Two IDAC Current Sources Using the ADS124S08
Register Register Name Setting Description
Address
02h INPMUX 12h Select AINP = AIN1 and AINN = AIN2
03h PGA 0Ah PGA enabled, Gain = 4
04h DATARATE 14h Continuous conversion mode, low-latency filter, 20-SPS data rate
05h REF 02h Positive and negative reference buffers enabled, REFP0 and REFN0
reference inputs selected, internal reference always on
06h IDACMAG 07h IDAC magnitude set to 1mA
07h IDACMUX 30h IDAC1 set to AIN0, IDAC2 set to AIN3
08h VBIAS 00h VBIAS not used for any input
09h SYS 10h Normal mode of operation
(1)
07h IDACMUX 03h IDAC1 set to AIN3, IDAC2 set to AIN0
(1)
This second IDACMUX setting and conversion is used for chopping IDAC excitation current sources (optional).

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Pseudo Code Example

The following shows a pseudo code sequence with the required steps to set up the device and the
microcontroller that interfaces to the ADC to take subsequent readings from the ADS124S0x in continuous
conversion mode. The dedicated DRDY pin indicates availability of new conversion data. Pseudo code is
shown without the use of the STATUS byte and CRC data verification. ADS124S08 firmware example
code is available from the ADS124S08 product folder.

Configure microcontroller for SPI mode 1 (CPOL = 0, CPHA = 1)

Configure microcontroller GPIO for /DRDY as a falling edge triggered interrupt input
Set CS low;
Send 06; // RESET command to make sure the device is properly reset after power-up
Set CS high;
Set CS low; // Configure the device
Send 42 // WREG starting at 02h address
05 // Write to 6 registers
12 // Select AINP = AIN1 and AINN = AIN2
0A // PGA enabled, Gain = 8
14 // Continuous conversion mode, low-latency filter, 20-SPS data rate
02 // Positive and negative reference buffers enabled,
// REFP1 and REFN1 reference selected, internal reference always on
07 // IDAC magnitude set to 1mA
30; // IDAC1 set to AIN0, IDAC2 set to AIN3
Set CS high;
Set CS low; // For verification, read back configuration registers
Send 22 // RREG starting at 02h address
05 // Read from 6 registers
00 00 00 00 00 00; // Send 6 NOPs for the read
Set CS high;
Set CS low;
Send 08; // Send START command to start converting in continuous conversion mode;
Set CS high;
Loop
{
Set CS low; // Configure the device for first chopped measurement
Send 47 // WREG starting at 07h address
00 // Write to 1 register
30; // IDAC1 set to AIN0, IDAC2 set to AIN3
Set CS high;
Wait for DRDY to transition low;
Set CS low;
Send 12 // Send RDATA command
00 00 00; // Send 3 NOPs (24 SCLKs) to clock out data, Record Measurement 1
Set CS high;
Set CS low; // Configure the device for chopped current sources (optional)
Send 47 // WREG starting at 07h address
00 // Write to 1 register
03; // IDAC1 set to AIN3, IDAC2 set to AIN0
Set CS high;
Wait for DRDY to transition low;
Set CS low;
Send 12 // Send RDATA command
00 00 00; // Send 3 NOPs (24 SCLKs) to clock out data, Record Measurement 2
Set CS high;
Average Measurement 1 and Measurement 2;
}
Set CS low;
Send 0A; //STOP command stops conversions and puts the device in standby mode;
Set CS to high;

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RTD Circuit Comparison Table

RTD Circuit Topology Advantages Disadvantages

Two-wire RTD, low-side
Least expensive Least accurate, no lead-resistance cancellation
reference
Three-wire RTD, low-side Sensitive to IDAC current mismatch, mismatch can be
reference, two IDAC Allows for lead-resistance cancellation removed by swapping IDAC currents and averaging
current sources two measurements
Three-wire RTD, low-side
Requires two measurements, first for RTD
reference, one IDAC Allows for lead-resistance cancellation
measurement, second for lead-resistance cancellation
current source
Three-wire RTD, high-side
Allows for lead-resistance cancellation, less sensitive Requires extra resistor for biasing, added voltage may
reference, two IDAC
to IDAC mismatch than using low side reference not be compatible with low supply operation
current sources
Four-wire RTD, low-side
Most accurate, no lead-resistance error Most expensive
reference

Design Featured Devices

Other Possible
Device Key Features Link
Devices
24-Bit, 4kSPS, 12-Ch Delta-Sigma ADC With PGA and Voltage Link to similar
ADS124S08 www.ti.com/product/ADS124S08
Reference for Precision Sensor Measurement devices
16-Bit, 4kSPS, 12-Ch Delta-Sigma ADC With PGA and Voltage Link to similar
ADS114S08 (1) www.ti.com/product/ADS114S08
Reference for Precision Sensor Measurement devices

(1)
The ADS114S08 is a 16-bit version of the ADS124S08 and may be used in similar applications.

Design References
See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.
Additional Resources
• Texas Instruments, ADS124S08 Evaluation Module
• Texas Instruments,
• ADS1x4S08 Evaluation Module User's Guide
• Texas Instruments, ADS1x4S08 Firmware Example Code
• Texas Instruments, A Basic Guide to RTD Measurements
• Texas Instruments, RTD Ratiometric Measurements and Filtering Using the ADS1148 and ADS1248
Family of Devices
For direct support from TI Engineers use the E2E community:
e2e.ti.com

SBAA330 – December 2018 Three-wire PT100 RTD measurement circuit with low-side
Submit Documentation Feedback 167 reference and two IDAC current sources
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 Analog Engineer's Circuit: Data
Converters
SBAA336 – December 2018

Four-wire PT100 RTD measurement circuit with

low-side reference

Joseph Wu

Power Supplies
AVDD AVSS, DGND DVDD, IOVDD
3.3V 0V 3.3V

Design Description
This cookbook design describes a temperature measurement for a four-wire RTD using the ADS124S08.
This design uses a ratiometric measurement for a PT100 type RTD with a temperature measurement
range from –200°C to 850°C. The four-wire RTD measurement is the most accurate of the RTD wiring
configurations because the lead-resistance is not a factor in the measurement. Included in this design are
ADC configuration register settings and pseudo code to configure and read from the device. This circuit
can be used in applications such as analog input modules for PLCs, lab instrumentation, and factory
automation. For more information about making precision ADC measurements with a variety of RTD wiring
configurations, see A Basic Guide to RTD Measurements.

3.3 V 3.3 V

330 nF 0.1 F

AVDD DVDD IOVDD

1 mA
Lead 1 AIN0
IDAC1 ADS124S08

Lead 2 4.99 k AIN1

4.7 nF
VRTD = 20 mV to 400 mV RRTD 47 nF PGA ADC
4.7 nF
AIN2
Lead 3 4.99 k

IDAC2
Lead 4
Mux

4.32 k REFP0

RREF 4.7 nF
VREF = 1.62 V 47 nF
1620
4.7 nF

4.32 k REFN0
AVSS DGND

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Design Notes
1. Use supply decoupling capacitors for both the analog and digital supplies. AVDD must be decoupled
with at least a 330-nF capacitor to AVSS. DVDD and IOVDD (when not connected to DVDD) must be
decoupled with at least a 0.1-µF capacitor to DGND. See the ADS124S0x Low-Power, Low-Noise,
Highly Integrated, 6- and 12-Channel, 4-kSPS, 24-Bit, Delta-Sigma ADC with PGA and Voltage
Reference data sheet for details on power supply recommendations.
2. Do not route the excitation currents through input filter resistors, using the same pin as an ADC input
and as the output for an IDAC current source. Excitation currents reacting with series resistance adds
error to the measurement.
3. A 1-µF capacitor is required between REFOUT and REFCOM to enable the internal reference for the
IDAC current.
4. Use a precision reference resistor with high accuracy and low drift. Because the measurement is
ratiometric, accuracy is dependent on the error of this reference resistor. A 0.01% resistor contributes
a gain error similar to that as the ADC.
5. When possible, use C0G (NPO) ceramic capacitors for input filtering. The dielectric used in these
capacitors provides the most stable electrical properties over voltage, frequency, and temperature
changes.
6. Input filtering for the ADC inputs and the reference inputs are selected using standard capacitor values
and 1% resistor values. An example design and analysis of these filters is found in the RTD
Ratiometric Measurements and Filtering Using the ADS1148 and ADS1248 Family of Devices
application report.
7. This design shows connections to three input pins of the ADC multiplexer. Remaining analog inputs
may be used for RTD, thermocouple, or other measurements.
8. The design for the four-wire RTD measurement is identical to the two-wire RTD measurement but
requires four terminal connections and eliminates the lead-resistance error. For measurements with
different RTD wiring configurations, see A Basic Guide to RTD Measurements.

Component Selection
1. Identify the range of operation for the RTD.
As an example, a PT100 RTD has a range of approximately 20Ω to 400Ω if the temperature
measurement range is from −200°C to 850°C. The reference resistor must be larger than the maximum
RTD value. The reference resistance and PGA gain determines the positive full scale range of the
measurement.
2. Determine values for the IDAC excitation current and reference resistor.
In this design, the IDAC current source drives the RTD through lead 1. The current exits the RTD
through lead 4 and is shunted by RREF to create a ratiometric measurement. The measurement is made
between lead 2 and lead 3 by the ADC, making a Kelvin connection to remove the lead resistance
error. With this four-terminal sensing, the 4-wire RTD measurement is the most accurate of the RTD
wiring configurations.
The excitation current source in this design is selected to be 1mA. This maximizes the value of the
RTD voltage while keeping the self-heating of the RTD low. The typical range of RTD self-heating
coefficients is 2.5mW/°C for small, thin-film elements and 65mW/°C for larger, wire-wound elements.
With 1-mA excitation at the maximum RTD resistance value, the power dissipation in the RTD is less
than 0.4mW and keeps the measurement errors from self-heating to less than 0.01˚C.
After selecting the IDAC current magnitude, set RREF = 1620Ω. This sets the reference at 1.62V and
the maximum RTD voltage is 400mV. The reference voltage acts as a level shift to place the input
measurement to near mid-supply, putting the measurement in the PGA input operating range. With
these values, the PGA gain can be set to 4 so that the maximum RTD voltage is near the positive full
scale range without exceeding it.
The reference resistor, RREF must be a precision resistor with high accuracy and low drift. Any error in
RREF reflects the same error in the RTD measurement. The REFP0 and REFN0 pins are shown
connecting to the RREF resistor as a Kelvin connection to get the best measurement of the reference
voltage. This eliminates any series resistance as an error from the reference resistance measurement.

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Using the maximum RTD resistance, the ADC input voltages are calculated in the following:
VAIN1 = IIDAC1 • (RRTD + RREF) = 1mA • (400Ω + 1620Ω) = 2.02V
VAIN2 = IIDAC1 • RREF = 1mA • 1620Ω = 1.62V
VINMAX = 1mA • 400Ω = 400mV
3. Verify that the design is within the range of operation of the ADC.
First, verify that VAIN1 and VAIN2 are within the input range of the PGA given that the gain is 4 and that
AVDD is 3.3V and AVSS is 0V. As the ADS124S0x Low-Power, Low-Noise, Highly Integrated, 6- and
12-Channel, 4-kSPS, 24-Bit, Delta-Sigma ADC with PGA and Voltage Reference data sheet shows,
the absolute input voltage must satisfy the following:
AVSS + 0.15V + [|VINMAX| • (Gain − 1) / 2] < VAIN1, VAIN2 < AVDD − 0.15V − [|VINMAX| (Gain − 1) / 2]
0V + 0.15V + [|VINMAX| • (Gain − 1) / 2] < VAIN1, VAIN2 < 3.3V − 0.15V − [|VINMAX| (Gain − 1) / 2]
0.75 < VAIN1, VAIN2 < 2.55V
Because the maximum and minimum input voltages seen at AIN1 and AIN2 (2.02 V and 1.62 V) are
between 0.75V and 2.55V, the inputs are in the PGA operating range.
Second, verify that the voltage at the IDAC output pin is within the current source compliance voltage.
The IDAC pin is AIN0, which have the same voltage as AIN1. At the maximum voltage, VAIN0 is 2.02V.
As shown in the Electrical Characteristics table in the ADS124S0x Low-Power, Low-Noise, Highly
Integrated, 6- and 12-Channel, 4-kSPS, 24-Bit, Delta-Sigma ADC with PGA and Voltage Reference
data sheet, the output voltage of the IDAC must be between AVSS and AVDD − 0.6V for an IDAC
current of 1mA. In this example, with AVDD = 3.3V, the IDAC output must be:
AVSS < VAIN0 = VAIN1 < AVDD − 0.6V
0V < VAIN0 < 2.7V
With the above result, the output compliance of the IDAC is satisfied.
4. Select values for the differential and common-mode filtering for the ADC inputs and reference inputs.
This design includes differential and common-mode input RC filtering. The bandwidth of the differential
input filtering is set to be at least 10 × higher than the data rate of the ADC. The common-mode
capacitors are selected to be 1/10 of the value the differential capacitor. Because of capacitor
selection, the bandwidth of common-mode input filtering is approximately 20 × higher than the
differential input filtering. While series filter resistors offer some amount of input protection, keep the
input resistors lower than 10kΩ, to allow for proper input sampling for the ADC.
With input filtering, differential signals are attenuated at a lower frequency than the common-mode
signals, which are significantly rejected by the PGA of the device. Mismatches in common-mode
capacitors cause an asymmetric noise attenuation, appearing as a differential input noise. With a lower
bandwidth for differential signals, the effects from the mismatch of input common-mode capacitors be
reduced. Input filtering for the ADC inputs and reference inputs are designed for the same bandwidth.
In this design, the data rate is chosen to be 20SPS using the low-latency filter of the ADS124S08. This
filtering provides a low noise measurement with single-cycle settling and the ability to reject 50-Hz and
60-Hz line noise. For the ADC input filtering, the bandwidth frequency for the differential and common-
mode filtering is approximated in the following equations.
fIN_DIFF = 1 / [2 • π • CIN_DIFF (RRTD + 2 • RIN)]
fIN_CM = 1 / [2 • π • CIN_CM (RRTD + RIN + RREF)]
For the ADC input filtering, RIN = 4.99kΩ, CIN_DIFF = 47nF, and CIN_CM = 4.7nF. This sets the differential
filter bandwidth to 330Hz and the common-mode filter bandwidth to 5kHz.
Similarly, the bandwidth for the reference input filtering is approximated in the following equations.
fREF_DIFF = 1 / [2 • π • CREF_DIFF • (RREF + 2 • RIN_REF)]
fREF_CM = 1 / [2 • π • CREF_CM • (RREF + RIN_REF)]
For the reference input filtering, RIN_REF = 4.32kΩ, CREF_DIFF = 47nF, and CREF_CM = 4.7nF. This sets the
differential filter bandwidth to 330Hz and the common-mode filter bandwidth to 5.7kHz. Matching the
ADC input and reference input filtering may not be possible. However, keeping the bandwidths close
may reduce the noise in the measurement.
For an in-depth analysis of component selection for input filtering, see the RTD Ratiometric
Measurements and Filtering Using the ADS1148 and ADS1248 Family of Devices application report.

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Measurement Conversion
RTD measurements are typically ratiometric measurements. Using a ratiometric measurement, the ADC
output code does not need to be converted to a voltage. This means that the output code gives a
measurement only as a ratio of the value of the reference resistor and does not require a precise value for
the excitation current. The only requirement is that the current through the RTD and reference resistor are
the same.
Equations for the measurement conversion are shown for a 24-bit ADC:
Output Code = 223 • Gain • (VRTD / VREF) = 223 • Gain • (IIDAC1 • RRTD) / (IIDAC1 • RREF) = 223 • Gain • (RRTD / RREF)
RRTD = RREF • [Output Code / (Gain • 223)]
The ADC converts the measurement to the RTD equivalent resistance. Because of non-linearity in the
RTD response, the conversion of the resistance to temperature requires an calculation from equation or
lookup table. For more information about the conversion of RTD resistance to temperature, see A Basic
Guide to RTD Measurements.

Register Settings

Configuration Register Settings for a Four-Wire PT100 RTD Measurement Circuit with Low-Side
Reference Using the ADS124S08
Register Register Name Setting Description
Address
02h INPMUX 12h Select AINP = AIN1 and AINN = AIN2
03h PGA 0Ah PGA enabled, Gain = 4
04h DATARATE 14h Continuous conversion mode, low-latency filter, 20-SPS data rate
05h REF 02h Positive and negative reference buffers enabled, REFP0 and REFN0
reference inputs selected, internal reference always on
06h IDACMAG 07h IDAC magnitude set to 1mA
07h IDACMUX F0h IDAC1 set to AIN0, IDAC2 disabled
08h VBIAS 00h VBIAS not used for any input
09h SYS 10h Normal mode of operation

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Pseudo Code Example

The following shows a pseudo code sequence with the required steps to set up the device and the
microcontroller that interfaces to the ADC to take subsequent readings from the ADS124S0x in continuous
conversion mode. The dedicated DRDY pin indicates availability of new conversion data. Pseudo code is
shown without the use of the STATUS byte and CRC data verification. ADS124S08 firmware example
code is available from the ADS124S08 product folder.

Configure microcontroller for SPI mode 1 (CPOL = 0, CPHA = 1)

Configure microcontroller GPIO for /DRDY as a falling edge triggered interrupt input
Set CS low;
Send 06; // RESET command to make sure the device is properly reset after power-up
Set CS high;
Set CS low; // Configure the device
Send 42 // WREG starting at 02h address
05 // Write to 6 registers
12 // Select AINP = AIN1 and AINN = AIN2
0A // PGA enabled, Gain = 4
14 // Continuous conversion mode, low-latency filter, 20-SPS data rate
02 // Positive and negative reference buffers enabled,
// REFP0 and REFN0 reference selected, internal reference always on
07 // IDAC magnitude set to 1 mA
F0; // IDAC1 set to AIN0, IDAC2 disabled
Set CS high;
Set CS low; // For verification, read back configuration registers
Send 22 // RREG starting at 02h address
05 // Read from 6 registers
00 00 00 00 00 00; // Send 6 NOPs for the read
Set CS high;
Set CS low;
Send 08; // Send START command to start converting in continuous conversion mode;
Set CS high;
Loop
{
Wait for DRDY to transition low;
Set CS low;
Send 12 // Send RDATA command
00 00 00; // Send 3 NOPs (24 SCLKs) to clock out data
Set CS high;
}
Set CS low;
Send 0A; //STOP command stops conversions and puts the device in standby mode;
Set CS to high;

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RTD Circuit Comparison Table

RTD Circuit Topology Advantages Disadvantages

Two-wire RTD, low-side
Least expensive Least accurate, no lead-resistance cancellation
reference
Three-wire RTD, low-side Sensitive to IDAC current mismatch, mismatch can be
reference, two IDAC Allows for lead-resistance cancellation removed by swapping IDAC currents and averaging
current sources two measurements
Three-wire RTD, low-side
Requires two measurements, first for RTD
reference, one IDAC Allows for lead-resistance cancellation
measurement, second for lead-resistance cancellation
current source
Three-wire RTD, high-side
Allows for lead-resistance cancellation, less sensitive Requires extra resistor for biasing, added voltage may
reference, two IDAC
to IDAC mismatch than using low side reference not be compatible with low supply operation
current sources
Four-wire RTD, low-side
Most accurate, no lead-resistance error Most expensive
reference

Design Featured Devices

Other Possible
Device Key Features Link
Devices
24-Bit, 4kSPS, 12-Ch Delta-Sigma ADC With PGA and Voltage
ADS124S08 www.ti.com/product/ADS124S08 Link to similar devices
Reference for Precision Sensor Measurement
16-Bit, 4kSPS, 12-Ch Delta-Sigma ADC With PGA and Voltage
ADS114S08 (1) www.ti.com/product/ADS114S08 Link to similar devices
Reference for Precision Sensor Measurement

(1)
The ADS114S08 is a 16-bit version of the ADS124S08 and may be used in similar applications.

Design References
See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.
Additional Resources
• Texas Instruments, ADS124S08 Evaluation Module
• Texas Instruments, ADS1x4S08 Evaluation Module User's Guide
• Texas Instruments, ADS1x4S08 Firmware Example Code
• Texas Instruments, A Basic Guide to RTD Measurements Application Report
• Texas Instruments, RTD Ratiometric Measurements and Filtering Using the ADS1148 and ADS1248
Family of Devices Application Report
For direct support from TI Engineers use the E2E community
e2e.ti.com

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 Analog Engineer's Circuit: Data
Converters
SBAA354 – January 2019

Two-channel, K-type thermocouple measurement circuit

with internal temperature sensor CJC

Joseph Wu

Input Measurement ADC Input Voltage ADC Digital Output

T = –270°C AINP – AINN = –6.5mV FCC0H or –83210
T = 1370°C AINP – AINN = 55mV 1B80H or 704010

Power Supplies
VDD GND
3.3V 0V

Design Description
This cookbook design describes a temperature measurement circuit with two thermocouples using the
ADS1118. Thermocouple voltage measurements are made with the ADS1118 internal voltage reference,
while cold-junction compensation (CJC) measurements are made with the onboard temperature sensor.
Two channels of the ADC are used for two K-type thermocouples with a temperature measurement range
from –270°C to 1370°C. Included in this design are ADC register settings to configure the device and
pseudo code is provided to configure and read from the device. This circuit can be used in applications
such as analog input modules for PLCs, lab instrumentation, and factory automation. For more information
about using precision ADCs with thermocouples, see A Basic Guide to Thermocouple Measurements.

3.3V
0.1 F 0.01 F
GND
3.3V GND GND
CCMA = 0.1 F
RPU = 1Mȍ
500ȍ AIN0 VDD
RDIFFA
CDIFF = 1 F Voltage
ADS1118
RDIFFB AIN1 Reference
(PGA Gain = 16)
500ȍ ±256mV FS
RPD = 1Mȍ CCMB = 0.1 F
SCLK
GND GND 16-bit Digital Filter CS
MUX PGA Ȉǻ and
ADC Interface DOUT/DRDY
GND
3.3V DIN
CCMA = 0.1 F
RPU = 1Mȍ
500ȍ AIN2
RDIFFA
CDIFF = 1 F Oscillator Temp Sensor
RDIFFB AIN3
500ȍ GND
RPD = 1Mȍ CCMB = 0.1 F

GND GND
GND

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Design Notes
1. Use supply decoupling capacitors for the supply. VDD must be decoupled with at least a 0.1-μF
capacitor to GND. See ADS1118 Ultrasmall, Low-Power, SPI™-Compatible, 16-Bit Analog-to-Digital
Converter with Internal Reference and Temperature Sensor for details on power supply
recommendations.
2. When possible, use C0G (NPO) ceramic capacitors for input filtering. The dielectric used in these
capacitors provides the most stable electrical properties over voltage, frequency, and temperature
changes. Because of size, this may not always be practical and X7R capacitors are the next best
alternative.
3. Cold-junction compensation is required for accurate measurement of the thermocouple temperature.
4. The K-type thermocouple is chosen for its large input range and thermocouple voltage. Other
thermocouples have different sensitivities and error tolerances. For measurements with other
thermocouples and a guide to use them, see A Basic Guide to Thermocouple Measurements.
5. Conversion tables and polynomial equations used to determine thermocouple temperature from the
thermoelectric voltage is found at the NIST website at http://srdata.nist.gov/its90/menu/menu.html.
Additionally, some thermocouple conversions may be determined from the Analog Engineer's
Calculator.
Component Selection
1. Identify the range of operation for the thermocouple.
The K-type thermocouple has a range of approximately −6.5mV to +55mV if the temperature
measurement range is from −270°C to 1370°C. This range is used to maximize the resolution of the
measurement, considering the full-scale range of the ADC.
2. Determine gain and input range of the ADC.
In the ADS1118, the programmable gain amplifier (PGA) is implemented through scaled capacitive
sampling, not as a true amplifier. With this PGA, the input range extends to the full supply range, but
has less amplification and lower input impedance. In this device, the maximum amplification gives a full
scale range of ±0.256V. This is much larger than the range of −6.5mV to +55mV for the thermocouple.
While it is not possible to over-range the PGA, the measurement uses a limited portion of the full scale
range. Comparing the thermocouple range to the full-range, the percent of the usable ADC range can
be calculated:
% of usable ADC range = [55mV–(–6.5mV)]/[0.256mV–(–0.256mV)] • 100% = 12.0%
Number of ADC codes in measurement range = 0.12 • 216 = 7864
With a range of −270°C to 1370°C for the thermocouple, 7864 codes are used to represent a
temperature range of 1640°C. This equates to approximately 0.21°C per ADC code which should be
enough for most thermocouple applications.
In other precision ADCs, the PGA is implemented similar to an instrumentation amplifier. If using a
different ADC, calculate the maximum gain allowed without over-ranging the PGA based on the
maximum thermocouple output voltage. Then ensure that the thermocouple biasing is near mid-supply
so that the input signal is in the common-mode input range of the PGA.
3. Set up the resistor biasing to establish the input DC level and burnout detection.
Equal biasing resistors are tied from either end of the thermocouple and to GND and VDD. In normal
operation, the resistors set the DC biasing point of the thermocouple to near mid-supply. If the
thermocouple burns out and becomes an open circuit, the resistors pull apart the thermocouple leads
to either supply. These resistors are set high (often 500kΩ to 10MΩ) to reduce the bias current going
through the thermocouple. Resistor bias current reacting with the thermocouple lead resistance cause
measurement error. However, the resistors must also be low enough to provide sufficient bias current
to overcome any input current from the resistor.
In this design, biasing resistors are chosen to be 1MΩ. This value sets the resistor biasing current to a
low 1.65µA. However, in the case of a burned out thermocouple, 1MΩ provides enough current to
separate the ADC inputs against the 710kΩ equivalent input impedance of the ADS1118.

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VDD VDD

VDD VDD
1M 1M

Good Burned out

thermocouple thermocouple
+ +
-6.5mV to
710k 0.86V 710k
55mV
- -

ADS1118 ADS1118

1M 1M

In the case of the good thermocouple, the thermocouple voltage has a range of –6.5mV to 55mV. The
remaining 3.3V of the VDD supply is dropped equally between the biasing resistors. With 1-MΩ bias
resistors, the thermocouple voltage has a DC operating point near mid-supply at 1.65V.
In the case of a burned out thermocouple, the open circuit creates a voltage divider with the two 1MΩ
around the 710-kΩ equivalent input impedance. The ADC input voltage with a burned out
thermocouple may be calculated as:
ADC input voltage = 3.3V • [710kΩ / (1MΩ + 710kΩ + 1MΩ)] = 0.85V
If the thermocouple burns out, the ADC input voltage is 0.86V, which is much larger that the positive
full-scale reading of the ADC. The ADC reports a reading of 7FFFh to indicate a burnout condition.
4. Select values for the differential and common-mode filtering for the ADC inputs and reference inputs.
If there is input filtering, the input current reacts with any series filter resistance to create an error. For
the ADS1118, the input current is modeled as an equivalent differential input impedance. As previously
mentioned, the equivalent differential input impedance is typically 710kΩ. For this reason, the input
series resistance is kept low or the added voltage appears as a gain error.
This design includes differential and common-mode input RC filtering. The bandwidth of the differential
input filtering is set to be at least 10 × higher than the data rate of the ADC. The common-mode
capacitors are selected to be 1/10 of the value the differential capacitor. Because of capacitor
selection, the bandwidth of common-mode input filtering is approximately 20 × higher than the
differential input filtering.
With input filtering, differential signals are attenuated at a lower frequency than the common-mode
signals, which are significantly rejected by the PGA of the device. Mismatches in common-mode
capacitors cause an asymmetric noise attenuation, appearing as a differential input noise. With a lower
bandwidth for differential signals, the effects from the mismatch of input common-mode capacitors are
reduced. Input filtering for the ADC inputs and reference inputs are designed for the same bandwidth.
In this design, the data rate is chosen to be 8SPS. For the ADC input filtering, the bandwidth frequency
for the differential and common-mode filtering is approximated in the following equations:
fIN_DIFF = 1 / [2 • π • CDIFF • (2 • RDIFF)]
fIN_CM = 1 / (2 • π • CCM • RDIFF)
For the ADC input filtering, RIN = 500Ω, CIN_DIFF = 1µF, and CIN_CM = 0.1µF. This sets the differential filter
bandwidth to 160Hz and the common-mode filter bandwidth to 3.2kHz.
5. Use cold-junction compensation to calculate the actual thermocouple voltage based on the cold-
junction temperature.
To get a precise measurement from a thermocouple, cold-junction compensation must be performed to
get an accurate temperature measurement. An accurate measurement of the cold-junction where the
thermocouple leads are tied is required. You cannot simply add the temperature of the cold-junction to
the temperature computed from the thermocouple voltage. To accurately determine the thermocouple
temperature, the proper method is to:
1. Convert the cold-junction temperature (TCJ) to a voltage (VCJ)
2. Add the cold-junction voltage to the measured thermocouple voltage (VCJ + VTC)
3. Convert the summed cold-junction voltage and thermocouple voltage to the thermocouple
temperature (TTC)

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The following flow diagram shows the conversion method to determine the actual temperature of the
thermocouple based on the ADC measurements.

ADS1118 MCU

Thermocouple VTC
Voltage

TActual

On-chip TCJC VCJC VActual

T V Ȉ V T Result
Temperature

Conversion tables and polynomial equations used to determine thermocouple temperature from the
thermoelectric voltage are found at the NIST website at http://srdata.nist.gov/its90/menu/menu.html.
Because the ADS1118 has an accurate internal temperature sensor, a measurement can be used. The
internal temperature sensor has a typical accuracy of 0.2°C for a range of 0°C to 70°C. This accuracy
is ideal for the cold-junction measurement. However, the device requires a good thermal contact to the
connection for the thermocouple cold-junction. Any error in the cold-junction measurement yields an
error in the resulting temperature measurement.
For more information about thermocouples and the cold-junction compensation measurement, see A
Basic Guide to Thermocouple Measurements.
Measurement Conversion
Conversions for the thermocouple voltage are relatively straight forward based on the full-scale range
setting of the ADC. In this design, the smallest full-scale range is used (±0.256V).
Measurement 1 (Thermocouple 1):
Output Code 1 = [215 • (VAIN0 – VAIN1) / (0.256V)]
Thermocouple 1 Voltage = VAIN0 – VAIN1 = [(Output Code 1) • 0.256V / 215]
Measurement 2 (Thermocouple 2):
Output Code 2 = [215 • (VAIN2 – VAIN3) / (0.256V)]
Thermocouple 2 Voltage = VAIN2 – VAIN3 = [(Output Code 2) • 0.256V / 215]
Conversions for the internal temperature sensor require some data manipulation. Temperature data from
the ADC are represented as a 14-bit result that is left-justified within the 16-bit conversion result. Data are
output starting with the most significant byte (MSB). When reading the two data bytes, the first 14 bits are
used to indicate the temperature measurement result. One 14-bit LSB equals 0.03125°C and negative
numbers are represented in binary twos complement format.
Measurement 3 (Internal Temperature Sensor):
Output Code 3 = [(Temperature) / (0.03125°C)]
Temperature = [(Output Code 3) • (0.03125°C)]
Output Code 3 is the first 14 bits of the two byte output data from the ADC. For more information about
the ADS1118 and the internal temperature sensor see ADS1118 Ultrasmall, Low-Power, SPI™-
Compatible, 16-Bit Analog-to-Digital Converter with Internal Reference and Temperature Sensor.

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Register Settings

Measurement 1 (Thermocouple 1 Voltage): Config Register (8D0Bh)

Bit Field Setting Description
15 SS 1 Start a single conversion
14:12 MUX[2:0] 000 AINP is AIN0 and AINN is AIN1 for thermocouple 1
11:9 PGA[2:0] 110 FSR is ±0.256V
8 MODE 1 Power-down and single-shot mode
7:5 DR[2:0] 000 8SPS
4 TS_MODE 0 ADC mode
3 PULL_UP_EN 1 Pullup resistor enabled on DOUT/DRDY pin
2:1 NOP[1:0] 01 Valid data, update the Config register
0 Reserved 1 Always write 1h

Measurement 2 (Thermocouple 2 Voltage): Config Register (BD0Bh)

Bit Field Setting Description
15 SS 1 Start a single conversion
14:12 MUX[2:0] 011 AINP is AIN2 and AINN is AIN3 for thermocouple 2
11:9 PGA[2:0] 110 FSR is ±0.256V
8 MODE 1 Power-down and single-shot mode
7:5 DR[2:0] 000 8SPS
4 TS_MODE 0 ADC mode
3 PULL_UP_EN 1 Pullup resistor enabled on DOUT/DRDY pin
2:1 NOP[1:0] 01 Valid data, update the Config register
0 Reserved 1 Always write 1h

Measurement 3 (Internal Temperature Sensor): Config Register (8D1Bh)

Bit Field Setting Description
15 SS 1 Start a single conversion
14:12 MUX[2:0] 011 AINP is AIN2 and AINN is AIN3 (ignored by TS_MODE)
11:9 PGA[2:0] 110 FSR is ±0.256V (ignored by TS_MODE)
8 MODE 1 Power-down and single-shot mode
7:5 DR[2:0] 000 8SPS
4 TS_MODE 1 Temperature sensor mode (bypasses MUX[2:0])
3 PULL_UP_EN 1 Pullup resistor enabled on DOUT/DRDY pin
2:1 NOP[1:0] 01 Valid data, update the Config register
0 Reserved 1 Always write 1h

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Pseudo Code Example

The following shows a pseudo code sequence with the required steps to set up the device and the
microcontroller that interfaces to the ADC in order to take subsequent readings from the ADS1118 in
single-shot conversion mode.
Data read back and device configuration are done with 32-bit transmission cycle with Config register read
back. The ADS1118 is configured to measure the thermocouple voltages with a full-scale range of
±256mV and a data rate of 8SPS. The device cycles from reading the voltage of thermocouple 1, the
voltage of thermocouple 2, and then the ADS1118 internal temperature sensor. After taking all three
readings, cold-junction compensation is used to convert the thermocouple voltages to the thermocouple
temperatures.

Configure microcontroller for SPI mode 1 (CPOL = 0, CPHA = 1)

Set CS low; // Start conversions
Send 8D0B8D0B; //Start conversion for thermocouple 1
// Use 32-bit data transmission cycle with Config register readback
// The first iteration of the loop has no data readback
Set CS high;
Loop
{
Wait 69ms // Wait for typical data period +10% for internal oscillator variation
Set CS low;
Send BD0BBD0B; // Read data for thermocouple 1, start conversion for thermocouple 2,
Set CS high;
Wait 69ms;
Set CS low;
Send 8D1B8D1B; // Read data for thermocouple 2, start conversion for temperature sensor,
Set CS high;
Wait 69ms;
Set CS low;
Send 8D0B8D0B // Read data temperature sensor, Start conversion for thermocouple 1
Set CS high;
// Cold-junction compensation to determine thermocouple temperature
Convert thermocouple 1 ADC data to voltage;
Convert thermocouple 2 ADC data to voltage;
Convert temperature sensor data to temperature;
Convert temperature sensor data to thermoelectric voltage; // By lookup table or calculation
Add thermocouple 1 voltage to temperature thermoelectric voltage;
Convert resulting voltage for thermocouple 1 to temperature; // By lookup table or calculation
Add thermocouple 2 voltage to temperature thermoelectric voltage;
Convert resulting voltage for thermocouple 2 to temperature; // By lookup table or calculation
}

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Design Featured Devices

Device Key Features Link Other Possible Devices

Ultrasmall, low-power, SPI™-compatible, 16-bit
(1)
ADS1118 analog-to-digital converter with internal reference and http://www.ti.com/product/ADS1118 Link to similar devices
temperature sensor

(1)
For cold-junction compensation, ensure that the device has a internal temperature sensor with specified limits. Alternately, an external
temperature sensor may be used with an ADC channel for the cold-junction measurement.

Design References
See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.
Additional Resources
• Texas Instruments, ADS1118 Evaluation Module
• Texas Instruments, ADS1118EVM User Guide and Software Tutorial
• Texas Instruments, A Basic Guide to Thermocouple Measurements
• Texas Instruments, Analog Engineer's Calculator
• Texas Instruments, Precision Thermocouple Measurement with the ADS1118
• Texas Instruments, Simple Thermocouple Measurement Solution Reference Design, <1°C Accurate
For direct support from TI Engineers use the E2E community:
e2e.ti.com

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 Analog Engineer's Circuit: Data
Converters
SBAA317 – December 2018

±12-V voltage sensing circuit with an isolated amplifier

and pseudo-differential input SAR ADC

Alex Smith

ISO224 Input Voltage ISO224 Output ADS7142 Input ADS7142

(VOUTP - VOUTN) (Pseudo-Differential) Digital Output
+12V +4V 3.3V FFFH
–12V –4V 0V 000H

Power Supplies and Reference Voltages

VDD1 VDD2 and Vcc AVDD GND
4.5 V - 18 V 5V 3.3 V 0V

Design Description
This circuit performs a ±12-V isolated voltage sensing measurement utilizing the ISO224 isolated
amplifier, TLV9002 operational amplifier, and the ADS7142 SAR ADC. The ISO224 can measure single-
ended signals of ±12V with a fixed gain of ⅓V/V and produces a ±4-V isolated differential output voltage
with an output common-mode voltage of VDD2 / 2. Channel 1 of the TLV9002 conditions the output of the
ISO224 to fit the input range of the ADS7142, while Channel 2 monitors the ISO224 fail-safe output. The
ADS7142 is a dual-channel ADC with a full-scale input and reference voltage of AVDD which can range
from 1.65V to 3.6V. For this cookbook circuit, the ADS7142 dual-channel input will be used in a pseudo-
differential configuration which allows for both positive and negative signals to be measured by the
ISO224. This circuit is applicable to many high Voltage industrial applications such as Train Control &
Management Systems, Analog Input Modules, and Inverter & Motor Control. The equations and
explanation of component selection in this design can be customized based on system specifications and
needs.

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Specifications

Specification Calculated Simulated

Transient ADC input settling at 140kSPS 403µV 88µV
Conditioned signal range 0V–3.3V 0V–3.3V
Noise (at the input) 262µVRMS 526µVRMS
Closed-loop bandwidth 175kHz 145kHz

Design Notes
1. The ISO224 was selected due to its wide input range, flexible power configuration, and high accuracy.
2. The ADS7142 was selected due to its very low power, high level of integration, flexible power
configurations, and small size.
3. The TLV9002 operational amplifier was selected for its cost optimization, configuration options, and
small size.
4. Select low impedance, low noise sources for AVDD, VCM, and the pseudo-differential input to AINN
which sets the common-mode voltage of the ADC.
5. Find the ADC full-scale range and common-mode specifications. This is covered in component
selection.
6. Select a COG capacitor for CFILT to minimize distortion.
7. For best performance, consider using a 0.1% 20ppm/°C film resistor for RFILT1,2 or better, to minimize
distortion.
8. Understanding and Calibrating the Offset and Gain for ADC Systems covers methods for error
analysis. Review the link for methods to minimize gain, offset, drift, and noise errors.
9. The TI Precision Labs - ADCs training video series covers methods for selecting the charge bucket
circuit RFILT and CFILT. These component values are dependent on the amplifier bandwidth, data
converter sampling rate, and data converter design. The values shown here will give good settling and
AC performance for the amplifier and data converter in this example. If the design is modified, a
different RC filter must be selected. Refer to Introduction to SAR ADC Front-End Component Selection
for an explanation of how to select the RC filter for best settling and AC performance.

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Component Selection
1. Select an isolated amplifier based on the input voltage range and determine the output common-mode
voltage and output voltage range:
The ISO224 power supplies can be 4.5V to 18V for the high-side power supply, and 4.5V to 5.5V for
the low-side power supply. The ISO224 has a ±12-V single-ended input range with a fixed gain of
⅓V/V, yielding ±4-V differential output at a common-mode voltage of VDD2 / 2, +2.5V for this example:
± 12V IN,Single -Ended æV ö
= ± 4VOUT,Differential @ 2.5V ç DD2 ÷ com m on - m od e
3 è 2 ø
2. Select an ADC with small size and low power:
The ADS7142 is a small sized, low power, dual channel ADC that can be used in a pseudo-differential
configuration. The max input range is set by the reference voltage and is equal to AVDD, 3.3V for this
example:
ADC Full - Scale Range = VREF = AVDD = 3.3 V

Find the required ADC common-mode voltage for pseudo-differential measurements:

VREF
VCM = = 1.65V
2
3. Select an operational amplifier that can convert the ±4-V differential, +2.5-V common-mode output of
the ISO224 to the 3.3-V pseudo-differential, 1.65-V common-mode input of the ADS7142. Additionally,
selecting an operational amplifier with a second channel that can monitor the fail-safe output feature of
the ISO224 is preferred:
The TLV9002 is a 2 channel, rail-to-rail input and output amplifier optimized for cost sensitive and
small size applications.
Channel 1 is used to convert the ±4-V differential, +2.5-V common-mode output of the ISO224 to a
3.3-V peak pseudo-differential output with a common-mode voltage of 1.65 V. When R1 = R4 and R2 =
R3, the transfer function is set by the following equation:
æ R4 ö æ R1 ö
VOUT = VOUTP ç ÷ + VOUTN ç ÷ + VCM
è R3 ø è R2 ø
The signal must be converted from ±4V to 3.3V, this means that the signal must be reduced by a factor
of 3.3V/±4V = 3.3V/8V. Substituting VCM with the previously calculated value of 1.65V and setting R2
and R3 to an easy to work with 10 kΩ yields the following equations:
æ R4 ö æ R1 ö
3.3V = 4V ç ÷ + 1.65V 0V = - 4V ç ÷ + 1.65V
è 10k W ø è 10k W ø
Solving for R1 and R4 yields values of 4.125 kΩ.
Additional information on this topic can be seen in the Interfacing a Differential-Output (Isolated)
Amplifier to a Single-Ended Input ADC tech note.
Channel 2 of the TLV9002 is used to monitor the fail-safe output feature of the ISO224. The ISO224
fail-safe output feature becomes active whenever the high-side power supply, VDD1, is missing
independent of the input signal on the VIN pin. The TLV9002 channel 2 output, VCOMP, is fed to a
GPIO port on the system controller and goes high whenever the Fail-Safe output feature is active. For
additional details please see the Fail-Safe Output Feature application note.
4. Select R1FILT, R2FILT, and CFILT for settling of the input signal and sample rate of 140kSPS:
Refine the RFILT and CFILT Values is a TI Precision Labs video showing the methodology for selecting
RFILT and CFILT. The final value of 1.1 kΩ and 330pF proved to settle to well below ½ of a least
significant bit (LSB) within the acquisition window.

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Submit Documentation Feedback 183 and pseudo-differential input SAR ADC
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DC Transfer Characteristics
The following graphs show the simulated inputs of the TLV9002 and the ADS7142 from a ±15-V input
signal to the ISO224. The ISO224 has a linear output of ±VIN/3 and the input to the TLV9002 can be seen
in the first graph. The second graph shows that the TLV9002 further reduces the gain by VIN / 2.43 and
shifts the common mode to 1.65V. This results in the full-range ±12-V input signal utilizing the 0V–3.3V
full-scale range (FSR) of the ADC with AVDD = VREF = 3.3V.
The following transfer function shows that the gain of the ISO224 and TLV9002 is 1/7.28 V/V.
Gain ISO224 × Gain TLV 9002 × VIN = VOUT
1 1 1
× × 12V = × 12V = 1.65V
3 2.43 7.28

±12-V voltage sensing circuit with an isolated amplifier SBAA317 – December 2018
and pseudo-differential input SAR ADC 184 Submit Documentation Feedback
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AC Transfer Characteristics
The simulated bandwidth of the signal chain is approximately 145kHz and the gain is –17.25dB which is a
linear gain of approximately 0.137V/V (attenuation ratio 1/7.28V/V). This matches the expected gain of the
system.

Transient ADC Input Settling Simulation

The following simulation shows the transient settling results with an acquisition time of 5.3μs. The 88μV of
noise is well within the 0.5 · LSB limit of 403μV. See Refine the Rfilt and Cfilt Values for detailed theory on
this subject.

SBAA317 – December 2018 ±12-V voltage sensing circuit with an isolated amplifier
Submit Documentation Feedback 185 and pseudo-differential input SAR ADC
Copyright © 2018, Texas Instruments Incorporated
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Noise Simulation
The simulated noise seen at the input of the ADC is greater than the expected calculated noise. This
difference is due to noise peaking in the simulation model which is not included in the calculation. The
following equations show that the ISO224 noise dominates the signal chain, and that the noise from the
TLV9002 is negligible. Refer to Calculating the Total Noise for ADC Systems for detailed theory on this
subject.
En = Gain(en ) (1.57 × BW )
1 1
EnISO224A = ×
3 2.43
( )
4mV / Hz × 1.57 × 145kHz = 262mVRMS

1
EnTLV9002 =
2.43
( )
27nV / Hz × 1.57 × 145kHz = 5mVRMS

EnISO224A + TLV9002 = EnISO224A + EnTLV9002 = 2622 mVRMS + 52 mVRMS = 262mVRMS

±12-V voltage sensing circuit with an isolated amplifier SBAA317 – December 2018
and pseudo-differential input SAR ADC 186 Submit Documentation Feedback
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Design Featured Devices

Device Key Features Link Similar Devices

ISO224 ±12-V single-ended input range, Fixed gain of ⅓, yielding ±4-V differential output, www.ti.com/product/ISO224 www.ti.com/isoamps
output common-mode voltage of +2.5V, 4.5V to 18-V high-side power supply, 4.5-
V to 5.5-V low side power supply, input offset: ±5mV at 25°C, ±42µV/°C max, gain
error: ±0.3% at 25°C, ±50ppm/°C maximum, nonlinearity: ±0.01% maximum,
±1ppm/°C, high-input impedance of 1.25MΩ
ADS7142 Dual-Channel, full-scale input span and reference set by AVDD, 12-bit www.ti.com/product/ADS7142 http://www.ti.com/Precision
performance by default, 16-bit performance with High Precision Mode, very low ADCs
current consumption of 0.45 µA at 600SPS
TLV9002 Dual-Channel, rail-to-rail input and output amplifier, low broadband noise of www.ti.com/product/TLV9002 http://www.ti.com/opamps
2727nV/√Hz, Low Input Offset Voltage of ±0.04-mV

Design References
See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.
Link to Key Files
TINA files for Isolated Design - http://www.ti.com/lit/zip/sbac226.

SBAA317 – December 2018 ±12-V voltage sensing circuit with an isolated amplifier
Submit Documentation Feedback 187 and pseudo-differential input SAR ADC
Copyright © 2018, Texas Instruments Incorporated
 Analog Engineer's Circuit: Data
Converters
SBAA312 – September 2018

±12-V voltage sensing circuit with an isolated amplifier

and differential input SAR ADC

Alex Smith

ISO224 Input Voltage ISO Output, ADC Input (VOUTP - VOUTN) Digital Output ADS7945
+12V +4V 1999H
–12V –4V E666H

Power Supplies and Reference Voltages

VDD1 VDD2 and AVDD REF5050 External Ref
15V 5V 5V

Design Description
This circuit performs a ±12-V isolated voltage sensing measurement utilizing the ISO224 isolated amplifier
and the ADS745 SAR ADC. The ISO224 can measure true differential signals of ±12V with a fixed gain of
⅓V/V and produces an isolated differential output voltage with an output common-mode voltage of VDD2 /
2. The ADS7945 is a fully differential input ADC with a full-scale input voltage of ±VREF and a common-
mode input voltage of VREF / 2 ±200mV. Selecting a +5-V reference allows the ADS7945 to accept the full-
scale and common-mode outputs from the ISO224. Capturing the ISO224 output with a fully differential
input ADC doubles the system dynamic range compared to a single-ended conversion. Many high-voltage
industrial applications such as Protection Relays, Channel-to-Channel Isolated ±10V Analog Input Cards,
and Inverter & Motor Control. The equations and explanation of component selection in this design can be
customized based on system specifications and needs.
15V 5V 5.2V to 18V 5V
VDD2
REF5050 5V
Isolation
Barrier ISO224 R1FILT
120Ÿ REF AVDD
VOU TP
AINP
±12VIN CFILT
120Ÿ 510pF
ADS7945
AINN
VOU TN R2FILT GND

GND2
GND1 GND2

SBAA312 – September 2018 ±12-V voltage sensing circuit with an isolated

Submit Documentation Feedback 188 amplifier and differential input SAR ADC
Copyright © 2018, Texas Instruments Incorporated
 www.ti.com

Specifications

Specification Calculated Simulated

Transient ADC input settling at 100ksps 305µV 11µV
Conditioned signal range ±4V ±4V
Noise (at the input) 1.9mVRMS 1.73mVRMS
Closed-loop bandwidth 175kHz 185kHz

Design Notes
1. The ADS7945 was selected due to its low power and a compatible analog input structure with the
ISO224.
2. Verify the systems linear operation for the desired input signal range. This is verified using simulation
in the DC Transfer Characteristics selection.
3. Select COG capacitors for CFILT to minimize distortion.
4. Understanding and Calibrating the Offset and Gain for ADC Systems covers methods for error
analysis. Review the link for methods to minimize gain, offset, drift, and noise errors.
5. The TI Precision Labs - ADCs training video series covers methods for selecting the charge bucket
circuit RFILT and CFILT. These component values are dependent on the amplifier bandwidth, data
converter sampling rate, and data converter design. The values shown here will give good settling and
AC performance for the amplifier and data converter in this example. If the design is modified, a
different RC filter must be selected. Refer to Introduction to SAR ADC Front-End Component Selection
for an explanation of how to select the RC filter for best settling and AC performance.

±12-V voltage sensing circuit with an isolated SBAA312 – September 2018

amplifier and differential input SAR ADC 189 Submit Documentation Feedback
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Component Selection
1. Select an isolated amplifier based on the input voltage range and determine the output common-mode
voltage and output voltage range:
ISO224:
– ±12-V single-ended input range
– Fixed gain of ⅓, yielding ±4-V differential output
– Output common-mode voltage of +2.5V
– 4.5-V to 18-V high-side power supply, 4.5-V to 5.5-V low-side power supply
– Input Offset: ±5mV at 25°C, ±42µV/°C maximum
– Gain Error: ±0.3% at 25°C, ±50ppm/°C maximum
– Nonlinearity: ±0.01% max, ±1ppm/°C
– High-input impedance of 1.25MΩ
2. Select an ADC with an appropriate common-mode and differential input range to pair with the +2.5-V
common-mode and ±4-V differential output of the ISO224:
ADS7945:
– ±5-V maximum analog input range
– Full-scale input span set by ±voltage reference
– Input common-mode range of VREF / 2 ±0.2V
– 2.7-V to 5.25-V power supply
– High SNR of 84, low power of 11.6mW at 2Msps
3. Select a voltage reference that supports the common-mode constraint set by the 2.5-V common-mode
output of the ISO224 and the VREF / 2 ±0.2-V common-mode input voltage of the ADS7945. This
means that the reference output voltage must be 5V, low noise, and a configurable input voltage is
preferred:
REF5050:
– 5-V output
– 5.2-V to 18-V input voltage power supply
– 3μVPP/V noise
4. Select R1FILT, R2FILT, and CFILT for settling of the input signal and sample rate of 100ksps:
Refine the RFILT and CFILT Values is a TI Precision Labs video showing the methodology for
selecting RFILT and CFILT. The final value of 120Ω and 510pF proved to settle to well below ½ of a
least significant bit (LSB) within the acquisition window.

SBAA312 – September 2018 ±12-V voltage sensing circuit with an isolated

Submit Documentation Feedback 190 amplifier and differential input SAR ADC
Copyright © 2018, Texas Instruments Incorporated
 www.ti.com

DC Transfer Characteristics
The following graph shows the simulated output for a ±15-V input. The desired linear range is a ±4-V
output for a ±12-V input. This simulation shows that the linear output range is approximately ±4.6V which
is well beyond the requirement.
The transfer function shows the ISO224 gain is ⅓ (that is, Gain · VIN = VOUT, (⅓)·(12V) = 4V).
4.60
(12, 4.00)
(13.8, 4.6)
2.30
Voltage (V)

0.00

-2.30
(-13.8, -4.6)
(-12, -4.00)
-4.60
-15.0 -10.0 -5.0 0.0 5.0 10.0 15.0
Input voltage (V)
AC Transfer Characteristics
The simulated bandwidth is approximately 186kHz and the gain is –9.57dB (or 0.332V/V) which closely
matches the expected gain and bandwidth for the ISO224 (specified fc = 175kHz, gain = 0.333V/V).
0

-20
Gain
-40 9.57dB Bandwidth
Gain (dB)

fc = 185.8kHz
-60

-80

-100

-120
10 100 1k 10k 100k 1MEG 10MEG
Frequency (Hz)

±12-V voltage sensing circuit with an isolated SBAA312 – September 2018

amplifier and differential input SAR ADC 191 Submit Documentation Feedback
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Transient ADC Input Settling Simulation

The following simulation shows the transient settling results with an acquisition time of 9.6μs. The 11-μV
settling error is well within the 0.5 * LSB limit of 305μV. See Refine the Rfilt and Cfilt Values for detailed
theory on this subject.
1.00

Vacq

0.00
1m End of tACQ
Error = 11µV
500u
Verror 0

-500u
-1m
10u 12u 15u 17u 20u
Time (s)

SBAA312 – September 2018 ±12-V voltage sensing circuit with an isolated

Submit Documentation Feedback 192 amplifier and differential input SAR ADC
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Noise Simulation
The following noise calculation looks only at the noise of the ISO224. The ISO224 noise is substantially
higher than other noise sources in the circuit, so the total noise can be approximated as the ISO224 noise.
The same method can be used for the B grade.

EnISO 224 A Gain en 1.57 * BW

1
EnISO 224 A 4 µV / Hz 1.57 * 176kHz 0.7mVRMS
3
The simulated noise is greater than the expected calculated noise. This difference is due to noise peaking
in the simulation model. The noise peaking is not included in the calculation. Refer to Calculating the Total
Noise for ADC Systems for detailed theory on this subject.
2.0m

Total Noise =
ADCIN
1.73mVRMS
1.0m

0.0
1 10 100 1k 10k 100k 1MEG 10MEG
Frequency (Hz)

±12-V voltage sensing circuit with an isolated SBAA312 – September 2018

amplifier and differential input SAR ADC 193 Submit Documentation Feedback
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Design Featured Devices

Device Key Features Link Similar Devices

ISO224 ±12-V single-ended input range, Fixed gain of ⅓, yielding ±4-V differential output, www.ti.com/product/ISO224 www.ti.com/isoamps
output common-mode voltage of +2.5V, 4.5-V to 18-V high-side power supply,
4.5-V to 5.5-V low side power supply, input offset: ±5mV at 25°C, ±42µV/°C max,
gain error: ±0.3% at 25°C, ±50ppm/°C maximum, nonlinearity: ±0.01% maximum,
±1ppm/°C, high-input impedance of 1.25MΩ
ADS7945 ±5 V max analog input range, full-scale input span set by ±voltage reference, www.ti.com/product/ADS7945 http://www.ti.com/opamps
input common mode range of VREF / 2 ±0.2V, 2.7-V to 5.25-V power supply, high
SNR of 84, low power of 11.6mW at 2Msps
REF5050 3ppm/°C drift, 0.05% initial accuracy, 4μVpp/V noise www.ti.com/product/REF5050 http://www.ti.com/vref

Design References
See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.
Link to Key Files
See the TINA files for Isolated Design - http://www.ti.com/lit/zip/sbac213.

SBAA312 – September 2018 ±12-V voltage sensing circuit with an isolated

Submit Documentation Feedback 194 amplifier and differential input SAR ADC
Copyright © 2018, Texas Instruments Incorporated
 Analog Engineer's Circuit: Data
Converters
SBAA282A – March 2018 – Revised March 2019

Antialiasing filter circuit design for single-ended ADC

input using fixed cutoff frequency

Manuel Chavez

Input ADC Input Digital Output ADS8319

Vin Min = 0.1V Vadc_in = 4.9V FAE1H or 6422510
VinMax = VREF = 4.9V Vadc_in = 0.1V 051FH or 131110

Power Supplies
Vcc Vee Vcm VREF AVDD DVDD
5.3V GND (0V) 2.5V 5V 5V 5V

Design Description
This cookbook is intended to demonstrate a method of designing an antialiasing filter for a single-ended
SAR ADC input using the Antialias Filter Designer on TI’s Analog Engineer’s Calculator. The objective of
the tool is to find filter specifications that will attenuate alias signals to one-half LSB of a given ADC. This
design approach uses a fixed cutoff frequency and the example circuit uses the ADS8319 ADC. This
single-ended device circuit is practical for low-power applications such as Data Acquisition, Lab
Instrumentation, Oscilloscopes, Analog Input Module, and battery-powered equipment.

R3 1.37k

C3 1n

GND
GND
-
R1 1.37k R2 909 R5 21.8
- INP
R4 2.37k
+ +
+
U2 OPA365
+
C5 1.1n

+
Vadc_in ADS8319
C1 3.9n

2.5V +
5VAC Vin U1 OPA365
5.3V R6 21.8
-
C2 1n

- 5.3V INM

SBAA282A – March 2018 – Revised March 2019 Antialiasing filter circuit design for single-ended
Submit Documentation Feedback 195 ADC input using fixed cutoff frequency
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Specifications

Specification Calculated / Goal Simulated

Attenuate 1mV alias signal at Nyquist to ½ Vout_Nyquist <= ½ LSB Vout_Nyquist = 21µV
LSB ½ LSB = 38.14µV at 250kHz Attenuation = –33.43dB
Vin_Nyquist = 1mV at 250kHz
Transient ADC Input Settling < 0.5 LSB or 38.15µV 91.5nV
Noise 78.9µV 87.77µV
Bandwidth 50kHz 50.1kHz

Design Notes

1. TI Precision Labs introduces the concept of frequency domain aliasing and describes how aliases are
error sources to avoid or minimize. The video on Aliasing and Anti-aliasing Filters covers how an
antialiasing filter can be used to minimize these aliasing errors.
2. The active filter in this cookbook is designed using TI’s Analog Engineer’s Calculator and TI FilterPro
(click to download). This software can be used to design active filter circuits for many applications.
3. Use 0.1%–1% tolerance resistors and 5% tolerance capacitors or better for good system accuracy.
4. RC charge bucket circuits are specially designed for each system; TI’s Precision Labs video on
Refining Rfilt and Cfilt Values explains how to optimize the RC charge bucket.
5. Circuit simulations are modeled with schematics and diagrams made using TINA-TI simulation
software (click to download).
6. For detail on choosing the right driver op amp, building and simulating the ADC model, and finding the
RC charge bucket values, see the TI Precision Labs video series Introduction to SAR ADC Front-End
Component Selection.

Antialiasing filter circuit design for single-ended SBAA282A – March 2018 – Revised March 2019
ADC input using fixed cutoff frequency 196 Submit Documentation Feedback
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Component Selection

1. Once a single-ended ADC has been chosen, determine whether the antialias filter will be designed
with a set cutoff frequency or set filter order. If the frequency is set, continue through the following
steps. If the filter order is set, use the "Find Usable Frequency Range" tab in the Analog Engineer's
Calculator. Both methods use tools from the Analog Engineer’s Calculator.
2. Using the Find Filter Order tab of the Anti-Alias Filter Designer, choose between a Bessel and
Butterworth filter under Choose Filter Type. Bessel is chosen in this case for maximum flatness in the
pass band and linear phase response.
3. Fill in the Nyquist Frequency to be ½ of the sampling rate of the ADC. The ADS8319 has a sampling
rate of 500ksps so the Nyquist frequency is 250kHz.
4. Determine the desired cutoff frequency of the filter to be designed and enter it in the Cutoff Frequency
box; a general guideline is for the cutoff frequency to be one decade above the desired input
frequency. In this case, the input frequency is 5kHz so the cutoff frequency is set to 50kHz.
5. For the Alias Signal Amplitude at Nyquist Frequency field, enter the largest expected alias signal
amplitude that will be attenuated to ½ LSB at the Nyquist frequency. This number can range from
microvolts up to the full scale voltage. In this low-noise system, a maximum alias signal amplitude of
1mVpp is expected.
6. The Full Scale Range of the ADC is typically equal to Vref and is set to 5V in this system. The bit
resolution of the ADS8319 is 16 bits and is filled into Number of Bits.
7. After clicking OK, the results displayed on the right side of the calculator are used to design the
necessary antialias filter.

With the resulting filter specifications, the lowpass antialias filter can be designed by transcribing these
numbers into TI FilterPro. The circuit specifications in this cookbook are fnyquist = 250k, fc = 50k, Valias =
1mV, FSR = 5V, and N bits = 16, so the Bessel example from Design Approach 1 is used continuing.

SBAA282A – March 2018 – Revised March 2019 Antialiasing filter circuit design for single-ended
Submit Documentation Feedback 197 ADC input using fixed cutoff frequency
Copyright © 2018–2019, Texas Instruments Incorporated
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On startup, TI FilterPro asks for the filter specifications to design around. After the final screen, an active
filter circuit is displayed, and this is the antialias filter of the system. Refer to the following screenshots for
the steps using FilterPro.

In step 1, Lowpass is selected since an antialias filter is a specific lowpass filter.

In step 2, the values for Passband Frequency (fc) and filter order are filled in from the Analog Engineer’s
Calculator. The option to Set Fixed filter order must be selected to match calculated parameters.

Antialiasing filter circuit design for single-ended SBAA282A – March 2018 – Revised March 2019
ADC input using fixed cutoff frequency 198 Submit Documentation Feedback
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For step 3, select the filter type to match calculations; Bessel is chosen in this example for maximum
flatness in the pass band and linear phase response.

Multiple feedback topology is chosen in step 4 because the filter attenuation will not be limited by the
bandwidth of the op amp. This topology has the disadvantages of inverting a signal and offering low input
impedance. Sallen-Key can also be selected since it is a non-inverting topology with high-input
impedance, but at higher frequencies the attenuation of the filter will converge or even rise due to the
bandwidth limitations of the op amp.

SBAA282A – March 2018 – Revised March 2019 Antialiasing filter circuit design for single-ended
Submit Documentation Feedback 199 ADC input using fixed cutoff frequency
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After clicking Finish, the filter schematic is displayed along with performance specifications of the resulting
filter. Component tolerances can be adjusted using the right side drop-down menus; 1% resistors and 5%
capacitors are chosen here as practical considerations. Component values can be modified by clicking on
a number and entering new values.

The circuit previously pictured can be designed in TINA-TI for simulation. Performance characteristics are
documented in the following sections.

Antialiasing filter circuit design for single-ended SBAA282A – March 2018 – Revised March 2019
ADC input using fixed cutoff frequency 200 Submit Documentation Feedback
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DC Transfer Characteristics
The following graph shows a linear output response for filter inputs from 0V to 5V. Since the filter amplifier
is in inverting configuration, the output voltage is a function of Vout = –Vin + 5V.

AC Transfer Characteristics
The bandwidth is simulated to be 50.1kHz, about 100Hz away from the desired value entered in the
Analog Engineer’s Calculator. At the Nyquist frequency, signals are attenuated by –33.43dB, which would
lower the amplitude of the input alias signal to 21.3µV. See the TI Precision Labs Op Amps: Bandwidth 1
for more details on this subject.

SBAA282A – March 2018 – Revised March 2019 Antialiasing filter circuit design for single-ended
Submit Documentation Feedback 201 ADC input using fixed cutoff frequency
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Transient ADC Input Settling Simulation

The following simulation shows the ADS8319 settling to a 5-Vpp AC signal at 5kHz through the data
acquisition period. This type of simulation shows that the RC charge bucket components are properly
selected. See the TI Precision Labs video on Refine the Rfilt and Cfilt Values for detailed theory on this
subject.

Noise Simulation
A simplified noise calculation is made here for a rough estimate. We neglect noise from the antialias filter
in this calculation since it is attenuated for frequencies greater than 50kHz.

'J12# 365 = AJ12# 365 ® )12# ¥-J ® B? = k7.2 J8¤¾*Vo ® 18/8¾1.57 ® 50/*V = 63.8µ84/5
The value for enOPA365 is taken from a data sheet noise curve. Note that calculated and simulated noise
values match well. Some of the discrepancy between the simulated and calculated noise is due to
inaccuracy from the bandwidth of the OPA365 model. See TI Precision Labs video on Calculating the
Total Noise for ADC Systems for detailed theory on noise calculations.

Antialiasing filter circuit design for single-ended SBAA282A – March 2018 – Revised March 2019
ADC input using fixed cutoff frequency 202 Submit Documentation Feedback
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Design Featured Devices

Device Key Features Link Similar Devices

ADS8319 16-bit, 500-kl, serial interface, micro-power, miniature, SAR ADC www.ti.com/product/ads8319 www.ti.com/adcs
OPA365 50-MHz, zero-crossover, low-distortion, high CMRR, RRI/O, single- www.ti.com/product/opa365 www.ti.com/opamp
supply operational amplifier

Design References
See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.
Link to Key Files
Source files for this design – http://www.ti.com/lit/zip/sbac197.

Revision History
Revision Date Change
A March 2019 Downstyle the title and changed title role to 'Data Converters'.
Added link to circuit cookbook landing page.

SBAA282A – March 2018 – Revised March 2019 Antialiasing filter circuit design for single-ended
Submit Documentation Feedback 203 ADC input using fixed cutoff frequency
Copyright © 2018–2019, Texas Instruments Incorporated
 Analog Engineer's Circuit: Data
Converters
SBAA323 – November 2018

Circuit showing overstress protection on ADC with

integrated analog front end

Dale Li

Input ADC Input Digital Output ADS7042

VinSEMin = –10V CH_x = –10V 8000H
VinSE = 0V CH_x = 0V 0000H
VinSEMax = +10V CH_x = +10V 7FFFH

Power Supplies
AVDD DVDD Valid Input Vnormal Overvoltage Input Vstressed
5V 3.3V ±10V

Design Description
For protection relay applications in smart grid markets, a simultaneous sampling ADC, such as
ADS8588S, is widely used to maintain the phase information between different voltage and current. The
working environment of these systems is very harsh and undesired signals with amplitudes up to ±30Vpk
(60Vpp) may be applied to the signal chain. Hence, it is important to protect the ADC input from
overvoltage damage and also maintain good performance. This document shows how to design the
overvoltage protection and also shows the performance impact of the overvoltage signal on adjacent
channels. Finally, the performance impact results are compared between a Texas Instruments device and
a pin for pin compatible competitor device.
AVDD DVDD

REXT
AIN_1P
Vstressed ADS8588S
(Up to ±30Vpeak) AIN_1GND
REXT
Digital
AGND
AGND REXT Interface
AIN_2P
Vnormal Voltage
Reference
(±10Vpeak) AIN_2GND

REXT
AGND
AGND
AGND DGND
Total 8 Input Channels

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Specifications

Specification Calculated Measured

60Vpp Overvoltage Max Input Current = 1mA SNR and THD performance and
overvoltage feedthrough

Design Notes
1. Use COG type capacitors for the CEXT filter capacitor.
2. Review the Electrical Overstress video series for a theoretical explanation of overstress on amplifiers.
Although this section covers amplifiers, the theory apples to data converters as well.
Component Selection
1. Find Rext(min) to limit the current less than 1mA. The suggested maximum current flowing into the
ADS8588S input pins is ±10mA which is commonly required based on the internal structure of the
ADC. This 10mA is an absolute maximum limit, and it is better to have some margins around this
number, restricting the current less than 1mA is recommended. For this example design the minimum
external resistance is 15kΩ.

30V 15V
REXT 15k :
1mA

+30Vpeak 1mA +15V

(max) (max)

AIN_nP

Vstressed REXT ? ADS8588S

AIN_nGND

AGND AGND

2. Choose Rext or Cext to set the bandwidth of the input filter to the desired frequency. Depending on the
application different cutoff frequencies may be required. In this case the cutoff frequency must be
6.4kHz to accommodate 128 harmonics of a 50-Hz signal. In this case a 1-nF capacitor is also desired,
as 1nF is a common industrial input filter capacitance value. After applying the equation, the external
resistor (Rext) is determined to be 24.9kΩ. Note that the external resistor calculated in this step is larger
than the minimum resistance value from step 1 (is Rext > Rext(min)).

1 1
REXT 24.9k :
2S ˜ fc ˜ CEXT 2S 6.4kHz (1nF )

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Test Setup
In a real world application with a multiple channel device, it is possible that one channel has an
overvoltage signal applied to it and the other channels have valid signals on them. In this case it is
desirable to have good performance on the channels with valid signals while protecting the channel with
the overvoltage signal from damage. The measurements in this cookbook document are all done with an
overvoltage signal applied to channel 1 and a valid signal applied to the other channels. All inputs are
protected using the circuit designed in component selection. The following diagram shows the test setup.

Signal Generator for HV AC Stressed Signal

Oscilloscope
FFT in GUI

Signal Generator for AC Test Signal ADS8588SEVM with PHI controller

Device Protection
The following figure shows a simplified circuit for each analog input channel inside ADS8588S. An internal
clamp protection circuit is designed on each of the 8 analog input channels and it allows each analog input
to swing up to a maximum voltage of ±15V. For input voltages beyond ±15V the internal input clamp
circuit may turn on. Further increasing the overvoltage signal will result in higher current flow in the
protection circuit (see the I-V Curve for input clamp protection circuit in the ADS8588S 16-Bit, High-Speed,
8-Channel, Simultaneous-Sampling ADC with Bipolar Inputs on a Single Supply data sheet). High input
current can become destructive, degrading or even destroying the ADC device. This is why we limit the
current to less than 1mA (see component selection section). Under a fault event the clamp protection
circuit will turn on and limit the input voltage to approximately 15V and limit the current to less than 1mA.
AVDD DVDD

RFB

Input Clamp
REXT AIN_nP RIN
+

16-Bit
Vin 3rd-Order ADC
PGA SAR
REXT LPF Driver
ADC
RIN
AGND
AIN_nGND
AGND
RFB

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ADC Input (AIN_P) Under Overvoltage Condition

The following figure shows the ADC input voltage when the ±30Vpeak overvoltage signal is applied. Note
that the clamp turns on and limits the ADC input to ±15Vpeak. The external resistor, REXT, limits the
current to less than one milliamp to protect the ADC from damage.

I-V Curve for the Internal Input Clamp Protection Circuit

The following figure shows the V-I curve for internal clamp. Note that it remains off and very low leakage
for input voltage inside the ±15-V range. It turns on and limits the voltage outside of the ±15-V range.

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SNR and THD (Channel 1 = Overvoltage)

The following figures were taken with a ±30Vpeak (60Vpp) electrical overstress signal applied to channel 1
and the remainder of the channels are connected to a valid input signal (1-kHz, –0.5dBFS sine wave). The
SNR and THD of the channels with the valid input signal is measured with the overvoltage signal applied
to channel 1. This test is done for the ADS8588S as well as a pin for pin comparable competitor device.
Note that the ADS8588S SNR and THD are either not effected by the fault signal or the effect is minimal.
Otherwise, the competitor device SNR and THD performance is substantially effected by the fault signal.
Note that this circuit was also tested with ±15Vpeak, ±18Vpeak, ±21Vpeak, ±24Vpeak, and ±27Vpeak
signals. As expected, larger overstress signals produce the worst-case results.
ADS8588S Competitor A ADS8588S Competitor A
100 -120

90 -110

80 -100

70 -90

CH2 CH2
SNR 60 THD -80
(dB) (dB)
50 -70

40 -60

30 -50

20 -40
20 25 30 35 40 45 50 55 60 65 20 25 30 35 40 45 50 55 60 65

Vstress Amplitude (Vpp) Vstress Amplitude (Vpp)

ADS8588S Competitor A ADS8588S Competitor A

100 -120

90 -110

80 -100

70 -90

CH3 CH3
SNR 60 THD -80
(dB) (dB)
50 -70

40 -60

30 -50

20 -40
20 25 30 35 40 45 50 55 60 65 20 25 30 35 40 45 50 55 60 65

Vstress Amplitude (Vpp) Vstress Amplitude (Vpp)

ADS8588S Competitor A ADS8588S Competitor A

100 -120

90 -110

80 -100

70 -90

CH4 CH4
SNR 60 THD -80
(dB) (dB)
50 -70

40 -60

30 -50

20 -40
20 25 30 35 40 45 50 55 60 65 20 25 30 35 40 45 50 55 60 65

Vstress Amplitude (Vpp) Vstress Amplitude (Vpp)

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SNR and THD (Channel 1 = Overvoltage) (Continued)

This is a continuation of the SNR and THD measurements where a ±30Vpeak (60Vpp) fault is applied to
channel 1, and a valid input signal is applied to other channels performance verification.
ADS8588S Competitor A ADS8588S Competitor A
100 -120

90 -110

80 -100

70 -90

CH5 CH5
SNR 60 THD -80
(dB) (dB)
50 -70

40 -60

30 -50

20 -40
20 25 30 35 40 45 50 55 60 65 20 25 30 35 40 45 50 55 60 65

Vstress Amplitude (Vpp) Vstress Amplitude (Vpp)

ADS8588S Competitor A ADS8588S Competitor A

100 -120

90 -110

80 -100

70 -90

CH6 CH6
SNR 60 THD -80
(dB) (dB)
50 -70

40 -60

30 -50

20 -40
20 25 30 35 40 45 50 55 60 65 20 25 30 35 40 45 50 55 60 65

Vstress Amplitude (Vpp) Vstress Amplitude (Vpp)

ADS8588S Competitor A ADS8588S Competitor A

100 -120

90 -110

80 -100

70 -90

CH7 CH7
SNR 60 THD -80
(dB) (dB)
50 -70

40 -60

30 -50

20 -40
20 25 30 35 40 45 50 55 60 65 20 25 30 35 40 45 50 55 60 65

Vstress Amplitude (Vpp) Vstress Amplitude (Vpp)

ADS8588S Competitor A ADS8588S Competitor A

100 -120

90 -110

80 -100

70 -90

CH8 CH8
SNR 60 THD -80
(dB) (dB)
50 -70

40 -60

30 -50

20 -40
20 25 30 35 40 45 50 55 60 65 20 25 30 35 40 45 50 55 60 65

Vstress Amplitude (Vpp) Vstress Amplitude (Vpp)

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Feedthrough of Fault Signal to the Rest of the Channels

The following figures were taken with a ±30Vpeak (60Vpp) electrical overstress signal applied to channel 1
and the remainder of the channels are floating. The feedthrough of the overvoltage signal to the floating
channels is measured using an oscilloscope. Note that both the ADS8588S and the competitor device are
similar for channel 2. On the rest of the channels (CH3 to CH8) the feedthrough of the ADS8588S is much
smaller than the TI device. This is a strong indication that for the ADS8588S the operation of channels
with valid input signals will not be significantly impacted when one channel in the system has an
overvoltage fault. On the other hand, for the competitor device all channels are adversely effected by the
fault. Note that this circuit was also tested with ±15Vpeak, ±18Vpeak, ±21Vpeak, ±24Vpeak, and
±27Vpeak signals. As expected, larger overstress signals produce the worst case results.
CH2 ± ADS8588S CH2 ± Competitor A

1.0V/div 1.0V/div

CH3 ± ADS8588S CH3 ± Competitor A

50mV/div 1.0V/div

CH4 ± ADS8588S CH4 ± Competitor A

50mV/div 1.0V/div

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Feedthrough of Fault Signal to the Rest of the Channels (Continued)

This is a continuation of the feedthrough test showing that the ADS8588S channels with valid input signals
are not effected by channels with faults.
CH5 ± ADS8588S CH5 ± Competitor A

50mV/div 1.0V/div

CH6 ± ADS8588S CH6 ± Competitor A

50mV/div 1.0V/div

CH7 ± ADS8588S CH7 ± Competitor A

50mV/div 50mV/div

CH8 ± ADS8588S CH8 ± Competitor A

50mV/div 20mV/div

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Design References
See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.
Texas Instruments, Reducing Effects of External RC Filter Circuit on Gain and Drift Error for Integrated
Analog Front Ends (AFEs): ±10V
Texas Instruments, Circuit to Increase Input Range on an Integrated Analog Front End (AFE) SAR ADC
spacer
Design Featured Devices

Device Key Features Link Other Possible Devices

ADS8588S 16-bit, 8 Channel Simultaneous-Sampling, Bipolar-Input SAR ADC http://www.ti.com/product/ADS8588S http://www.ti.com/adcs
REF5025 Low-noise, low drift, high precision voltage reference http://www.ti.com/product/REF5025 http://www.ti.com/power-
management/voltage-
reference

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 Analog Engineer's Circuit: Data
Converters
SBAA269A – February 2018 – Revised March 2019

Digitally-isolated ADS8689 circuit design

Reed Kaczmarek

Input ADC Input Digital Output ADS7042

VinMin = –12.288V AIN_P = –12.288V, AIN_N = 0V 8000H or -3276810
VinMax = 12.288V AIN_P = 12.288V, AIN_N = 0V 7FFFH or 3276710

Power Supplies
AVDD Vee Vdd
5V 6.5 V 5V

Design Description
This design shows a digitally isolated high-voltage SAR ADC that is capable of full AC performance at
maximum throughput. This design is intended for channel-to-channel isolated analog input modules as
well as measuring a signal with a very large common mode. Programmable logic controller, analog input
modules, and many 4- to 20-mA signal applications will benefit from this design. See Isolated Power
Supply Low-Noise, 5V, 100mA for details on the isolated power supply design suitable for these
applications. This cookbook includes links to design files.
This circuit implementation is applicable in applications such as Analog Input Modules, Electrocardiogram
(ECG), Pulse Oximeter, and Bedside Patient Monitors.

5V 6.5V Isolated 5V
LDO Power
Supply

ISO7741

AVDD SCLK SCLK

AIN_P CS CS
ADS8689
SDI SDI
RBurden
+

AIN_N
Analog
SDO SDO
Input GND
Signal
Install
for
Current
Inputs
Copyright © 2018, Texas Instruments Incorporated

SBAA269A – February 2018 – Revised March 2019 Digitally-isolated ADS8689 circuit design
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Specifications

Specification Calculated Measured

SCLK Frequency 6.66MHz 6.67MHz
Sampling Rate 100ksps 100ksps
Signal-to-Noise Ratio (SNR) 92dB Min: 92.29dB
Max: 92.46dB
Total Harmonic Distortion (THD) –112dB Min: –108.8dB
Max: –111.38dB

Design Notes
1. Select a SAR ADC that will meet the input voltage range, sampling rate, and resolution for the system.
This is covered in the component selection section.
2. Select a digital isolator that will allow for the required isolation specification as well as the correct
number of channels and channel directions. This is covered in the component selection section.
3. Install the burden resistor for current inputs. This design will remove any common mode limitation of
the inputs due to the channel-to-channel isolation. The burden resistor should be selected so that the
maximum current input will stay within the full scale range of the SAR ADC.
Component Selection
1. Select a SAR ADC that meets the input voltage range, sampling rate, and resolution for the system:
• Desired input range: ±12V
• Desired effective number of bits (ENOB): 14 bits
• Desired sampling rate: 100ksps
• ADS8689 input range: ±12.228V
• ADS8689 ENOB: 14.8 bits
• ADS8689 maximum sampling rate: 100ksps

NOTE: There is a wide selection of TI SAR ADCs that match the specifications in the previous
list.

2. Select a digital isolator that will allow for the required isolation specification as well as the correct
number of bidirectional channels:
• TI offers digital isolators with isolation rating ranging from 2.5kVRMS to 5.7kVRMS.
• Choose isolation ratings based on the system requirements.
• For a standard SPI interface, the digital isolator needs to be 4-channels with 3 channels in the
same direction and 1 channel in the opposite direction.
• The ISO774x is a digital isolator family for 4-channel devices with all combinations of channel
directions and the ability to select a 2.5kVRMS or a 5.0kVRMS isolation rating.
3. Understand the expected delays to the digital signal from the digital isolator:
• The ISO7741 has a typical propagation delay of 10.7ns with a maximum of 16ns.
• Round trip isolation delay is 21.4ns typical or 32ns maximum.
• SCLK is running at 6.66MHz resulting in a period of 150ns.
• The typical roundtrip delay is 14% of the SCLK period.
• The maximum roundtrip delay is 21% of the SCLK period.

NOTE: The delay from the isolator results in a delay between the ideal SDO read relative to SCLK
and the actual SDO read. This delay can be adjusted for by adding an SCLK return signal
that travels through the digital isolator to all for the SDO to be read at exactly the correct
time. Adding a return clock requires another channel of isolation.

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Measured FFT
This performance was measured on a custom 4-channel, channel-to-channel isolated ADS8689 PCB.
The input signal is a 24Vpp, 1-kHz sine wave. The AC performance indicates minimum SNR = 92.2dB
and minimum THD = –108.8dB, which matches well with the specified performance of the ADC of SNR
= 92dB and THD = –112dB.

Channel SNR(dB) THD (dB)

1 92.29 –109.95
2 92.38 –108.82
3 92.46 –109.53
4 92.42 –111.38

TVS Diode Performance Degradation

A 14-V bidirectional TVS diode was used in this design to protect the input of the SAR ADC. The TVS
diode actually degrades total harmonic distortion (THD) due to the added capacitance. The THD was seen
to be around 6dB worse with the TVS diode installed versus uninstalled.

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Design Featured Devices

Device Key Features Link Similar Devices

ADS8689 (1) 16 bit resolution, SPI, 100-ksps sample rate, single-ended www.ti.com/product/ADS8689 www.ti.com/adcs
input, and ±12.288-V input range.
ISO7741 (2) High-speed, robust-EMC reinforced quad-channel digital www.ti.com/product/iso7741 www.ti.com/iso
isolator

(1)
The ADS8689 has in internal attenuator and programable gain amplifier that allows for a wide input voltage range.
(2)
The ISO7741 is used to isolate the digital input signals.

Design References
See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.
Link to Key Files
Source files for Digitally-Isolated ADS8689 – http://www.ti.com/lit/zip/sbac179.

Revision History
Revision Date Change
A March 2019 Downstyle the title and changed title role to 'Data Converters'.
Added link to circuit cookbook landing page.

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 Analog Engineer's Circuit: Data
Converters
SBAA239A – January 2018 – Revised January 2019

Reducing effects of external RC filter circuit on gain and

drift error for integrated analog front ends (AFEs): ±10V

Cynthia Sosa

Input ADC Input Digital Output

VinMin = –10V AIN-xP = –10V, AIN-xGND = 0V –3276810, 8000H
VinMax = 10V AIN-xP = 10V AIN-xGND = 0V 3276710, 7FFFH

Power Supplies
AVDD DVDD
5V 5V

Design Description
This cookbook design describes how to select filter component values and how to minimize the gain error
and drift introduced by this filter on a fully-integrated analog front end (AFE) SAR ADC. The design uses
the input impedance drift at the full scale range of ±10V of the ADS8588S. This external RC filter
minimizes external noise and provides protection from electrical overstress. Minimizing gain error and drift
are important to end equipment such as: Multi-Function Relays, AC Analog Input Modules, and Terminal
Units. This design describes two correction methods, a no-calibration correction factor and a 2-point
calibration. Implementing calibration can minimize both the gain error introduced by the external resistor
and the internal device gain error to negligible levels.

REXT AIN_xP RIN

Vin 1MŸ
3rd
2nd 16-B
CEXT PGA Order
Order
16-Bit SAR CHx_OUT
REXT 1MŸ
Low-Pass
SAR
AIN_xGND RIN

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Specifications

Specification Calculated Measured

Introduced Gain Error (25°C) 0.9901% 0.9894%
Introduced Gain Error (125°C) 0.995% –1.1388%
Introduced Gain Error Drift 0.49ppm/°C –0.8031ppm/°C

Design Notes
1. Use low drift REXT resistors to maintain low drift and minimize gain error. This design uses resistors with
a temperature coefficient of 25ppm/°C and ±0.1% tolerance.
2. The internal programmable gain amplifier (PGA) presents a constant resistive impedance of 1MΩ
3. The REXT value introduced is directly proportional to its introduced error
4. Calibration can also be used to eliminate system offset gain error
5. The TI Precision Labs – ADCs training video series covers methods for calculating gain and offset
error and eliminating these errors through calibration, see Understanding and Calibrating the Offset
and Gain for ADC Systems. Using SPICE Monte Carlo Tool for Statistical Error Analysis explains how
to use Monte Carlo Analysis for statistical error analysis.

Component Selection
External anti-aliasing RC filters reduce noise and protect from electrical overstress; if a large resistor value
is used, this will further limit the input current. A large external resistive value will also provide a low cutoff
frequency, which is desired for relay protection applications as the input frequencies are usually 50 or 60
Hz. Furthermore, a balanced RC filter configuration is required for better common-mode noise rejection;
matching external resistors are present on both the negative and positive input paths. To minimize the
introduced drift error, the external resistors should be low drift; 25ppm/°C resistors.
1. Choose a high-value REXT based on the desired cutoff frequency. A cutoff frequency of 320Hz was
used to eliminate harmonics from a 50- or 60-Hz input signal.
REXT = 10kΩ
2. Choose CEXT
1 1
C EXT 24 . 8 nF
2 ˜ S ˜ f C ˜ 2 ˜ R EXT 2 ˜ S ˜ 320 Hz ˜ 2 ˜ 10 k :
Nearest standard capacitor value available, CEXT = 24nF

Calculate Gain Error Drift

This section demonstrates how to calculate the introduced gain error drift. The additional drift from the
external filter resistor is small compared to the internal device drift.

1. Calculate effective internal impedance due to maximum negative drift (–25ppm/°C)

R IN ( 25 ppm / q C ) R IN ˜ [Drift ( ppm / q C ) ˜ G T ( q C ) 1]
R IN ( 25 ppm / q C ) 1M : ˜ [ 25 ppm / q C ˜ (125 q C 25 q C ) 1]
R IN ( 25 ppm / q C ) 0 . 9975 M :
2. Calculate effective external resistance due to maximum positive drift (25ppm/°C)
R EXT ( 25 ppm / q C ) R EXT ˜ [Drift ( ppm / q C ) ˜ G T ( q C ) 1]
R EXT ( 25 ppm / q C ) 1 0 k : ˜ [ 25 ppm / q C ˜ (125 q C 25 q C ) 1]
R EXT ( 25 ppm / q C ) 10 . 025 k :

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3. Calculate nominal gain error introduced by the external resistor at room temperature
1
GainError (R EXT ) RoomTemp
R IN
1
R EXT
1
GainError (R EXT ) RoomTemp
1M :
1
10 k :
GainError (R EXT ) RoomTemp 0 .009901 or 0 .9901 %
4. Calculate nominal gain error introduced by the external resistor at highest rated temperature
1
GainError (R EXT ) 125 qC
0.9975 M :
1
10 .025 k :
GainError (R EXT ) 125 qC 0.009950 or 0 .995 %
5. Calculate gain error drift introduced by the external resistor
GainError (REXT ) RoomT emp GainError (REXT ) 125qC
GainError _ Drift (REXT ) ˜ 10 6
GT
0.009901 0.00950
GainError _ Drift (REXT ) ˜ 10 6
(125qC 25qC)
GainError _ Drift (REXT ) 0.49ppm / qC

The maximum gain error temperature drift of the ADS8588S is ±14ppm/°C, which is orders of magnitude
larger than the calculated drift error introduced, making the introduced error negligible. The minimal drift
error introduced by the external resistors has greatly to do with the low drift coefficient of the input
impedance (±25ppm/⁰C).
To measure the introduced gain error drift, two test signals are sampled and applied at 0.5V from the full
scale input range within the linear range of the ADC. The signals are applied and sampled with and
without the external RC filter present. These measurements are performed at both temperatures, 25°C
and 125°C. The percent gain errors are solved for by finding the percent error of the ideal slope and the
measured slope for each of the four distinctive test conditions, resulting in four distinct percent gain error
measurements. The drift (ppm/°C) with and without the RC present is then calculated by converting the
percent gain errors to decimal format then following step 5 shown above. The introduced gain error drift is
then solved for by subtracting the drift of the RC and no RC present.

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Uncalibrated Correction
An uncalibrated correction targets to solve the input voltage before any losses occur due to the RC filter
by working backwards from the ADC measured samples using a voltage divider.
1. Apply known test signal and measure equivalent code

Vin Measured Code Equivalent Measured Input

9.5V 30841 9.412

2. Calculate the input voltage before RC losses

R RIN
VIN _ NoLoss VIN _ Equivalent ˜ EXT
RIN
1M: 10 k:
VIN _ NoLoss 9.412 ˜
1M:
VIN _ NoLoss 9.50612 V

Uncalibrated Correction Measurements

Using a voltage correction can be beneficial, but not the most comprehensive. The correction factor can
have a worst-case error of 0.2456% at room temperature due to change in internal impedance.

Room Temperature (25°C) Measurements

Vin Code Reading Correction Error %
9.5 30841 9.412 9.506120 0.0644
8.5 27594 8.421 8.505210 0.0613
5 16232 4.954 5.003540 0.0708
0 1 0 0.000000 –
–5 –16230 –4.953 –5.002530 0.0506
–8.5 –27593 –8.421 –8.505210 0.0613
–9.5 –30839 –9.411 –9.505110 0.0538

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2-Point Calibration Method

A two point calibration applies and samples two test signals at 0.5V from the full scale input range within
the linear range of the ADC. These sample measurements are then used to calculate the slope and offset
of the linear transfer function. Calibration will eliminate both the gain error introduced by the external
resistor and the internal device gain error.
1. Apply test signal at 2.5% of input linear range

Vmin Measured Code

–9.5V –30839

2. Apply test signal at 97.5% of input linear range

Vmax Measured Code

9.5V 30841

3. Calculate slope and offset calibration coefficients

Code max Code min
m
Vmax Vmin
30841 ( 30839 )
m 3246 . 3158
9 .5 ( 9 .5 )
b Codemin m ˜ Vmin
b ( 30839 ) 3246 .3 ˜ ( 9.5 V ) 1.0001
4. Apply calibration coefficient to all subsequent measurements
Code b
VinCalibrate
m
30841 1.0001
VinCalibrate 9.5000
3246.3158

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2-Point Calibration Method Measurements

Calibration Coefficients
m = 3246.3158; b = 1.0001

At room temperature without calibration, a gain error is present. Once calibration is applied to the
measured results from the ADC, the gain error is minimized to nearly zero.

Room Temperature (25°C) Measurements

Voltage Error Without Voltage Error With
VIN Code Uncalibrated VIN Calibrated VIN
Calibration % Calibration %
9.5 30841 9.412 9.500000 –0.926316 –0.000001
8.5 27594 8.421 8.499789 –0.929412 –0.002480
5 16232 16232 4.999822 –0.920000 –0.003568
0 1 0 0.000000 – –
–5 –16230 –4.953 –4.999822 –0.0940000 –0.003567
–8.5 –27593 –8.421 –8.500097 –0.929412 0.001144
–9.5 –30839 –9.411 –9.500000 –0.936842 0.000000

When exposed to high temperatures, the gain error increases, as expected. Once calibration is applied,
the voltage error is decreased but not eliminated; the error still present is the drift error.

High Temperature (125°C) Measurements

Relative Voltage Error Relative Voltage Error
VIN Code Uncalibrated VIN Calibrated VIN
Without Calibration % With Calibration %
9.5 30826 9.407 9.495379 –0.978947 –0.048639
8.5 27582 8.417 8.496093 –0.976471 –0.045968
5 16224 4.951 4.997357 –0.980000 –0.052854
0 0 0 –0.000308 0 –
–5 –16224 –4.951 –4.997973 –0.980000 –0.040531
–8.5 –27581 –8.417 –8.496401 –0.976471 –0.042344
–9.5 –30826 –9.407 –9.495995 –0.978947 –0.042153

Design References
See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.
Design Featured Devices

Device Key Features Link Similar Devices

ADS8588S 16-bit, high-speed 8-channel simultaneous-sampling ADC with bipolar www.ti.com/product/ADS8588S www.ti.com/adcs
inputs on a single supply

Revision History

Revision Date Change

A January 2019 Downscale title, updated header on first page.

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 Analog Engineer's Circuit: Data
Converters
SBAA268A – February 2018 – Revised March 2019

Isolated power supply, low-noise circuit: 5V, 100mA

Reed Kaczmarek

Power Supplies
AVDD Vee Vdd
5.0V 6.5V 5.0V

Design Description
This design shows an isolated power supply using a transformer driver and a low dropout regulator (LDO).
This design is intended to be combined with a digitally-isolated SAR ADC, such as in Digitally-Isolated
ADS8689 Design. Industrial applications that require an isolation interface are the primary application for
this design in combination with a SAR ADC. The transformer driver and LDO can be selected differently
based on the output current requirements and output voltage noise requirements. This power supply was
built and tested on a PCB with the ADS8689 and later in this document the performance of the ADS8689
is shown to prove the effectiveness of the power supply.
This circuit implementation is applicable in applications such as Analog Input Modules, Electrocardiogram
(ECG), Pulse Oximeters, and Bedside Patient Monitors.

SN6505B
LP2981-5.0
GND D2 6.5 V 5V
IN OUT
10 µF 0.1 µF EN 10 µF
Enable EN Vcc
GND
CLK D1
+

5 VDC 10 µF 0.1 µF

Copyright © 2018, Texas Instruments Incorporated

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Specifications

Specification Goal Measured

LDO Output Current < 100mA 16mA per channel
LDO Output Voltage Noise < 1mVRMS N/A
ADS8689 Signal-to-Noise Ratio 92dB 92.4dB
(SNR)
ADS8689 Total Harmonic –112dB 111.3dB
Distortion (THD)

Design Notes
1. Determine the required supply current that is needed on the secondary side of the transformer. This
information is used for component selection.
2. Choosing the transformer and transformer driver are very important to creating a correct isolated power
supply.
3. The CLK pin on the SN6505B can be connected to an external clock or left floating to use the internal
420-kHz clock.
Component Selection
1. Select a transformer driver based on the required output current.
• SN6505 will provide up to 1A of output current. The SN6505A has a 160-kHz internal clock and the
SN6505B has a 420-kHz internal clock.
• SN6501 will provide up to 350mA of output current.
2. Select a transformer with the desired turns ratio and current rating.
• This design takes 5-V input and produces 6.5-V output. The turns ratio is determined as shown in
the following:
(1)
• The 760390014 from Wurth Electronics was used in this design since it has a 1:1.3 turns ratio and
a current rating that meets the 100-mA design specification.
3. Select a low dropout regulator (LDO) to use the transformer output and produce a low-noise supply
voltage.
a. The LDO should be selected to meet the output current requirement of the system and output
voltage noise requirement of the system.
b. The LP2981-5.0 is a fixed output voltage LDO that was selected for this design. This LDO is able
to provide 100mA of output current. Also, the LDO output is accurate with only 160µVRMS of output
voltage noise.
4. Select the rectifier diodes for the fast switching of the SN6505B.
• The SN6505x Low-Noise 1-A Transformer Drivers for Isolated Power Supplies data sheet
recommends using low-cost Schottky rectifier MBR0520L.
• The forward voltage drop will take away from the output voltage of your isolated power supply.
• The diodes must be rated for the expected current level for this supply.

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Measured Transformer Driver Outputs

The following image is an oscilloscope capture of the two transformer drive lines from the SN6505B.
These are 0V to 5V pulses at a frequency of 411kHz.

Measured SN6505B Stage Output Ripple

The following image is an oscilloscope capture of the output voltage following the rectifiers of the
SN6505B power stage. This is the input to the LP2981-5.0 LDO. Result: 1.12mVRMS.

SBAA268A – February 2018 – Revised March 2019 Isolated power supply, low-noise circuit: 5V, 100mA
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Measured FFT
This power supply was implemented on a channel-to-channel isolated ADS8689 PCB. Measuring the
AC performance of the ADS8689 proves the effectiveness of this isolated power supply. The AC
performance indicates SNR = 92.4dB and THD = –111.3dB, which matches well with the specified
performance of the ADC: SNR = 92dB and THD = –112dB).

0 10 20 30 40 50

-20 f = 2kHz SNR = 92.4dB

-40 THD = -111.38dB
Amplitude (dB)

-60

-80

-100

-120

-140

-160

-180

-200
10 20 30 40 50
Frequency (kHz)

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Design Featured Devices

Device Key Features Link Similar Devices

ADS8689 12-bit resolution, SPI, 1-Msps sample rate, single-ended input, www.ti.com/product/ADS8689 www.ti.com/adcs
AVDD/Vref input range 1.6V to 3.6V.
SN6505B Low-Noise 1-A, 420-kHz transformer driver www.ti.com/product/SN6505B www.ti.com/isolation/transformer-
driver/products.html
LP2981 100mA ultra-low dropout regulator with shutdown www.ti.com/product/LP2981 www.ti.com/ldo

Design References
See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.

Revision History
Revision Date Change
A March 2019 Downstyle the title and changed title role to 'Data Converters'.
Added link to circuit cookbook landing page.

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 Analog Engineer's Circuit: Data
Converters
SBAA252A – February 2018 – Revised March 2019

Powering a dual-supply op-amp circuit with one LDO

Reed Kaczmarek

LDO Input LDO Output Output Noise Level

Vin+ > 6V 5.2V 27µVRMS
Vin– < –5V –200mV 22µVRMS

Design Description
This design shows a power supply that can be used to create a positive operational-amplifier (op amp)
supply and a small negative op-amp supply. This small negative voltage is adjustable and is necessary in
many operational amplifiers in order to ensure linearity down to ground. This design shows the
TPS7A3901 as the power supply for creating the positive and negative voltage rails for operational
amplifier circuits. This low dropout regulator (LDO) differs from most in its ability to regulate small negative
voltages, as the following image shows. This is a generic circuit implementation that can be used in many
Industrial applications.

TPS7A3901
VIN+ 6V VPOS 5.2V
INP OUTP
10µF R1P 34NŸ 10µF
GND FBP
R2P 10NŸ
VIN- -5V
INN VNEG -0.2V
10µF OUTN
R1N 1.69NŸ 10µF
FBN
R2N 10NŸ
BUF

Copyright © 2018, Texas Instruments Incorporated

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Specifications

Measured Performance of ADS8900B With LDO

Parameter Test Condition Data Sheet Specification Measured ADS8900B Performance
SNR Vin_max = 5V, Vin_min = 0V 104.5dB 102.2dB
THD Vin_max = 5V, Vin_min = 0V –125dB –123.5dB

Design Notes
1. Determine the linear range of the op amp based on common mode, output swing, and linear open-loop
gain specification.
2. Set the adjustable LDO outputs to match the linear range of op amp.
3. Select X7R capacitors according to their temperature performance.
4. In cases where a negative supply is not available, an alternative solution is to use a Low Noise
Negative Bias Generator (LM7705).
Component Selection
1. A common configuration shows in the following image using an OPA320 in a buffer configuration with a
0-V to 5-V desired linear signal swing. The power supplies are both 200mV away from the desired
input and output swing. This topology ensures linear input and output swing for this amplifier.

+5.2V

- Rfilt
+

+
OPA320
Cfilt
+

Vin
-0.2V

Copyright © 2018, Texas Instruments Incorporated

2. Select the components for the adjustable LDO outputs. Using the previous OPA320 example, the rails
for the system will be –200mV and +5.2 V.

Desired Output R1 R2
+5.2V 34kΩ 10kΩ
–200mV 1.69kΩ 10kΩ

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ADS8900B 20-Bit FFT Taken With LDO Adjusted to 5.2V and –0.2V
The FFT in the following was measured with an input signal very near full scale ±5V (–0.2dBFS). Note that
the SNR and THD is very good compared to the case where the supply is adjusted to 5V and GND. Note
the TPS7A3901 is a convenient way to generate a linear –0.2-V supply.

fin = 2kHz SNR: 102.3 dB

Amplitude = -0.2dBFS THD: -123.5 dB

ADS8900B 20-Bit FFT Taken With LDO Adjusted to 5.0V and GND
The FFT shown in the following image was measured with an input signal very near full scale ±5V
(–0.2dBFS). Note that the SNR and THD is poor compared to the case where the supply is adjusted to
5.2V and –0.2V.

fin = 2kHz SNR: 54.8 dB

Amplitude = -0.2dBFS THD: -40.7 dB

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Design Featured Devices

Device Key Features Link Similar Devices

TPS7A3901 The TPS7A39 device is a dual, monolithic, high-PSRR, positive and www.ti.com/product/TPS7A39 www.ti.com/product/LM7705 (1)
negative low-dropout (LDO) voltage regulator capable of sourcing (and
sinking) up to 150mA of current. It has a wide output voltage range of
1.2V to 30V for the positive output and –30V to 0V for the negative
output. This device is ideally suited for generating a small negative
supply voltage that is useful in cases where a single-supply amplifier
needs a small negative supply so that the output can linearly swing to
0V.
ADS8900B Bipolar differential inputs, SAR ADC with internal reference buffer, SPI www.ti.com/product/ADS8900B www.ti.com/adcs
interface
OPA320 Precision, Zero-Crossover, 20Mhz, RRIO, CMOS Operational Amplifier www.ti.com/product/opa320 www.ti.com/opamp

(1)
The LM7705 is another option for a negative voltage supply. It is not an LDO regulator, but instead it is a switched-capacitor regulator.

Design References
See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.

Revision History
Revision Date Change
A March 2019 Downstyle the title and changed title role to 'Data Converters'.
Added link to circuit cookbook landing page.

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 Analog Engineer's Circuit: Data
Converters
SBAA322 – January 2019

Active-filtering circuit for audio DACs

Paul Frost

Design Goals

Filter Characteristics
Filter Input Cutoff Frequency Filter Gain
4VPP, 1.42VRMS –3dB @ 23kHz –1 V/V, 0 dB

Design Description
This circuit shows the implementation of a second-order active-filter for audio digital-to-analog converter
(DAC) applications. In applications such as automotive head units, home theater soundbars, and AV
receivers, it is critical to minimum undesirable noise in the audible range, approximately 20Hz to 22kHz.
For this reason, many delta-sigma type audio DACs implement noise shaping techniques that force the
noise generated by the over-sampling functionality of the DAC outputs side of the audible range, this is
process is called 'noise-shaping', while the noise itself is called 'out-of-band noise'. Many common audio
DACs, such as the PCM1753-Q1, have noise-shaping that forces the out-of-band noise to approximately
50% the sampling rate, fS, of the digital source. While this noise is not generally considered audible, it can
have detrimental effects on the amplifier circuits that are found on the output of audio DACs. For example,
this out-of-band noise may be aliased by class-D amplifiers that operate at higher frequencies back into
the audible range. In addition, this noise would also experience the same analog gain of the output
amplifiers if no filtering is implemented. The second-order active-filter design allows a higher level of noise
attenuation closer to the audible band than a simple, first-order RC filter. In addition, it allows the audio
output of the system to have a lower impedance and current drive than the audio DAC can provide due to
the output drive capabilities of the op amp featured in the filter.
+5V
C2
R3
R2 330pF
3.6k +5V
13k
I2S PCM1753-Q1 VOUTx í
R1 OPA
Audio Out
3.6k C1 1678
3.3nF + C3
10 …F
í5V

Design Notes
1. It is important to note that the fC of the design is optimized for a sample rate of at least 44.1kHz, which
is common in audio systems. The fC should be approximate 50% of the sample rate, to attenuate the
out-of-band noise from the delta-sigma modulator. If a higher frequency sample rate is used, the cutoff
frequency could be moved further out in the frequency domain to allow a wider bandwidth from the
audio DAC.
2. Not all audio DACs require a second-order active filter. Some audio DACs feature different noise-
shaping architectures that may move the out-of-band noise further away from the audible range,
meaning that a simple RC filter may be enough to attenuate the unwanted noise.
3. Most audio system feature a DC blocking capacitor to allow the audio output to be ground centered. In
this design, the blocking capacitor could be directly on the output of the DAC, but as the amplifier will
also have some small offset, the capacitor is generally placed directly on the output of the filter or the
input of the amplifier or headphone driver that would proceed the active filter.

SBAA322 – January 2019 Active-filtering circuit for audio DACs

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Design Steps
1. Select a DAC based on the needs of the application. Consider the required signal-to-noise ratio (SNR),
total harmonic distortion and noise (THD+N), and supported I2S interface sample rates. While most
audio DACs support rates ranging from 16kHz to 192kHz, not all support rates like 384kHz or 768kHz.
Higher rates result in noise shaping that moves the out-of-band noise further from the audible range,
but not all audio sources can provide them.
2. The amplifier selected for the design (OPA1678) is a CMOS input amplifier. CMOS input amplifiers
have lower current noise at the inputs of the amplifier at lower frequencies than JFET type amplifiers.
The current-noise will translate to voltage-noise on the output as the filter features input large
resistance values, so it is important to select an amplifier with low current-noise.
3. Select the resistor and capacitor values for the filter to have a –3dB point at approximately 23kHz. The
fC of the circuit can be calculated using the following equation:
1
fC
2S R2 ˜ R3 ˜ C1˜ C2
4. The capacitors used for the filter should be COG/NP0 type ceramics. COG/NP0 type capacitors have a
lower voltage coefficient of capacitance, meaning that the capacitive value of the component is less
impacted by the voltage bias across the device. As the capacitors are key for performance of the filter,
other types of ceramic capacitors should be avoided in the signal path.
5. Thin-film resistors are recommended for the resistive elements in the filter. All resistors feature voltage
noise, which is well understood to be dependant on resistance and temperature, as shown in the first
equation following. But resistors also have a current noise, which is dependant on the voltage across
the resistor, frequency, and a constant, C, that is dependant on the material of which the resistor is
composed, as shown in the second equation that follows.
ST = 4kRT
where
• k is Boltzman's constant
• R is resistance
• T is temperature
SE = ( C × U2 ) / ƒ
where
• C is a constant derived from the resistor material
• U is the differential voltage across the resistor
• ƒ is the frequency

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Simulated Filter Response

The following graph shows the simulated filter response of the second-order active filter as well as the
response of a simple, first order RC filter with approximately the same fC. Note that the filter roll-off for the
first order filter is –20dB/decade, while the roll-off for the active filter is –40dB/decade.

SBAA322 – January 2019 Active-filtering circuit for audio DACs

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Simulated Noise Performance

The following graph shows the simulated total noise contribution of the circuit, with the exception of the
DAC itself. The was simulated using the OPA1678, which is specified as having 4.5nV/√Hz at 1kHz, and
the OPA1612, which is specified as having 1.1 nV/√Hz at 1kHz. The results show that the contribution of
the current noise in the system result in a greater total noise in the OPA1612 versus the OPA1678, even
though the OPA1612 has lower voltage noise.

Measured Output Spectrum

The output of the DAC was measured in the frequency domain with the second-order, active-filter as well
as the first-order RC filter. The output of the DAC was set to –60dB full-scale amplitude at 1kHz frequency
with a sample rate of 48kHz.
The graph shows that the out-of-band noise begins to increase at around 24kHz, which is expected given
the noise-shaping of the PCM1753-Q1. The second-order filter has approximately a 20dB lower output at
100kHz when compared to the RC filter.
-40
Second-Order, Low-Pass, Active Filter
First-Order, Passive, RC Filter
-60
Output (dBrA)

-80

-100

-120

-140
0 20000 40000 60000 80000 100000
Frequency (Hz) sbaa

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Design References
See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.
Source files for this circuit
For direct support from TI Engineers use the E2E community
e2e.ti.com
Design Featured Devices

Device Key Features Link Other Possible Devices

PCM1753-Q1, 24-bit resolution, 106dB typical SNR, 0.002% typical THD+N, http://www.ti.com/product/PCM1753-Q1 Audio DACs from Texas
PCM1754-Q1 single-ended, voltage-output, audio DAC Instruments
(1)

OPA1678 Low distortion, low noise, low input current, dual amplifier for http://www.ti.com/product/OPA1678 Audio Amplifiers Overview
audio applications

(1)
The PCM1753 and PCM1754 are similar parts, only differentiated by being SPI controlled versus HW controlled.

Other Links:
Learn more about using precision DACs at our Precision DAC Learning Center.
See Designing a Premium Audio System - TI Training for more information.
Learn about TI's audio DAC portfolio and find more technical content.

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 Analog Engineer's Circuit: Data
Converters
SBAA346 – January 2019

Auxiliary circuits for high-performance audio

Paul Frost

Design Goals

LDO Input Voltage LDO Output Voltage Voltage Supervisor Mute

Threshold (1)
12V 3.3V 7V
(1)
If the VBATTERY voltage is below this threshold, MUTE should be asserted.

Design Description
Power conditioning is a critical aspect in audio applications. Circuits commonly found in automotive head
units and premium aftermarket automotive audio systems will implement a hardware level mute that will
ensure that the audio digital-to-analog converters (DACs) and amplifiers are muted as supplies are
established. The supplies will also need some conditioning to reduce noise coupled into the audio DAC.
This circuit shows a low-noise, low-dropout (LDO) voltage regulator used to generate the +3.3-V supply for
an audio DAC. An added benefit of an LDO is that there is a wider input voltage range at which the LDO
can maintain the supply voltage. A voltage supervisor is used to notify the DAC when the source of the
LDO begins to collapse, so the audio DAC can soft-mute the output before its supply is removed. This will
reduce unwanted clicking or pops during shutdown and startup.
VDD
IN OUT
VBATTERY 10 …F R1
35.7k 10nF
12V
EN TPS7A8300 FB 22 …F
R2
11.5k VDD
2.2nF
NR GND 470
VOUTL
I2S
CNR/SS 10nF PCM5102A 470
VOUTR

XSMT 2.2nF

MCU MUTE
ENABLE VCC
R3
10k CCT 10nF
VSENSE 10k
SNS TPS389001 CT
R4 10nF 1nF
2k
MUTE
GND SNS_OUT

Design Notes
1. In this circuit the DAC mutes the output when soft-mute pin (XSMT) is held low, but not all DACs
feature active-low mute inputs. Some devices feature enable signals for other devices such as mute
switches and amplifiers require MUTE to be active high. In those cases, a simple N-channel MOSFET
can be added to the output to invert the signal.

SBAA346 – January 2019 Auxiliary circuits for high-performance audio

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VDD +3.3V
VCC
10k
TPS389001 10k MUTE

MUTE
SNS_OUT

2. During power-up events, the capacitor on the CT pin (CCT) of the supervisor allows additional delay
from when the SNS pin value rises above the threshold voltage and when the SNS_OUT goes high.
This can be used to the delay the deactivation of the MUTE output for the LDO to establish its voltage
(as it must charge the output capacitors). In addition, this can be useful if there are other devices that
need time to initialize before the DAC comes out of mute. The additional propagation delay can be
calculated using the following equation:
tPD CCT u 1.07s 25Ps
3. Brown-out events occur when the supplies of a device are partially reduced, but not low enough to
issue a full power-on reset (POR) within the device. For this reason, it is recommended to ensure a full
reset occurs during these events. The supervisor circuit accomplishes this as the XSMT acts as a reset
circuit for the audio DAC.
4. Most audio DACs operate in either a VCOM or VREF architecture. The VCOM architecture uses a
simple voltage divider from the supply to create the output amplitude reference. This is beneficial as it
ensures that there will not be output clipping from the DAC if the supply is not the nominal value, as
the output scales with the input voltage. The drawback of this architecture is the limited power-supply
rejection ratio (PSRR) for the power supply noise. While a capacitor on the VCOM pin of the audio
DAC will provide some filtering, it may still impact the output.
In a VREF configuration, an internal reference is generated by the audio DAC. This will result in better
PSRR performance for the system. The drawback of this design is that if the supply voltage does drop,
the output could clip.
Design Steps
1. Select an LDO regulator for its current output capability, voltage-input range, and output noise. At
minimum, the LDO sourcing the audio DAC must be able to supply the required current of the DAC. In
addition, if there are other devices on the same bus, such as amplifiers, then the quiescent current of
those devices must be taken into account. The LDO input voltage range must accommodate the main
supply source, which, in this circuit, is assumed to be a 12-V battery.
2. The feedback (FB) voltage must be calculated to provide the correct output voltage. In this circuit, the
resistors R1 and R2 can be calculated as the following shows.
§ V ·
R1 R2 ¨ DD 1¸
© VREF ¹
Given the design goal of +3.3V for VDD, and the VREF for this LDO is approximately 0.8V, use a R1 of
35.7kΩ and R2 of 11.5kΩ. In addition, note that the FB node has a current requirement and it is
recommended that the following equation is used for guidance when selecting R2.
VREF
! 5PA
R2
3. Select the voltage supervisor for the features desired in the system. In this circuit, the selected
supervisor has an enable input pin. This feature allows a user (or microcontroller) mute signal to be
used to override the supervisor output. In addition, some supervisors allow multiple supply rails to be
monitored, which is useful for the output amplifiers.
4. The sense voltage is calculated using the following equation.
R4
VSENSE VBATTERY u
R3 R 4
The SNS-OUT pin is pulled low when the SNS voltage is less than the reference voltage,
approximately 1.15V. Using 10kΩ for R3 and 2kΩ for R4, it is estimated that the device will be muted if
the VBATTERY supply drops below approximately 6.9V.

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The capacitor CNR/SS is used by the LDO to reduce noise and enables the LDO soft-start function.
5. The DAC is selected based on the needs of the application. Consider the required SNR, THD+N, and
supported I2S interface sample rates. While most audio DACs support rates ranging from 16kHz to
192kHz, not all support rates like 384kHz or 768kHz. Higher rates result in noise shaping that moves
the out-of-band noise further from the audible range, but not all audio sources can provide them.
6. The capacitors used for the audio filter should be COG, NP0 type ceramics. COG, NP0 type capacitors
have a lower voltage coefficient of capacitance, meaning that the capacitive value of the component is
less impacted by the voltage bias across the device. As the capacitors are key for performance of the
filter, other types of ceramic capacitors should be avoided in the signal path.
7. The capacitors used for the input and output of the LDO should have low equivalent series resistance
(ESR), such as X7R-, X5R-, and COG-type capacitors.
8. The resistors used for the LDO and voltage supervisor can be thick-film, though the accuracy of the
resistor dividers will impact the LDO output voltage and the supervisor threshold. For this reason, it
recommended that R1, R2, R3, and R4 have a maximum tolerance of 1%.
9. Thin-film resistors are recommended for the resistive elements in the DAC output filter.
Power-Up Mute Transient
The following simulation shows the power-up transient of the circuit. It can be seen that MUTE output is
not released until the VBAT input reaches approximately 6.9V.

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Power-Down Mute Transient

The following simulation shows that the MUTE output is asserted to low when the VBAT input drops below
6.9V.

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Brown-Out Mute Transient

The following simulation demonstrates that the DAC will be in a mute condition before the VDD supply of
the DAC is compromised by the brown-out event. When the VBAT voltage drops below approximately
6.9V, the MUTE signal is asserted low. Once the VBAT recovers, the MUTE signal de-asserted.

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Design References
See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.
Download the companion simulation files for this circuit.
For direct support from TI Engineers use the E2E community
E2E Community
Design Featured Devices

Device Key Features Link Other Possible Devices

PCM5102A 2VRMS DirectPath™, 112-dB audio stereo DAC with 32- http://www.ti.com/product/PCM5102A Audio DACs from Texas
bit, 384-kHz PCM interface Instruments
TPS7A8300 2-A, 6-µVRMS, low-noise, LDO voltage regulator http://www.ti.com/product/TPS7A8300 LDO Regulator Overview
TPS389001 Low quiescent current, 1% accurate voltage supervisor with http://www.ti.com/product/TPS3890 Power Management Overview
programmable delay
CSD13380F3 12-V N-channel FemtoFET™ MOSFET http://www.ti.com/product/CSD13380F3 MOSFETs from Texas
Instruments

Other Links:
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Learn about TI's audio DAC portfolio and find more technical content.

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 Analog Engineer's Circuit: Data
Converters
SBAA333 – January 2019

Current-to-voltage converter circuit for audio DACs

Paul Frost

Design Goals

DAC IOUT Amplitude DAC IOUT Common Mode VOUT Amplitude

Current
7.8 mAP-P –6.2mA 2.1VRMS

Design Description
Many high-performance audio digital-to-analog converters (DACs) feature a current output that must be
converted into a voltage output for use with audio amplifiers. In premium automotive audio applications,
for example, it is critical to ensure the DAC signal-to-noise ratio (SNR) and total harmonic distortion plus
noise (THD+N) performance is not compromised by the current-to-voltage (I-V) output stage.
R1 820

C1 4.7nF

PCM1794A-Q1 R3 240

-10V
OUTP C2 10nF
± R2 511
+
+ OPA1612
+5V -5V
DSM ±
+
+5V + OPA1612
+ OPA1612 511
+ +5V
OUTN
±
-10V
10nF 240

4.7nF

820

Design Notes
1. The first stage of the circuit converts the current output to a voltage output by providing a virtual
ground potential to the OUTP and OUTN nodes of the DAC. The current flowing from the DAC then
creates a voltage across the resistor, R1, in the feedback loop. Note that current-output audio DACs
have a common-mode current that creates an offset to ensure that the DAC is always sourcing current.
This common-mode current also results in the output of the first stage always being a negative value.
The supplies of the amplifiers of the circuit are not required to be symmetrical.
2. The second stage of the circuit is a differential amplifier that converts the differential voltage of the first
stage into a single-ended output voltage.

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Design Steps
1. The DAC is selected based on the needs of the application. Consider the required SNR, THD+N, and
supported I2S interface sample rates. While most audio DACs support rates ranging from 16kHz to
192kHz, not all support rates like 384kHz or 768kHz. Higher rates result in noise shaping that moves
the out-of-band noise further from the audible range, but not all audio sources can provide them. Also
note that not all current-output audio DACs have the same amplitude and common-mode current.
2. Select the amplifier based on its noise and THD performance. Ideally, these amplifiers should not gate
the SNR performance of the DAC. A JFET or bipolar-input amplifier is recommended for its low
voltage-noise. The higher current-noise is not an issue as the resistance values of the circuit are low.
3. The gain of the circuit is calculated with the following equation. Using R1 = 820Ω, R2 = 511Ω, and R3
= 240Ω, the output current will be approximately 6VP-P or 2.1VRMS. For this circuit, superior noise
performance is achieved by having the first stage have a large gain, and the second stage actually
attenuate the signal.
§ R3 ·
VOUT (IIN ) IIN u R1u ¨ ¸
© R2 ¹
4. The cutoff frequency (fC) of the first stage can be calculated with the following equation:
1
fC FIRSTSTAGE
2 u S u R1u C1
The fC of the second stage is calculated with the following equation:
1
fC SECONDSTAGE
2 u S u R3 u C2
Using C1 = 4.7nF and C2 = 10nF, the fC of the first stage is approximately 44.2kHz and the fC of the
second stage is approximately 66.3kHz.
5. The capacitors used for the filter should be COG/NP0 type ceramics. COG/NP0 type capacitors have a
lower voltage coefficient of capacitance, meaning that the capacitive value of the component is less
impacted by the voltage bias across the device. As the capacitors are key for performance of the filter,
other types of ceramic capacitors should be avoided in the signal path.
6. Thin-film resistors are recommended for the resistive elements in the circuits. All resistors feature
voltage noise, which is well understood to be dependent on resistance and temperature, as shown in
the first equation that follows. But resistors also have a current-noise, which is dependent on the
voltage across the resistor, frequency, and a constant, C, that is dependant on the material of which
the resistor is composed, as shown in the second following equation:
ST = 4kRT,
where
• k is Boltzman's constant
• R is resistance
• T is temperature
SE = ( C × U2 ) / ƒ
where
• C is a constant derived from the resistor material
• U is the differential voltage across the resistor
• ƒ is the frequency

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DC Transfer Characteristics
The simulation shows that the 7.8-mAP-P differential input current results in an approximately 6VP-P output,
or 2.1VRMS.

Filter Characteristics
The filters created by the two amplifier stages have a –3-dB corner frequency of approximately 32.1kHz.
This will attenuate out-of-band noise from the output, while not affecting the audible range (20Hz to
22kHz).

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Noise Simulation
The following simulation shows the benefit of having the majority of the gain of the circuit in the first stage.
The two curves were generated by the same circuit with different resistor values, but resulting in the same
total gain. The green line has a higher gain in the first stage, but lower total noise.

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Design References
See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.
See the HiFi Audio circuit design application report.
Download the companion simulation files for this circuit.
For direct support from TI Engineers use the E2E community
E2E Community
Design Featured Devices

Device Key Features Link Other Possible Devices

PCM1794A-Q1 24-bit, 192-kHz sampling, advanced segment, audio http://www.ti.com/product/PCM1794A-Q1 Audio DACs from Texas Instruments
stereo digital-to-analog converter
OPA1612 Ultra-low noise, ultra-low distortion, high-performance, http://www.ti.com/product/OPA1612 Audio Amplifiers from Texas
bipolar-input audio operational amplifier Instruments

Other Links:
Learn more about how to use precision DACs at our Precision DAC Learning Center.
Learn about TI's audio DAC portfolio and find more technical content.

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 Analog Engineer's Circuit: Data
Converters
SBAA343 – January 2019

Circuit for offset adjustment of input signals

using precision DAC for measurement equipment

Uttama Kumar Sahu

Design Goals
Power Supply DAC Output Voltage Output Current Output
VCC: 24V, VSS: –5V, VDD: 5V 0V to 2.5V 0V to 5V 0A to 10A

Design Description
Signal-measurement equipment like Oscilloscope (DSO) and Data aquisition (DAQ) must manage input
signals that are not within the input range of the measurement analog-to-digital converter (ADC). To bring
the unknown input signal in the measurement range of the ADC, the first operation needed is offset
control. A programmable offset control circuit providing both positive and negative offset, performs this
function. This circuit uses a precision digital-to-analog converter (DAC), followed by a unipolar-to-bipolar
conversion circuit using an op amp. The output of this circuit is fed to a summing amplifier that adds this
DC output to the input signal.
R R

±
± R VOUT
+
V-SIGNAL +

RG1 CFB

RG2
VREF
± R

DAC +
V-OFFSET
R
VDAC

Design Notes
1. Choose a DAC with the required resolution and output range
2. Choose an op amp with low offset and low drift to minimize error. Thermal noise may be an additional
requirement in some applications
3. Choose RG1, RG2, and RFB such that the desired output offset is met
4. Choose the compensation capacitor CFB such that it is larger than the input capacitance of the op-amp
inputs

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Design Steps
1. Select the DAC80504 device: a 16-bit, 4-channel buffered voltage output DAC with 2.5-V internal
reference. Devices with an external reference option or devices with accessible internal references are
desirable in this application as the reference is used to create an offset. The DAC selection in this
design should primarily be based on DC error contributions, typically described by offset-error, gain-
error, and integrated non-linearity (INL) error.
2. Select an op amp such as the OPA227 operational amplifier that combines low noise and wide
bandwidth with high precision to make it the ideal choice for applications requiring both AC and
precision DC performance. Amplifier input offset voltage (VOS) is a key consideration for this design.
VOS of an operational amplifier is a typical data sheet specification, but in-circuit performance is also
impacted by drift overtemperature, the common-mode rejection ratio (CMRR), and power supply
rejection ratio (PSRR); therefore, give consideration to these parameters as well.
3. The DC transfer function of the offset voltage is given by:
æ R FB R FB ö æ R FB ö
V OFFSET = V DAC ç 1 + + ÷ - V REF ç ÷
ç R G2 R G1 ø ÷ ç R G2 ÷
è è ø
• First, using the previous transfer function, consider the negative full-scale output case when VDAC is
equal to 0V, VREF is equal to 2.5V, and VOFFSET is equal to –5V. This case is used to calculate the
ratio of RFB to RG2 and is shown in the following equation:
R FB
-5 V = - (2.5V )
R G2
That gives, RFB = 2 × RG2.
• Second, consider the positive full-scale output case when VDAC is equal to 2.5 V, VREF is equal to
2.5V, and VOUT is equal to 5V. This case is used to calculate the ratio of RFB to RG1 and is shown in
the following equation:
æ R FB R FB ö æ R FB ö
5V = ç 1 + + ÷ (2.5 V ) - ç ÷ (2.5 V )
ç R G2 R G1 ÷ø ç R G2 ÷
è è ø
This means, RG1 = RFB.
• Finally, select a value of RG2 to calculate the ideal values of RFB and RG1. The key considerations for
seeding the value of RG2 should be the drive strength of the reference source as well as choosing
small resistor values to minimize noise contributed by the resistor network. For this design, RG2 was
chosen to be 8kΩ, which will limit the peak current draw from the reference source to approximately
312µA, under nominal conditions. The 312µA is well within the 5-mA limit of the DAC80504 device.
By putting the value of RG2 in previous equations, RG1 and RFB is calculated as RG1 = RFB = 16kΩ.
4. In general, the compensation capacitor CFB is not set by fixed equations, but rather by choosing values
while observing the output small-signal step response. Through simulation in this example, select CFB ≥
22pF.

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DC Transfer Characteristics

T 6.00

5V
V-OFFSET
-5V

-6.00
10.00

V-OUT -5.33V 8V

-10.00
0.00 1.25 2.50
V-DAC (V)

Small-Signal Step Response Without Compensation

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Small-Signal Step Response With CFB = 22pF

Design Featured Devices and Alternative Parts

Device Key Features Link

DAC80504 4-channel, true 16-bit, SPI, voltage-output DAC with precision internal reference http://www.ti.com/product/DAC80504
DAC80508 8-channel, true 16-bit, SPI, voltage-output DAC with precision internal reference http://www.ti.com/product/DAC80508
DAC80004 Ultra-small, true 16-bit quad voltage output DAC with 1LSB INL/DNL http://www.ti.com/product/DAC80004
DAC8560 16-bit, single-channel, low-power, ultra-low glitch, voltage output DAC with 2.5V, http://www.ti.com/product/DAC8560
2ppm/°C reference
OPA227 High precision, low noise operational amplifiers http://www.ti.com/product/OPA227
OPA188 Precision, low-noise, rail-to-rail output, 36-V zero-drift operational amplifier http://www.ti.com/product/OPA188

Design References
See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.
Link to Key Files
TINA source files – http://www.ti.com/lit/zip/sbam418.
For direct support from TI Engineers use the E2E community:
e2e.ti.com

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 Analog Engineer's Circuit: Data
Converters
SBAA332 – January 2019

DAC force and sense reference drive circuit

Paul Frost

Design Goals

DAC Output Range DAC VREFH Input Voltage DAC VREFL Input Voltage
–5V to 5V 5V –5V

Design Description
High-precision digital-to-analog converters (DACs) used in applications like magnetic resonance imaging
(MRI) machines and arbitrary waveform generators (AWG) generally require a high-precision voltage
reference. A cause of common issues with these systems is the undesired series resistance on the
reference input of the DAC. The resistance will induce a DAC input-code dependent voltage potential
across them as the input current of the R-2R ladder changes based on the code. The end result is that the
reference voltage will seem to change based on the DAC code, which will cause a bow shaped integrated
non-linearity error curve.
To remedy this issue, high-precision DACs often feature a reference force and sense pin for each of the
reference inputs (VREFH and VREFL). While these pins are essentially just two parallel connections to the
reference input nodes of the R-2R ladder, each with their own series resistance, the addition of an
external unity-gain reference buffer will allow the voltage at the node to be compensated by the amplifier.
The small bias current flowing into the op amp inverting input will generate a minimum voltage across the
series resistance of the sense input, while output of the op amp can source the current required by the R-
2R ladder.

VSS
100nF
±
+5.5V OPA828
+ 100nF
VIN OUT-S
10 …F
VREF+ VCC
EN OUT-F VSS
REF6050 RESR VCC VREFH-F VREFH-S 100nF
SS GND-S 80m VCC
R1 ± VDAC
CL 2k 100nF
FILT GND-F R2 GND DAC8871 + 100nF
CFILT 47…F
2k OPA828
100nF VCC
10…F VSS
VSS VREFL-F VREFL-S
VSS
100nF VCC
100nF
± VREF-
OPA211 +
+ 100nF OPA828
± 100nF
VCC
VSS

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Design Notes
1. The reference selected only has a positive 5-V output, necessitating an inverting amplifier to generate
the VREF- value. The resistors R1 and R2 also create a current path from the reference output to a –5V
potential. This current is provided by the voltage reference. The current can be limited by increasing
the values of R1 and R2, at the expense of additional noise being created by the circuit. The current
noise of the amplifier and the thermal noise of the resistors contribute to the total noise of the circuit.
2. The noise of the reference is reduced by adding CFILT, which filters the noise generated by the bandgap
of the internal reference. The output of the reference also requires a capacitor (CL) with a minimum
equivalent series resistance (ESR). It is possible to create this resistance on the PCB with an extended
trace, shown as RESR.
3. The noise of the DAC is primarily created by the thermal noise of the resistor ladder. Thermal noise is
calculated using the following the equation, where Kb is Boltzman's constant, T is the temperature in
kelvin, R is the resistance of the ladder, and F is the frequency range.
VNOISE 4 ˜ K b ˜ T ˜ R ˜ 'F
The DAC8871 typical output impedance of approximately 6.25kΩ, and assuming room temperature
operation, has a thermal noise that can be calculated as shown in the following equation:
23
VNOISE 4 ˜ 1.38 ˜ 10 J / K ˜ 300K ˜ 6.25k: ˜ 1Hz
10.17nV / Hz
Design Steps
1. The DAC is selected for its resolution, accuracy, and noise performance. The resolution may be
dependant on the application, but it is common to see 16-bit or greater resolution in this circuit. Errors
in the output of the DAC are considered non-linearity errors. Non-linearity errors are expressed as
integrated non-linearity error (INL) and differential non-linearity error (DNL). Assuming an ideal
reference on the input of the DAC, the INL and DNL errors of the system will be caused by resistor
inaccuracies of the R-2R ladder.
2. The reference is selected based on the accuracy, thermal drift, and noise requirements of the
application. The output voltage accuracy is generally specified as a percentage. The thermal drift is
specified in units of ppm/°C (parts-per-million). The noise of the circuit has two specification: the low-
frequency noise, usually specified in VPEAK-PEAK over a limited frequency domain (0.1Hz to 10Hz), and
the total integrated noise, specified in VRMS.
3. The op amp used to invert the reference voltage should be selected on its noise performance. The
amplifier will contribute noise to the system in two ways, its voltage noise and current noise. The
contribution from the voltage-noise can be minimized by selecting a bipolar input amplifier, which
generally have a low voltage noise. Bipolar input amplifiers also have higher current noise than CMOS
input amplifiers, but the current noise is converted to voltage noise via the resistors R1 and R2 of the
circuit. By minimizing the resistance of those components, the current noise contribution of the
amplifier can be minimized.
4. The amplifiers selected to drive the force and sense inputs of the DAC should be selected for their fast
settling and bandwidth. When the DAC is updated with a new input code, the switches in the R-2R
resistor ladder will cause a sudden change in current that is being demanded from the reference
inputs. This results in a transient on the reference inputs that will also be conveyed on the DAC output.
If the reference buffer amplifiers can settle quickly, the error on the output will be minimized.
In addition, the voltage noise of these amplifiers will contribute to the total noise of the system. For this
reason a bipolar or JFET input amplifier should be selected.
5. Select an output buffer if the circuit is desired to drive a load. The DAC8871 is an un-buffered device,
meaning that the output of the DAC is a node on the resistor ladder. This amplifier is selected based
on the requirements of the load: such as current output capability, capacitive load stability, slew-rate,
and voltage range.
6. The capacitors CFILT and CL are low-ESR, ceramic type capacitors. The voltage rating of the capacitors
needs to be compliant with the 5-V reference output.

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Reference Buffer Load Transient

The reference buffer must be able to quickly source transient currents necessary for the R-2R ladder
when the DAC changes codes. Given the architecture of the DAC8871, the maximum transient current
would occur when the DAC transitions from zero- or full-scale code to the mid-scale. This transient is
simulated with a current source between the VREFH and VREFL inputs. The following simulation shows the
differential reference voltage during the current transient, simulated with the OPA828 and OPA227. This
shows that the reference error magnitude and duration is reduced with the OPA828.

Reference Buffer Total Noise

The total noise generated by the circuit is shown in the following simulation. The reference, inverting
amplifier, and reference buffers each contribute to the noise. Note that the VREF- input has greater noise
due to the contribution of the inverting amplifier and the discrete resistors in its feedback network.

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Design References
See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.
Download the companion simulation files for this circuit.
Design Featured Devices

Device Key Features Link Other Possible Devices

DAC8871 16-bit, single-channel, serial-interface, high-voltage, bipolar-output http://www.ti.com/product/DAC8871 Precision DACs from Texas
DAC Instruments
OPA828 Low-offset, low-drift, low-noise, 45-MHz bandwidth, JFET-input http://www.ti.com/product/OPA828 Precision Amplifier Overview
operational amplifier
OPA221 Low-power, 1.1nV/√Hz noise, high-performance operation amplifier http://www.ti.com/product/OPA211 Precision Amplifier Overview
REF6050 Low-noise, high-precision, 5-V output voltage reference http://www.ti.com/product/REF6050 Series Voltage References
from Texas Instruments

Other Links
Learn more about how to design with precision DACs with our Precision DAC Learning Center.
Learn about TI's precision DAC portfolio and find more technical content.

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 Analog Engineer's Circuit: Data
Converters
SBAA341 – January 2019

Power-supply margining circuit for LDOs using a

precision DAC

Uttama Kumar Sahu

Design Goals
Power Supply (VDD) Nominal Output Margin High Margin Low
5V 3.3V 3.3V + 10% 3.3V – 10%

Design Description
A power-supply margining circuit is used for tuning the output of a power converter. This is done either to
adjust the offset and drift of the power supply output or to program a desired value at the output.
Adjustable power supplies like Low-Dropout Regulators (LDOs) and DC/DC converters provide a feedback
or adjust input that is used to set the desired output. A precision voltage output digital-to-analog converter
(DAC) is suitable for controlling the power supply output linearly. The following image shows an example
power-supply margining circuit. Typical applications of power-supply margining is in Test and
Measurement, Communications Equipment, and Power Delivery.

VIN IN OUT VOUT

LDO R1 C1
R3
VFB
ADJ DAC
GND
R2 RPUL L-DOWN
GND
GND
GND

Design Notes
1. Choose a DAC with the required resolution, pulldown resistor value, and output range.
2. Derive the relationship of the DAC output to VOUT.
3. Choose R1 based on typical current through the feedback circuit.
4. Calculate the start-up or nominal value of VDAC considering the power-down and power-up conditions of
the DAC.
5. Select R2, and R3 such that the desired start-up output voltage is met along with the DAC output
voltage range for the desired tuning range.
6. Calculate the margin low and margin high DAC outputs.
7. Choose a compensation capacitor to achieve the desired step response.

SBAA341 – January 2019 Power-supply margining circuit for

Submit Documentation Feedback 256 LDOs using a precision DAC
Copyright © 2019, Texas Instruments Incorporated
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Design Steps
1. Select the LDO TPS79501 device for the calculations. The DAC53608 device is an ultra-low cost, 10-
bit, 8-channel, unipolar output DAC suitable for such applications
2. The output voltage of the power supply is given by:
VOUT VREF I1R1 VREF I2 I3 R1

where
• I1 is the current flowing through R1
• I2 is the current flowing through R2
• I3 is the current flowing through R3
DACs in this application typically include power-down mode, which includes an internal pulldown
resistor at the voltage output. Hence, replacing the values of the currents in the previous equation
yields:
• When the DAC is in Power Down mode:
§§ V · § VREF ··
VOUT VREF ¨ ¨ REF ¸ ¨ ¸ ¸¸ R1
¨ R
© © 2 ¹ © R3 RPULL-DOWN ¹ ¹
• When the DAC output is powered-up:
§ § VREF · § VREF VDAC · ·
VOUT VREF ¨¨ ¨ ¸ ¨ ¸ ¸¸ R1
© © R2 ¹ © R3 ¹¹
For DAC53608, RPULL-DOWN is 10kΩ. For the LDO part number TPS79501, the value of VREF is 1.225V.
3. R1 can be calculated by the following method.
The current through the FB pin of TPS79501 is 1µA. To make this current negligible, I1 should be >>
IFB. Choose I1 to be 50µA. Calculate R1 as follows:
VOUT VREF
R1 41.5 k:
I1
The nominal value of I1 can be given by:
• When the DAC is in Power Down mode
§ VREF · § VREF ·
I1 Nom ¨ ¸ ¨ ¸
© R 2 ¹ © R3 10 k: ¹
• When the DAC output is powered-up
§ VREF · § VREF VDAC ·
I1 Nom ¨ ¸ ¨ ¸
© R2 ¹ © R3 ¹
The values of I1 at Margin High and Margin Low outputs are given by:
VOUT-HIGH VREF
I1-HIGH 57.95 PA
R1
VOUT-LOW VREF
I1-LOW 42.05 PA
R1
I1-HIGH I1-Nom I1-Nom I1-LOW 7.65 PA
4. The nominal or startup value of VDAC can be calculated using the following method:
To make sure the 10-kΩ resistor does not impact when the DAC is transitioning from power-down to
power-up, the power-up value for the DAC voltage can be calculated with:
VREF VREF VDAC
R3 10 k: R3
The previous equation can be further simplified to:
§ 10 k: ·
VDAC VREF ¨ ¸
© R3 10 k: ¹

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5. The values of R2 and R3 can be calculated as follows:

If the power-up or nominal value of VDAC is kept at one-third of VREF, that is, 408.3mV, then R3 will be 2
× 10kΩ = 20kΩ. R2 can be calculated as:
VREF VREF
50 P:
R2 R3 10 k:
Replacing the value of R3, R2 can be calculated to equal 133kΩ.
6. Subtracting the Margin High and Nominal values of I1 and the corresponding equations, we get
VREF VDAC VREF
7.95 PA
R3 R3 10 k:
So, the Margin High value of VDAC will be 249mV and similarly, the Margin Low value can be calculated
as 567mV from the following equation:
VREF VREF VDAC
7.95 PA
R3 10 k: R3
7. The step response of this circuit without a compensation capacitor has some overshoot and ringing as
shown in the following curves. This kind of transient response can cause errors at the load circuits. To
minimize this, use a compensation capacitor C1. The value of this capacitance is usually obtained
through simulation. A comparative output shows the waveforms with a compensation capacitor of
22pF.

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DC Transfer Characteristics

T 5.00

VDAC: 249mV
VOUT: 3.63V

VOUT (V)
VDAC: 567mV
VOUT: 2.97V

VDAC: 408.3mV
VOUT: 3.3V

2.00
0.00 500.00m 1.00
VDAC (V)

Small Signal Step Response Without Compensation

Small-Signal Step Response With C1= 22pF

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Design Featured Devices and Alternative Parts

Device Key Features Link

DAC53608 8-channel 10-bit, I2C interface, buffered-voltage-output DAC http://www.ti.com/product/DAC53608
DAC60508 8-channel, true 12-bit, SPI, voltage-output DAC with precision internal reference http://www.ti.com/product/DAC60508
DAC60501 12-bit, 1-LSB INL, DAC with precision internal reference http://www.ti.com/product/DAC60501
DAC8831 16-bit, ultra-low power, voltage output DAC http://www.ti.com/product/DAC8831
TPS79501-Q1 Automotive catalog single output LDO, 500mA, adj.(1.2 to 5.5V), low-noise, high PSRR http://www.ti.com/product/TPS79501-Q1

Design References
See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.
Link to Key Files
TINA source files – http://www.ti.com/lit/zip/sbam415.
For direct support from TI Engineers use the E2E community
e2e.ti.com

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 Analog Engineer's Circuit: Data
Converters
SBAA342 – January 2019

Power-supply margining circuit for SMPS using

a precision DAC

Uttama Kumar Sahu

Design Goals

Power Supply (DAC Nominal Output Margin High Margin Low

VDD)
5V 5V 5V + 10% 5V – 10%

Design Description
A power-supply margining circuit is used for tuning the output of a power converter. This is done either to
adjust the offset and drift of the power-supply output or to program a desired value at the output.
Adjustable power supplies like LDOs and DC/DC converters provide a feedback or adjust input that is
used to set the desired output. A precision voltage output DAC is suitable for controlling the power-supply
output linearly. An example power-supply margining circuit is shown in the following figure. Typical
applications of power-supply margining is in Test and Measurement, Communications Equipment, and
General Purpose Power Supply Modules.
L
VIN IN PH VOUT
BOO T
SMPS R1 C1
CL
CB R3
VFB
SENSE DAC
GND
R2 RPUL L-DOWN
GND
GND GND GND
GND

Design Notes
1. Choose a DAC with required resolution, pulldown resistor value, and output range
2. Derive the relationship of the DAC output to VOUT
3. Choose R1 based on typical current through the feedback circuit
4. Calculate the start-up or nominal value of VDAC, considering the power-down and power-up conditions
of the DAC
5. Select R2, and R3 such that the desired start-up output voltage is met along with the DAC output
voltage range for the desired tuning range
6. Calculate the margin low and margin high DAC outputs
7. Choose a compensation capacitor to get the desired step response

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Design Steps
1. Select the switching DC/DC converter TPS5450 for the calculations. The DAC53608 device is an ultra-
low cost, 10-bit, 8-channel unipolar output DAC suitable for such applications
2. The output voltage of the power supply is given by
V OUT V REF I1 R 1 V REF I2 I3 R1

where
• I1 is the current flowing through R1
• I2 is the current flowing through R2
• I3 is the current flowing through R3
DACs in this application typically include power-down mode, which includes an internal pulldown
resistor at the voltage output. Hence, replacing the values of the currents in the previous equation
yields:
• When DAC is in power-down mode:
æ æ V REF ö æ V REF öö
V OUT = V REF + ç ç ÷+ç ÷÷ R1
çç R 2 ÷ ç R 3 + R PULLDOW N ÷÷
èè ø è øø
• When DAC output is powered-up:
§ § V REF · § V REF V DAC ··
V OUT V REF ¨ ¨ ¸ ¨ ¸¸ R1
¨¨ R 2 ¸ ¨ R3 ¸¸
©© ¹ © ¹¹
For DAC53608, RPULLDOWN is 10kΩ. For the LDO device TPS5450, the value of VREF is 1.221V.
3. R1 can be calculated with the following method:
The current through the FB pin of the TPS5450 device is negligible. Select I1 to be 50µA. So, R1 is
calculated as follows:
V OUT V REF
R1 75.6 k:
I1
The nominal value of I1 is given by:
• When DAC is in power-down mode:
§ V REF · § V REF ·
I1 ¨ ¸ ¨ ¸
Nom ¨ R2 ¸ ¨ R 3 10 k: ¸
© ¹ © ¹
• When DAC output is powered-up:
§ V REF · § V REF V DAC ·
I1 ¨ ¸ ¨ ¸
Nom ¨ R2 ¸ ¨ R3 ¸
© ¹ © ¹
The values of I1 at margin high and margin low outputs are given by:
VOUT HIGH V REF
I 1 HIGH 56.6 $
R1
VOUT LOW V REF
I1 LOW 43.4
R1
I1 HIGH I1 Nom I1 Nom I1 LOW 6.6 $
4. The nominal, or startup value of VDAC is calculated by the following method:
To make sure the 10-kΩ resistor does not impact when the DAC is transitioning from power-down to
power-up, the power-up value for the DAC voltage is calculated with:
V REF V REF V DAC
R3 10 k: R3

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The previous equation is further simplified to:

§ 10 k: ·
V DAC V REF ¨ ¸
¨ R 3 10 k: ¸
© ¹
5. The values of R2 and R3 are calculated as follows:
If the power-up or nominal value of VDAC is kept at 1/3 of VREF, that is, 407mV, then R3 is 2 × 10kΩ =
20kΩ. And, R2 can be calculated as:
V REF V REF
50 $
R2 R 3 10k:
Replacing the value of R3, calculate R2 = 131.3kΩ.
6. Subtracting the margin high and nominal values of I1 and the corresponding equations yields:
V REF V DAC V REF
6.6 $
R3 R 3 10 k:
The margin high value of VDAC is 275mV and similarly, the margin low value is calculated as 539mV
using the following equation:
V REF V REF V DAC
6.6 $
R 3 10 k: R3
7. The step response of this circuit without a compensation capacitor causes the inductor current to reach
its limit as shown in the following figure. This kind of surge can take the inductor into saturation. To
minimize the surge, a compensation capacitor C1 is used as the circuit diagram shows. The value of
this capacitance is usually obtained through simulation. A comparative output shows the waveforms
with a compensation capacitor of 10nF.
Output With DAC in Power Down Mode

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Small-Signal Step Response Without Compensation

Small-Signal Step Response With C1 = 10nF

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Design Featured Devices and Alternative Parts

Device Key Features Link

DAC53608 8-channel 10-bit, I2C interface, buffered-voltage-output digital-to-analog converter (DAC) http://www.ti.com/product/DAC53608
DAC60508 8-channel, true 12-bit, SPI, voltage-output DAC With precision internal reference http://www.ti.com/product/DAC60508
DAC60501 12-bit, 1-LSB INL, digital-to-analog converter (DAC) with precision internal reference http://www.ti.com/product/DAC60501
DAC8831 16-bit, ultra-low power, voltage output digital to analog converter http://www.ti.com/product/DAC8831
TPS5450 5.5-V to 36-V input, 5-A, 500-kHz step-down converter http://www.ti.com/product/TPS5450

Design References
See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.
Link to Key Files
TINA source files – http://www.ti.com/lit/zip/sbam416.
For direct support from TI Engineers use the E2E community
e2e.ti.com

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 Analog Engineer's Circuit: Data
Converters
SLAA866 – December 2018

Loop-powered 4- to 20-mA transmitter circuit

Garrett Satterfield

Design Goals

Loop Supply Voltage DAC Output Voltage Output Current Error

12V–36V 0V–3V 4mA–20mA <1% FSR

Design Description
The loop powered current transmitter regulates the current in series loop consisting of the power supply,
transmitter, and load resistance. The active circuitry in the transmitter derives power from the loop current,
meaning the current consumption of all devices must be less than the zero-scale current, which can be as
low as 3.5mA in some applications. A regulator steps down the loop voltage to supply the DAC, op amp
and additional circuitry. The op amp biases the transistor to regulate the current flowing from Loop+ to
Loop-. The circuit is commonly used in 2-wire field sensor-transmitters such as Flow Transmitters, Level
Transmitters, Pressure Transmitters, and Temperature Transmitters.

VREG
LDO Loop+

R2122.15k

R1
DAC ++
30.542k A1
- OPA317
DAC7311

R5 20

4.32k R3 R4 26.7

Loop-

Design Notes
1. Select a single channel DAC with the required resolution and accuracy for the application. Use an op
amp with low offset and low drift to minimize error.
2. Select a low power DAC, op amp, and voltage regulator to ensure a total sensor-transmitter quiescent
current of less than 4mA.
3. Minimize current flow through R1, R2, and R3 by selecting a large ratio of R3/R4 to minimize thermal
drift of the resistors.
4. Use precision low drift resistors for R1-R4, R7-R8 to minimize error.
5. Use a voltage regulator with a wide input voltage range and low dropout voltage to allow for a wide
range of loop supply voltages.

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Design Steps
The output current transfer function is:

§ VDAC VREG ·§ R3 ·
IOUT ¨ ¸¨ 1
© R1 R2 ¹ © R4 ¸¹
1. Select a large ratio of R3/R4:

R3 4.32k:
R4 26.7:
2. Calculate R2 based on the zero-scale current (4mA), regulator voltage, and gain ratio (R3/R4).

VREG § R3 · 3V § 4.32k: ·
R2 1¸ 1¸ 122.10k:
IOUT,ZS © R4 ¹ 4mA ¨© 26.7:
¨
¹
3. Calculate R1 to set the full-scale current based on the full-scale DAC voltage and current span of
16mA.

VDAC,FS § R3 · 3V § 4.32k: ·
R1 ¨ 1¸ ¨ 1¸ 30.524k:
IOUT,SPAN © R4 ¹ 16mA © 26.7: ¹
4. Calculate the zero-scale output current based on the chosen resistance values.

VREG § R3 · 3V § 4.32k: ·
IOUT,ZS ¨ 1¸ ¨ 1¸ 3.9983mA
R2 © R4 ¹ 122.15k: © 26.7: ¹
5. Calculate the full-scale current based on the chosen resistor values.

§ VDAC VREG ·§ R3 · § 3V 3V ·§ 4.32k: ·

IOUT,FS ¨ ¸¨ 1 1¸ 19.9891mA
© R1 R2 ¹ © R4 ¹¸ ¨ 30.542k:
© 122.15k: ¸¨
¹© 26.7: ¹

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DC Transfer Characteristic

T 19.99m
19.9922mA

IOUT

4.0014mA

4.00m

0.00 1.00 2.00 3.00

Input voltage (V)

Small Signal Step Response

T 9.87m

Loop Current

9.33m
1.10

Input Voltage

1.00

0.00 5.00u 10.00u 15.00u 20.00u

Time (s)

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Devices

Device Key Features Link Other Possible Devices

DACs
DAC7311 12-bit resolution, single channel, ultra-low power, 1 LSB INL, SPI, 2V http://www.ti.com/product/DAC7311 http://www.ti.com/dacs
to 5.5V supply
DAC8560 16-bit resolution, single channel, internal reference, low power, 4 LSB http://www.ti.com/product/DAC8411 http://www.ti.com/dacs
INL, SPI, 2V to 5.5V supply
DAC8830 16-bit resolution, single channel, ultra-low power, unbuffered output, 1 http://www.ti.com/product/DAC8830 http://www.ti.com/dacs
LSB INL, SPI, 2.7V to 5.5V supply
DAC161S997 16-bit, 4-20mA current output, 100uA supply current, SPI, 2.7V to http://www.ti.com/product/DAC161S9 http://www.ti.com/dacs
3.3V supply 97
Amplifiers
TLV9001 Low-Power, 0.4mV Offset, Rail-to-Rail I/O, 1.8V to 5.5V supply http://www.ti.com/product/TLV9001 http://www.ti.com/opamps
OPA317 Zero-Drift, Low-Offset, Rail-to-Rail I/O, 35uA supply current max, 2.5V http://www.ti.com/product/OPA317 http://www.ti.com/opamps
to 5.5V supply
OPA333 microPower, Zero-Drift, Low Offset, Rail-to-Rail I/O, 1.8V to 5.5V http://www.ti.com/product/OPA333 http://www.ti.com/opamps
supply

Design References
See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.
Links to Key Files
TI Designs TIPD158, Low Cost Loop-Powered 4-20mA Transmitter EMC/EMI Tested Reference Design
TI Designs TIDA-00648, 4-20mA Current Loop Transmitter Reference Design
TI Designs TIDA-01504, Highly-Accurate, Loop-Powered, 4mA to 20mA Field Transmitter with HART
Modem Reference Design
Source Files for Loop-Powered 4- to 20-mA Transmitter – http://www.ti.com/lit/zip/slac782.
For direct support from TI Engineers use the E2E community:
e2e.ti.com
Other Links:
Precision DAC Learning Center
http://www.ti.com/data-converters/dac-circuit/precision/overview.html

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 Analog Engineer's Circuit: Data
Converters
SLAA868 – December 2018

Programmable low-side current sink circuit

Garrett Satterfield

Design Goals

VCC DAC Output Output Current Error Maximum Resistive

Voltage Load
5V 0mV – 510mV 0mA – 100mA <0.25% FSR 44.9Ω

Design Description
The programmable low-side current sink sets the current through a load based on the DAC output voltage.
The current is sensed through RSET and the op amp biases a transistor regulate the current through the
load. Components CF, RISO, and RFB provide compensation to ensure stability of the circuit.
Vcc

25 RLOAD

Vcc Q1
TLV9061
DAC + R ISO
A1

DAC60501

CF

R FB
5.1 R SET

Design Notes
1. Choose a DAC with low offset error, gain error, and drift. RRIO op amps should be used to reduce
error near the rails and maximize resistive load drive. An op amp with low offset voltage should be
chosen to minimize error.
2. Use a high-precision, low-drift resistor for RSET for accurate current regulation.
3. RSET should be minimized for efficiency and power dissipation. Most of the power dissipation should
occur through RLOAD
4. To drive large RLOAD, a separate high voltage supply may be used for driving the current to the load.

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Design Steps
1. Calculate the RSET value for the maximum DAC output voltage and desired maximum output current.
VDAC,max 510mV
RSET 5.1:
IOUT,max 100mA

2. The maximum resistive load is given by:

Vcc ISET,maxRSET 5V 100mA u 5.1
RLOAD,max 44.9:
ISET,max 100mA

3. Ensure Q1 is rated for the power dissipation at maximum current.

PDiss,Q2 Vcc u ISET,max ISET,max 2 u (RLOAD RSET ) 5V u 100mA 100mA 2 u (25: 5.1:) 0.2W

4. The output error can be approximated based on DAC TUE, amplifier offset voltage, resistor tolerance,
and reference initial accuracy using root sum square (RSS) analysis.
2
§ VOS,Amplifier · § 0.3mV ·
2
Output TUE(%FSR) 2
TUEDAC ¨ u 100 ¸ 2
TolR 2
AccuracyRe f 0.12 ¨ 510mV u 100 ¸ 0.12 0.12 0.183% FSR
¨ FSR ¸ SET
© ¹
© ¹

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DC Transfer Characteristic

T
0.10
100.0099mA
Current (A)

50.00m

152.83pA

0.00

0.00 200.00m 400.00m 600.00m

Input voltage (V)

Small Signal Step Response

T 50.98m

AM1

49.02m
260.00m

VG1

250.00m

0.00 10.00u 20.00u 30.00u 40.00u 50.00u

Time (s)

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AC Loop Gain Analysis

T 118.45
Gain (dB)

16.27

Phase margin: 63.77

at frequency (Hz): 6.30MEG

-85.90

116.07
Phase [deg]

-39.26

-194.58
10 100 1k 10k 100k 1MEG 10MEG 100MEG
Frequency (Hz)

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Devices

Device Key Features Link Other Possible Devices

DACs
DAC60501 12-bit resolution, 1LSB INL, Single-Channel, Voltage Output DAC with http://www.ti.com/product/DAC60501 http://www.ti.com/pdacs
5 ppm/°C Internal Reference
DAC80501 16-bit resolution, 1LSB INL, Single-Channel, Voltage Output DAC with http://www.ti.com/product/DAC80501 http://www.ti.com/pdacs
5 ppm/°C Internal Reference
DAC8830 16-bit resolution, single channel, ultra-low power, unbuffered output, 1 http://www.ti.com/product/DAC8830 http://www.ti.com/pdacs
LSB INL, SPI, 2.7-V to 5.5-V supply
Amplifiers
TLV9061 Ultra-Small, 0.3-mV Offset, Rail-to-Rail I/O, 1.8-V to 5.5-V supply http://www.ti.com/product/TLV9061 http://www.ti.com/opamps
OPA317 Zero-Drift, Low-Offset, Rail-to-Rail I/O, 35-µA supply current max, 2.5- http://www.ti.com/product/OPA317 http://www.ti.com/opamps
V to 5.5-V supply
OPA388 Precision, Zero-Drift, Zero-Crossover, Low Noise Rail-to-Rail I/O, 2.5- http://www.ti.com/product/OPA388 http://www.ti.com/opamps
V to 5.5-V supply

Design References
See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.
Links to Key Files
Source Files for Low-Side Current Sink – http://www.ti.com/lit/zip/slac784.
TI Precision Labs - Op Amps: Stability 6
For direct support from TI Engineers use the E2E community
e2e.ti.com
Other Links
Precision DAC Learning Center
http://www.ti.com/data-converters/dac-circuit/precision/overview.html

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 Analog Engineer's Circuit: Data
Converters
SLAA867 – December 2018

Programmable, two-stage, high-side current source circuit

Garrett Satterfield

Design Goals

Supply Voltage DAC Output Output Current Error Max Load Compliance
(VCC) Voltage Resistance Voltage
5V 0V–2V 0–100mA <1% FSR 45Ω 4.5V

Design Description
The programmable high-side current source supplies an adjustable current to a ground reference load.
The first op amp stage sets a reference current based on the DAC output voltage. The second op amp
stage acts as a current mirror that gains the reference current and regulates the current sourced from the
output PMOS to the load. RSET, RA, and RB set the output current based on the DAC voltage.
Components CCOMP, RISO, and RFB provide compensation to ensure stability of the circuit. Common end
equipment that utilize this circuit include PLC Analog Output Modules, Field Transmitters, Digital
Multimeters, Printers,Optical Modules , LED Drivers, and EPOS.
Vcc

470 RA RB 4.7
R FB

CF VB
VA

R ISO
Q2
A2
Vcc Q1 +
OPA2388 OPA2388
DAC + R ISO Vcc
A1

DAC8050x 40 R LOAD

CF

R FB
2k R SET

Design Notes
1. Choose a DAC with low offset, gain, and drift errors. RRIO op amps should be used to maintain low
compliance voltage and op amps with low offset should be selected.
2. Minimize the current flow through RA, Q1, and RSETby selecting a large ratio of RA:RB to maximize
efficiency while also minimizing heating and drift in the first stage.
3. Use high-precision, low-drift resistors for RSET, RA, and RB to minimize error caused by resistor
mismatch and temperature drift.
4. Minimize the resistance of RB to maximize compliance voltage.
5. Avoid placing Q2 near thermally sensitive components in layout as the power dissipation causes
heating.

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Design Steps
1. Set the reference current in the sink stage by selecting RSET based on VDAC. The reference current
should be minimized as it flows directly to ground and reduced efficiency. Set the reference current to
1mA and calculate RSET.
VDAC,max 2V
RSET 2k:
ISET 1mA
2. Select the required gain ratio based on the desired output current and IOUT/ISET = 100mA/1mA = 100,
this is the required ratio of RA:RB.
3. Calculate the maximum value of RB from the maximum allowable voltage drop to drive the maximum
current through the maximum load.
VCC IOUT,maxRLOAD,max 5V 0.1A * 45:
RB 5:
IOUT,max 0.1A
4. The voltage VA is VCC – ISETxRA which is equal to the voltage VB due to the op amp feedback. Select RA
to achieve a voltage drop of <500mV to maintain the desired compliance voltage. A standard
resistance of 4.7Ω is chosen.
VA VB
VCC VA 470mV
RA 470:
ISET 1mA
5. Calculate RB based on RA and the gain selected in step 2.
RA
RB
100
6. Verify the power dissipation of Q2. The power dissipation of Q2 based on the load is given by:
PDiss,Q2 VCC u IOUT IOUT 2 u RLOAD RB 5V u 0.1A 0.1A 2 u 40: 4.7: 0.053W
The maximum power dissipation of Q2 occurs when the load resistance is zero:
PDiss,Q2,max VCC u IOUT IOUT 2 u RB 5V u 0.1A 0.1A 2 u 4.7 0.453W
Ensure Q2 is rated for this power dissipation.

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DC Transfer Characteristics
T 100.00m

I_Load 99.999012mA
1.267nA

0.00
1.00m

I_SET

0.00
4.00

V_Load

0.00
2.00

V_SET

0.00

0.00 500.00m 1.00 1.50 2.00

Input voltage (V)

Small-Signal Step Response

T 2.91

V_A1

2.78
557.74u

I_RSET

500.00u
1.07

V_A2

1.04
55.00m

I_LOAD

50.00m
1.10

Vin

1.00

0.00 100.00u 200.00u 300.00u

Time (s)

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Compliance Voltage
T 100.00m

45ohm

I_LOAD

90.96m
4.55

4.5V

V_LOAD

0.00

0.00 10.00 20.00 30.00 40.00 50.00

Input resistance (ohms)

High Voltage Supply Modification

This circuit design example uses a low voltage supply for VCC. Some applications, such as 4–20mA
current loops, require a high voltage supply to drive large resistive loads. To modify this current source for
higher voltage supply, choose a high voltage, rail-to-rail input/output amplifier such as OPA192.

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Devices

Device Key Features Link Other Possible Devices

DACs
DAC80501 16-bit resolution, 1LSB INL, Single-Channel, Voltage Output DAC with http://www.ti.com/product/DAC80501 http://www.ti.com/pdacs
5ppm Internal Reference
DAC80508 16-bit resolution, 1LSB INL, Octal-Channel, Voltage Output DAC with http://www.ti.com/product/DAC80508 http://www.ti.com/pdacs
5ppm Internal Reference
DAC8775 16-bit resolution, Quad-Channel, ±10V, ±24mA Voltage and Current http://www.ti.com/product/DAC8775 http://www.ti.com/pdacs
Output DAC, with Integrated DC/DC Converter
Amplifiers
OPA388 Precision, Zero-Drift, Zero-Crossover, Rail-to-Rail Input/Output, 2.5-V http://www.ti.com/product/OPA388 http://www.ti.com/opamps
to 5.5-V Supply
OPA192 Precision, High-Voltage, Rail-to-Rail Input/Output, 4.5-V to 36-V http://www.ti.com/product/OPA192 http://www.ti.com/opamps
Supply
TLV170 Cost Sensitive, Rail-to-Rail Output, 2.7-V to 36-V Supply http://www.ti.com/product/TLV170 http://www.ti.com/opamps

Design References
See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.
Links to Key Files
TI Designs TIPD102, High-Side V-I Converter, 0-2V to 0-100mA, 1% Full Scale Error Reference Design
TI Designs TIPD215, Less Than 1-W, Quad-Channel, Analog Output Module With Adaptive Power
Management Reference Design
TI Designs TIDA-01525, 8-channel, 16-bit, 200mA current output DAC reference design
Source Files for Programmable, Two-Stage, High-Side Current Source – http://ti.com/lit/zip/slac783.
For direct support from TI Engineers use the E2E community:
e2e.ti.com
Other Links:
Precision DAC Learning Center
www.ti.com/pdac

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 Analog Engineer's Circuit: Data
Converters
SBAA344 – January 2019

Circuit for differential output from a single-ended

precision DAC

Uttama Kumar Sahu

Design Goals
Power Supply DAC Output Offset Range
VCC: 10V, VSS: –10V, VDD: 5V 0V to 5V ±5V

Design Description
This single-ended to differential conversion circuit features two operational amplifiers (op amp). It
generates a bipolar differential output from a unipolar digital-to-analog converter (DAC) channel. These
types of circuits are very useful in low-noise applications like Optical module, Metro data center
interconnect, Ultrasound scanners, and X-ray systems. While another design approach using a fully-
differential amplifier (FDA) is good for AC performance, the op amp approach will achieve best DC
characteristics. Nevertheless, the specific op amp or FDA will impact the comparison of the two
topologies.

VDD
VREF ±
VDAC U1 VOUTP
DAC +
R1 R2
VDIFF

±
U2 VOUTN
+
VCM

Design Notes
1. Choose a DAC with required resolution and output range
2. Select an op amp to meet the system specifications considering the following key requirements:
• Swing to rail: For 5-V supply rails it is common to use a rail-to-rail zero-crossover distortion device
(for example, OPA320 and OPA365)
• Offset voltage and drift: One of the advantages of this circuit over the FDA approach is that some
op amps can have very good DC performance
• Bandwidth and quiescent current: Another advantage of this circuit over the FDA approach is that
a wide range of op-amp bandwidth and related quiescent currents are available. For lower
sampling rate, a low-bandwidth, low-current op amp may be an optimal choice
3. Choose R1 and R2 to minimize thermal noise at the output

SBAA344 – January 2019 Circuit for differential output from a single-ended precision DAC
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Design Steps
1. Select a DAC such as DAC80501 that is a 16-bit single channel buffered voltage output DAC with
2.5-V internal reference. The reference output can also be used as the common-mode voltage (VCM)
2. Select a low-distortion op amp such as OPA320
3. The DC transfer function of the circuit is described with the following equations:
VOUTP VDAC

§ R2 ·
VOUTN VCM ¨ 1 ¸ VDAC
© R1 ¹

• R1 and R2 is chosen as 1kΩ to have a gain of 1 and to minimize noise. Use 0.1% tolerance to
minimize gain error.
• The thermal noise contributed by U1 to the differential output has two paths: directly through U1
and with inversion through U2. Both these noise are correlated and hence they will add directly.
DAC80501 has an output noise density (en-DAC) of 74nV/√Hz and OPA320 has a noise density (en-
AMP) of 7nV/√Hz. The noise gain of U1 (Gn-U1) is 1. So, the total noise density contributed by output
of U1 (en-U1) is given by:
2 2
en U1 2u en DAC en AMP 148.66nV Hz

• The thermal noise contributed by the gain resistors R1 and R2, (en-R) is given by:
23
en R 4.K.T.(R1 || R2 ) 4.(1.38 u 10 J / K).(298.15K).(500:) 2.87nV Hz

• The uncorrelated noise density contributed by U2 (en-U2) is a combination of the thermal noise of the
gain resistors (en-R), thermal noise of U2 (en-AMP), and the noise contributed by VCM when fed through
the VREF output of DAC80501 (en-VREF). en-VREF is 140nV/√Hz. The noise gain of U2 (Gn-U2), that is,
1+(R2/R1) is 2. So, en-U2 is written as:
2 2 2
en U2 en VREF .Gn U2 en AMP .Gn U2 en R .Gn U2 280.4nV Hz

• Finally, combining the noise from U1 and U2, we get the total noise density at the differential output
(en-T):
2 2
en T en U1 en U2 317.37nV Hz

The simulated value for the thermal noise at the differential output is shown in the following figure. The
simulated value 316.9nV/√Hz is close to the calculated value. The thermal noise for the DAC output
and VREF output were emulated with equivalent resistors for noise simulation.

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Thermal Noise Density at The Differential Output (VCM = VREF)

T 600.00n

VDIFF 10kHz, 316.9nV/rtHz

300.00n
500.00n

VOUTN

200.00n
200.00n

VOUTP

0.00
1.00 1.00k 1.00MEG
Frequency (Hz)

DC Transfer Characteristics (VCM = 0V)

T 20.00
10V
VDIFF

0.00
1.00

VOUTN
0V
-5.00
6.00

VOUTP
5V
0.00
0.00 2.50 5.00
V-DAC (V)

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Frequency Response (Amplitude)

T 10.00

VDIFF

-10.00
10.00

VOUTN

-40.00
3.00

VOUTP

-9.00
10.00 31.62k 100.00MEG
Frequency (Hz)

Frequency Response (Phase)

T 0.00

VDIFF

-300.00
200.00

VOUTN

-300.00
0.00

VOUTP

-300.00
10.00 31.62k 100.00MEG
Frequency (Hz)

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Group Delay
Group delay is the time delay between the applied input signal and the output signal. All amplifiers and
filters have a group delay. Group delay is highlighted for this circuit because the inverting and noninverting
path both have different group delays. This can create distortion for higher frequency signals. See the
group delay in time domain plot for additional detail.

T 30.00n

VOUTN
20.00n
Time (s)

10.00n

VOUTP

0.00
10.00 31.62k 100.00MEG
Frequency (Hz)

Output Transient Response

T 5.00
V-DAC

0.00
20.00
VDIFF

-10.00
1.00
VOUTN

-6.00
6.00
VOUTP

-1.00
0.00 10.00u 20.00u
Time (s)

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Design Featured Devices and Alternative Parts

Device Key Features Link

DAC80501 16-bit, 1-LSB INL, digital-to-analog converter (DAC) with precision internal reference http://www.ti.com/product/DAC80501
DAC80508 8-channel, true 16-bit, SPI, voltage-output DAC with precision internal reference http://www.ti.com/product/DAC80508
DAC8562 16-bit, dual-channel, low-power, ultra-low glitch, voltage output DAC with 2.5V, 4ppm/°C http://www.ti.com/product/DAC8562
reference
OPA320 Precision, zero-crossover, 20MHz, 0.9pA Ib, RRIO, CMOS operational amplifier http://www.ti.com/product/OPA320
OPA365 2.2-V, 50-MHz, low-noise, single-supply rail-to-rail operational amplifier http://www.ti.com/product/OPA365

Design References
See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.
Link to Key Files
TINA source files – http://www.ti.com/lit/zip/sbam419.
For direct support from TI Engineers use the E2E community:
e2e.ti.com

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 Analog Engineer's Circuit: Data
Converters
SBAA345 – January 2019

High-current voltage output circuit using a precision DAC

Uttama Kumar Sahu

Design Goals
Power Supply DAC Output Voltage Output Current Output
VCC: 24V, VSS: –5V, VDD: 5V 0V to 2.5V 0V to 5V 0A to 10A

Design Description
High-current voltage output can be obtained from a digital-to-analog converter (DAC) using a power
amplifier at the DAC output. To have additional flexibility with amplifier performance like accuracy,
bandwidth, and higher current, the circuit as shown in the following figure is more suitable. For example,
power amplifiers typically have much higher output offset error compared to a precision amplifier. The
DAC programs the output voltage along with the gain of the amplifier. The amplifier maintains the output
voltage using negative feedback. The high current to the load is provided by the transistor. This circuit is
useful in applications where components must be tested with different AC or DC voltage excitation such
as memory and semiconductor test equipment, LCD test equipment, and others.
VCC
VOUT

IL
VB IB
C1 R1
VSS

VDD
VCC

DAC RL
VFB

GND
R2

GND GND

Design Notes
1. Choose a DAC with the required resolution and output range.
2. Choose an op amp with low offset and low drift to minimize error. Choose a part with sufficient gain-
bandwidth product (GBW), as required by the output signal.
3. Choose R1 and R2 such that the desired output voltage is met along with the DAC output voltage,
along with tolerance which maintains the desired accuracy.
4. Choose the compensation capacitor C1 such that it is larger than the input capacitance of the op-amp
inputs.
5. Choose a transistor that can provide the required load current and has a high hFE so that the base
current is sufficiently smaller than the output current limit of the op amp. A bipolar-junction transistor
(BJT) Darlington pair or a high-power metal-oxide semiconductor field-effect transistor (MOSFET) are
preferable.

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Design Steps
1. The DAC80501 device is a 16-bit, single-channel, high-performance precision DAC. The DAC80501
device is specified monotonic, by design, and offers excellent linearity of less than 1LSB. These
devices include a 2.5V, 5ppm/˚C internal reference, giving full-scale output voltage ranges of 1.25V,
2.5V, or 5V.
2. The OPA227 operational amplifier combines low noise and wide bandwidth with high precision to make
it the ideal choice for applications requiring both AC and precision DC performance. The OPA227
device is unity-gain stable and features high slew rate (2.3V/µs) and wide bandwidth (8MHz).
3. The transfer function of the output voltage is given by:
æ R ö
VOUT = VDAC ç 1 + 1 ÷
è R 2 ø

To get an output voltage of 5V with a DAC output of 2.5V, for example, chose both R1 and R2 as 10kΩ.
This keeps the quiescent current through the feedback network as 5V / 20kΩ = 250µA. This current
works for this design because this design is for a high-output current. In case the output current is
lower, the resistance values can be increased so that the quiescent current is negligible, compared to
the output current.
4. The base current, IB, for the transistor for a given load current IL is given by:
IC 1 æ æ V OUT öö
IB = = ç I L + çç ÷÷ ÷÷
h FE h FE ç
è è R1 + R 2 øø
To get a maximum load current of 10A, the collector current (IC) of the transistor is approximately 10A
(ignoring 250-µA quiescent current). To keep IB less than 20mA, hFE should be greater than (10A /
20mA) = 500
5. In general, compensation capacitor C1 is not set by fixed equations, but rather by choosing values
while observing the output small-signal step response. Through simulation in this example, select C1 ≥
22pF.
DC Transfer Characteristics

T 6.00
5V

VOUT

0.00
0.00 1.25 2.50
VDAC (V)

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Small Signal Step Response Without Compensation

T 2.00m
IB
-1.00m
600.00m
IL
0.00
1.30
VB
500.00m
100.00m
VDAC
0.00
200.00m
VFB
0.00
300.00m
VOUT
0.00
0.00 10.00u 20.00u
Time (s)

Small Signal Step Response With C1 = 22pF

T 2.00m
IB
0.00
500.00m
IL
0.00
1.20
VB
500.00m
100.00m
VDAC
0.00
1.00
VFB
0.00
300.00m
VOUT
0.00
0.00 10.00u 20.00u
Time (s)

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Alternative Design With Power Amplifier

The following figure depicts the simplified circuit diagram of an alternative design using a power amplifier.
To achieve a high-current output from the DAC, use a power amplifier like the OPA541 device.. However,
as previously mentioned, this circuit may have accuracy and bandwidth limitations. Depending on the
system requirements, either of the circuit topologies can be used for generating high-current output. The
output transfer function of this circuit is the same as the following figure.
C1

R2 R1

VCC
GND
VDD
±
VOUT
DAC + OPA541
RL IL
GND VSS
GND

Design Featured Devices and Alternative Parts

Device Key Features Link

DAC80501 16-bit, 1-LSB INL, digital-to-analog converter (DAC) with precision internal reference http://www.ti.com/product/DAC80501
DAC8551 16-Bit, ultra-low glitch, voltage output, digital-to-analog converter http://www.ti.com/product/DAC8551
DAC8811 16-bit, single-channel, serial input multiplying DAC with 0.5-µs settling time http://www.ti.com/product/DAC8811
DAC8831 16-bit, ultra-low power, voltage output digital-to-analog converter http://www.ti.com/product/DAC8831
OPA227 High Precision, Low Noise Operational Amplifiers http://www.ti.com/product/OPA227
OPA541 High Power Monolithic Operational Amplifier http://www.ti.com/product/OPA541
THS4011 290-MHz low-distortion voltage-feedback amplifier http://www.ti.com/product/THS4011

Design References
See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.
Link to Key Files
TINA source files – http://www.ti.com/lit/zip/sbam417.
For direct support from TI Engineers use the E2E community
e2e.ti.com

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 Analog Engineer's Circuit: Data
Converters
SBAA335 – January 2019

Programmable voltage output with

sense connections circuit

Garrett Satterfield

Design Goals

DAC Output Output Voltage Minimum Load Maximum Line Error

Voltage VLOAD Resistance RLOAD Resistance
Compensation
0V–5V 0V–10V 1kΩ +25% of RLOAD <0.25% FSR

Design Description
The programmable voltage output with sense connections circuit provides a precise voltage across a load,
compensating for parasitic series resistance. The amplifier A1 uses feedback from the high-side and low-
side of the attached load to accurately regulate the voltage between VSENSE+ and VSENSE-. The digital-to-
analog converter (DAC) output and discrete resistors set the voltage across the load. This circuit is used in
applications where additional line resistance may be present and must be compensated for by increasing
the output voltage to deliver the correct voltage to the load. Common end equipment that use this circuit
include PLC Analog Output Modules, Memory and Semiconductor Test Equipment, Spectroscopy, and
Data Acquisition (DAQ) Cards.
25k 50k

5.5V R2 R4

VOUT R LINE+
A1 VSENSE+
25k
DAC + OPA196
R1 R LOAD
1k
50k
DAC80501 VSENSE-
R3

R LINE-

Design Notes
1. Select a DAC with low total unadjusted error (TUE) and with the required resolution for the application.
A DAC with integrated reference, like the DAC80501 device, can be used to minimize components and
solution size.
2. Choose a high-voltage amplifier, with rail-to-rail output to ensure sufficient output swing to drive the
load and line resistance. The amplifier should have low offset voltage and offset voltage drift so it does
not significantly contribute to output error.
3. Resistor mismatch directly contributes to gain error at the output. Use resistors with 0.05% tolerance or
better and low thermal drift.
4. For correct compensation of additional line resistance the ratio of R2:R4 must match the ratio of R3:R1
as closely as possible.
5. The amplifier supply voltage is chosen based on the required output voltage, additional line resistance,
and amplifier output swing at maximum load current.
6. To reduce error at zero-scale a negative voltage can be supplied to the amplifier.

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Design Steps
1. The transfer function for VOUT based on DAC voltage and resistor values is:
R3 R3 R4
VLOAD ˜ VDAC ;
R1 R1 R2
2. A 50-kΩ resistance is chosen for R3. A relatively large value should be selected to reduce the current
in the feedback paths. R1 is then calculated:
VDAC,FS 5V
R1 ˜ R3 ˜ 50k: 25k:
VLOAD,FS 10V
3. R4 and R2 are chosen equal to R3 and R1, respectively.
4. Calculate the maximum load current based on the minium load resistance and full scale VLOAD. The
maximum load current impacts the amplifier output voltage swing and the additional line resistance the
circuit can compensate.
VLOAD,FS 10V
ILOAD,max 10mA
RLOAD,min 1k:
5. The required VCC voltage is calculated to drive 25% additional load resistance and still maintain voltage
regulation across RLOAD. VO,rail is the approximate amplifier output swing from V+ at a 10-mA load
current.
VCC,min VO,rail 0.25 ˜ RLOAD,min ˜ I LOAD,max VLOAD,FS 500mV 250: ˜ 10mA 10V 13V
6. The output error can be approximated based on the DAC TUE, amplifier offset voltage, resistor
tolerance, and reference initial accuracy using root sum square (RSS) analysis.
2 2
2 § VOS · § 100PV ·
Output TUE(%FSR) TUEDAC ¨ ˜ 100 ¸ 4 ˜ R2Tol 2
AccuracyRe f 0.12 ¨ 5V ˜ 100 ¸ 4 ˜ 0.052 0.12 0.173%
© FSR ¹ © ¹

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DC Transfer Characteristic

T 10.00

9.999983V
VLoad

7.27mV

0.00
10.70

Vo

0.00
0.00 1.00 2.00 3.00 4.00 5.00
Input voltage (V)

Small-Signal Step Response

T 2.60

VDAC

2.50
5.22

VLoad

5.00
5.59

Vo

5.35
0.00 10.00u 20.00u 30.00u
Time (s)

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Load Transient 10-kΩ to 5-kΩ RLOAD

T 5.97

VLoad

4.19
6.02

Vo

4.29
0.00 25.00u 50.00u 75.00u 100.00u
Time (s)

Maximum Additional Line Resistance at Amplifier VCC = 13V

T 10.00

VLoad

8.39
12.59

252Ohm

Vo

10.00
0.00 100.00 200.00 300.00 400.00 500.00
Input resistance (ohms)

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Devices

Device Key Features Link Other Possible Devices

DACs
DAC80501 16-bit resolution, 1-LSB INL, single-channel, voltage output DAC with http://www.ti.com/product/DAC80501 http://www.ti.com/pdacs
5ppm/°C internal reference
DAC81416 16-bit resolution, 1-LSB INL, 16-channel ±20-V high-voltage output http://www.ti.com/product/DAC81416 http://www.ti.com/pdacs
DAC with 5ppm/°C internal reference
DAC80508 16-bit resolution, 1-LSB INL, octal-channel, voltage output DAC with http://www.ti.com/product/DAC80508 http://www.ti.com/pdacs
5ppm/°C internal reference
Op Amps
OPA196 Low-offset (100µV), Low-drift, rail-to-rail I/O, 2.25-V to 36-V supply http://www.ti.com/product/OPA196 http://www.ti.com/opamps
TLV170 Cost-sensitive, rail-to-rail output, 2.7-V to 36-V supply http://www.ti.com/product/TLV170 http://www.ti.com/opamps
OPA192 Precision, ultra-low offset (5µV) and drift, rail-to-rail I/O, 4.5-V to 36-V http://www.ti.com/product/OPA192 http://www.ti.com/opamps
supply

Links to Key Files

See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.
Download source files for Programmable Voltage Output with Sense Connections –
http://www.ti.com/lit/zip/sbac228.
For direct support from TI Engineers use the E2E community: e2e.ti.com.
Other Links
Learn more about how to design with precision DACs in our Precision DAC Learning Center.
Learn more about TI's precision DAC portfolio and find additional technical resources:
http://www.ti.com/data-converters/dac-circuit/precision/overview.html.

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 Analog Engineer's Circuit: Data
Converters
SBAA331 – January 2019

Unipolar negative voltage source from unipolar DAC

circuit

Paul Frost

Design Goals

DAC Supply Amplifier DAC Output Output Voltage Output Power-On Reset
Voltage Supply Range Range Current Output
Voltage Capability
5.5V ±5.5V 0V to 2.5V –5V to 0V ±20mA –5V

Design Description
This circuit shows how to convert a positive unipolar digital-to-analog (DAC) output to a negative unipolar
output using only an external operational amplifier (op amp) and resistors. In many applications, such as
active antenna systems (AAS) and macro remote radio units (RRU), a DAC output is used to bias the gate
of gallium nitride (GaN) power amplifier (PA). For these amplifiers to be powered down, a negative
potential must be applied to the gate. As such, it is beneficial to have the gate voltage be negative by
default. PA biasing applications also require current output source and sink capability that usually exceeds
that of most DACs.
These design goals are achieved by utilizing a voltage-output DAC that also features a reference. The
DAC output and reference output are connected to differential amplifier with the reference connected to
the inverting input. This enables the zero-scale output of the DAC to set the output of the amplifier to its
negative full-scale value.
R1 R3
+5.5 V
2k 4k

+5.5 V
VDD VREFIO R2 ±
(+2.5 V) 2k OUTPUT
DAC60501 + OPA207
R4 í5.5 V
4k

Design Notes
1. At power-on, the DAC output will assume a default value. This value can be configured in some
devices by connecting a reset-select pin to a high or low potential, which selects a start-up value of
zero-scale or mid-scale. In AAS designs, it is beneficial to start at zero-scale to ensure the PA is
disabled. Other applications may require a DAC to start at mid-scale.
2. The amplifier selected must provide the output current required by the application. Rail-to-rail outputs
allow the op amp power supplies to be minimized without clipping the desired output range of the
circuit. In AAS applications, there is usually a capacitive load on the output as well, so capacitive load
stability is important to consider.
3. The op amp must feature a bipolar supply, as the op amp inputs will always be greater than or equal to
0V in operation. The negative supply must be low enough to allow the output to reach its most
negative value.

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Design Steps
1. Select a DAC for the circuit based on initial on key requirements, such as the resolution, channel
count, output accuracy, and power supply. These performance requirements are application dependant
and can vary. However, a few additional items must be considered as well.
• The reference used to provide the offset of the differential amplifier will be required to source
current. Current will flow from the reference through the resistors in the feedback network (R1 and
R3) to the output of the amplifier. The maximum current would occur when the DAC output is at 0V
and the output of the amplifier is at its most negative potential. The following equation shows how
to calculate this current. If the current load is too great for the desired DAC reference, then a unity-
gain buffer can be added to the circuit.
VREF VOUTMIN
IREF MAX
R1 R3
• The output of DAC will also have to drive a resistive load, comprised of R2 and R4. The maximum
required current drive capability is expressed in the following equation:
VDAC MAX
IDAC MAX
R2 R4
• DACs which have an output range from 0V to VREF allow the resolution to be optimized for the
negative output.
2. The output range of the system can be calculated using the following equation. This is assuming that
R3 and R4 are equal and R1 and R2 are equal.
R3
VOUT VDAC VREF
R1
3. Select resistor values to achieve a balance between output noise and power consumption. Lower
resistor values will minimize the thermal noise of the resistors, but increase the power dissipation. The
minimum resistance values are limited by the output drive capabilities of the DAC and reference
output. The accuracy of the output transfer function is heavily dependent on the accuracy of the
resistor ratios. High-accuracy resistors are recommended.
DC Transfer Characteristics
The following simulation shows the output transfer function of the circuit:

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Small-Step Response
The following figure displays an LSB step response of the circuit with 15-pF load on the output.

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Design References
See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.
Download the companion simulation files for this circuit.
Design Featured Devices

Device Key Features Link Other Possible Devices

DAC60501 12-bit, 1-LSB, voltage-output digital-to-analog converter with precision http://www.ti.com/product/DAC60501 Precision DACs from Texas
internal reference. Instruments
OPA207 Low-power, high-precision, low-noise, rail-to-rail output, operational http://www.ti.com/product/OPA207 Precision Amplifier Overview
amplifier

Other Links:
Learn more about using precision DACs at our Precision DAC Learning Center.
Learn about TI's precision DAC portfolio and find more technical content.

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 Analog Engineer's Circuit: Data
Converters
SLAA869 – December 2018

Unipolar voltage output DAC to bipolar voltage

output circuit

Garrett Satterfield

Design Goals

DAC Supply Amplifier Supply DAC Voltage Output Voltage Error

Voltage Voltage
5V ±15V 0V–2.5V ±10V <0.25% FSR

Design Description
The unipolar to bipolar output voltage circuit converts the voltage from a unipolar DAC into a bipolar
voltage span. The circuit consists of a DAC, op amp, voltage reference, and 3 resistors to set the scale
and span of the bipolar output voltage. This circuit is commonly used in PLC Analog Output Modules,
Field Transmitters, and other applications requiring a programmable bipolar voltage.
5V

15V
VOUT
DAC +
A1
VREF
OPA188
DAC80501
-15V

8.25k 33k

RG1 RFB
11k RG2

Design Notes
1. Choose a DAC with low gain error, offset error, drift, and INL. A high-voltage op amp with low offset
voltage and low offset voltage drift should be used.
2. Use precision 0.1% or better tolerance resistors with low temperature drift.
3. To minimize solution size a DAC with integrated reference may be used.

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Design Steps
1. The voltage output based on DAC voltage, reference voltage, and resistors is given by:
§ RFB RFB · RFB
VOUT ¨1 ¸ VDAC VREF
© RG1 RG2 ¹ RG1

2. Set the DAC voltage to zero to calculate ratio of RFB and RG1 to create the desired negative full-scale
output. Select standard resistor values to produce this gain.
VNegativeFS RFB 10V 33k:
VREF RG1 2.5V 8.25k:
3. Calculate RG2 based on the full-scale range required, in this case 20V to produce ±10V range.
RFB 33k:
RG2 11k:
VFSR RFB 20V 33k:
1 1
VDAC RG1 2.5V 8.25k:

4. The output error can be approximated based on DAC TUE, amplifier offset voltage, resistor tolerance,
and reference initial accuracy using root sum square (RSS) analysis.
2 2
§ VOS,Amplifier · § 6uV ·
Output TUE(%FSR) TUE2DAC ¨¨ u 100 ¸¸ 2
TolR 2
TolR 2
TolR 2
AccuracyRe f 0.12 ¨ 2.5V u 100 ¸ 3 u 0.12 0.12 0.224% FSR
© FSR ¹
G1 G2 FB
© ¹

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DC Transfer Characteristic

T
10.00

9.9999V
Voltage (V)

0.00

-10.00002V

-10.00
0.00 1.00 2.00 3.00
Input voltage (V)

Small Signal Step Response

T 1.85

VDAC

1.75
4.80

VF1

4.00
0.00 5.00u 10.00u 15.00u 20.00u
Time (s)

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Devices

Device Key Features Link Other Possible Devices

DACs
DAC8560 16-bit resolution, single channel, internal reference, low power, 4 LSB http://www.ti.com/product/DAC8560 http://www.ti.com/pdacs
INL, SPI, 2V to 5.5V supply
DAC80501 16-bit resolution, 1LSB INL, Single-Channel, Voltage Output DAC with http://www.ti.com/product/DAC80501 http://www.ti.com/pdacs
5ppm Internal Reference
DAC8830 16-bit resolution, single channel, ultra-low power, unbuffered output, 1 http://www.ti.com/product/DAC8830 http://www.ti.com/pdacs
LSB INL, SPI, 2.7V to 5.5V supply
Amplifiers
OPA188 Low-Noise, Low Offset Voltage, RRO, Zero-Drift, ±2V to ±18V supply http://www.ti.com/product/OPA188 http://www.ti.com/opamps
OPA196 Low-Power, Low Offset Voltage, RRIO, ±2V to ±18V supply http://www.ti.com/product/TLV9001 http://www.ti.com/opamps
TLV170 Cost Sensitive, Rail-to-Rail Output, ±1.35V to ±18V supply http://www.ti.com/product/OPA317 http://www.ti.com/opamps

Design References
See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.
Links to Key Files
TI Design TIDP125, Bipolar ±10V Output from a Unipolar DAC for Industrial Voltage Drivers.
Source Files for Unipolar Voltage Output DAC to Bipolar Voltage Output – http://www.ti.com/lit/zip/slac785.
For direct support from TI Engineers use the E2E community:
e2e.ti.com
Other Links:
Precision DAC Learning Center
http://www.ti.com/pdacs

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