DR.G.U.

POPE COLLEGE OF ENGINEERING

POPE NAGAR, SAWYERPURAM
DEPARTMENT OF ELECTRONICS AND COMMUNICATION
ENGINEERING
Internal Assessment Test-III
Regulation: 2017
Sub with code: EC8552& Computer Architecture and Organization Class: III ECE

Staff Name: A.ANANTHAKUMARI Date&Time: 10/11/20&4 PM

Time: 1 hour Total Marks: 60

PART –A (1*20=20)

1. Any condition that causes a processor to stall is called as _________

a) Hazard
b) Page fault
c) System error
d) None of the mentioned

T
View Answer

Answer: a
EN
Explanation: An hazard causes a delay in the execution process of the processor.
D
2. The periods of time when the unit is idle is called as ________
U

a) Stalls
ST

b) Bubbles
c) Hazards
d) Both Stalls and Bubbles
R

View Answer
M

Answer: d
Explanation: The stalls are a type of hazards that affect a pipe-lined system.

3. The contention for the usage of a hardware device is called ______

a) Structural hazard
b) Stalk
c) Deadlock
d) None of the mentioned
View Answer

Answer: a
Explanation: The processor contends for the usage of the hardware and might enter into a
deadlock state.

4. The situation wherein the data of operands are not available is called ______
a) Data hazard
b) Stock
c) Deadlock
d) Structural hazard
View Answer

Answer: a
Explanation: Data hazards are generally caused when the data is not ready on the
destination side.

5. The stalling of the processor due to the unavailability of the instructions is called as
___________
a) Control hazard
b) structural hazard
c) Input hazard
d) None of the mentioned
View Answer

Answer: a
Explanation: The control hazard also called as instruction hazard is usually caused by a

T
cache miss.
EN
6. The time lost due to the branch instruction is often referred to as ____________
a) Latency
D
b) Delay
c) Branch penalty
U

d) None of the mentioned

ST

View Answer

Answer: c
R

Explanation: This time also retards the performance speed of the processor.
M

7. The pipeline bubbling is a method used to prevent data hazard and structural hazards.
a) True
b) False
View Answer

Answer: a
Explanation: The periods of time when the unit is idle is called a Bubble.

8. ____________ method is used in centralized systems to perform out of order execution.

a) Scorecard
b) Score boarding
c) Opti evev222qaqwswmizing
d) Redundancy
View Answer
Answer: b
Explanation: In a scoreboard, the data dependencies of every instruction are logged. Instructions
are released only when the scoreboard determines that there are no conflicts with previously
issued and incomplete instructions.

9. To increase the speed of memory access in pipelining, we make use of _______

a) Special memory locations
b) Special purpose registers
c) Cache
d) Buffers
View Answer

Answer: c
Explanation: By using the cache we can reduce the speed of memory access by a factor of
10.

T
EN
10. The periods of time when the unit is idle is called as _____
a) Stalls
b) Bubbles
D
c) Hazards
d) Both Stalls and Bubbles
U

View Answer
ST

Answer: d
Explanation: The stalls are a type of hazards that affect a pipelined system.
R
M

11. The situation wherein the data of operands are not available is called ______
a) Data hazard
b) Stock
c) Deadlock
d) Structural hazard
View Answer

Answer: a
Explanation: Data hazards are generally caused when the data is not ready on the destination
side.

12.The main virtue for using single Bus structure is ____________

a) Fast data transfers
b) Cost effective connectivity and speed
c) Cost effective connectivity and ease of attaching peripheral devices
d) None of the mentioned
View Answer

Answer: c
Explanation: By using a single BUS structure we can minimize the amount of hardware
(wire) required and thereby reducing the cost.

13. ______ are used to overcome the difference in data transfer speeds of various devices.
a) Speed enhancing circuitory
b) Bridge circuits
c) Multiple Buses
d) Buffer registers
View Answer

Answer: d
Explanation: By using Buffer registers, the processor sends the data to the I/O device at the
processor speed and the data gets stored in the buffer. After that the data gets sent to or from the
buffer to the devices at the device speed.

T
EN
14. To extend the connectivity of the processor bus we use ________
a) PCI bus
b) SCSI bus
D
c) Controllers
d) Multiple bus
U

View Answer
ST

Answer: a
Explanation: PCI BUS is used to connect other peripheral devices that require a direct
R

connection with the processor.

M

15. The bus used to connect the monitor to the CPU is ______
a) PCI bus
b) SCSI bus
c) Memory bus
d) Rambus
View Answer

Answer: b
Explanation: SCSI BUS is usually used to connect video devices to the processor.

16. In multiple Bus organisation, the registers are collectively placed and referred as ______
a) Set registers
b) Register file
c) Register Block
d) Map registers
Answer: b
Explanation: None.

17. The main advantage of multiple bus organisation over a single bus is _____
a) Reduction in the number of cycles for execution
b) Increase in size of the registers
c) Better Connectivity
d) None of the mentioned

Answer: a
Explanation: None.

18. The ISA standard Buses are used to connect ___________

a) RAM and processor
b) GPU and processor
c) Harddisk and Processor
d) CD/DVD drives and Processor

T
View Answer

Answer: c
EN
Explanation: None.
D
19.What characteristics of RAM memory is not suitable for permanent storage.
U

a)Volatile
ST

b)Non Volatile

c)Too bulky
R
M

d)Too slow

20) -------is/are types of exception.

a)trap

b)Interrupt

c)system calls

d)All the above

Ans :c

PART-B (15*2=30)

1.The standard SRAM chips are costly as _________

a)They use highly advanced micro-electronic devices
b) They house 6 transistor per chip
c) They require specially designed PCB’s
d) None of the mentioned

Answer: b
Explanation: As they require a large number of transistors, their cost per bit increases.

2. When consecutive memory locations are accessed only one module is accessed at a time.
a) True
b) False
Answer: a
Explanation: In a modular approach to memory structuring only one module can be accessed at a
time.
3. In memory interleaving, the lower order bits of the address is used to _____________
a) Get the data
b) Get the address of the module
c) Get the address of the data within the module
d) None of the mentioned

T
Answer: b
EN
Explanation: To implement parallelism in data access we use interleaving.
4. The number successful accesses to memory stated as a fraction is called as _____
D
a) Hit rate
b) Miss rate
U

c) Success rate
ST

d) Access rate
Answer: a
Explanation: The hit rate is an important factor in performance measurement.
R

advertisement
M

5. The number failed attempts to access memory, stated in the form of a fraction is called as
_________
a) Hit rate
b) Miss rate
c) Failure rate
d) Delay rate
Answer: b
Explanation: The miss rate is a key factor in deciding the type of replacement algorithm.
6. In associative mapping during LRU, the counter of the new block is set to ‘0’ and all the others are
incremented by one, when _____ occurs.
a) Delay
b) Miss
c) Hit
d) Delayed hit
Answer: b
Explanation: Miss usually occurs when the memory block required is not present in the cache.
7. In LRU, the referenced blocks counter is set to’0′ and that of the previous blocks are incremented by
one and others remain same, in the case of ______
a) Hit
b) Miss
c) Delay
d) None of the mentioned
Answer: a
Explanation: If the referenced block is present in the memory it is called as hit.
advertisement

8. If hit rates are well below 0.9, then they’re called as speedy computers.
a) True
b) False

T
Answer: b
Explanation: It has to be above 0.9 for speedy computers.
EN
9. The extra time needed to bring the data into memory in case of a miss is called as __________
a) Delay
D
b) Propagation time
U

c) Miss penalty
ST

d) None of the mentioned

Answer: c
R

Explanation: None.
M

10. The miss penalty can be reduced by improving the mechanisms for data transfer between the
different levels of hierarchy.
a) True
b) False

Answer: a
Explanation: The extra time needed to bring the data into memory in case of a miss is called as miss
penalty.

1.The directly mapped cache no replacement algorithm is required.

a) True
b) False
Answer: a
Explanation: The position of each block is pre-determined in the direct mapped cache, hence no need
for replacement.

2. The surroundings of the recently accessed block is called as ______

a) Neighborhood
b) Neighbour
c) Locality of reference
d) None of the mentioned

Answer: c
Explanation: The locality of reference is a key factor in many of the replacement algorithms.

3. In set associative and associative mapping there exists less flexibility.

a) True
b) False

T
Answer: b
EN
Explanation: The above two methods of mapping the decision of which block to be removed rests
with the cache controller.
D
4. The algorithm which replaces the block which has not been referenced for a while is
U

called _____
ST

a) LRU
b) ORF
c) Direct
R

d) Both LRU and ORF

M

Answer: a
Explanation: LRU stands for Least Recently Used first.

5. In associative mapping during LRU, the counter of the new block is set to ‘0’ and all the
others are incremented by one when _____ occurs.
a) Delay
b) Miss
c) Hit
d) Delayed hit

Answer: b
Explanation: Miss usually occurs when the memory block required is not present in the cache.

6. The LRU provides very bad performance when it comes to _________

a) Blocks being accessed is sequential
b) When the blocks are randomised
c) When the consecutive blocks accessed are in the extremes
d) None of the mentioned

Answer: a
Explanation: The LRU in case of the sequential blocks as to waste its one cycle just incrementing the
counters.

7. The algorithm which removes the recently used page first is ________
a) LRU
b) MRU
c) OFM
d) None of the mentioned

Answer: b
Explanation: In MRU it is assumed that the page accessed now is less likely to be accessed again.

8. The LRU can be improved by providing a little randomness in the access.

T
a) True
b) False EN
Answer: a
D
Explanation: None.
U

9. In LRU, the referenced blocks counter is set to’0′ and that of the previous blocks are
ST

incremented by one and others remain same, in the case of ______

a) Hit
b
R

0
L) Miss
M

c) Delay
d) None of the mentioned

Answer: a
Explanation: If the referenced block is present in the memory it is called as a hit.

The counter that keeps track of how many times a block is most likely used is _______
a) Count
b) Reference counter
c) Use counter
d) Probable counter
View Answer
Answer: b
Explanation: None.

key factor/s in commercial success of a computer is/are ________

a) Performance
b) Cost
c) Speed
d) Both Performance and Cost
View Answer
Answer: d
Explanation: The performance and cost of the computer system is a key decider in the commercial
success of the system.

2. The main objective of the computer system is ________

a) To provide optimal power operation
b) To provide the best performance at low cost
c) To provide speedy operation at low power consumption
d) All of the mentioned

Answer: b
Explanation: An optimal system provides the best performance at low costs.

T
3. A common measure of performance is ________
a) Price/performance ratio
EN
b) Performance/price ratio
D
c) Operation/price ratio
d) None of the mentioned
U

View Answer
ST

Answer: a
Explanation: If this measure is less than one then the system is optimal.
R

4. The performance depends on ________

a) The speed of execution only
M

b) The speed of fetch and execution

c) The speed of fetch only
d) The hardware of the system only
Answer: b
Explanation: The performance of a system is decided by how quick an instruction is brought into the
system and executed.

advertisement

5. The main purpose of having memory hierarchy is to ________

a) Reduce access time
b) Provide large capacity
c) Reduce propagation time
d) Reduce access time & Provide large capacity

Answer: d
Explanation: By using the memory Hierarchy, we can increase the performance of the system.
6. The memory transfers between two variable speed devices are always done at the speed of the
faster device.
a) True
b) False
View Answer
7. An effective to introduce parallelism in memory access is by _______
a) Memory interleaving
b) TLB
c) Pages
d) Frames
View Answer
Avvnswer: a
Explanation: Interleaving divides the memory into modules.

advertisement

8. The performance of the system is greatly influenced by increasing the level 1 cache.
a) True

T
b) False
View Answer EN
9. Two processors A and B have clock frequencies of 700 Mhz and 900 Mhz respectively.
Suppose A can execute an instruction with an average of 3 steps and B can execute with an
D
average of 5 steps. For the execution of the same instruction which processor is faster.
a) A
U

b) B
ST

c) Both take the same time

d) Insufficient information
R

Answer: a
M

Explanation: None.

10. If the instruction Add R1, R2, R3 is executed in a system which is pipelined, then the value
of S is (Where S is a term of the Basic performance equation).
a) 3
b) ~2
c) ~1
d) 6
View Answer
Answer: c
Explanation: Pipelining is a process of fetching an instruction during the execution of other instruction.

The reason for the implementation of the cache memory is ________

a) To increase the internal memory of the system
b) The difference in speeds of operation of the processor and memory
c) To reduce the memory access and cycle time
d) All of the mentioned

Answer: b
Explanation: This difference in the speeds of operation of the system caused it to be
inefficient.

The physical memory is not as large as the address space spanned by the processor.
a) True
b) False
answer: a
Explanation: This is one of the main reasons for the usage of virtual memories.
advertisement

2. The program is divided into operable parts called as _________

a) Frames
b) Segments

T
c) Pages
d) Sheets
Answer: b EN
Explanation: The program is divided into parts called as segments for ease of execution.
3. The techniques which move the program blocks to or from the physical memory is called
D
as ______
U

a) Paging
b) Virtual memory organisation
ST

c) Overlays
d) Framing
R

Answer: b
M

Explanation: By using this technique the program execution is accomplished with a usage of less
space.

4. The binary address issued to data or instructions are called as ______

a) Physical address
b) Location
c) Relocatable address
d) Logical address

Answer: d
Explanation: The logical address is the random address generated by the processor.

5. __________ is used to implement virtual memory organisation.

a) Page table
b) Frame table
c) MMU
d) None of the mentioned

Answer: c
Explanation: The MMU stands for Memory Management Unit.

6. ______ translates the logical address into a physical address.

a) MMU
b) Translator
c) Compiler
d) Linker

Answer: a
Explanation: The MMU translates the logical address into a physical address by adding an offset.

7. The main aim of virtual memory organisation is ________

a) To provide effective memory access
b) To provide better memory transfer

T
c) To improve the execution of the program
d) All of the mentioned EN
Answer: d
D
Explanation: None.
U
ST
R
M