CONTROL ENGINEERING VOLUME: 13 | NUMBER: 1 | 2015 | MARCH

FPGA Implementation of a Simple 3D Graphics

Pipeline

Vladimir KASIK, Ales KURECKA

Department of Cybernetics and Biomedical Engineering, Faculty of Electrical Engineering and Computer
Science, VSB–Technical University of Ostrava, 17. listopadu 15, 708 33 Ostrava, Czech Republic

[email protected], [email protected]

DOI: 10.15598/aeee.v13i1.1125

Abstract. Conventional methods for computing 3D require much larger frequencies to achieve comparable
projects are nowadays usually implemented on stan- speeds. FPGA also support high parallelization and
dard or graphics processors. The performance of these may be used to achieve high computational through-
devices is limited especially by the used architecture, puts.
which to some extent works in a sequential manner.
This project originated as a semester project with an
In this article we describe a project which utilizes pa-
initial goal of drawing 3D projections of simple wire-
rallel computation for simple projection of a wireframe
frame models in real-time on a single chip, where the
3D model. The algorithm is optimized for a FPGA-
intent was to achieve very high values of fps. Since
based implementation. The design of the numerical
the described problem commonly lies beyond the boun-
logic is described in VHDL with the use of several basic
daries of usual microcontrollers/CPUs, the solution has
IP cores used especially for computing trigonometric
led to the creation of a hardware graphics pipeline for
functions. The implemented algorithms allow smooth
drawing on a screen via the VGA interface [1].
rotation of the model in two axes (azimuth and eleva-
tion) and a change of the viewing angle. Tests carried
out on a FPGA Xilinx Spartan-6 development board
have resulted in real-time rendering at over 5000 fps. 2. Graphics Pipeline
In the conclusion of the article, we discuss additional
possibilities for increasing the computational output in Current GPUs comprise many cores containing unified
graphics applications via the use of HPC (High Perfor- shaders, which allow the realization of operations pre-
mance Computing). viously carried out by vertex units, pixel units, TMUs
(texture mapping units) and ROPs (render output
units). Drawing of 3D models on the screen is basically
the results of several consecutive blocks (simplified) [5]:
Keywords
• Primitive processing – reading primitives, vertices
3D projection, FPGA, parallel processing, real and their connection.
time, VGA, VHDL.
• Vertex shader – the vertex shader transforms co-
ordinates of vertices by their multiplication with
the matrices of the scene. This is where the trans-
1. Introduction formation from 3D → 2D occurs.

The drawing of graphics scenes in 3D obtained from • Primitive assembly – vertices are joined into pri-
their representations requires the processing of large mitives.
volumes of data. Special chips are available for this • Rasterization – primitives are rasterized into pi-
purpose – GPUs which rely on mass parallelization. xels.
Under usual circumstances, CPUs are not suitable for
these tasks (even though there do exist instruction sets • Pixel shader – this is applied to each pixel of the
supporting multiple computations), since by their de- rasterized scene and computes its color. This step
sign they process instructions serially and hence would also applies textures.

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A vertex unit (whose functionality is nowadays in- 2.1. Perspective Projection

cluded in the vertex shader) will suffice for the pur-
poses of this work. The data source is a ROM with the Displaying a 3D object in two dimensions is a linear
vertices of the model, which is then transformed by transformation over the R3 vector space into R2 . A
the vertex unit to vertices in a plane. These vertices special case of this is the projection transformation.
are then joined by line segments and drawn in video This transformation can be described by the projection
RAM, from which the VGA adapter will subsequently matrix. During projection, the dimension degrades
generate VGA signal for the screen. from dimR3 = 3 to dimR2 = 2 and the vectors ob-
tained by the transformation can be used to display
The graphics pipeline consists of the unit carrying
the object on a plane (e.g. a screen). There exist two
out the computation of the projection matrix (Grx-
types of projection which are used in graphics: par-
GenerateProjectionMatrix ) and the unit multiplying
allel projections (which include isometric, orthogonal,
the projection matrix with the vertices of the displayed
oblique projections etc.) and perspective projections.
model (GrxVertexProjection). Both GrxGeneratePro-
In this article we focus on the latter type of projec-
jectionMatrix and GrxVertexProjection together form
tions. Linear perspective projections always work with
the vertex unit and ensure the actual 3D → 2D display.
a representation of the beams from the projected ob-
The obtained 2D vertices are scaled to the required size
ject to the observer’s eye (the camera) through a plane,
and converted from decimal numbers represented with
on which the object is projected. See Fig. 2 for an il-
a fixed decimal point to integers into the monitor co-
lustration.
ordinates system and stored in the memory cache (the
2D vertex bank). Vertices from the cache are read by
the unit drawing the wireframe model based on their
connection map (from the ROM model). The model
is drawn in the black-and-white video RAM (frame
buffer), from which display data are read by the VGA
adapter and displayed on the screen.
Displaying is ensured by the VGA adapter with bi-
nary modulation of base colors. The control of the
whole Cubido3D project is ensured by one primary and
several local FSMs (Finite State Machines). A sim-
plified diagram of the graphics pipeline is provided in
Fig. 2: Perspective projection of an object onto a plane.
Fig. 1.

The transformation matrix realizing perspective pro-

jection is obtained by multiplication of 3 matrices [4]:

A = P · T · R. (1)

• The transformation matrix R, which is obtained

by a composition of rotation by axes x and z:
 
1 0 0 0
 0 cos(θx ) − sin(θx ) 0 
Rx = 
 0 sin(θx ) cos(θx )
, (2)
0 
0 0 0 1
 
cos(θz ) − sin(θz ) 0 0
 sin(θz ) cos(θz ) 0 0 
Rz =  , (3)
 0 0 1 0 
0 0 0 1

Fig. 1: Simplified diagram of the Cubido3D graphics pipeline. R = Rx · Rz . (4)

Individual blocks of the graphics pipeline consist of Rotation is typically entered in the form of an azi-
separate VHDL modules or optimized IP cores which muth and elevation, where the following relations
are a part of the Xilinx ISE development kit. hold:

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where f is the focal distance, which can be com-

θz = −θaz , puted from the viewing angle:
π (5) √
θx = θel − . 2
2 f= , (9)
2 · tan( φ2 )
Figure 3 illustrates the effects of the transforma-
tion matrix. φ determines the rate of the projection deforma-
tion of the object. If φ = 0, the projection de-
grades to an orthogonal projection.

Fig. 3: Effects of the transformation matrix on the displayed

Fig. 5: Effect of viewing angle on perspective deformation of
object.
the display.

• The translation matrix T translated the starting

point [0, 0, 0] of the coordinate system of the object
and has the shape: 3. Implementation
 
0 0 0 vx The Cubido3D project implements a hardware-based
 0 1 0 vy  graphics pipeline based on FPGA. Projection, transla-
T= . (6)
 0 0 1 vz  tion of objects and generation of video signal is adapted
0 0 0 1 for an architecture based on a programmable logic.
The translation moves the beginning of the coor- Aside from the graphics pipeline, the project also
dinate system, usually to the center of the object. includes a VGA adapter generating the video signal
This forms the center based on which the object for the screen, a memory of displayed models, blocks
is rotated (Fig. 4). generating the background image + panel image and
supporting logic (distribution of clock signal, control
of the graphics pipeline etc.). Pipelining and strong
√
 
cos(θel ) · sin(θaz ) parallelism are commonly used to obtain the target fre-
1 3 
v= + · − cos(θel ) · cos(θaz )  . (7) quency of 100 MHz.
2 2
sin(θel )

3.1. Cubido3D

Cubido3D forms the Top Level Module. It synchro-

nizes input signals, controls the azimuths and elevation
by counters with acceleration and the viewing angle by
a counter with overflow protection. Combinations of
buttons also allow the selection of the drawing model
and the generation of a global reset.
Fig. 4: Effects of the translation matrix on the displayed object.
The selected data of the model are, together with
If the coordinates of object vertices are set so that the azimuth, elevation and viewing angle, transferred
the object lies in [0, 0, 0], the matrix becomes a to GrxGraphicUnit. Cubido3D connects the VGA
unit matrix and the translation is not necessary. adapter and FPs display on a 7-segmented display.
Since FPGA doesn’t have sufficient memory for double
• The perspective transformation P carries out the buffering, video RAM has a capacity of only 1 frame
actual conversion from 3D → 2D and has the form: and must thus be redrawn synchronously at the time
  the screen is in an inactive area. Due to this, redraw-
0 0 0 0 ing is always called during the receipt of the vertical
 0 1 0 0  synchronization impulse. Drawing is fast (takes ap-
P=
 0
, f = d, (8)
0 1 0  proximately 200 µs in case of a cube) and thus finishes
0 0 − f1 d
f
before the screen transfers to the active area.

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divisor. All additional computations are carried out by

the DSP48A1 unit which is part of the architecture of
the used FPGA. DSP48A1 is specifically configured to
carry out the following computation:

R = A + (B − C) · D. (10)

The unit works with numbers with a fixed decimal

(FXP) in the 10Q8 format. The computation is illus-
trated in the Fig. 7:

Fig. 6: Example of an output generated by FPGA captured on

a VGA interface.

3.2. Implementation of the Graphics

Pipeline

The graphics pipeline consists of the unit for comput-

ing the projection matrix, the vertex unit, the simple
rendering unit and a two-port video memory.
The pipeline first deletes video RAM, computes the
projection matrix with transferred parameters (az-
imuth, elevation, viewing angle) and reads the normal-
ized 3D model from the vertex memory and their inter-
connections. This is then displayed in 2D and rescaled
for display on the screen (numbers are converted with a
certain offset and scale from FXP to integer form). The
computer 2D vertices are stored into the small cache.
The wireframe model is then drawn in the video mem-
ory from the computed 2D vertices.

1) Calculation of the Projection Matrix Fig. 7: Computation of the projection matrix by the GrxGe-
(GrxGenerateProjectionMatrix ) nerateProjectionMatrix module.

GrxGenerateProjectionMatrix is a unit which com- The resulting projection matrix is serialized into a
putes the matrix of a perspective display from received 4×4×10Q8 bus, and thus has a width of 288 bits. The
values of the azimuth, elevation and viewing angle bus is connected to computational units via registers
(amount of perspective deformation). The computa- and bus multiplexes controlled by the state automaton.
tion of formulas Eq. (1) to Eq. (9) is adapted for pro- The largest amount of running time is used by the se-
cessing via FPGA. The center of the projection (the rial divisors, and hence they are initiated shortly after
target point) is fixed to the initial point of the coor- the computation of the matrix begins and they work
dinate system. Despite best efforts to make the com- in parallel with the other computations.
putation as parallel as possible, it is strongly sequen-
tial and its processing is carried out by a state ma-
chine with 28 states. The computation of trigonometric 2) Vertex Unit (GrxVertexProjection)
functions is carried out by the CORDIC unit (Cordic-
Core_SINCOS entity), which computes in parallel the The vertex unit computes 2D vertices of the image by
sine and cosine functions for the entered angle. The projecting their 3D template through multiplication
computation of the tangent of the viewing angle is car- with the projection matrix received from GrxGene-
ried out in 2 steps: the first is the computation of the rateProjectionMatrix . The whole principle is very si-
sine and cosine of the viewing angle, followed by their milar to the computation carried out by the GrxGe-
division. Division is carried out in an adjoined serial nerateProjectionMatrix unit. The computation is con-

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trolled by a state machine (12 states) together with a

divisor and 2 DSP48A1. Both DSP48A1 realize the
following computation:

R = A + B · D. (11)

The steps of the computation carried out by the ver-

tex unit are illustrated in the Fig. 8:
Fig. 9: One of the models stored in ModelDescriptionROM
drawn directly by the graphics pipeline with a detailed
view of the rasterization of the wireframe model.

and hence also writing can be stopped by a signal, and

if necessary this can be setup by the state machine
controlling video memory.
The state machine (12 states) first captures, com-
pares and if necessary adjusts the order and coordi-
nates of the input vertices (the unit transforms all line
segments into the first half of the first quadrant – an-
gular coefficient 0 to π4 ). This is necessary to allow
Fig. 8: Multiplication of the projection matrix and a vertex.
the generation of coordinate x by a counter; larger co-
efficients would lead to the loss of points on the line,
see Fig. 10. It then computes their angular coefficient
Since the computations of vertices are mutually in-
(the increase in the vertical axis per unit step on the
dependent, they can be carried out in parallel in several
horizontal axis). The number of the fractional (break-
identical vertex units.
line) bits of the angular coefficient is set automatically
The coordinates for the templates of vertices are read so as to reach the target vertex. The unit then uses
from the model memory by the superordinate state ma- the counter to generate the horizontal coordinate and
chine in GrxGraphicsUnit. The obtained coordinates of generates the vertical one by the accumulator. The
vertices in the plane are first converted from FXP for- vertical coordinate is rounded. Coordinates are also
mat to coordinates on the screen, or more specifically adjusted by the offset specified in point 1 and trans-
in the video memory, and stored in the memory cache formed back into their quadrant. Finally, the write
(Vertex2D_Bank ). signal is created.

3) Wireframe Model Rendering

(GrxDrawWireframe)

GrxDrawWireframe draws the wireframe from the 2D

vertex bank (Vertex2D_Bank ). The unit reads the
connection map between individual vertices from the
model memory into the wireframe model, and these
vertices are then read from the bank of 2D vertices Fig. 10: Drawing of a line segment and the effect of the angular
coefficient.
and transferred to GrxDrawLine2D, which draws a line
segment between the vertices.
Generation of coordinates for a write request is car-
Memory control is managed by the unit’s own re- ried out in 2 cycles, and the unit is hence capable of
sources. drawing 1 pixel per 2 cycles. In general the drawing
process takes circa 40 + 2n cycles (where n is the num-
ber of drawn points). Interrupts of writing called by
4) Drawing a Line Segment the video memory unit are not taken into account. Fi-
(GrxDrawLine2D) gure 9 illustrates the generation of a line segment.
This unit draws a line segment defined by 2 integer
2D vertices into the memory. The vertices need not 5) Video Memory (GrxVideoRAM )
be ordered or otherwise preprocessing (the unit takes
care of this automatically). The speed of generating This module implements the video memory with a
points on the line is 1 point per 2 clocks. Generation function for quick deletion of the whole RAM. Read-

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ing and writing is realized by a state automaton, which 1) Model Memory

works with a larger internal data bus than the required (ModelDescriptionROM )
external one (and hence also a smaller internal address
bus). This allows much quicker deletion of RAM. Part The definition of models consists of a list of vertices
of the external address bus (the upper bits) addresses a (Vertex3DBankROM ) and their connections (Vertex-
location in RAM, whereas the lower bits map the exter- PointerROM ). Models are stored sequentially. Mod-
nal data bus to the greater internal data bus. Writing elsDescriptorROM is used to store the offset to Ver-
can in some cases take longer than 1 clock, since it is tex3DBankROM and VertexPointerROM, where the
necessary to first read a data block in RAM, change model begins and simultaneously the length of the
the corresponding group of bits in this block via the records of the model in these memories. Vertex-
input data for writing and then write this block, as PointerROM consists of a map of vertex connections
illustrated in Fig. 11. The current block is cached. – it contains tuples of indices (addresses) into Ver-
tex3DBankROM which define a line segment in the
wireframe model. Figure 12 illustrates the model mem-
ory architecture.

Fig. 11: Video memory architecture.

3.3. VGA Adapter

(GrxAdapterVGA)

A generic VGA adapter which supports various reso-

lutions and color depths based on the configuration of
[6]. Its correct operation is based on an incoming signal Fig. 12: Model memory architecture.
with a VGA pixel frequency from the main clock dis-
tribution through the DCM (Digital Clock Manager)
module.
Clock domains are strictly separated. All simple sig- 2) Background Video Signal Generator
nals are resynchronized by the GResynchronizer block (BackgroundVisualizer )
(part of the library of general project components) and
the transmission of video signal from the input clock This takes care of the generation of RGB signals for
domain is resolved via a FIFO queue with separated drawing the background in VGA. It draws a vertical
clocks for reading and writing. This queue is also used color shift from black.
as a line cache (writing is carried out on a line-by-line
basis). The queue is inserted as an IP core to ensure
timing and synchronization. Synchronization of writ-
ing in the line cache is carried out via the LineStrobe
(beginning of a line) and FrameStrobe (beginning of a
frame) signals in combination with the PixelRequest-
Axis (current coordinate for writing) signal.

3.4. Project-Oriented Modules

The source files of the project connect individual com-

ponents into larger wholes – they connect the memo-
ries, the graphics pipeline, and the VGA adapter and
also take care of synchronization, adjustment and pro- Fig. 13: Examples of generated background for various azi-
cessing of input and output signals. muths and elevation (rotated by 90◦ ).

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The hue is based on the azimuth and elevation and 3.5. The Libgenerics Library
hence changes depending on the "rotation" of the ob-
ject. The formula used for the video signal v is: This library provides the basic functional blocks and
functions:

 
− cos(θaz ) − cos(θel )

• GResynchronizer – Resynchronizer of one-bit
cos(θaz ) − cos(θ el )
 
 2+ 
   2

 asynchronous signals into the internal clock do-
cos(θaz )
 cos(θel ) − 2

main.
vcolor = y ·  +
 
 2048 



 (12) • GResetSynchronizer – Resynchronizer of reset into
the internal clock domain.

rand() • GDebounceFilter – Debouncing filter for button

+ . press.
4

The computation of goniometric functions is carried • GEdgeDetector – Detector of rising/falling/both

out by a separate CORDIC core with its own controller, edges of the monitored signal.
which periodically sends the azimuth and elevation to
the core and then writes these in the registers. The • GAccumulator – Accumulator register with syn-
computation is then a simple connection of adders and chronous reset and overflow detection.
multipliers with suitable pipelining.
• GRandGeneratorLFSR – Linear shift feedback
Since an 8-bit color depth is insufficient for drawing register (LSFR) implementing a general pseudo-
a color shift, the dithering technique is used through random number generator. This is requires pri-
the simple generation of noise generated by the GRand- marily for the creation of a smooth color shift in
GeneratorLFSR block. the drawn background.

• GNonOverflowCounter – A non-overflowing bidi-

3) Panel Image (PanelImageROM ) rectional synchronous counter with synchronous
reset and pre-divisor. This is used to set the view-
This ROM stores the panel image drawn on the screen ing angle.
(Fig. 14). The image has a resolution of 640×32 with a
2-bit color depth. The colors on the image are indexed. • GAccelerateCounter – Bidirectional binary
counter with customizable TOP value and syn-
chronous reset. The counter freely overflows
in both directions, has a configurable counter
Fig. 14: One of the images stored in PanelImageROM . acceleration speed and a pre-divisor of the clock
signal. This is used to set the azimuth and
Image data are stored in the ROM organized as elevation and creates the effect of "gradual"
(640 × 32) × 2 bits. The address is this computed from rotation of the object on the screen.
coordinates and the data output is 2-bit – i.e. 4 indexed
colors in total. The output of the previous ROM is sent • GBcdCounter – Generic BCD increasing counter
to the look-up table which converts the index to a spe- with synchronous reset.
cific color with a 256 color depth. Figure 15 illustrates
the realization of the memory. • GBcd7Display – BCD display driver consisting of
7 segmented digits. Forms the FPS indicator to-
gether with GBcdCounter .

• GBlockRAM – 2-port block RAM with a single

clock signal.

• GSerialDivider – Unsigned generic serial divisor.

Designed based on the application note [2]. The
computation takes approximately 2n + 2 clock cy-
Fig. 15: Storage of the panel image. cles (where n is the bus width), which allows for
future improvement.

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4. Future Work Individual Rivyera cards are equipped with massive

FPGA circuits of the S6-LX150 line. Each user FPGA
circuit on the card is connected to a memory subsys-
Parallel processing may under certain conditions be
tem consisting of up to 512 MiB DDR3 RAM, 256 kiB
used to improve the efficiency of the 3D functions.
of EEPROM memory and a micro SD/HC Flash (se-
However, it needs to be said that this method is only
lected). Data transmission between individual FPGA
suitable for algorithms which can be efficiently paral-
circuits will be carried out through the bus architecture
lelized. In this case it is possible to use a large number
and connection diagrams implemented in the sophisti-
of FPGA circuits which are interconnected via appro-
cated API.
priate data channels. Currently, there exists a num-
ber of commercially available HPC (High-Performance
Computing) systems ranging from dozens to thousands
of FPGA circuits. These computational units may sig-
nificantly speed up the computations in various areas,
such as medical imaging, cryptography, statistical data
processing, biological sciences etc.
Efficient HPC systems usually place FPGAs in in-
Fig. 18: HW and SW computing methods in Rivyera HPC.
dividual cards inserted into slots of the motherboard
with high data throughput. Communication between
the user and FPGA cards is secured by the host com- Assuming the efficient use of connections and op-
puter via the corresponding API interface. timal digit design, we can reach a data throughput
between adjacent FPGAs of up to 2 Gb · s−1 . How-
The Rivyera HPC (SciEngines GmbH) system with ever, the actually usable throughput may differ based
Xilinx FPGA circuits was selected for the further de- on API and FPGA limitations [8] An efficient systolic
velopment of the project. The efficient use of such a chain can be used between FPGA circuits on a single
HPC system is based especially on the design of a suit- card as well as between individual cards in the system.
able design of the logical structure for FPGA circuits The Rivyera can be equipped with up to 128 FPGA
and the programming of applications for data exchange circuits (or up to 256 FPGA circuits by doubling the
between the user and the FPGA logic. The digit de- number of cards).
sign for FPGA based on VHDL can be created through
the Xilinx ISE development kit. The programming of
application software on the host PC is then possible
through the API for C and Java.

Fig. 16: Overview of a Rivyera HPC with FPGA circuits. Fig. 19: RIVYERA supercomputer with 256 FPGAs [8].

Rivyera HPC offers a highly efficient bus system

which allows the organization of FPGA circuits into 5. Conclusion
a systolic chain, which minimizes delays in the system
caused by connections.
The implementation of the project is intended for the
Xilinx Spartan-6 circuit with a graphics output to
VGA, e.g. [3]. The procedures and outputs of the
project are useful in many built-in control systems
which are based on FPGA circuits. The most inter-
esting applications will probably be found in techni-
cal equipment which relies on virtualization and real-
time computations. One of the areas where highly ef-
ficient computations and parallelism are both required
is medical data imaging. Another advantage of this
Fig. 17: Linear systolic chain based on FPGA [8]. hardware-based solution is that it increases functional

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CONTROL ENGINEERING VOLUME: 13 | NUMBER: 1 | 2015 | MARCH

safety, which is a difficult task in the case of sequen- ISSN 1350-2409. DOI: 10.1049/ip-cds:20040838.
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even home care systems, see [7]. Techniques for design amples and notes written with C++ [online]. 2013.
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tronics, Communications and Networks (CEC-
Number of FSMs 12 Net). XianNing: IEEE, 2011, pp. 3917–3921.
Number of Block RAMs 32 of 32 (100 %) ISBN 978-1-61284-458-9. DOI: 10.1109/CEC-
Number of Slice LUTs 4237 of 9112 (46 %) NET.2011.5768261.
Number of bonded IOBs 28 of 232 (12 %)
Number of BUFG/BUFCTRLs 3 of 16 (18 %) [7] PENHAKER, M., M. STANKUS, J. KIJONKA
Number of DSP48A1s 10 of 32 (31 %)
Number of PLL_ADVs 1 of 2 (50 %) and P. GRYGAREK. Design and Application of
Mobile Embedded Systems for Home Care Ap-
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Acknowledgment Bali Island: IEEE, 2010, pp. 412–416. ISBN 978-
1-4244-6079-3. DOI: 10.1109/ICCEA.2010.86.
This paper has been elaborated in the framework of [8] SciEngines GmbH. 2014. Available at: http://
the project "Support research and development in the www.sciengines.com.
Moravian-Silesian Region 2013 DT 1 - International
research teams" (RRC/05/2013). Financed from the
budget of the Moravian-Silesian Region. The work About Authors
and the contributions were supported by the project
SP2014/194 "Biomedicinske inzenyrske systemy X".
Vladimir KASIK was born in Vyskov, Czech Re-
public, in 1973. He received his M.Sc. in Cybernetics,
Automation and Control from the Brno University of
References Technology, Czech Republic, in 1996 and his Ph.D. in
Technical Cybernetics from VSB–Technical University
[1] KASIK, V., A. KURECKA and P. POSPECH. of Ostrava, Czech Republic in 2000. Currently he is
3D Graphics Processing Unit with VGA Output. an assistant professor at VSB–Technical University of
IEE Proceedings - Circuits, Devices and Systems. Ostrava, Department of Cybernetics and Biomedical
2005, vol. 152, iss. 3, pp. 388–393. ISSN 1474-6670. Engineering, Ostrava, Czech Republic, where he
DOI: 10.3182/20130925-3-CZ-3023.00081. teaches and collaborates with industry in the areas of
programmable logic, electronics, embedded and con-
[2] AVR200. Multiply and Divide Routines. At-
trol systems. He is the author of several international
mel, 2009. Available at: http://www.atmel.com/
publications and in earlier years he attended a vari-
Images/doc0936.pdf.
ety of lecture stays in Universite Joseph Fourier and
[3] Nexys3. Board Reference Manual. Digilent, 2013. L’Institut National Polytechnique de Grenoble, France.
Available at: http://www.digilentinc.com/
Data/Products/NEXYS3/Nexys3_rm.pdf. Ales KURECKA was born in 1989. He received
his M.Sc. degree from VSB–Technical University of
[4] BENSAALI, F., A. AMIRA and A. BOURI- Ostrava, Czech Republic in 2013. He is currently a
DANE. Accelerating matrix product on re- Ph.D. student at the department of Cybernetics and
configurable hardware for image processing Biomedical Engineering. His research interests include
applications. IEE Proceedings - Circuits, Devices primarily localization techniques and embedded sys-
and Systems. 2005, vol. 152, iss. 3, pp. 236–246. tems.

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