SLLS025A − JULY 1986

• Dual Circuits Capable of Driving D OR P PACKAGE

High-Capacitance Loads at High Speeds (TOP VIEW)

• Output Supply Voltage Range up to 24 V

1A 1 8 VCC1
• Low Standby Power Dissipation E 2 7 1Y
2A 3 6 2Y
description GND 4 5 VCC2
The SN75372 is a dual NAND gate interface
circuit designed to drive power MOSFETs from logic symbol†
TTL inputs. It provides high current and voltage
2
levels necessary to drive large capacitive loads at E EN
high speeds. The device operates from a VCC1 of
5 V and a VCC2 of up to 24 V. 1 TTL/MOS 7
1A 1Y
The SN75372 is characterized for operation from 3 6
2A 2Y
0°C to 70°C.
† This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.

schematic (each driver)

VCC1 VCC2

To Other
Driver

Input A
Output Y
Enable E

GND

To Other
Driver

       !"#   $"%&! '#( Copyright  1986, Texas Instruments Incorporated
'"! !  $#!! $# )# #  #* "# Revision Information
'' +,( '"! $!#- '#  #!#&, !&"'#
#-  && $##(

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3−1

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

 




SLLS025A − JULY 1986

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC1 (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Supply voltage range, VCC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 25 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Peak output current, VO (tw < 10 ms, duty cycle < 50%) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Voltage values are with respect to network GND.
DISSIPATION RATING TABLE
25°C
TA = 25 C DERATING FACTOR 70°C
TA = 70 C
PACKAGE
POWER RATING ABOVE TA = 25°C POWER RATING
D 725 mW 5.8 mW/°C 464 mW
P 1000 mW 8.0 mW/°C 640 mW

recommended operating conditions

MIN NOM MAX UNIT
Supply voltage, VCC1 4.75 5 5.25 V
Supply voltage, VCC2 4.75 20 24 V
High-level input voltage, VIH 2 V
Low-level input voltage, VIL 0.8 V
High-level output current, IOH −10 mA
Low-level output current, IOL 40 mA
Operating free-air temperature, TA 0 70 °C

3−2 •
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SLLS025A − JULY 1986

electrical characteristics over recommended ranges of VCC1, VCC2, and operating free-air
temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT
VIK Input clamp voltage II = − 12 mA −1.5 V
VIL = 0.8 V, IOH = − 50 µA VCC2 −1.3 VCC2 −0.8
VOH High-level output voltage V
VIL = 0.8 V, IOH = − 10 mA VCC2 −2.5 VCC2 −1.8
VIH = 2 V, IOL = 10 mA 0.15 0.3
VOL Low-level output voltage VCC2 = 15 V to 24 V, VIH = 2 V, V
0.25 0.5
IOL = 40 mA
VF Output clamp-diode forward voltage VI = 0, IF = 20 mA 1.5 V
Input current at maximum input
II VI = 5.5 V 1 mA
voltage
Any A 40
IIH High-level input current VI = 2.4 V µA
A
Any E 80
Any A −1 −1.6
IIL Low-level input current VI = 0.4 V mA
Any E −2 −3.2
Supply current from VCC1, both
ICC1(H) 2 4 mA
outputs high VCC1 = 5.25 V, VCC2 = 24 V,
Supply current from VCC2, both All inputs at 0 V, No load
ICC2(H) 0.5 mA
outputs high
Supply current from VCC1, both
ICC1(L) 16 24 mA
outputs low VCC1 = 5.25 V, VCC2 = 24 V,
Supply current from VCC2, both All inputs at 5 V, No load
ICC2(L) 7 13 mA
outputs low
Supply current from VCC2, standby VCC1 = 0, VCC2 = 24 V,
ICC2(S) 0.5 mA
condition All inputs at 5 V, No load
† All typical values are at VCC1 = 5 V, VCC2 = 20 V, and TA = 25°C.

switching characteristics, VCC1 = 5 V, VCC2 = 20 V, TA = 25°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tDLH Delay time, low-to-high-level output 20 35 ns
tDHL Delay time, high-to-low-level output 10 20 ns
tTLH Transition time, low-to-high-level output 20 30 ns
CL = 390 pF, RD = 10 Ω, See Figure 1
tTHL Transition time, high-to-low-level output 20 30 ns
tPLH Propagation delay time, low-to-high-level output 10 40 65 ns
tPHL Propagation delay time, high-to-low-level output 10 30 50 ns

•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265 3−3
•
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SLLS025A − JULY 1986

PARAMETER MEASUREMENT INFORMATION

≤ 10 ns ≤ 10 ns

5V 20 V 3V
Input 90% 90%
1.5 V 1.5 V 10%
10% 0V
VCC1 VCC2 0.5 µs
Input

tPHL tPHL
Pulse
Generator RD tDHL tTLH
(see Note A) Output tTHL
CL = 390 pF VOH
GND (see Note B) tDLH
VCC2 −3 V VCC2 −3 V
2.4 V Output 2V 2V
VOL
TEST CIRCUIT VOLTAGE WAVEFORMS

NOTES: A. The pulse generator has the following characteristics: PRR = 1 MHz, ZO ≈ 50 Ω.
B. CL includes probe and jig capacitance.

Figure 1. Test Circuit and Voltage Waveforms, Each Driver

TYPICAL CHARACTERISTICS

HIGH-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE

vs vs
HIGH-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT CURRENT
VCC2 0.5
VCC1 = 5 V VCC1 = 5 V
VCC2 = 20 V VCC2 = 20 V
OH − High-Level Output Voltage − V

VOL − Low-Level Output Voltage − V

VCC2 −0.5 VI = 0.8 V VI = 2 V

0.4

VCC2 −1 TA = 70°C
TA = 25°C
0.3
TA = 70°C TA = 0°C
VCC2 −1.5

0.2
VCC2 −2
VV0H

TA = 0°C
VOL

0.1
VCC2 −2.5

VCC2 −3 0
− 0.01 − 0.1 −1 −10 −100 0 20 40 60 80 100
IOH − High-Level Output Current − mA IOL − Low-Level Output Current − mA

Figure 2 Figure 3

3−4 •
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•
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SLLS025A − JULY 1986

TYPICAL CHARACTERISTICS
POWER DISSIPATION (BOTH DRIVERS)
vs
VOLTAGE TRANSFER CHARACTERISTICS FREQUENCY
24 1200
VCC1 = 5 V VCC1 = 5 V
VCC2 = 20 V VCC2 = 20 V
20 No Load 1000 Input: 3-V Square Wave

D − Power Dissipation − mW
TA = 25°C 50% Duty Cycle
O − Output Voltage − V

TA = 25°C
16 800
CL = 600 pF

CL = 1000 pF
12 600
CL = 2000 pF

8 400 CL = 4000 pF
VV)

PT
P
4 200
CL = 400 pF
Allowable in P Package Only
0 0
0 0.5 1 1.5 2 2.5 10 20 40 100 200 400 1000
f − Frequency − kHz
VI − Input Voltage − V

Figure 4 Figure 5

PROPAGATION DELAY TIME, PROPAGATION DELAY TIME,

LOW-TO-HIGH-LEVEL OUTPUT HIGH-TO-LOW-LEVEL OUTPUT
vs vs
FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
200 200
VCC1 = 5 V
180 180 VCC2 = 20 V
CL = 4000 pF
RD = 10 Ω
See Figure 1
PLH − Propagation Delay Time,

t PHL − Propagation Delay Time,

160 160
High-to-Low-Level Output − ns

CL = 4000 pF
Low-to-High-Level Output − ns

VCC1 = 5 V
140 VCC2 = 20 V 140
RD = 10 Ω
120 See Figure 1 120
CL = 2000 pF
100 100 CL = 2000 pF

80 80
CL = 1000 pF CL = 1000 pF
60 60
tkSVR

kSVR

CL = 200 pF CL = 390 pF CL = 200 pF

40 40 CL = 390 pF

20 20
CL = 50 pF CL = 50 pF
0 0
0 10 20 30 40 50 60 70 80 0 10 20 30 40 50 60 70 80
TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C

Figure 6 Figure 7

•
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SLLS025A − JULY 1986

TYPICAL CHARACTERISTICS

PROPAGATION DELAY TIME, PROPAGATION DELAY TIME,

LOW-TO-HIGH-LEVEL OUTPUT HIGH-TO-LOW-LEVEL OUTPUT
vs vs
VCC2 SUPPLY VOLTAGE VCC2 SUPPLY VOLTAGE
200 200
VCC1 = 5 V
VCC1 = 5 V
180 CL = 4000 pF 180 RD = 10 Ω
RD = 10 Ω
TA = 25°C
TA = 25°C
t PLH − Propagation Delay Time,

t PLH − Propagation Delay Time,

160 160 See Figure 1
Low-to-High-Level Output − ns

High-to-Low-Level Output − ns
See Figure 1 CL = 4000 pF
140 140

120 120
CL = 2000 pF
100 100 CL = 2000 pF

80 80
CL = 1000 pF CL = 1000 pF
60 60
CL = 200 pF CL = 390 pF CL = 390 pF
40 40 CL = 200 pF

20 20
CL = 50 pF CL = 50 pF
0 0
0 5 10 15 20 25 0 5 10 15 20 25
VCC2 − Supply Voltage − V VCC2 − Supply Voltage − V

Figure 8 Figure 9

PROPAGATION DELAY TIME, PROPAGATION DELAY TIME,

LOW-TO-HIGH-LEVEL OUTPUT HIGH-TO-LOW-LEVEL OUTPUT
vs vs
LOAD CAPACITANCE LOAD CAPACITANCE
200 200
VCC1 = 5 V VCC1 = 5 V
180 VCC2 = 20 V 180 VCC2 = 20 V
TA = 25°C TA = 25°C
t PLH − Propagation Delay Time,

t PLH − Propagation Delay Time,

Low-to-High-Level Output − ns

High-to-Low-Level Output − ns

160 See Figure 1 160 See Figure 1

140 140
RD = 24 Ω RD = 24 Ω
120 RD = 10 Ω 120

100 100
RD = 10 Ω
80 80

RD = 0
kSVR

kSVR

60 60
RD = 0
40 40

20 20

0 0
0 1000 2000 3000 4000 0 1000 2000 3000 4000
CL − Load Capacitance − pF CL − Load Capacitance − pF

Figure 10 Figure 11
NOTE: For RD = 0, operation with CL > 2000 pF violates absolute maximum current rating.

3−6 •
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•
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SLLS025A − JULY 1986

THERMAL INFORMATION

power dissipation precautions

Significant power may be dissipated in the SN75372 driver when charging and discharging high-capacitance
loads over a wide voltage range at high frequencies. Figure 5 shows the power dissipated in a typical SN75372
as a function of load capacitance and frequency. Average power dissipated by this driver is derived from the
equation
PT(AV) = PDC(AV) + PC(AV) = PS(AV)
where PDC(AV) is the steady-state power dissipation with the output high or low, PC(AV) is the power level during
charging or discharging of the load capacitance, and PS(AV) is the power dissipation during switching between
the low and high levels. None of these include energy transferred to the load, and all are averaged over a full
cycle.
The power components per driver channel are
tHL tLH
P t + PL t L
PDC(AV) = H H
T

P [ C V2 f
C(AV) C
tH
PLH t LH + PHL t HL tL
PS(AV) =
T
T = 1/f

where the times are as defined in Figure 14. Figure 12. Output Voltage Waveform

PL, PH, PLH, and PHL are the respective instantaneous levels of power dissipation, C is the load capacitance.
VC is the voltage across the load capacitance during the charge cycle shown by the equation
VC = VOH − VOL
PS(AV) may be ignored for power calculations at low frequencies.
In the following power calculation, both channels are operating under identical conditions:
VOH =19.2 V and VOL = 0.15 V with VCC1 = 5 V, VCC2 = 20 V, VC = 19.05 V, C = 1000 pF, and the
duty cycle = 60%. At 0.5 MHz, PS(AV) is negligible and can be ignored. When the output voltage is high, ICC2
is negligible and can be ignored.
On a per-channel basis using data sheet values,

P
DC(AV)
ƪ ǒ Ǔ
+ (5 V) 2 mA ) (20 V) 0 mA
2 2
ǒ Ǔƫ (0.6) ) ƪ(5 V) ǒ16 2mAǓ ) (20 V) ǒ7 mA
2
Ǔƫ (0.4)
PDC(AV) = 47 mW per channel
Power during the charging time of the load capacitance is
PC(AV) = (1000 pF) (19.05 V)2 (0.5 MHz) = 182 mW per channel
Total power for each driver is
PT(AV) = 47 mW + 182 mW = 229 mW
and total package power is
PT(AV) = (229) (2) = 458 mW.

•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265 3−7
•
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443

 




SLLS025A − JULY 1986

APPLICATION INFORMATION

driving power MOSFETs

The drive requirements of power MOSFETs are much lower than comparable bipolar power transistors. The
input impedance of a FET consists of a reverse biased PN junction that can be described as a large capacitance
in parallel with a very high resistance. For this reason, the commonly used open-collector driver with a pullup
resistor is not satisfactory for high-speed applications. In Figure 12(a), an IRF151 power MOSFET switching
an inductive load is driven by an open-collector transistor driver with a 470-Ω pullup resistor. The input
capacitance (Ciss) specification for an IRF151 is 4000 pF maximum. The resulting long turn-on time due to the
combination of Ciss and the pullup resistor is shown in Figure 12(b).

48 V

V OL − Gate Voltage − V
5V
4
470 Ω
3
4 8
7 1/2 SN75447
IRF151 2
3

OH − VOL
TLC555P 1
6 5
0

V0H
0 0.5 1 1.5 2 2.5 3

V
2 1 t − Time − µs

(b)

(a)

Figure 13. Power MOSFET Drive Using SN75447

3−8 •
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•
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SLLS025A − JULY 1986

APPLICATION INFORMATION

A faster, more efficient drive circuit uses an active pullup as well as an active pulldown output configuration,
referred to as a totem-pole output. The SN75372 driver provides the high speed, totem-pole drive desired in
an application of this type, see Figure 13(a). The resulting faster switching speeds are shown in Figure 13(b).

48 V

5V
M

V OL − Gate Voltage − V
4
4 8
7 3

TLC555P 3 2
IRF151
6 5 1/2 SN75372 1

OH − VOL
2 1
0

V0H
0 0.5 1 1.5 2 2.5 3

V
t − Time − µs
(b)
(a)

Figure 14. Power MOSFET Drive Using SN75372

Power MOSFET drivers must be capable of supplying high peak currents to achieve fast switching speeds as
shown by the equation
VC
I +
pk tr

where C is the capacitive load, and tr is the desired drive time. V is the voltage that the capacitance is charged
to. In the circuit shown in Figure 13(a), V is found by the equation
V = VOH − VOL
Peak current required to maintain a rise time of 100 ns in the circuit of Figure 13(a) is

(3 * 0)4(10 *9)
I + + 120 mA
PK 100(10 *9)

Circuit capacitance can be ignored because it is very small compared to the input capacitance of the IRF151.
With a VCC of 5 V, and assuming worst-cast conditions, the gate drive voltage is 3 V.
For applications in which the full voltage of VCC2 must be supplied to the MOSFET gate, the SN75374 quad
MOSFET driver should be used.

•
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 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

SN75372D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 75372

SN75372DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 75372

SN75372P ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 SN75372P

SN75372PE4 ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 SN75372P

SN75372PSR ACTIVE SO PS 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 A372

SN75372PSRE4 ACTIVE SO PS 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 A372

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 20-Dec-2018

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN75372DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 20-Dec-2018

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN75372DR SOIC D 8 2500 340.5 338.1 20.6

Pack Materials-Page 2
 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

www.ti.com
 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

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