A Comparative Study of Linearity Enhancement

Techniques of Power Mixer in Wideband

Communication Systems
Phuong Nguyen, Hao Do, Cuong Huynh and Anh Tran
Faculty of Electrical and Electronic Engineering, HCMUT
E-mail: [email protected], [email protected],
[email protected], [email protected]

Abstract—This paper covers techniques that improve the

power mixer linearity used in wideband communication systems.
The power mixer is designed to operate in the 0.3-6GHz range
with IF signals from 5-100MHz. The circuit designs in the
topic use 28nm CMOS technology. The mixer cell features a
design based on an active double-balanced mixer. Using several
techniques such as Derivative Superposition, Current Bleeding,
Current Injection, and Negative Resistance Compensation, one Fig. 1. Diagram of wireless transceiver system.
by one, comparing the linearity of the techniques to choose which
technique has the best result to improve mixer’s linearity. Layout
for NRC technique (providing stable linearity and meeting the such as intermodulation interference, power compression in
requirements set). From the simulation results, the power mixer the system, and deteriorating the quality of the transmitted
using NRC technique achieves IIP3 of 12.75dBm, OIP3 is 32.93 signal. Besides, we can see that the linearity’s mixer block
dBm, IRR is 254dBc, LO-RF isolation is 227 dBc, P1dB is linearity plays a decisive role in the linearity of the whole
16.92dBm and power consumption is 589.5 mW.
generator system. Therefore, the topic focuses on improving
Index Terms—mixer, up-conversion, power mixer, linearity
enhancement, Derivative Superposition (DS), Current Injection the linearity of mixer.
(CI), Current Bleeding (CB), Negative Resistance Compensation This topic researches and applies advanced linearity tech-
(NRC). niques for power mixers in wideband communication systems
with bandwidth of 5-100 MHz, working frequency from 0.3
I. I NTRODUCTION to 6.0 GHz. There are several techniques to enhance linearity
U rrently,the demands for wideband wireless communi- such as derivative superposition, third-order distortion can-
C cation systems are increasing rapidly over the past few
years. Wireless communication is moving toward 5G cellular
cellation and linearization for the MOSFET transconductance
stage.
network, Wi-Fi 6 with wideband, high data transmission speed, II. D ESIGN AND A NALYSIS
low cost and low power consumption. The above system char-
A. Structure of Power Mixer and the Optimum Parameters
acteristics have gradually become important issues in technical
research and development of wireless wideband systems. In The power mixer is designed with 64 mixer cells with a
telecommunication, 5G cellular network reduces latency to just similar structure. The above mixer cells are divided into 7
1 millisecond compared to 50 milliseconds of 4G standard. groups with the number of cells in groups increasing to adjust
Also, the new Wi-Fi 6 standard has sped up to 10Gbps. the output power.
Every day, many electronic devices such as phones, tablets, One basic mixer cell consists of 3 stage: transconductace
smart homes connect to wireless networks and data networks. stage, switching stage and transimpedance stage. This mixer
Therefore, it is necessary to design transceiver systems with cells also have: First, cascade-stage (M3 and M4) is added to
higher bandwidth and reasonable power consumption. With increase output impedance, increase the isolation between IF
the ability to scale transistor size, systems using CMOS port and LO, RF port. Besides, cascode MOSFETs are used to
technology have increasingly high operating frequency and on/off mixer cell, thereby adjusting the output power. Second,
switching speed. Besides the above benefits, scale down the the 50Ω output impedance is used for wide-band impedance
size of CMOS technology also causes strong nonlinearity and matching. This load is shared by 64 mixer cell. Third, low
low gain [6]. pass filters (R1-C1 and R2-C2) helps to minimize interference
Fig.1 shows a schematic diagram of a wireless transceiver from control voltage source (VCTR) and filter out LO leakage
system. Nonlinearity of transmitter causes many problems signals from M5-8 to the gate of M3-4 through C1, C2.
Fig.3. Mixer cells are divided into 7 groups and controlled
by 7 bits. It is permissible to adjust power gain in the range
978-1-7281-5353-7/19/$31.00 ©2019 IEEE from 0 to 36dB with each power step of 6dB [7].
 Fig. 4. a) Schematic of half mixer cell. b) Parasitic capacitor in NMOS.

Fig. 2. Structure of mixer cell.

Fig. 3. Power mixer block diagram.

There are three main parameters to be optimized such as

conversion gain, port to port isolation and linearity:
W Fig. 5. ”Two-tone” method [1].
gm = µn Cox (VGS − Vth ) (1)
L
Port to port isolation: Because mixer structure is symmetrical
and balanced, isolation from LO to RF port is very good. IIP3 of transconductance stage is calculated by [1]:
With high-frequency signals, values of capacitances are small, r
signals from the transistor terminals can easily pass through 4 2 − 3a(VGS0 − Vth )
AIIP 3 = (VGS0 − Vth ) (4)
the capacitor to the other terminals. 3 a
Consider transistor operating in saturation region. Parasitic
capacitors at the gate and drain terminals are calculated by the v
u8
formulas:
GS0 − Vth )
u (V
3
u
CGD = W Cov (2) AIIP 3 =u − 4(VGS0 − Vth )2 (5)
t µ0
2 +Θ
CGS = W Lef f Cox + W Cov (3) 2νsat L
3
From (2) and (3), when increasing size of transistor to IIP3 increases when VGS0 − Vth increasing. When VGS0 −
increase CG, parasitic capacitor also increases, leading to more 1
Vth = µ0 , IIP3 reach to maximum value:
signal leakage. Therefore, when designing, it is necessary to 3
trace off between parameters to optimize the circuit com- 2νsat L
pletely.
2 1
Linearity: Linearity is evaluated through the third-order in- AIIP 3 = µ0 (6)
termodulation intercept point or the third harmonic component 3 2νsat L +Θ
(Intermodulation-IM) due to interference. For mixers, linearity
is determined by the transconductance stage. Since it is the From (4),(5) and (6), it can be seen that the linearity depends
main amplifier in the circuit, the nonlinearity of the M1- on the DC bias voltage at the gate terminal of M1-M2 and the
M2 transistor leads to the nonlinearity of the circuit. M1-2 channel length (L) of those transistors.
transistors are a common source, using a small channel length, In addition, to ensure the linearity, transistors of cascade-
so transistors are strongly influenced by mobility degradation. stage and switching stage must have a large size enough to
IP3 can be defined with ”two-tone” method [1] as Fig. 5. ensure adequate current.
 The derivative superposition method is applied at the
transconductance stage by adding two transistors M10 and
M20. They are provided vgs so that both operate in the
saturation region while M10 and M20 are provided vgs’ so
that they operate in sub-threshold region.
2) Current Bleeding (CB) technique: Consider a single bal-
anced active mixer using Current Bleeding by adding PMOS
MBld. This PMOS has two tasks: being an additional current
source as well as being a member of the switching stage. MBld
helps increase the total transconductance of transconductance
stage, thereby increasing the conversion gain of the system
[5].
Conversion gain of mixer is calculated by:
Fig. 6. Transconductance of transistor according to Vgs in CMOS 28nm
technology. 2
CG = (gm1 + gmBld )ZL (9)
π

Fig. 8. Schematic of single balance active mixer using CB technique.

Fig. 7. Schematic of mixer using DS technique.

B. Enhance linearity techniques

1) Derivative Superposition - DS technique: Consider tran-
sistor operating in the common source mode, iDS current is
represented in Taylor series as follows:
2 3
iDS = IDC + gm vgs + gm2 vgs + gm3 vgs + ... (7)

IIP3 is calculated by:

r
4 gm
IIP3 = (8)
3 gm3
Fig. 6 shows transconductance of NMOS according to Vgs .
From (8), IIP3 may be increased by gm or decreasing gm3.
With the desire to bring gm3 to 0 when operating in the
Fig. 9. Schematic of mixer using CB technique.
saturated region, the proposed solution is to add a parallel
MOSFET and polarize in to working in sub-threshold region PMOS pair having high output impedance parallel with
[2]. Meanwhile, gm3 of system is equal to the sum of gm3 of NMOSs having a low output impedance of switching stage.
the two transistors. The added adjustment of the voltage vgs Then, IF signal can easily flow into switching stage, which
and size of MOSFET can help gm3 to be zero at the desired makes improve linearity. The more size of NMOSs, the
input voltage range. lower output impedance, but the bigger parasitic capacitance.
Therefore, it is necessary to optimize the size of these NMOS
so that the smallest possible impedance value is available and
the parasitic capacitor value is not too large.

Fig. 11. Schematic of single balance active mixer using NRC technique.

Fig. 10. Schematic of single balance active mixer using CI technique.

3) Current Injection (CI) technique: As mentioned in the

above section, the common-source transconductance limits
the linearity of mixer circuit. Therefore, the transconductance
stage must be linearized.
The power consumption of Gilbert-cell mixer can be de-
clined by using low supply voltage. However, the linearity and
conversion gain will also be reduced because of low supply
voltage. Hence, like the CB technique, three PMOS transistors
M9-M11 is implemented as a current injection to compensate
for the decrease of linearity and conversion gain [8]. This
technique increases Ibias of mixer. Besides, the mixer’s CG
and linearity are improved without modification current via
the switching stage. Furthermore, low power is obtained by
reducing the supply voltage without too much influence on Fig. 12. OIP3 simulation of power mixer using DS technique @6GHz.
gain.
4) Negative Resistance Compensation (NRC) technique:
Fig. 11 two transistors M9, M10 are connected cross-coupled.
Then, M9, M10 operate as a negative impedance to compen-
sate for the positive impedance generated by the switching
stage. In other words, M9 and M10 give −gm9,10 to re-
duce Gm,LO look from the switching stage. This technique
increases the flow through the transconductace stage and
conversion gain [8]. The IF currents flowing into the LO
switches and conversion gain become:
Gm,LO
iLO = gm1,2 vIF (10)
2(Gm,LO − gm9,10 )
2 Gm,LO
CG = gm1,2 Rout (11)
π (Gm,LO − gm9,10 )

III. S IMULATION R ESULTS

Fig. 13. P1dB simulation of power mixer using DS technique @6GHz.
The power mixer (64 mixer cells) with four techniques
and CMOS 28nm technology is simulated by using Cadence
 TABLE I
S UMMARY OF I NSTANCE PARAMETER

Technique Transistor Size

M1, M2 w/l=54/0.24µm
Mixer cell M3, M4 w/l=60/0.12µm
M5, M8 w/l=12/0.15µm
DS techique M10, M20 w/l=300/0.06µm
CB techique M9, M10 w/l=35.84/0.3µm
CI technique M11 w/l=144/0.22µm
M9, M10 w/l=7/0.15µm
NRC technique M9, M10 w/l=90/0.24µm
C1, C2 500fF
R1, R2 500kΩ

simulator. Use an IF signal generator with a DC level of Fig. 14. Comparison of OIP3 and IIP3 between techniques.
600mV and an LO oscillator with a duty cycle of 50
Configuration simulated parameter includes: for LO fre-
quency ¡ 3.4GHz, use input IF signal 20MHz; for LO fre-
quency ¿ 3.4GHz, use input IF signal 100MHz; the IF signal
input power is fixed to -40dBm.
The table below contains the dimensions of the transistors
used:
Simulation results of power mixer’s linearity using DS
technique are shown in Fig. 11 and Fig. 12.
The parameters of the power mixer from techniques are
summarized in table II, the simulation results at 6GHz.
Based on Fig. 14, NRC technique has better simulation
results that meet the set requirements. Conducting the mixer
layout with NRC technique (Fig. 15) and the results of post-
layout are shown in Fig. 16.

TABLE II
T HE P ERFORMANCE C OMPARISON OF P OWER M IXER

Parameter Mixercell DS CB CI NRC

OIP3(dBm) 29.86 34.13 35.93 33.73 32.93
IIP3(dBm) 10.29 14.00 16.47 11.52 12.75
CG(dB) 19.57 20.13 19.46 22.21 20.18
IIR(dBc) 267.2 239.5 256.5 274 254
Fig. 15. Layout of mixer cell using NRC technique.
LO-RF 247 228 250 226 227
leakage(dBc)
P1dB(dBm) 15.92 16.6 12.07 15.31 16.92
Power 579.6 593.64 579.96 579.96 589.5
Consumption(dBm)

C ONCLUSION
This paper presents the design and simulation of a power
mixer for wideband communication systems in comparison
with linearity enhancement methods using 28nm CMOS tech-
nology. Four techniques help to increase linearity at high
frequency, but reduces linearity at low frequency. Mixer using
DS technique has higher linearity at 1÷6GHz but it consumes
more 15.04 mW. Mixer using CB and CI technique has not
consumes more power but can only improve linearity at IIP3
3÷6GHz and 1.5÷6GHz. The double-balanced active mixer Fig. 16. Comparison of OIP3 and IIP3 between pre-layout and post-layout
after applying NRC technique has increased linearity at almost of mixer cell using NRC technique.
band and met the specifications set.
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