D. Y. Patil College of Engineering, Akurdi, Pune-44.

Department of Computer Engineering

__________________________________________________________________________

Multiple Choice Questions

SUB: Digital Electronics and Logic Design Class: SE

Unit – I Quiz 1

1. The number of digits in octal number system is

a.8 b.7 C. 10 D. none

2. The number of digits in Hexadecimal system is

a.15 b. 17 c.16 d. 8
3.The number of bits in a nibble is
a.16 b. 5 c.4 d. 8

4.The digit F in Hexadecimal system is equivalent to _____in decimal system

a.16 b. 15 c. 17 d. 8

5.Which of the following binary numbers is equivalent to decimal 10

a.1000 b. 1100 c.1010 d.1001
6.The number FF in Hexadecimal system is equivalent ___in decimal system
a.256 b. 255 c. 240 d. 239

7.IC s are
a. analog b. digital c. both analog and digital d. mostly analog
8.The rate of change of digital signals between High and Low Level is
a. very fast b.fast c. slow d. very slow
9. Digital circuits mostly use
a. Diodes b. Bipolar transistors
c. Diode and Bipolar transistors d. Bipolar transistors and FETs

10.Logic pulser
a. generates short duration pulses
b. generate long duration pulses
c. generates long and short duration
d. none of above
11.What is the output state of an OR gate if the inputs are 0 and 1?
a.0 b. 1 c. 3 d. 2
12.What is the output state of an AND gate if the inputs are 0 and 1?
 a.0 b. 1 c. 3 d. 2
13.A NOT gate has ______
a. Two inputs and one output
b. One input and one output
c. One input and two outputs
d. none of above
14.An OR gate has _______
a. Two inputs and one output
b. One input and one output
c. One input and two outputs
d. none of above
15.The output of a logic gate can be one of two _____
a. Inputs b. Gates C. states d.none
16.Logic states can only be ___ or 0
a.3 b. 1 c. 3 d. 2
17.The output of a ____ gate is only 1 when all of its inputs are 1
a. NOR b. XOR c. AND d. NOT
18.A NAND gate is equivalent to an AND gate plus a _____gate put together.
a. NOR b. XOR c. AND d. NOT
19.The decimal number 127 may be represented by
a. 1111 1111B b. 1000 0000B c. EEH d. 0111 1111
20. Numbers are stored and transmitted inside a computer in
a. binary form b. ASCII code form c. decimal form d. alphanumeric form

21.. A byte corresponds to

a. 4 bits b. 8 bits c. 16 bits d. 32 bits

22.. A Kb corresponds to
a. 1024 bits b. 10bytes c.210 bytes d. 100 bytes
23. Convert (9B2 - 1A) H to its decimal equivalent.
a. 2482.110 b. 2488.210 c. 2483.210 d. 2484.110
24. Convert 0.640625 decimal numbers to its octal equivalent.
a. (0.61) 8 b. (0.51) 8 c. (0.72) 8 d. (0.54) 8
25. What is commutative property of Boolean algebra.
a. A+B=B+A b. A.B = B.A c. Both of above d. None of above
 Unit – I Quiz2

  1. Convert the fractional binary number 0001.0010 to decimal.

A. 1.40 B. 1.125
C. 1.20 D. 1.80
2.  Convert the fractional binary number 10010.0100 to
decimal.

A. 24.50 B.
C. 18.40 D.

3.What is the decimal value of 2–1 ?

A. 0.5
C. 0.05
 4. How many unique symbols are used in the decimal
number system?

A. One B.
C. Ten D.
5. In positive logic, ________.
A. a HIGH = 1, a LOW = 0 B. a LOW = 1, a HIGH =
 
C. only HIGHs are present D. only LOWs are prese

6. Convert the fractional binary number 0000.1010 to

decimal.

A. 0.625
C. 0.55

7. Give the decimal value of binary 10000110.

A. 13410
C. 11010

8. The output of an OR gate is LOW when ________.

A. all inputs are LOW B. any input is LOW

C. any input is HIGH D. all inputs are HIGH

9. What are the symbols used to represent digits in

the binary number system?

A. 0,1 B. 0,1,2 C. 0 through 8 D.1,2

10. If a signal passing through a gate is inhibited by
sending a LOW into one of the inputs, and the output
is HIGH, the gate is a(n):

A. AND B. NOR C.OR

11. When used with an IC, what does the term

"QUAD" indicate?

A. 2 circuits B. 4 circuits C. 6circuits D. 8circuits

12. The Boolean expression for a 3-input AND gate

is ________.

A. X = AB B. X = ABC C. X = A + B + C D. X = AB + C

13. What are the pin numbers of the outputs of the

gates in a 7432 IC?

A. 3, 6, 10, and 13 B. 1, 4, 10, and 13

C. 3, 6, 8, and 11 D. 1, 4, 8, and 11

I4. Implementing the expression AB + CDE using

NAND logic, we get:

A. (A)
C. (C)

15. A 4-variable AND-OR-Invert circuit produces a 0

at its Y output. Which combination of inputs is
correct?

A. B. C.
16. Boolean Algebra obeys
a. commutative law b. associative law
c. distributive law d. commutative,
associative, distributive law
17.A+A.B=
a. B b. A.B C.A d. A or B

18.Demorgan’s first theorem is

a. A.A’=0 b. A”=A c. (A+B)’=A’.B’
d. (AB)’=A’+B’

19.. Demorgan’s second theorem is

a. A.A’=0 b. A”=A c. (A+B)’=A’.B’
d. (AB)’=A’+B’

20. Which of the following is true

a. SOP is a two level logic
b. POS is a two level logic
c. both SOP and POS are two level logic
d. Hybrid function is two level logic

21.The problem of logic race occurs in

a. SOP functions
b. Hybrod functions
c. POS functions
d. SOP and POS functions

22. In which function is each term known as min

term
a. SOP b. POS c. Hybrid D. both
SOP and POS

23. The function Y=AC+BD+EF is

. SOP b. POS c. Hybrid D. both
SOP and POS

24. The expression Y=∏M(0,1,3,4) is

a. SOP b. POS c. Hybrid D. both
SOP and POS
25.In a karnaugh map for an expression having ‘don’t
care terms’ the don’t cares can be treated
a. a. 0 b. 1 c. 1 or 0 d.
none of above
 D. Y. Patil College of
Engineering, Akurdi, Pune-44.
Department of Computer Engineering
___________________________________________
_______________________________

Multiple Choice Questions test

SUB: Digital Electronics and Logic Design
Class: SE

Unit –II Quiz 1

1. VLSI refers to digital ICs having
a. More than 1000 gates c. More than 100 but less than 9999
b. More than 100 gates d. More than 100 but less than 999
2. IC chip used in digital clock is
a. SSI c. VLSI
b. LSI d. MSI
3. Logic families which are in use now a days are
c
.

T
T
L
,

E
C
L

&

C
M
O
a. DTL & EMOS S
b. TTL, ECL, CMOS and RTL d
.

T
 T
L
,

E
C
L
,

C
M
O
S

&

D
T
L
4. TTL circuit with totempole output has
a. High output impedance c. Very high output impedance
b. Low output impedance d. Any of the above
5.
6. TTL uses
a. Multi emitter transistor
b. Multi collector transistor
c. Multi base transistor
d. Multi emitter or multi collector transistor
7. Advanced low power schootky is a part of
a. ECL family c. TTL family
b. CMOS family d. None of the above

7. For wired AND connection use

a. TTL gates with active pull up
b. TTL gates with open collector
c. TTL gates without active pull up and with open collector
d. Any one of the above
8. Time delay of a TTL standard family is above
a. 180 ns c. 18 ns
b. 50 ns d. 3 ns
9. As compared to TTL, ECL has
a. Lower power dissipation c. Higher propagation delay
b. Lower propagation delay d. Higher noise margin
10. As compared to TTL CMOS logic has
a. Higher speed of operation c. Smaller physical size
b. Higher power dissipation d. All the above
11. Which logic family has the
 highest power dissipation
per gate
c.
C
M
O
a. ECL S
d.
P
M
O
b. TTL S
12. Which is the most commonly used logic family
c.
C
M
O
a. ECL S
d.
P
M
O
b. TTL S
13. Fill in the banks of the statements below concerning the following logic families: Standard TTL
(74 XXXLL), Low power TTL (74LXX) Low power Schottky TTL (74L SXX), Schottky TTL (74
SXX), Emitter coupled logic (ECL), CMOS
a. Among the TTL families, -------------family requires considerably less power than the
standard TTL (74 XX) and also has comparable propagation delay.
b. Only the -------------- family can operate over a wide range of power supply voltages

14.An open collector

output can ________
current, but it cannot
________.

A. sink, source current B.

C. sink, source voltage D. source, sink voltage

15. In standard TTL the ‘totem pole stage refers

a. The multi-emitter input stage. c. The output buffer
b. The phase splitter d. Open collector output stage

16. The inverter 74 AL S01 has the following specifications: The fan out
based on the above will be

1
a. 0 c.60
2
b. 0 d.100
17. The noise margin of a TTL gate is about
a. 0.2 V c. 0.6 V
b. 0.4 V d. 0.8 V

18. A Darlington emitter follower circuit is sometimes used in the output stage of a TTL gate
in order to
a. Increase its to IOL c. Increase its speed of operation
b. Reduce its IOH d. Reduce power dissipation

19. The output of the 74 series GATE of TTL gates is taken from a BJT in
a. Totem pole and common collector configuration
b. Either totem pole or open collector configuration
c. Common base configuration
d. Common collector configuration

20. The full forms of the abbreviations TTL and CMOS in reference to logic families are
a. Triple Transistor Logic and Chip Metal Oxide Semiconductor
b. Tristate Transistor Logic and Chip Metal Oxide Semiconductor
c. Transistor Transistor Logic and Complementary Metal Oxide Semiconductor
d. Tristate Transistor Logic and Complementary Metal Oxide Silicon

21. Which of the following logic families has the shortest propagation delay?

a. CMOS b. BiCMOS
c. ECL d. 74SXX

22. Why must CMOS devices be handled with care?

a. so they don’t get dirty

b. because they break easily
c. because they can be damaged by static electricity discharge

23. What is the major advantage of ECL logic?

a. very high speed b. wide range of operating voltage

c. very low cost d. very high power

24. What is the range of invalid TTL output voltage?

A. 0.0–0.4 V B. 0.4–2.4 V C. 2.4–5.0 V D. 0.0–5.0 V

25. PMOS and NMOS ________.

A. represent MOSFET devices utilizing either

 exclusively within a given gate.
are enhancement-type CMOS devices used to produce a series of high-speed logic
B.
known as 74HC
represent positive and negative MOS-type devices, which can be operated from
C.
differential power supplies and are compatible with operational amplifiers
None of the above

D.

UNIT II- Quiz II

1.What is unique about TTL devices such as the

74SXX?

These devices use Schottky transistors and diodes to prevent them from going into saturation; this
A.
results in faster turn-on and turn-off times, which translates into

B. The gate transistors are silicon (S), and the gates therefore have lower values of leakage current.
C. The S denotes the fact that a single gate is present in the IC rather than the usual package of 2–6 gates.
D. The S denotes a slow version of the device, which is a consequence of its higher power rating.
2.  Which of the following logic families has the shortest propagation delay?

A. CMOS B. BiCMOS
C. ECL D. 74SXX
3.  Why must CMOS devices be handled with care?

A. so they don’t get dirty

B. because they break easily
C. because they can be damaged by static electricity discharge
4.  Special handling precautions should be taken when working with MOS devices. Which of the following
statements is not one of these precautions?

A. All test equipment should be grounded.

B. MOS devices should have their leads shorted together for shipment and storage.
C. Never remove or insert MOS devices with the power on.
D. Workers handling MOS devices should not have grounding straps attached to their wrists.
5.  What should be done to unused input

They should be left disconnec

A.
minimize power loading on th
All unused gates should be co
B.
resistor.</sub<cc<>
All unused inputs should be co
C.
both the unused inputs and un
Unused AND and NAND inp
D.
and NOR inputs should be g

6.Assume that a particular IC has a supply voltage (Vcc) equal to +5 V and ICCH = 10

mA and ICCL = 23 mA. What is the power dissipation for the chip?
A. 50 mW B. 82.5 mW C. 115 mW D. 165 mW

7. What is the major advantage of ECL logic?

A. very high speed B. wide range of operating voltage

C. very low cost D. very high power

8. What is the range of invalid TTL output voltage?

A. 0.0–0.4 V B. 0.4–2.4 V C. 2.4–5.0 V D. 0.0–5.0 V

9. What is the difference between the 54XX and 74XX series of TTL logic gates?

A. 54XX is faster.
B. 54XX is slower.
C. 54XX has a wider power supply and expanded temperature range.
D. 54XX has a narrower power supply and contracted temperature range.

10. Why is a pull-up resistor needed for an open collector gate?

A. to provide Vcc for the IC B. to provide ground for the IC

C. to provide the HIGH voltage D. to provide the LOW voltage

11. PMOS and NMOS ________.

represent MOSFET devices utilizing either P-channel or N-channel devices exclusively within a

A.
given gate

B. are enhancement-type CMOS devices used to produce a series of high-speed logic known as 74HC
represent positive and negative MOS-type devices, which can be operated from differential power
C.
supplies and are compatible with operational amplifiers
D. None of the above

12. Ten TTL loads per TTL driver is known as:

A. noise immunity B. fan-out C. power dissipation D. propagation delay

13. The high input impedance of MOSFETs:

A. allows faster switching B. reduces input current and power dissipation

C. prevents dense packing D. creates low-noise reactions

14. The time needed for an output to change from the result of an input change is
known as:

A. noise immunity B. fan-out C. propagation delay D. rise time

15. What is the advantage of using low-power Schottky (LS) over standard TTL
logic?

A. more power dissipation B. less power dissipation

C. cost is less D. cost is more
16. A TTL totem-pole circuit is designed so that the output transistors:
A. are always on together B. provide linear phase splitting
C. provide voltage regulation D. are never on together
  17. Fan-out is determined by taking the ________ result(s) of ________.

A.
smaller,  B. larger, 

C.
smaller,  D. average, 

  18. How many 74LSTTL logic gates can be driven from a 74TTL gate?

A. 10 B. 20 C. 200 D.400

19. What is the standard TTL noise margin?

A. 5.0 V B. 0.0V C. 0.8 V D. 0.4V

20. Which logic family is characterized by a multiemitter

transistor on the input?

A. ECL B.CMOS C. TTL D. None of the above

21. What should be done with unused inputs to a TTL

NAND gate?

A. let them float B. tie them LOW C. tie them HIGH

22. How is the speed–power product of a logic family
determined?

A. The propagation delay in  s is multiplied by the power dissipation in mW.

B. The propagation delay in ms is multiplied by the power dissipation in
C. The propagation delay in ns is multiplied by the power dissipation in mW.
D. The propagation delay in ns is multiplied by the power dissipation in

23. The problem of the VOH(min) of a TTL IC being too

low to drive a CMOS circuit and meet the CMOS
requirement of VIH(min) is usually easily overcome by:

A. adding a fixed voltage-divider bias resistive network at the output of the TTL device
B. avoiding this condition and only using TTL to drive TTL
C. adding an external pull-down resistor to ground
D. adding an external pull-up resistor to VCC

24. How many 74LSTTL logic gates can be driven from

a 74TTL gate?

A. 10 B.
C. 200 D.

25. What is the difference between the 74HC00 series

and the 74HCT00 series of CMOS logic?

A. The HCT series is faster.

B. The HCT series is slower.
C. The HCT series is input and output voltage compatible with TTL.
D. The HCT series is not input and output voltage compatible with TTL.