BENM 2123 MICROPROCESSOR

TECHNOLOGY
Chapter 2: The Architecture of ARM Processor
Introduction
 Two types of processor architecture
• Complex instruction set computing (CISC) platform – e.g., 68k
• Reduced instruction set computing (RISC) platform – e.g.,ARM
CISC vs RISC Features
CISC RISC
 Emphasis on hardware  Emphasis on software
 Includes multi-clock complex  Single-clock, reduced instruction only
instructions (2 to 10 clock cycle)
 Memory-to-memory: “LOAD” and  Register to register: “LOAD” and
“STORE” incorporated in instructions “STORE” are independent instructions
 Small code sizes, high cycles per  Large code sizes, low cycles per
second second
 CISC chips do all of the processing  RISC chips distribute some of their
themselves processing to other chips
 Many complex instructions  Simple instructions, few in number
 Variable length instructions  Fixed length instructions
 Complexity in microcode  Complexity in compiler
 Many instructions can access memory  Only LOAD/STORE instructions
access memory
 Many addressing modes  Few addressing modes
CISC vs RISC Features (cont.)

CISC: Memory-to-memory: “LOAD” and “STORE” RISC: Register to register: “LOAD” and “STORE”

Data Data Register

Register
Data Data

Memory Memory

 What’s the problem with memory to memory data processing?

CISC vs RISC Instructions

 RISC-based code images are usually twice the size of

comparable CISC algorithms
 Example: Add a constant number to a memory variable
located at memory location 0x00004000
CISC – 68K RISC -ARM
Source Destination Destination Source
MOVE #constant,D0 LDR R0,#constant
ADDA D0,$00004000 LDR R2,#&00004000
Adds the source operand to the LDR R1, [R2]
Add
destination address register and ADD R0,R1
stores the result in the address
address register STR R1,[R2]
CISC vs RISC Instructions (cont.)

 Machine language is in
the form of binary numbers
 Each instruction will
store data in binary form
 To retrieve the
instruction stored in
memory, decoding is
required first.
ARM Architecture: Load-Store
 Common architecture for RISC processors
 What load-store architecture does?
• Instruction sets will only process (add, subtract, etc.) values that are in
registers only
• The results of the process will be stored in registers
• The operation that involve memory is copy memory content into register
(load instructions) and copy register content into memory (store instructions)
 How about CISC like 68K?
• CISC processor allow processes involving memory with memory and between
memory and register
• E.g., Add memory content stored at address $2000 with memory content
stored at address $2004, or subtract memory content stored at address $3000
from register A content.
Brief History of ARM

 ARM is short for Advanced RISC Machines Ltd.

 Founded in 1990, owned by Acorn, Apple and
VLSI
Known as computer manufacturer before
becoming ARM
Acorn developed a 32-bit RISC processor for it’s
own use Acorn Archimedes
 ARM7TDMI is developed in 1998.
Why ARM here?
 ARM is one of the most licensed and thus widespread
processor cores in the world
 Used especially in portable devices due to low power
consumption and reasonable performance (MIPS/watt)
 Uses ARM instruction set and Thumb instruction set
(extension of ARM instruction set)
 RISC processors add more line of codes which means more memory is
required. Therefore, to reduce memory requirements (cost), ARM created
the Thumb instruction set as an option for their RISC processor cores.
ARM Architecture

 32-bitRISC processor core (32-bit instructions)

 16 registers available (when reuse the registers, a total of 37
pieces of 32-bit integer registers)
 Pipelined (ARM7: 3 stages)
 Cached (depending on the implementation)
 Von Neuman-type bus structure (ARM7), Havard (ARM9)
 8/16/32-bit data types
 7 modes of operation (usr, fiq, irq, svc, abt, sys, und)
 Simple structure  reasonable good speed/power consumption
ratio
Introduction: ARM-based Products
Introduction: ARM-based Products
Introduction: ARM-based Products
Introduction: ARM7TDMI
 The ARM7TDMI processor is a member of the
Advanced RISC machine family of general
purpose 32-bit microprocessor

 What does ARM7TDMI means?

 ARM7 – 32 bit Advanced RISC Machine
 T – Thumb architecture extension
 Two separate instruction sets, 32 bit ARM instructions
and 16 bit Thumb instructions
 D – Debug extension Making it much easier and
 I – Embedded ICE (in-circuit emulation) macrocell
less expensive to build and
extension test a complete system.
 M – Enhanced multiplier (making it suitable for all
sorts of DSP algorithms)
Thumb as it was called, gave software designers the flexibility to either put more code
into the same amount of memory or reduce the amount of memory needed for a given
design.
ARM Programmer’s Model (cont.)
 Programmer’s model – conceptual view of the structure
and operation of a computing system.
 The information that the programmer needs to know
about the processor.
 What are the registers inside ARM(data, address and special
registers)?
 What are the processor modes?
 What are the program status registers?
 What are the processor’s operating state?
 What are the mode bits?
 What are the data types supported by ARM?
ARM Programmer’s Model: Registers

Most application programs will

execute in User mode. The
others are known as privilege
modes, and they provide a way
to access protected resources.
How Stack Pointer (SP) works?
Processor Operating States
The ARM7TDMI processor has 2 operating states:
(1) ARM state
32-bit, word-aligned ARM instructions are executed
in this state.
(2) Thumb state
16-bit, half-word aligned Thumb instructions

In Thumb state, the Program Counter (PC) uses bit1 to select between alternate
halfwords.

Note: Transition between ARM and Thumb states does not affect the processor
mode or the register contents.You can switch the operating state between ARM
state and Thumb state using BX instruction.
Comparison between ARM state registers
and Thumb state registers

When operating in the 16-bit Thumb state, the

application encounters a slightly different set of
registers.
 ARM model – 17 registers
Thumb model – 12 registers
Operating Modes
The ARM7TDMI processor has 7 modes of operations:
 User mode (usr)
- Normal program execution mode. For programs and applications.

Privilege Modes Description

Fast Interrupt mode (fiq) Entered when a high priority (fast) interrupt is raised.
Supports a high-speed data transfer or channel
process. Correspond to interrupt levels available on
ARM.
Interrupt mode (irq) Entered when a low priority (normal) interrupt is
raised. Used for general-purpose interrupt handling.
Correspond to interrupt levels available on ARM
Supervisor mode (svc) Protected mode for the operating system. It’s a state
after reset and generally the mode in which OS kernel
executes
Abort mode (abt) Implements virtual memory and/or memory
protection (used to handle memory access violations)
Undefined mode (und) Used to handle undefined instruction. It supports a
software emulation of hardware coprocessors.
System mode (sys) A privileged user mode for the operating system (runs
OS tasks). A special version of user mode that allows
full read-write access of CPSR
 Program Status Register
 CPSR: Current Program Status Register (used in user mode)
 SPSR: Saved Program Status Register (used in privilege mode)
 To monitors and control internal operations
 Condition Code Flags
• N: Negative result from ALU
• Z: Zero result from ALU
• C: ALU operation carried out
• V: ALU operation overflowed

7 operating
mode

0: ARM state
1: Thumb state

Can be altered by arithmetic and logical instructions. Eg:

subtractions, logical shift, rotation, etc.
Format of the CPSR and SPSR
Mode bits
 Processor modes determine
• Which register are active, and
• Access rights to CPSR register itself
 Each processor mode is either
• Privileged: full read-write access to the CPSR
• Non-privileged: only read access to the control field of CPSR but read-write access to
the condition flags
 ARM has seven modes
• Privileged: abort, fast interrupt request, interrupt request, supervisor, system and
undefined
• Non-privileged: user
Bit value Mode
b10000 User
b10001 FIQ
b10010 IRQ
b10011 Supervisor
b10111 Abort
b11011 Undefined
b11111 System
Internal ARM7TDMI structure
 Register bank
• Store processor state
• 2 read ports, 1 write port
• r15 has additional read and write ports
 Arithmetic logic unit (ALU)
• Perform arithmetic and logic functions
 Instruction decoder and control
• Decode instructions
 Memory data registers (Write
data register & Read Data
Register)
• Hold data retrieve from and write to
memory
 Barrel shifter
• Preprocess (shift or rotate) data before it
enters ALU
 Address register and incrementer
• Select and hold memory addresses
ARM Architecture: Pin Description
Memory for ARM Systems
 Conceptually viewed as a set of storage elements that hold data or instructions,
each element holding a fixed number of bits and having an address.
 The ARM address bus is 32-bits (4,294,967,295 = 4G address space).
 The programmer provides sequences of 32-bit values are placed in memory starting
at addresses that are divisible by 4.
 Eg: every instruction is 32-bits; when an assembler or compiler produces code it
automatically puts the first byte of the first instruction at an address divisible by 4.
 When the CPU fetches an instruction, it fetches all 32-bits and adds 4 to the PC.
 How are 32-bit values arranged as 4 bytes
in the memory?
 The programmer must know how the memory is organized.
 ARM allows the hardware designer to select either of 2 methods: “little endian” and
“big endian”
 “little endian” – starts with LSB of data at the first memory location (default).
 “big endian” – starts with MSB of data at the first memory location.
 Linear array of bytes numbered from 0 to 232-1
 Data format
• 8-bit (1 byte) – can be anywhere of 4-byte aligned boundary
• 16-bit (half word) – must occupy two byte locations starting at even byte address
• 32-bit (1 word) – must occupy a group of 4-byte starting at address that is multiple of four

1 byte (8-bits) in
1 memory
location
 Example
 For example, suppose we have a 32 bit quantity, written as
90AB12CD16, which is hexadecimal. Since each hex digit is 4 bits, we
need 8 hex digits to represent the 32 bit value.
 So, the 4 bytes are: 90, AB, 12, CD where each byte requires 2 hex
digits.
 It turns out there are two ways to store this in memory.
In little endian, you store the least In big endian, you store the most
significant byte in the smallest address. significant byte in the smallest address.
Here's how it would look: Here's how it would look:

90 AB 12 CD16
MSB LSB
Instruction execution
ARM is a RISC processor with a pipeline operation, while one instruction is being executed,
the one to be executed next is being decoded and the one after is being fetched.

 Fetch – Instructions are fetch from memory and placed in the instruction pipeline. The control unit in
the CPU uses the address in the PC and fetch, read the contents of the memory at this address. Once the
contents are in CPU, the value in the PC is advanced by adding 4 to it.

 Decode – Instructions are decoded and the data path control signals prepared for the next cycle.
The 32-bit value fetched is decoded to determine which instruction it represents

 Execute – the operands are read from the register bank, shifted, combined in the ALU and the result
written back

 For simple instructions – each complete per clock cycle

Instruction execution (cont.)
Instruction set
 There are 2 instruction sets in ARM7TDMI: ARM instruction set (32-bit) and Thumb
instruction set (16-bit).

What is instruction set??

 Architecture of CPU drives its working ability from the instruction set architecture (ISA) upon
which it is designed.
 ISA can be defined as an interface to allow easy communication between the programmer and the
hardware.
 ISA prepares the processor to respond to all the user commands like execution of data, copying
data, deleting it, editing it, etc.
 Major terms that are often used in ISA:

 Instruction Set: A group of instructions that can be given to the computer. These instructions direct
the computer in terms of data manipulation. A typical instruction consists of 2 parts: Opcode and
Operand
 Opcode (operational code): the instruction applied
 Operand: the memory register or data upon which instruction is applied.

Example: LDR R0,#constant

opcode operand
ARM Architecture: Instruction Set
 All ARM instructions are 32 bits except the compressed 16-bit Thumb
instructions)
 All ARM instructions are aligned on 4-byte boundaries in memories
 Higher number of formats than other RISC processors, but the most
notable features are:
• Load-store architecture. Only load and store instructions can access memory.
Data processing instructions operate on register contents only.
• 3-address data processing instructions
• Conditional execution of every instruction
• Open instruction set extension through the coprocessor instruction set
• Etc.
 Outcome of higher number of ARM instruction format:
• Disadvantage – more complex decoding
• Advantage – higher code density
• Yet, the code density outweighs the complex decoding performance
Example of ARM Instruction Set
ARM Instruction Summary (cont.)
ARM Instruction Summary (cont.)
ARM Architecture: Input/Output System
 Input/output peripherals (e.g., disk controller, network interfaces) appear as
mapped memory devices
 Internal registers in peripherals appear as addressable locations within the
ARM’s memory map
 Interrupt request to processors
• Normal interrupt (IRQ)
• Fast interrupt (FIQ)
 Some I/O system use direct memory access (DMA)
• DMQ = the feature that allows certain I/O systems within the computer to
access memory independently of the processor
• To handle high-bandwidth data traffic