Acknowledgement

Prabal Dutta, Design of Microprocessor-Based

Systems

Joe Bungo, The ARM Architecture (with focus on

the Cortex-M3)

This materials have been prepared with the

assistance of Dr. Royan Ong from ProvenPac

Pr ovenPac © Copyright 2016 Dr Royan Ong 1

Topics (1/2)

Introduction to ARM Cortex-M3

Development Environment
Programmer’s Model
Immediate Instructions
Memory Access Instructions
Arithmetic Instructions
Logic Instructions

Pr ovenPac © Copyright 2016 Dr Royan Ong 2

Topics (2/2)

Program Flow Instructions

Function Handling

Other Instructions

Exception Handling

Pr ovenPac © Copyright 2016 Dr Royan Ong 3

 Part 1: Introduction to ARM Cortex-M3

Pr ovenPac © Copyright 2016 Dr Royan Ong 4

Where can you find an ARM?

IR Fire
Detector Exercise
Utility Intelligent
Intelligent Meters Machines Energy Efficient
Appliances Vending
Tele-parking toys

Source: Joe Bungo, The ARM Architecture

Pr ovenPac © Copyright 2016 Dr Royan Ong 5

Roadmap of the ARM Architecture

v4 v5 v6 v7
Halfword and Improved SIMD Instructions
Thumb-2
signed halfword interworking Multi-processing
/ byte support CLZ v6 Memory architecture
Architecture Profiles
Saturated arithmetic Unaligned data support
7-A - Applications
System mode DSP MAC
7-R - Real-time
instructions Extensions:
7-M - Microcontroller
Thumb Thumb-2 (6T2)
instruction set Extensions: TrustZone® (6Z)
(v4T) Jazelle (5TEJ) Multicore (6K)
Thumb only (6-M)

Pr ovenPac © Copyright 2016 Dr Royan Ong 6

ARM processors

Source: ARM, ARM Processors and Architectures: A Comprehensive Overview, 2012

Pr ovenPac © Copyright 2016 Dr Royan Ong 7

Cortex families are the first products of
architecture v7

Source: Joseph Yiu, The Definitive Guide to the ARM Cortex-M3

Pr ovenPac © Copyright 2016 Dr Royan Ong 8

 Cortex consist of three families

ARM Cortex-A x1-4

– Applications with full OS such as Cortex-A15

...2.5GHz
x1-4
iOS, Android, Embedded Linux Cortex-A9
Cortex-A8
x1-4

ARM Cortex-R Cortex-A5

– Real-time signal processing Cortex-R4

and control applications
Cortex-M4SC300™
Cortex™-M3
ARM Cortex-M Cortex-M1

– Microcontroller-oriented Cortex-M0
12k gates...
for MCU and SoC applications
Source: Joe Bungo, The ARM Architecture

Pr ovenPac © Copyright 2016 Dr Royan Ong 9

 Cortex-A is for Applications

Architecture v7A

MMU
MMU (Memory Management Unit)

AXI
AXI (Advanced eXtensible Interface (AXI), the third generation
of AMBA interface defined in the AMBA 3 specification, is
targeted at high performance, high clock frequency system
designs and includes features that make it suitable for high
speed sub-micrometer interconnect:
•separate address/control and data phases
•support for unaligned data transfers using byte strobes
•burst based transactions with only start address issued
•issuing of multiple outstanding addresses with out of
order responses
•easy addition of register stages to provide timing
closure.

VFP & NEON

support
Neon is a SIMD (Single Instruction Multiple Data) accelerator
processor integrated in as part of the ARM Cortex-A8. What
does SIMD mean? It means that during the execution of one Source: Joe Bungo, The ARM Architecture
instruction the same operation will occur on up to 16 data sets
Pr ovenPac
in parallel. It is also synonymous with the term vector processor.
© Copyright 2016 Dr Royan Ong 10
Cortex-A8
ARMv7-A Architecture
– Thumb-2,Thumb-2EE
– TrustZone extensions

Dual-issue, super-scalar 13-stage

pipeline
– Branch Prediction & Return Stack
– NEON and VFP

64/28-bit AXI Interface

L1 cache: 16/32KB each
Unified L2 cache
– 0-2MB
– 8-way set-associative

Optional features
– VFPv3 Vector Floating-Point
– NEON media processing engine
Source: ARM, ARM Processors and Architectures: A Comprehensive Overview, 2012

Pr ovenPac © Copyright 2016 Dr Royan Ong 11

Cortex-A15 MPCore
1-4 processors per cluster
32kB L1 caches
Integrated L2 Cache
– 512KB – 4MB

System-wide coherency support

Backward-compatible with
AXI3 interconnect
Integrated Interrupt Controller
– 0-224 external interrupts for
entire cluster

CoreSight debug
Advanced Power Management
Source: ARM, ARM Processors and Architectures: A Comprehensive Overview, 2012

Pr ovenPac © Copyright 2016 Dr Royan Ong 12

Cortex-R is for Real-time

Architecture v7R

MPU (Memory Protection Unit optional)

AXI

Dual Issue

Source: Joe Bungo, The ARM Architecture

Pr ovenPac © Copyright 2016 Dr Royan Ong 13

Cortex-M is for Microcontrollers

Architecture v6M
and v7M/v7ME

MPU (Memory
Protection Unit
optional)

AHB Lite & APB

Source: Joe Bungo, The ARM Architecture

Pr ovenPac © Copyright 2016 Dr Royan Ong 14

Cortex-M0
ARMv6-M Architecture
– 16-bit Thumb-2

3-stage pipeline
von Neuman architecture
AHB-Lite bus interface
Fixed memory map
1-32 interrupts
Low power support
Core configured with or
without debug
Source: ARM, ARM Processors and Architectures: A Comprehensive Overview, 2012

Pr ovenPac © Copyright 2016 Dr Royan Ong 15

Cortex-M3
ARMv7-M Architecture
– Thumb-2 only

3-stage pipeline
von Neumann architecture
Optional MPU
AHB-Lite bus interface
Fixed memory map
1-240 interrupts
Serial wire or JTAG debug
Source: ARM, ARM Processors and Architectures: A Comprehensive Overview, 2012

Pr ovenPac © Copyright 2016 Dr Royan Ong 16

 Cortex-M instruction sets

ARMv7-M
Architecture

ARMv6-M
Architecture

Source: ARM, ARM Processors and Architectures: A Comprehensive Overview, 2012

Pr ovenPac © Copyright 2016 Dr Royan Ong 17

Who embeds Cortex-M?

Source: Joe Bungo, The ARM Architecture

Pr ovenPac © Copyright 2016 Dr Royan Ong 18

So what’s the difference?

Source: Joe Bungo, The ARM Architecture

Pr ovenPac © Copyright 2016 Dr Royan Ong 19

It is all down to peripherals, peripherals,
peripherals…

Source: Joe Bungo, The ARM Architecture

Pr ovenPac © Copyright 2016 Dr Royan Ong 20

Different ARM cores for different
functionality
2500

2000
Max Frequency ((Mhz)

1500

1000

500

0
Cortex-A9
Cortex-M0 Cortex-M3 ARM7 ARM926 ARM1026 ARM1136 ARM1176 Cortex-A8
Dual-core
Max Freq (MHz) 50 150 184 470 540 610 750 1100 2000
Min Power (mW/MHz) 0.012 0.06 0.35 0.235 0.36 0.335 0.568 0.43 0.5
Source: Joe Bungo, The ARM Architecture

Pr ovenPac © Copyright 2016 Dr Royan Ong 21

Example of ARM-based SoCs
ARM core part of SoC Clocks and DMA
– Debug/trace via Reset Controller Port

JTAG/CoreSight FLASH
ARM External
Processor

AMBA AXI
Memory
External/internal memories core Interface

– Varying width, speed, size DEBUG

nIRQ
SDRAM
nFIQ On chip
Can include ARM peripherals CoreLink
memory
Interrupt
– Interrupt controller Controller APB

AMBA APB
Bridge
– Other peripherals and Other
CoreLink
interfaces Peripherals

Custom
ARM based
Can include on-chip memory Peripherals
SoC
from ARM

Connected using AMBA

Source: ARM, ARM Processors and Architectures: A Comprehensive Overview, 2012

Pr ovenPac © Copyright 2016 Dr Royan Ong 22

Cortex-M comes in various flavours

Many components are optional

– Selected by chip manufacturers

Source: https://en.wikipedia.org/wiki/ARM_Cortex-M

Pr ovenPac © Copyright 2016 Dr Royan Ong 23

ARM Microprocessor Bus Architecture
(AMBA) connects core with peripherals
High Performance
APB
ARM processor UART

High
Bandwidth AHB Timer
APB
External
Bridge
Memory Keypad
Interface

High-bandwidth DMA PIO

on-chip RAM Bus Master
Low Power
Non-pipelined
High Performance Simple Interface
Pipelined
Burst Support
Multiple Bus Masters

Source: ARM, ARM Processors and Architectures: A Comprehensive Overview, 2012

Pr ovenPac © Copyright 2016 Dr Royan Ong 24

ARM Highspeed Bus (AHB) structure

Arbiter

HADDR
HADDR HWDATA Slave
Master HWDATA
#1
HRDATA
#1
HRDATA

Address/Control
Slave
#2
Master
#2

Write Data
Slave
Read Data #3
Master
#3

Slave
#4
Decoder

Source: ARM, ARM Processors and Architectures: A Comprehensive Overview, 2012

Pr ovenPac © Copyright 2016 Dr Royan Ong 25

 Part 2: Development Environment

Pr ovenPac © Copyright 2016 Dr Royan Ong 26

Major development environments

Mentor Graphics Sourcery CodeBench

– Formerly CodeSourcery
– http://www.mentor.com/embedded-software/sourcery-tools/sourcery-codebench/overview

Keil MDK-ARM Microcontroller Development Kit

– www.keil.com/arm/mdk.asp

Tasking VX-toolset for ARM v4.3

– http://www.tasking.com/products/arm/

IAR Systems Embedded Workbench for ARM

– http://www.iar.com/en/Products/IAR-Embedded-Workbench/ARM/

Pr ovenPac © Copyright 2016 Dr Royan Ong 27

Sourcery CodeBench command line for
ARM are:

EABI = embedded application binary interface

Sourcery CodeBench Lite is free

– No integrated development environment
– No additional features apart from compiler
Source: Joseph Yiu, The Definitive Guide to the ARM Cortex-M3

Pr ovenPac © Copyright 2016 Dr Royan Ong 28

Sourcery CodeBench example
/* example.s */
.equ: equate /* define constants */
.equ STACK_TOP, 0x20000800
.text: assemble to program region .text
.global _start
.global: _start can be shared with other .code 16
object files .syntax unified

.code 16: code is in Thumb _start:

.word STACK_TOP, start
.syntax unified: unified assembly .type start, function
language syntax used /* Start of main program */
start:
_start: start of program region movs r0, #10
movs r1, #0
.word: Starting stack pointer is /* Calculate 10+9+8...+1 */
0x20000800 and reset vector is start loop:
adds r1, r0
start: reset handler subs r0, #1
bne loop
.type start, function: start is a function /* Result is now in R1 */
deadloop:
.end: end of file b deadloop
.end
Source: Joseph Yiu, The Definitive Guide to the ARM Cortex-M3

Pr ovenPac © Copyright 2016 Dr Royan Ong 29

Sourcery CodeBench example:
Assembling with arm-none-eabi-as

arm-none-eabi-as -mcpu=cortex-m3 -mthumb example.s -o example.o

-mcpu=cortex-m3: Processor is a Cortex-M3

-mthumb: Thumb instructions used

-o example1.o: Object file is named example1.o

Source: Joseph Yiu, The Definitive Guide to the ARM Cortex-M3

Pr ovenPac © Copyright 2016 Dr Royan Ong 30

☺
Sourcery CodeBench example: Linking
with arm-none-eabi-ld

arm-none-eabi-ld -Ttext 0x0 -o example.out example.o

-Ttext 0x0: locate the text section in

example1.o starting from location 0x0

-o example1.out: Output file is named

example1.out

Source: Joseph Yiu, The Definitive Guide to the ARM Cortex-M3

Pr ovenPac © Copyright 2016 Dr Royan Ong 31

☺
Sourcery CodeBench example: Creating the
binary with arm-none-eabi-objcopy

arm-none-eabi-objcopy -Obinary example.out example.bin

-Obinary: Create a binary file

Source: Joseph Yiu, The Definitive Guide to the ARM Cortex-M3

Pr ovenPac © Copyright 2016 Dr Royan Ong 32

☺
Sourcery CodeBench example: Disassembly
with arm-none-eabi-objdump

arm-none-eabi-objdump -S example.out > example.list

example.out: file format elf32-littlearm

Disassembly of section .text:

00000000 <_start>:
0: 20000800 .word 0x20000800
4: 00000009 .word 0x00000009
00000008 <start>:
8: 200a movs r0, #10
a: 2100 movs r1, #0
0000000c <loop>:
c: 1809 adds r1, r1, r0
e: 3801 subs r0, #1
10: f47f affc bne.w c <loop>
00000014 <deadloop>:
14: f7ff bffe b.w 14 <deadloop>

Source: Joseph Yiu, The Definitive Guide to the ARM Cortex-M3

Pr ovenPac © Copyright 2016 Dr Royan Ong 33

☺
Keil MDK-ARM comes with an IDE
•Eclipse based IDE enabling
workspace customization and project
management

•Enhanced source code editor with

syntax highlighting

•Visual debugging with memory,

register and disassembly views

•JTAG probe debug support and easy

setup via debug configuration choices

•Creating & Debugging Linux Apps

Using CodeBench for ARM

•Code analysis, formatting and

refactoring capabilities

•Custom board support through Board

Builder, a tool for automatically
generating linker scripts, debug
configuration files, and start-up code
based on a board’s memory map

Free edition has 32k code limit

Pr ovenPac © Copyright 2016 Dr Royan Ong 34
☺
Keil MDK-ARM has a built-in simulator

Most device peripherals can be simulated

Pr ovenPac © Copyright 2016 Dr Royan Ong 35
☺
 Part 3: Programmer’s model

Pr ovenPac © Copyright 2016 Dr Royan Ong 36

ARM’s architecture is 32-bits

When used in relation to ARM

– Byte: 8 bits
– Halfword: 16 bits
– Word: 32 bits

Halfword and word can be little or big endian

Most ARM implement two instruction sets

– ARM Instruction Set: 32-bits
– Thumb Instruction Set: 16 bits

Jazelle cores can execute Java bytecode

Pr ovenPac © Copyright 2016 Dr Royan Ong 37
Block diagram of the Cortex-M3

Source: Joseph Yiu, The Definitive Guide to the ARM Cortex-M3

Pr ovenPac © Copyright 2016 Dr Royan Ong 38

3-stage fetch-decode-execute pipeline

1st Stage - Fetch 2nd Stage - Decode 3rd Stage - Execute

Address Data Phase

AGU Phase & Write Load/Store &
Back Branch

Instruction
Fetch
Decode & Multiply & Divide Write
(Prefetch)
Register Read

Branch Shift ALU & Branch

Branch forwarding & speculation

Execute stage branch (ALU branch & Load Store Branch)

Prefetch buffers up to three 32-bit instructions

Fetch possible instructions for conditional branch
– At most one single idle cycle (no pipeline flush)
Source: Joe Bungo, The ARM Architecture

Pr ovenPac © Copyright 2016 Dr Royan Ong 39

Load-Store architecture

CLK CLK CLK

Flags'
PCSrcD PCSrcE PCSrcM PCSrcW
Control
RegWriteD RegWriteE RegWriteM RegWriteW
Unit
MemtoRegD MemtoRegE
MemtoRegM MemtoRegW
27:26 MemWriteD MemWriteE MemWriteM
Op

CondExE
25:20 ALUControlD ALUControlE
Funct
15:12
Rd BranchD BranchE
ALUSrcD ALUSrcE
FlagWriteD FlagWriteE
ImmSrcD
31:28 CondE Cond

RegSrcD
CLK FlagsE Unit
CLK
0 1 CLK
CLK
InstrF

InstrD

19:16
0 WE3 ALUFlags WE
RA1D SrcAE
1 PC' PCF A1 RD1
A RD 15 1 ALUResultE

ALU
0 ReadDataW
3:0
0 A RD
Instructi on RA2D
A2 RD2 0 SrcBE Data
Memory 1
1 Memory
A3 Register WriteDataE
WD

ExtImmE
WD3 File
1
R15 ALUOutM ALUOutW
PCPlus4F 0
+

15:12 WA3E WA3M WA3W

4
23:0 Extend

PCPlus8D
ResultW

Data processing performed on registers

Source: Joe Bungo, The ARM Architecture

Pr ovenPac © Copyright 2016 Dr Royan Ong 40

16 32-bit registers

Source: Joseph Yiu, The Definitive Guide to the ARM Cortex-M3

Pr ovenPac © Copyright 2016 Dr Royan Ong 41

Registers are typically used in the
following manner by C compilers

Name Typical usage by C compilers

R0 Argument / return value / temporary variable
R1-R3 Argument / temporary variables
R4-R11 Saved variables
R12 Temporary variable
R13 (SP) Stack Pointer
R14 (LR) Link Register
R15 (PC) Program Counter

R0–R3, R12, LR, PSR, PC automatically pushed

by hardware upon exceptions, popped upon exit

Pr ovenPac © Copyright 2016 Dr Royan Ong 42

Special Function Registers only
accessible by special instructions

xPSR: ALU flags, execution status, current executing interrupt

PRIMASK: disable all interrupts except NMI (Non-Maskable Interrupt)
and HardFault
FAULTMASK: disable all interrupts except NMI
BASEPRI: disable all interrupts of specific/lower priority level
CONTROL: define privileged status and stack pointer selection
Source: Joseph Yiu, The Definitive Guide to the ARM Cortex-M3
Pr ovenPac © Copyright 2016 Dr Royan Ong 43
Program Status Register (xPSR)

APSR EPSR IPSR

APSR: Application Program Status Register
– NZCVQ: negative, zero, carry, overflow, saturate flags

EPSR: Execution Program Status Register

– IT: If/Then block information
– ICI: Interruptible-continuable instruction

IPSR: Interrupt Program Status Register

– Interrupt/exception number

Pr ovenPac © Copyright 2016 Dr Royan Ong 44

Three states of operation

There is no User Handler state

Source: Joseph Yiu, The Definitive Guide to the ARM Cortex-M3

Pr ovenPac © Copyright 2016 Dr Royan Ong 45

Privilege levels improves system
reliability and security

Prevent system configuration registers from being

accessed by untrusted programs

Protect critical memory locations such as OS area

(MPU required)

OS launches user application in User Level

Source: Joseph Yiu, The Definitive Guide to the ARM Cortex-M3

Pr ovenPac © Copyright 2016 Dr Royan Ong 46

Processor always start in Privileged
Thread state

Privileged Thread is the state OS runs

User Thread is the state application code runs
Exception events is only way to go to the
Privileged Handler state
Source: Joseph Yiu, The Definitive Guide to the ARM Cortex-M3

Pr ovenPac © Copyright 2016 Dr Royan Ong 47

System Timer (SysTick)
Flexible system timer
– 24-bit self-reloading down counter
• Reload on 0
• Optionally cause SysTick interrupt
– Reload register
– Calibration register

Clock source is CPU clock or external reference

Calibration Register provides value required for

10ms interval
– STCALIB inputs tied to appropriate value
Pr ovenPac © Copyright 2016 Dr Royan Ong 48
4GB memory space

Source: Joseph Yiu, The Definitive Guide to the ARM Cortex-M3

Pr ovenPac © Copyright 2016 Dr Royan Ong 49

Memory map with some common
peripherals mapped

Source: Joseph Yiu, The Definitive Guide to the ARM Cortex-M3

Pr ovenPac © Copyright 2016 Dr Royan Ong 50

Default memory access

Prevents user programs from accessing critical memory

Default permission used when MPU not present or disabled

Source: Joseph Yiu, The Definitive Guide to the ARM Cortex-M3

Pr ovenPac © Copyright 2016 Dr Royan Ong 51

System Control Block (SCB)
Address Type Reset Value Function

0xE000E000 Read/Write 0x00000000 Master Control register - RESERVED

0xE000E004 Read Only IMP DEFINED Interrupt Controller Type Register

0xE000ED00 Read Only IMP DEFINED CPUID Base Register

0xE000ED04 Read/Write 0x00000000 Interrupt Control State Register

0xE000ED08 Read/Write 0x00000000 Vector Table Offset Register

0xE000ED0C Read/Write Bits[10:8] = 000 Application Interrupt/Reset Control

Register

Registers to configure, control, and deal with

interrupts, exceptions, and debug

Pr ovenPac © Copyright 2016 Dr Royan Ong 52

More SCB registers
Address Type Reset Value Function
0xE000ED10 Read/Write 0x00000000 System Control Register

0xE000ED14 Read/Write 0x00000000 Configuration Control Register

0xE000ED18 Read/Write 0x00000000 System Handlers 4-7 Priority Register

0xE000ED1C Read/Write 0x00000000 System Handlers 8-11 Priority Register

0xE000ED20 Read/Write 0x00000000 System Handlers 12-15 Priority Register

0xE000ED24 Read/Write 0x00000000 System Handler Control and State

Register
0xE000ED28 Read/Write n/a - status Configurable Fault Status Registers (3)

0xE000ED2C Read/Write n/a - status HardFault Status Register

0xE000ED30 Read/Write n/a - status DebugFault Status Register

0xE000ED34 Read/Write Unpredictable MemManage Address Register

0xE000ED38 Read/Write Unpredictable BusFault Address Register

0xE000ED3C Read/Write Unpredictable Auxiliary Fault Status Register (vendor

specific)
0xE000EF00 Write Only Software Trigger Interrupt Register

Pr ovenPac © Copyright 2016 Dr Royan Ong 53

Processor core and devices are
connected via busses

Source: Joseph Yiu, The Definitive Guide to the ARM Cortex-M3

Pr ovenPac © Copyright 2016 Dr Royan Ong 54

Cortex-M uses the AMBA (Advanced
Microcontroller Bus Architecture)
High Performance
APB
ARM processor UART
High
Bandwidth Timer
AHB APB
External
Bridge
Memory Keypad
Interface

High-bandwidth DMA PIO

on-chip RAM Bus Master

Advanced High-performance Bus (AHB)

– Pipelined, burst transfers, multiple masters
Advanced Peripheral Bus (APB)
– Low power, latched address/control, simple
interface, suitable of many peripherals
Source: Joe Bungo, The ARM Architecture

Pr ovenPac © Copyright 2016 Dr Royan Ong 55

The ARM instruction categories

Memory access
– Load from data memory (RAM) to registers
– Store register value to data memory (RAM)

Data processing
– Arithmetic, shift, rotate, comparison, moving

Bitfield instructions

Branch and Control

Miscellaneous

Pr ovenPac © Copyright 2016 Dr Royan Ong 56

ARM instructions…

Can be conditionally executed based on flags

– Reduces branch overhead

Have powerful addressing modes (memory access

instructions)
– PC-relative addressing
– Pre-increment addressing
– Post-increment addressing

Can have its results shifted and rotated

Can have different operand size

Pr ovenPac © Copyright 2016 Dr Royan Ong 57
Flexible ARM instructions

Various Powerful
operand sizes addressing
modes

Conditional Shifted/rotated
execution operands
Source: http://infocenter.arm.com/

Pr ovenPac © Copyright 2016 Dr Royan Ong 58

Conditional execution

Source: ARM, ARM v7-M Architecture Reference Manual

Pr ovenPac © Copyright 2016 Dr Royan Ong 59

Powerful addressing modes
Offset addressing: [<Rn>,<offset>]
– Offset added/subtracted to/from Rn
– Result used as the data memory address
– Rn is unaltered

Pre-indexed addressing: [<Rn>,<offset>]!

– Offset added/subtracted to/from Rn
– Result used as the data memory address
– Rn = Rn + offset

Post-indexed addressing: [<Rn>],<offset>

– Rn used, unaltered, as the data memory address
– Rn = Rn + offset
Pr ovenPac © Copyright 2016 Dr Royan Ong 60
Various operand sizes (suffixed to
instruction)
B Unsigned byte, zero extended

SB Signed byte, sign extended

H Unsigned halfword, zero extended

SH Signed halfword, sign extended

(omit) Word

D Unsigned double word

Source: http://infocenter.arm.com/

Pr ovenPac © Copyright 2016 Dr Royan Ong 61

Shifted/rotated second operand

LSL #n Logical shift left n (0 ≤ n ≤ 31)

LSR #n Logical shift right n (1 ≤ n ≤ 32)

ASR #n Arithmetic shift right n (1 ≤ n ≤ 32)

ROR #n Rotate right n (1 ≤ n ≤ 31)

RRX Rotate right one bit, with extend

» Bit [0] is written to shifter_carry_out,
» Bits [31:1] shifted right one bit
» Carry flag is shifted into bit [31]

Pr ovenPac © Copyright 2016 Dr Royan Ong 62

Cortex-M3 instruction set summary (1/6)

Source: ARM, Cortex-M3 Devices Generic User Guide

Pr ovenPac © Copyright 2016 Dr Royan Ong 63

Cortex-M3 instruction set summary (2/6)

Source: ARM, Cortex-M3 Devices Generic User Guide

Pr ovenPac © Copyright 2016 Dr Royan Ong 64

Cortex-M3 instruction set summary (3/6)

Source: ARM, Cortex-M3 Devices Generic User Guide

Pr ovenPac © Copyright 2016 Dr Royan Ong 65

Cortex-M3 instruction set summary (4/6)

Source: ARM, Cortex-M3 Devices Generic User Guide

Pr ovenPac © Copyright 2016 Dr Royan Ong 66

Cortex-M3 instruction set summary (5/6)

Source: ARM, Cortex-M3 Devices Generic User Guide

Pr ovenPac © Copyright 2016 Dr Royan Ong 67

Cortex-M3 instruction set summary (6/6)

Source: ARM, Cortex-M3 Devices Generic User Guide

Pr ovenPac © Copyright 2016 Dr Royan Ong 68