CHAPTER 3.

2: ARM
ASSEMBLY LANGUAGE
PROGRAMMING
BENM 2123: MICROPROCESSOR
TECHNOLOGY

DATA TRANSFER INSTRUCTIONS: LOADS,

STORES
Outline
• Introduction
• Loads and Stores
• Single register data transfer (LDR/STR)
• LDR, LDRB, LDRH, LDRSB, LDRSH, STR, STRB, STRH

• PC-relative LDR instructions

• Loading constants
• ADR
Introduction
The ARM is a Load/Store Architecture:
– Only load and store instructions can access memory
– Does not support memory to memory data processing
operations.
– Must move data values into registers before using them.

Data transfer instructions transfer data between registers

and memory:
• Memory to register (LDR)
• Register to memory (STR)
Load-Store Architecture
• Load-store architecture means that if you want to work on any variable from the
memory, you need to load the data into the registers (registers are in the core), perform
any operation you want, then store it back to memory.
• The instruction set is designed for this architecture.
• You can’t perform operation directly inside the memory

Data Register
Data

Register
Data
Data

Memory Memory
Memory to memory data processing is not allowed because it can slow
down the memory access. Therefore, all data operation needs to be
done in register before transfer it back to memory.
Loads and Stores – The instructions
• The ARM has three sets of instructions which interact with main
memory. These are:
• Single register data transfer (LDR/STR)
• Block data transfer (LDM/STM) - ignore
• Single Data Swap (SWP) - ignore

Single register data transfer (LDR/STR)

• Load – take a single value from memory and write it to general
purpose register. (MEMORY  REGISTER)
• Store – read a value from a general purpose register and store it to
memory. (REGISTER  MEMORY)
• Memory system must support all access sizes 10 types of addressing modes
1. Base register addressing
• Syntax: (today’s class)
2. Base displacement addressing
• Offset – immediate, register,
op{<type>}{<cond>} Rt, <address> scaled register.
• Pre-indexed - immediate,
register, scaled register.
LDR or B? SB? H? Refer next Destination Addressing • Post-indexed - immediate,
STR SH? slide register mode (10 register, scaled register.
types) (cover next class)
Loads and Stores – The instructions
(cont.)
• Condition Code Suffixes
Loads and Stores (cont.)
Most often used Load/Store instructions

Load instructions: LDR, LDRB, LDRH, LDRSB, LDRSH

Store instructions: STR, STRB, STRH
Components of any computer
Base register
• To transfer a word of data, we need to specify two things:
• Register: r0-r12
• r13 – stack pointer, r14: link register, r15: PC
• How to access the memory?
• Think of memory as a single one-dimensional array, so we can address it
simply by supplying a pointer to a memory address.
• Besides pointer, we also need to identify the base register. Base register
will point to the beginning of the memory array.

Base register
A register which contains a pointer to memory
Example: [r0]
• specifies the memory address pointed to by the value in r0
• This is called register indirect addressing
Data Transfer: Memory to Register (LDR)
Load Instruction Syntax:
Data flow
LDR r1, [r0] ; Load r1 with contents of memory location pointed to by
contents of r0.
where
1) operation name (LDR)
2) register that will receive value (r1)
3) register containing pointer to memory/base register [r0]

• ARM Instruction Name:

• LDR(meaning Load Register, so 32 bits or one word are loaded at a time)

1 r0 contains the memory

address that it points in 2 3
the memory

0x00000200 0x00000200
0x12345678
r1 0x12345678
r0
Base register 0x00000204 The value contained in memory
location 0x00000200 is loaded in r1
0x00000208

0x0000020C
LDR r1, [r0]
Loads
LDR

Example:
Consider the instruction
LDR r9, [r0] ; load a word from the memory address pointed by r0 into r9

Assuming the address in register r0 is 0x6000, before and after the instruction is
executed, the data appear as follows:

Before load
r0 0×00006000 Address
0×6000 0×EE
r9 0×12345678
0×6001 0×FF
After load 0×6002 0×80
r0 0×00006000 0×6003 0×A7

r9 0×A780FFEE
Loads (cont.)
LDRB

Example:
Consider the instruction
LDRB r9, [r0] ; load a byte into r9

Assuming the address in register r0 is 0x6000, before and after the instruction is
executed, the data appear as follows:
Before load
r0 0×00006000 Address Memory
0×6000 0×EE
r9 0×12345678
0×6001 0×FF
After load 0×6002 0×80
r0 0×00006000 0×6003 0×A7

r9 0×000000EE

Assume little endian. If big 8 bits of memory copied to bottom of register; upper 24
endian, r9 = 0xEE000000 bits of register zeroed
Loads (cont.)
LDRH

Example:
Consider the instruction
LDRH r9, [r0] ; load a halfword into r9

Assuming the address in register r0 is 0x6000, before and after the

instruction is executed, the data appear as follows:

Before load
r0 0×00006000 Address Memory
0×6000 0×EE
r9 0×12345678
0×6001 0×FF
After load 0×6002 0×80
r0 0×00006000 0×6003 0×A7

r9 0×0000FFEE
Loads (cont.)
LDRSB

Example:
Consider the instruction
LDRSB r9, [r0] ; load signed byte into r9

Assuming the address in register r0 is 0x6000, before and after the instruction is
executed, the data appear as follows:

Before load
r0 0×00006000 Address Memory
0×6000 0×EE
r9 0×12345678
0×6001 0×8C
After load 0×6002 0×80
r0 0×00006000 0×6003 0×A7

r9 0×FFFFFFEE 0xEE = 1110 1110

Extend the sign until 32 bit

Loads (cont.)
LDRSH

Example:
Consider the instruction
LDRSH r9, [r0] ; load signed half into r9

Assuming the address in register r0 is 0x6000, before and after the instruction is
executed, the data appear as follows:

Before load
r0 0×00006000 Address Memory
0×6000 0×EE
r9 0×12345678
0×6001 0×8C
After load 0×6002 0×80
r0 0×00006000 0×6003 0×A7

r9 0×FFFF8CEE
Data Transfer: Register to Memory (STR)
Store Instruction Syntax:

Data flow
STR r0,[r1] ; Store contents of r0 into the location pointed by r1
where
1) operation name (STR)
2) register that will transfer value (r0)
3) register containing pointer to memory/base register [r1]
1
3
Base register
0x5
r1 0x00000200 0x00000200

0x00000204

0x00000208
2 0x0000020C
r0 contains value 0x5 Write the value 0x5
contained in r0 to
r0 0x5 memory location
pointed to by r1
Stores
STR

Example:
Consider the instruction
• STR r9, [r0] ; Store word from r9 to location pointed to by contents of r0

Assuming the address in register r0 is 0x6000, before and after the instruction is
executed, the data appear as follows:

Before store Before store After store

r0 0×00006000
Address Memory Address Memory
r9 0×12345678 0×6000 0×BE 0×6000 0×78
0×6001 0×BA 0×6001 0×56
After store
0×6002 0×ED 0×6002 0×34
r0 0×00006000
0×6003 0×FE 0×6003 0×12
r9 0×12345678
Stores (cont.)
STRB

Example:
Consider the instruction
• STRB r9, [r0] ; Store byte from r9 to location pointed to by
contents of r0

Assuming the address in register r0 is 0x6000, before and after the

instruction is executed, the data appear as follows:

Before store Before store After store

r0 0×00006000
Address Memory Address Memory
r9 0×12345678 0×6000 0×BE 0×6000 0×78
0×6001 0×BA 0×6001 0×BA
After store
0×6002 0×ED 0×6002 0×ED
r0 0×00006000
0×6003 0×FE 0×6003 0×FE
r9 0×12345678
Stores (cont.)
STRH

Example:
Consider the instruction
• STRH r9, [r0] ; Store halfword from r9 to location pointed to by
contents of r0

Assuming the address in register r0 is 0x6000, before and after the instruction is
executed, the data appear as follows:

Before store Before store After store

r0 0×00006000
Address Memory Address Memory
r9 0×12345678 0×6000 0×BE 0×6000 0×78
0×6001 0×BA 0×6001 0×56
After store
0×6002 0×ED 0×6002 0×ED
r0 0×00006000
0×6003 0×FE 0×6003 0×FE
r9 0×12345678
PC-relative LDR and LDRD instructions

• type
• B unsigned byte, zero extend on load
• SB signed byte, sign extend (LDR only)
• H unsigned halfword, zero extend on load
• SH signed halfword, sign extend (LDR only)
• (omit) word

Source: http://infocenter.arm.com/
PC-relative LDR label must be within a
certain range

LDR: Label must be within -4095 and +4095

of the current program counter value

Source: http://infocenter.arm.com/
PC-relative LDR examples
• LDR R0, LookUpTable
• Load R0 with a word from the data memory location LookUpTable

• LDRSB R7, localdata

• Load R7 with a byte (sign extended) from the data memory location
localdata

In these instructions, the destination registers will not

know the memory address of the data pointed by the
label. Therefore, in order to retrieve the memory address,
you need to use ADR.
ADR loads the register with the address of
the operand
ADR
• Generate PC-relative address

• label
• Location of stored variable of which its address is to be loaded into
Rd
• Label must be within -4095 and +4095 of the current program
counter value
• In other words, ADR makes Rd as a pointer to the constant
label
Load an address into register (cont.)
Application of ADR
ADR example
ADR R0, lit ; returns the address of lit
LDR R2, [R0], #4 ; load 0x12345678 into R2
; increment R0 by 4
; to point to next value
LDR R3, [R0] ; load 0x88888888 into R3

lit DCD 0x12345678, 0x88888888 ; stored in ROM

ADR is best for

• Pointing to strings stored in memory
• Pointing to constants stored in memory
• Filter coefficients, encryption keys, etc.
Loading constants
• LDR can be used to load 32 bit size constant
• The size of the constant is 0 – (232-1) = 0 - 4,294,967,295
(less than 4KB)

LDR rd, =constant ; this instruction requires the constant to be

;placed in a literal pool

• The literal pool is an area of memory (in the text

segment), which is used to store constants.
• Usually the assembler groups various literal data (e.g.,
DCD 0x12345678) together into data blocks called literal
pools.