Microprocessor Programming

and Interfacing
8086/8088 Architecture

Dr. Suvadip Batabyal

Dept. of CSIS
BITS Pilani, Hyderabad

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Computer, MiP, CPU

Computer

Microprocessor
CPU

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 System BUS
ADDRESS BUS:
PROCESSOR BUS No of Address lines
• 20 lines –A19–A0
• 1 M Byte of memory can be addressed

DATA BUS:
No of Data lines
• 16 lines –D15–D0

CONTROL LINES:
-Active low signals
• MEMR
• MEMW
• IOR
• IOW

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 Size of Microprocessor
• SIZE OF A MICROPROCESSOR
– Size of Data Bus
– Size of Registers
– Size of ALU

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 Comparison of x86 MiP
16-bit Microprocessor 32-bit Microprocessor

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 Addressing Concept
4 bits

Address lines : 3 (Unidirectional)

Data lines : 4 (Bidirectional)

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 Memory of MiP
PROCESSOR MEMORY
• ROM
• Non-Volatile
• Read Only
• RAM
• Volatile
• Random Access Memory
• MEMORY DATA SIZE
• Bit Organized
• Nibble Organized
• Byte Organized

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 High Level view of Memory Org.

Add Bus

Memory –
Data Bus
Registers to hold bits
Memory

Read

Write

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 Computer Languages
• Machine language: language native to computer. In 0’s and 1’s.
Difficult for users to understand, code, debug, etc.

• Assembly language: use of mnemonics. Do not have to work with

binary values. Assemblers.

• High level language: close to human language. Compilers.

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 RISC & CISC
WHAT IS THE EFFECT ?
• If Instructions is present anywhere
• Size of Instruction varies
-Complicates Instruction Decoder

ISA

 CISC (Complex Instruction Set Computer)

Operands for Arithmetic/Logic operation can be in Register/ Memory

 RISC (Reduced Instruction Set Computer)

Operands for Arithmetic/Logic operation only in Registers
Register –Register Architecture
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 Characteristics of X86 family
• CISC architecture (Instruction length varying from 1-byte
to 5-bytes).
• Instructions broken up into micro-operations.
• Complex instruction decoder.

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 8086 Simplified View

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 Basic Computer Architecture
• Bus Interface Unit (BIU)
• handles all transfers of data and addresses on the buses for the
execution unit

• Execution Unit (EU)

• Actual function is performed here
 instructs BIU from where to fetch an instruction
 decodes it,
 executes it

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 8086 Detailed View

Execution Unit (EU) Bus Interface Unit (BIU)

EU executes instructions that have BIU fetches instructions, reads data

already been fetched by the BIU. from memory and I/O ports, writes
data to memory and I/ O ports.
BIU and EU functions separately.
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 8086 Detailed View
Dedicated Adder to generate
20 bit address

Four 16-bit segment

registers

Code Segment (CS)

Data Segment (DS)
Stack Segment (SS)
Extra Segment (ES)

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 Memory Segmentation
• Segmentation is the process in which the main memory of the
computer is divided into different segments and each segment has
its own base address.
• All registers are of 16bits.
• Advantages of segmentation:
– Re-locatable code. Any program or data can be loaded in any address in memeory.
– provides a powerful memory management mechanism.
– Data related or stack related operations can be performed in different segments.
– allows the use of 16 bit registers to give an addressing capability of 1 Megabytes.
Without segmentation, it would require 20 bit registers.

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 8086 Memory Address Space

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 Physical Address Generation

Offset Value (16 bits)

Segment Register (16 bits) 0000

Adder

Physical Address (20 Bits)

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 Physical Address Generation
20 Address lines  8086 can address up to 220 =
1M bytes of memory

However, the largest register is only 16 bits

Physical Address will have to be calculated Physical

Address : Actual address of a byte in memory. i.e. the
value which goes out onto the address bus.

Memory Address represented in the form – Seg :

Offset (Eg - 89AB:F012)

Each time the processor wants to access memory, it

takes the contents of a segment register, shifts it one
hexadecimal place to the left (same as multiplying by 16 bytes of contiguous
1610), then add the required offset to form the 20- bit memory
address

89AB : F012  89AB  89AB0 (Paragraph to byte  89AB x 10 = 89AB0)

F012  0F012 (Offset is already in byte unit)
+ -------
98AC2 (The absolute address)
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 Physical Address Calculation

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 Segment Registers
• The Bus Interface Unit (BIU) contains four 16 bit special purpose
registers (mentioned below) called as Segment Registers.

• Code segment register (CS): is used for addressing memory

location in the code segment of the memory, where the executable
program is stored. IP points to the next instruction to be executed.
Logical address=> CS:IP
• Stack Segment Register (SS): is used fro addressing stack segment
of the memory. The stack segment is that segment of memory which
is used to store stack data. SP points to the top of the stack. BP is
used to reference data anywhere in the stack.
• Data segment register (DS): points to the data segment of the
memory where the data is stored. Displacement: BX, DI, SI
• Extra Segment Register (ES): also refers to a segment in the
memory which is another data segment in the memory.
Displacement: BX, DI, SI
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 Segmentation Concepts
• Address used in instructions are called logical address which are
translated by BIU to physical address.
• Segments begin at paragraph boundaries, where a paragraph is 16
bytes.
• Segments can overlap with new segments starting every 16 bytes.
That is there can be more than one logical address for the same
physical location. For example, 0000:0100, 0001:00F0 and
0010:0000 all refer to 00100H.
• A segment can have a maximum size of 64k.
• All program will have at least the code segment.

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 BIU Registers
Segment
Registers

8086’s 1-megabyte The 8086 can directly address Programs obtain access to
memory is divided into four segments (256 K bytes code and data in the
segments of up to 64K within the 1 M byte of memory) segments by changing the
bytes each. at a particular time. segment register content to
point to the desired
segments.

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 Segmentation Concepts
8086 registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

categorized into OF DF IF TF SF ZF AF PF CF
4 groups

Sl.No. Type Register Name of register

width
1 General purpose 16 bit AX, BX, CX, DX
register
8 bit AL, AH, BL, BH, CL, CH, DL, DH
2 Pointer register 16 bit SP, BP

3 Index register 16 bit SI, DI

4 Instruction Pointer 16 bit IP

5 Segment register 16 bit CS, DS, SS, ES

6 Flag (PSW) 16 bit Flag register

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 BIU Registers
Segment
Registers Code Segment Register

16-bit

CS contains the base or start of the current code segment; IP

contains the distance or offset from this address to the next
instruction byte to be fetched.

BIU computes the 20-bit physical address by logically shifting

the contents of CS 4-bits to the left and then adding the 16-bit
contents of IP.

That is, all instructions of a program are relative to the

contents of the CS register multiplied by 16 and then offset is
added provided by the IP.

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 BIU Registers
Segment
Registers Data Segment Register

16-bit

Points to the current data segment; operands for most

instructions are fetched from this segment.

The 16-bit contents of the Source Index (SI) or Destination

Index (DI) or a 16-bit displacement are used as offset for
computing the 20-bit physical address.

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 BIU Registers
Segment Stack Segment Register
Registers
16-bit

Points to the current stack.

The 20-bit physical stack address is calculated from the

Stack Segment (SS) and the Stack Pointer (SP) for stack
instructions such as PUSH and POP.

In based addressing mode, the 20-bit physical stack address

is calculated from the Stack segment (SS) and the Base
Pointer (BP).

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 BIU Registers
Segment Extra Segment Register
Registers

16-bit

Points to the extra segment in which data (in excess of 64K

pointed to by the DS) is stored.

String instructions use the ES and DI to determine the 20-bit

physical address for the destination.

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 BIU Registers
Segment Instruction Pointer
Registers
16-bit

Always points to the next instruction to be executed within the

currently executing code segment.

So, this register contains the 16-bit offset address pointing to

the next instruction code within the 64KB of the code segment
area.

Its content is automatically incremented as the execution of the

next instruction takes place.

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 Instruction queue

A group of First-In-First-Out
(FIFO) in which up to 6 bytes
of instruction code are pre
fetched from the memory
ahead of time.

This is done in order to speed

up the execution by
overlapping instruction fetch
with execution.

This mechanism is known as

pipelining.

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 Segmentation Concepts
EU decodes and executes
instructions.

A decoder in the EU control

system translates instructions.

16-bit ALU for

performing arithmetic
and logic operation

Four general purpose

registers (AX, BX, CX, DX);

Pointer registers (Stack

Pointer, Base Pointer);

and
Some of the 16 bit registers can be used as
two 8 bit registers as :
Index registers (Source
Index, Destination Index) AX can be used as AH and AL
each of 16-bits BX can be used as BH and BL
CX can be used as CH and CL
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DX can be used as DH and DL
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 EU Registers
EU Accumulator Register (AX)
Registers
Consists of two 8-bit registers AL and AH, which can be
combined together and used as a 16-bit register AX.

AL in this case contains the low order byte of the word, and
AH contains the high-order byte.

The I/O instructions use the AX or AL for inputting /

outputting 16 or 8 bit data to or from an I/O port.

Multiplication and Division instructions also use the AX or

AL.

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 EU Registers
EU Base Register (BX)
Registers
Consists of two 8-bit registers BL and BH, which can be
combined together and used as a 16-bit register BX.

BL in this case contains the low-order byte of the word, and BH

contains the high-order byte.

This is the only general purpose register whose contents can be

used for addressing the 8086 memory.

All memory references utilizing this register content for

addressing use DS as the default segment register.

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 EU Registers
Counter Register (CX)
EU
Registers Consists of two 8-bit registers CL and CH, which can be combined
together and used as a 16-bit register CX.

When combined, CL register contains the low order byte of the

word, and CH contains the high-order byte.

Instructions such as SHIFT, ROTATE and LOOP use the contents of

CX as a counter.

Example:

The instruction LOOP START automatically decrements CX

by 1 without affecting flags and will check if [CX] = 0.

If it is zero, 8086 executes the next instruction; otherwise

the 8086 branches to the label START.

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 EU Registers
EU Data Register (DX)
Registers
Consists of two 8-bit registers DL and DH, which can be
combined together and used as a 16-bit register DX.

When combined, DL register contains the low order byte of the

word, and DH contains the high-order byte.

Used to hold the high 16-bit result (data) in 16 x 16

multiplication or the high 16-bit dividend (data) before a 32 by
16 division and the 16 bit reminder after division.

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 EU Registers
Stack Pointer (SP) and Base Pointer (BP)
EU
Registers SP and BP are used to access data in the stack segment.

SP is used as an offset from the current SS during execution

of instructions that involve the stack segment in the external
memory.

SP contents are automatically updated (incremented/

decremented) due to execution of a POP or PUSH instruction.

BP contains an offset address in the current SS, which is used

by instructions utilizing the based addressing mode.

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 EU Registers
EU Source Index (SI) and Destination Index (DI)
Registers
Used in indexed addressing.

Instructions that process data strings use the SI and DI

registers together with DS and ES respectively in order to
distinguish between the source and destination addresses.

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 Auxiliary Carry Flag
Carry Flag
This is set, if there is a carry from the
lowest nibble, i.e, bit three during This flag is set, when there is
addition, or borrow for the lowest a carry out of MSB in case of
Flag Register nibble, i.e, bit three, during addition or a borrow in case
subtraction. of subtraction.
Sign Flag Zero Flag
Parity Flag
This flag is set, when the This flag is set, if the result of
result of any computation This flag is set to 1, if the lower
the computation or comparison
is negative byte of the result contains even
performed by an instruction is
number of 1’s ; for odd number
zero
of 1’s set to zero.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OF DF IF TF SF ZF AF PF CF

Over flow Flag Trap Flag

This flag is set, if an overflow occurs, i.e, if the result of a signed If this flag is set, the processor
operation is large enough to accommodate in a destination enters the single step execution
register. The result is of more than 7-bits in size in case of 8-bit mode by generating internal
signed operation and more than 15-bits in size in case of 16-bit interrupts after the execution of
sign operations, then the overflow will be set. each instruction

Direction Flag Interrupt Flag

This is used by string manipulation instructions. If this flag bit Causes the 8086 to recognize
is ‘0’, the string is processed beginning from the lowest external mask interrupts; clearing IF
07-Feb-19 address to the highest address, i.e., auto incrementing mode. disables these interrupts.
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Otherwise, the string is processed from the highest address
ELECTRICAL towards the lowest address, i.e., auto incrementing mode.
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 Summary
Register Name of the Register Special Function

AX 16-bit Accumulator Stores the 16-bit results of arithmetic and logic operations

AL 8-bit Accumulator Stores the 8-bit results of arithmetic and logic operations

BX Base register Used to hold base value in base addressing mode to access
memory data
CX Count Register Used to hold the count value in SHIFT, ROTATE and LOOP
instructions
DX Data Register Used to hold data for multiplication and division operations

SP Stack Pointer Used to hold the offset address of top stack memory

BP Base Pointer Used to hold the base value in base addressing using SS
register to access data from stack memory
SI Source Index Used to hold index value of source operand (data) for string
instructions
DI Data Index Used to hold the index value of destination operand (data) for
string operations

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 Difference between 8086 & 8088
Sl. No. 80886 8088
1. The data bus is of 16 bits. The data bus is of 8 bits.
2. It has 6 byte instruction It has 4 byte instruction queue
queue. as it can fetch only 1 byte at a
time.
3. It has Bank High Enable It has Status Signal (SSO).
(BHE) signal.
4. It has memory control pin It has complemented memory
(M/IO) signal. control pin (IO/M) signal of
8086.
5. Input/Output voltage level is Input/Output voltage level is
measured at 2.5 mA. measured at 2.0 mA
6. It has 3 available clock It has 2 available clock speeds
speeds (5 MHz, 8 MHz (8086- (5 MHz, 8 MHz)
2) and 10 MHz (8086-1)).
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 X86 -ISA
Programming Model

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 Programming Model
• The programming model of 8086 is considered to be program
visible.
• Registers are visible to the application program.
• Some registers are program invisible and cannot be addressed in
application programs.
• Only 80286 and above contain program invisible registers.

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 Programming Model

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 Memory Addressing
• Real
– Access only 1MB of memory
– Only 20 Address lines required.
– 8086 and 8088 operate only in real mode.
• Protected
– support multitasking
– memory management protection enabled
– 80286 and above operate either in real mode or protected mode.
– Allows access to data and program both above as well as with 1 M byte of memory.
• In the 64-bit operation mode of Pentium 4 and core2, there is no real
mode operation.

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 Thank You.

Questions???

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