LAB# 14

BAHRIA UNIVERSITY KARACHI CAMPUS

Department of Computer Science

DIGITAL LOGIC DESIGN

LAB EXPERIMENT # 14

Introduction to Verilog Programming

OBJECTIVE:
 To Introduce FPGA Kit (Spartan 3A).
 To Understand its Xilinx Development Tools.
 To Understand the Basic Verilog Gate-Level Modelling.

EQUIPMENT:
 Personal Computer
 Xilinx ISE Design Suite 14.2
 Spartan-3A FPGA Kit
THEORY:
1. SPARTAN-3A FPGA KIT Key Features.
Fig. 1.13: NOR Gate Symbol & TTL IC
TABLE 14.1: SPARTAN-3A Package Specifications
Xilinx Clocks Memory Analog Connectors and Interfaces Display
Device Interface
Devices

Spartan- 50 MHz 4 Mbit 4-channel Ethernet 10/100 PHY

16 by
3A crystal Platform D/A JTAG USB download port
2-Line
(XC3S70 oscillato converter Two 9-pin RS-232 serial port
LCD
0A- r on- Flash PROM PS/2-style mouse/keyboard port
FG484) board 2-channel 15-pin VGA connector capable of
32M x 16 A/D 4,096 colors
Platform Open DDR2 converter One FX2 100-pin and two 6-pin
Flash slot for SDRAM Signal expansion connectors
(XCF04S optional amplifier 20 user I/O available on standard
- user- 32 Mbit header pins
VOG20C installed parallel Flash Stereo mini-jack for PWM audio
) clock Rotary/push button function
2-16 Mbit switch
SPI Flash Eight individual LED outputs
devices Eight slider switches
Four push-button switches.
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Fig. 14.1: Spartan-3A FPGA Kit

2. Xilinx Software.

The Xilinx ISE 14.2 software will be used in this manual. All menus structures and screen shots
are taken from the ISE 14.2 version.

2.1 Starting the Xilinx ISE.

To start the ISE Design Suite 14.2software, double-click the ISE Design Suite 14.2 Icon on your
desktop, or Select Start > All Programs > Xilinx ISE Design Suite 14.2> ISE Design Tools >
Project Navigator, as shown in Fig. 14.2.

Fig. 14.2: Xilinx ISE Design Suite 14.2 Icon

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Transcript
Toolbar Sources window Processes window Workspace
window

Fig. 14.3: XILINX Software Main Window

2.2 Creating a New Project.

To create a new project using the New Project Wizard, do the following:

From Project Navigator, select File > New Project. The New Project Wizard appears. See figure
5. Enter the project path and name as shown below. Click Next.

Fig. 14.4: Project Window

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The New Project Wizard—Device Properties page appears.

Select the following values in the New Project Wizard—Device Properties page:
 Product Category: All
 Family: Spartan3A and Spartan3AN
 Device: XC3S700A
 Package: FG484
 Speed: -4
 Synthesis Tool: XST (VHDL/Verilog)
 Simulator: ISim (VHDL/Verilog)
 Preferred Language: Verilog

Click Next, then Finish to complete the project creation.

Fig. 14.5: XILINX Software Main Window

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2.3 Adding Source Files Using the New Source Wizard and ISE Text Editor.

In this section, you create a file using the New Source wizard, specifying the name and ports of
the component. The resulting HDL file is then modified in the ISE Text Editor.

To create the source file, do the following:

1. Select Project > New Source. The New Source Wizard opens in which you specify the
type of source you want to create.
2. In the Select Source Type page, select Verilog Module.
3. In the File Name field, enter logic_gates.

Fig. 14.6: Adding Source File

1. Click Next.

2. In the Define Module page, enter two input ports named a, b and c as an output port.

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Fig. 14.7: Specifying Inputs and Outputs

6. Click Next to view a description of the module.

7. Click Finish to open the empty HDL file in the ISE Text Editor.

Following is an example Verilog file.

Fig. 14.8: ISE Text Editor

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In the ISE Text Editor, the ports are already declared in the HDL file, and some of the basic file
structure is already in place. Keywords are displayed in blue, comments in green, and values are
black. The file is color-coded to enhance readability and help you recognize typographical errors.

3. Verilog VHDL Programming.

 AND Gate.
The AND function is similar to the multiplication in mathematics. This is the all or
nothing operator and it provides a logic 1 output only when all the inputs of the gate are
at logic 1, and logic 0 output for all other input combinations. The logic operator for the
AND function is a dot (∙) sign. The AND function is described in terms of the following
“truth table”. In terms of logic symbols, OUT = A●B.

module and1 (Y, A, B);

output Y;
Input: A Input: B Out: A●B
input A, B;
and (Y, A, B);
0 0 0
endmodule
0 1 0
1 0 0
1 1 1

 OR Gate.
The OR function is similar to the mathematical function of addition and the output for the
OR gate may be analyzed using the laws of addition. The logic operator for the OR function is a
plus (+) sign. The output will be logic 0 only if all the inputs are logic 0, and the output will be
logic 1 anytime any input is at logic 1. Here, OUT = A+B.

module or1 (Y,A,B);

output Y; Input: A Input: B Out: A+B
input A, B;
or (Y, A, B); 0 0 0
endmodule 0 1 1
1 0 1
1 1 1

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4. TestBench / Timing Diagram

A TestBench is used to test the gate that we have created. TestBench is another
Verilog Code that creates a circuit involving the circuit to be tested by applying different
waveforms. This code will send different inputs to the code under test and get the output
and displays to check the accuracy. We will use ISim Simulation tool that is integrated
into Xilinx ISE. ISim provides a Test Bench Waveform Editor in which you can
graphically define your test benches or test fixtures.
To create and view TestBench in Xilinx ISE, highlight the module and inside the
design area select the simulation radial button. Select your TestBench anddouble click
simulate behavioral model. ISim will be launched and from there you can look at your
waveform to debug your top level module. (The TestBench / Timing Diagram of 2-input
AND Gate is shown in Figure 9).

Fig. 14.9: AND Gate TestBench / Timing Diagram

Exercises:
1. Write the Verilog Codes for the Basic Gates (2 – Inputs). i.e. AND, OR, NOT, NOR, NAND,
XOR and XNOR and verify through Test Bench / Timing Diagram.

2. Write the Verilog Code for the Full Adder Circuit as shown below. Attach the RTL
Schematic and Timing Diagram with this Lab.

Teacher Signature: ________________________

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Student Registration No: ________________________

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