physical design -inputs

Physical Design : It is the process of transforming a Logical description (in form of Netlist) into the
physical layout(finally in form of GDS2) , which describes the position of cells and routes the
interconnection between them.

Import Design :
Foundry inputs Ip related inputs Design related inputs Tdf
1. technology file (.tf) 1.physical library (.lef) 1. gated net list (.vg) 1.size of block

2.rc tech file 2.logical library (.lib) 2.standard design constrains 2. inputs and
i.TLU file (.sdc) outs of port
ii.cap tabular locations

Technology File
Technology file: format is .tf:
Technology file defines basic characteristic of cell library pertaining to a particular technology
node. They are units used in the design, graphical characteristics like colors, stipple patterns, line
styles, physical parameters of metal layers, coupling capacitances, capacitance models, dielectric
values, device characteristics, design rules. These specifications are divided into technology file
sections.
Units for power, voltage, current etc are defined in technology section.
The color section defines primary and display colors that a tool uses to display designs in the
library. Stipple pattern are defined in stipple sections. Different layer definitions like its current
density, width etc are defined in layer section. Fringe capacitances generated by crossing of
interconnects are defined in fringe cap section.
Similarly several other specifications like metal density, design rules that apply to design in
library, place and route (P&R) rules, slot rule, resistance model are defined in their respective sections.
Layer Info :
Mask Name
Visible
Selectable
Line Style(Solid)
Pattern
Pitch
Cut Layer TLU PLUS

TLU+ files: format is .TLUP:

1. R,C parasitics of metal per unit length.
2. These(R,C parasitics) are used for calculating Net Delays.
3. If TLU+ files are not given then these are getting from .ITF file.
4. For Loading TLU+ files we have load three files .
5. Those are Max Tlu+, Min TLU+,MAP file.
6. MAP file maps the .ITF file and .tf file of the layer and via names.
 Physical Libraries

Physical libraries: format is .lef:

1. physical information of std cells, macros, pads.
2. Pin information.
3. Define unit tile placement.
4. Hight of the placement Rows .
5. Minimum Width of Resolution
6. Preferred routing Directions.
7. Pitch of the routing tracks.
8. Antena Rules.
9. Routing Blockages
In physical info height,area,width are present.
and also it contains two views

1)Cell View:
In this all layout information is present,it is used at the time of tapeout
2)FRAM view:
Fram view is abstract view, it is used at the Place & Route
For every technology the layer and the via statements are different. So for the layer and via, the type of
the layer (layer may be routing type, master slice or overlap), width/pitch and spacing, direction,
resistance, capacitance, and antenna factor are defined.

Logical Libraries

1. Timing information of Standard cells,Soft macros,Hard macros.

2. functionality information of Standard cells,Soft macros.
3. And design rules like max transition ,max capacitance, max fanout.
4. In timing information Cell delays ,Setup,Hold time are present.
5. Cell delay is Function of input transition and output load.
6. Cell delay is calculated based on lookup tables.
7. Cell delays are calculated by using linear delay models,Non linear delay models,CCS models.

.lib is basically a timing model contains cell delays, transition, setup and hold time requirements. CCS
and NLDM techniques are used to generate .lib files. In CCS (composite current source) current source is
used for driver modeling, CCS has 20 variables to account input slew and output load data where as,
NLDM uses the voltage source for driver modeling and it has only 2 variables which are not sufficient for
modeling the nonlinearity of any circuit. So CCS is more accurate than NLDM. Because of the difference
in number of variables used in both the models, size of CCS file is 10X times larger than the NLDM file.
Also the run time for CCS is more when compared to NLDM.

The design needs to be tested for certain PVT (process voltage and temperature) corners. But for every
PVT corner, the timing of the cells are different. Hence there is a .lib file for every PVT corner.

In .lib file following unit attributes are present

Capacitive load unit
Slew rate : Lower and upper limit values are defined in terms of percentage for both rise and fall time
Input threshold at rise and fall time
Output threshold for rise and fall time
Look Up table templates are defined for different parameters like delay, hold, passive energy, recovery,
removal, setup, with different matrix.
For each cell (AND, NAND, Or etc..) following attributes are defined:
Area of cell, Leakage power, Capacitance ,Rise and fall capacitance

Netlist

Netlist: Format is .V

It contains Logical connectivity Of all Cell(Std cells, Macros).

It contain List of nets.
In the design for Knowing connectivity by using Fly lines.

SDC (Synopsys Design Constraints).

There is a common format, for constraining the design, which is supported by almost all the tools, and
this format is called SDC - Synopsis Design Constraints format.
The file is saved with an .sdc extention
SDC syntax is a TCL based format, that is, all commands follow the TCL syntax
SDC contains mainly following constraints that are very essential for design
Clock definition, Generated clock, Input/output delay,
Min/Max delay, False path, Multi cycle path,
Case analysis, Disable timing arc
The constraints are the following types according the commands types:
Basic commands
Object Access Commands
Timing Commands
Environment Commands
Multi-Voltage Commands
Basic Constraints commands False path : set_false_path
these commands used to set the attributes from Input/Output delay : set_input_delay
that instance & set_output_delay
cmd: set: used to define variables Min/Max delay : set_min_delay
for example: set_units [-capacitance cap_unit] / set_max_delay
[-resistance res_units] [-time time_unit] [- Multicycle path : set_multicycle_path
voltage voltage_unit][-current current_unit] [-
power power_unit] Environmental constraints
Object Access Constraints commands these commands are used to setup the
These commands specify how to access objects environment of the design under analysis
in a design instance. commands are:
these commands are used to get the location of set_driving_cell
an object in the design. set_input_transition
the object can be a cell, a block, a port, a pin, or set_load
anything else in the design. set_max_fanout
for example: set_max_area
all_clocks set_operating_conditions
# Returns a collection of all clocks. set_wire_load_model
Examples: set_case_analysis.......etc
foreach_in_collection clkvar [all_clocks] {
. . .} Multi-Voltage Commands
set_clock_transition 0.150 [all_clocks] these commands apply when multi-voltage
get_libs [-regexp] [-nocase] patterns islands are present in s design.
# Returns a collection of libraries that are commands are:
currently create_voltage_area
# loaded in the design. set_level_shifter_strategy
set_level_shifter_threshold
Timing Constraints commands set_max_dynamic_power
these commands are related to timing
set_max_leakage_power
specifications of the design
Clock gating method (ICG) [logic intent of the
which contains,
design]
Clock definition : create_clock Multiple height cells
Generated clock : create_generated_clock Multi-voltage design (MVD)
Clock transition : set_clock_transition
Power shut-off (PSO) or Power Gating
Clock Uncertainty : set_clock_uncertainty
Multi-Vth design (MV)
Clock Latency : set_clock_latency
Propagated clock : set_propagated_clock
Dyamic voltage and frequency scaling (DVFS)
Disable timing : set_disable_timing
 UPF(Unified Power Format)

This is for low power devices once the design is extracted in the form of technology independent cells,
timing constraints are imported from the SDC file.

If the design consists of multiple power domains, then using the UPF power domains, isolation cells, level
shifters, power switches, retention flops are placed.

The logical intent of the design is completely provided with the help of RTL code but its complicated to
provide power information. Hence the power intent of the design is specified in UPF. Power management
file will be built at the architecture level of design stage. This forms a complete description of the design.
Various methods used for the power management are:

Clock gating method (ICG) [logic intent of the design]

Multiple height cells

Multi-voltage design (MVD)

Power shut-off (PSO) or Power Gating

Multi-Vth design (MV)

Dyamic voltage and frequency scaling (DVFS).