a 67 MSPS Digital Receive

Signal Processor
AD6620
FEATURES FUNCTIONAL BLOCK DIAGRAM
High Input Sample Rate
67 MSPS Single Channel Real I I I
33.5 MSPS Diversity Channel Real REAL,
SERIAL OR
33.5 MSPS Single Channel Complex DUAL REAL, CIC
FILTERS
FIR
FILTER
OUTPUT PARALLEL
OR COMPLEX FORMAT OUTPUTS
NCO Frequency Translation INPUTS Q Q Q

Worst Spur Better than –100 dBc

Tuning Resolution Better than 0.02 Hz COS –SIN

2nd Order Cascaded Integrator Comb FIR Filter

Linear Phase, Fixed Coefficients EXTERNAL ␮P
COMPLEX JTAG
AD6620 NCO SYNC PORT
OR SERIAL
Programmable Decimation Rates: 2, 3 . . . 16 CIRCUITRY CONTROL

5th Order Cascaded Integrator Comb FIR Filter

Linear Phase, Fixed Coefficients
Programmable Decimation Rates: 1, 2, 3 . . . 32
Programmable Decimating RAM Coefficient FIR Filter
Up to 134 Million Taps per Second
256 20-Bit Programmable Coefficients
Programmable Decimation Rates: 1, 2, 3 . . . 32 both narrowband and wideband carriers to be extracted. The
Bidirectional Synchronization Circuitry RAM-based architecture allows easy reconfiguration for multi-
Phase Aligns NCOs mode applications.
Synchronizes Data Output Clocks
Serial or Parallel Baseband Outputs The decimating filters remove unwanted signals and noise from
Pin Selectable Serial or Parallel
the channel of interest. When the channel of interest occupies
Serial Works with SHARC®, ADSP-21xx, Most Other
less bandwidth than the input signal, this rejection of out-of-
DSPs band noise is called “processing gain.” By using large decimation
16-Bit Parallel Port, Interleaved I and Q Outputs
factors, this “processing gain” can improve the SNR of the
Two Separate Control and Configuration Ports
ADC by 36 dB or more. In addition, the programmable RAM
Generic ␮P Port, Serial Port Coefficient filter allows antialiasing, matched filtering, and
3.3 V Optimized CMOS Process
static equalization functions to be combined in a single, cost-
JTAG Boundary Scan
effective filter.
The input port accepts a 16-bit Mantissa, a 3-bit Exponent,
GENERAL DESCRIPTION and an A/B Select pin. These allow direct interfacing with the
The AD6620 is a digital receiver with four cascaded signal- AD6600, AD6640, AD6644, AD9042 and most other high-
processing elements: a frequency translator, two fixed- speed ADCs. Three input modes are provided: Single Channel
coefficient decimating filters, and a programmable coefficient Real, Single Channel Complex, and Diversity Channel Real.
decimating filter. All inputs are 3.3 V LVCMOS compatible. When paired with an interleaved sampler such as the AD6600,
All outputs are LVCMOS and 5 V TTL compatible. the AD6620 can process two data streams in the Diversity
As ADCs achieve higher sampling rates and dynamic range, it Channel Real input mode. Each channel is processed with coher-
becomes increasingly attractive to accomplish the final IF stage ent frequency translation and output sample clocks. In addition,
of a receiver in the digital domain. Digital IF Processing is less external synchronization pins are provided to facilitate coherent
expensive, easier to manufacture, more accurate, and more frequency translation and output sample clocks among several
flexible than a comparable highly selective analog stage. AD6620s. These features can ease the design of systems with
diversity antennas or antenna arrays.
The AD6620 diversity channel decimating receiver is designed
to bridge the gap between high-speed ADCs and general pur- Units are packaged in an 80-lead PQFP (plastic quad flatpack)
pose DSPs. The high resolution NCO allows a single carrier to and specified to operate over the industrial temperature range
be selected from a high speed data stream. High dynamic range (–40°C to +85°C).
decimation filters with a wide range of decimation rates allow

SHARC is a registered trademark of Analog Devices, Inc.

REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com
under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2001
AD6620
TABLE OF CONTENTS ARCHITECTURE
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1 As shown in Figure 1, the AD6620 has four main signal pro-
cessing stages: a Frequency Translator, two Cascaded Integrator
ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Comb FIR Filters (CIC2, CIC5), and a RAM Coefficient FIR
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Filter (RCF). Multiple modes are supported for clocking data
TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 into and out of the chip. Programming and control is accom-
plished via serial and microprocessor interfaces.
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . 11
Input data to the chip may be real or complex. If the input data
EXPLANATION OF TEST LEVELS . . . . . . . . . . . . . . . . 11 is real, it may be clocked in as a single channel or interleaved
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 with a second channel. The two-channel input mode, called
Diversity Channel Real, is typically used in diversity receiver
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . 12
applications. Input data is clocked in 16-bit parallel words,
PIN CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . 13 IN[15:0]. This word may be combined with exponent input bits
INPUT DATA PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 EXP[2:0] when the AD6620 is being driven by floating-point or
gain-ranging analog-to-digital converters such as the AD6600.
OUTPUT DATA PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Frequency translation is accomplished with a 32-bit complex
FREQUENCY TRANSLATOR . . . . . . . . . . . . . . . . . . . . . 19
Numerically Controlled Oscillator (NCO). Real data entering
SECOND ORDER CASCADED INTEGRATOR this stage is separated into in-phase (I) and quadrature (Q)
COMB FILTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 components. This stage translates the input signal from a digital
FIFTH ORDER CASCADED INTEGRATOR intermediate frequency (IF) to baseband. Phase and amplitude
COMB FILTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 dither may be enabled on-chip to improve spurious performance
of the NCO. A phase offset word is available to create a known
RAM COEFFICIENT FILTER . . . . . . . . . . . . . . . . . . . . . 25 phase relationship between multiple AD6620s.
CONTROL REGISTERS AND ON-CHIP RAM . . . . . . . 27 Following frequency translation is a fixed coefficient, high speed
PROGRAMMING THE AD6620 . . . . . . . . . . . . . . . . . . . 30 decimating filter that reduces the sample rate by a program-
ACCESS PROTOCOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 mable ratio between 2 and 16. This is a second order, cascaded
integrator comb FIR filter shown as CIC2 in Figure 1. (Note:
MICROPORT CONTROL . . . . . . . . . . . . . . . . . . . . . . . . 32 Decimation of 1 in CIC2 requires 2× or greater clock into
SERIAL PORT CONTROL . . . . . . . . . . . . . . . . . . . . . . . . 35 AD6620). The data rate into this stage equals the input data
rate, fSAMP. The data rate out of CIC2, fSAMP2, is determined by
JTAG BOUNDARY SCAN . . . . . . . . . . . . . . . . . . . . . . . . 37
the decimation factor, MCIC2.
APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 44
RCF
I-RAM
3 256 ⴛ 18
EXP[2:0] INPUT INTERLEAVE
16 DATA DE- C-RAM MRCF
IN[15:0]
INTERLEAVE 256 ⴛ 20
CIC5 MULTI- Q-RAM
PLEXER 256 ⴛ 18

SCALING MCICS
FREQUENCY 3
TRANSLATOR CIC2 MULTI-
I 18 PLEXER fSAMP5
23
16 EXP
SCALING MCICS 23
Q 18 SCALING
OUTPUT
fSAMP2
SCALING, SOUT DVOUT
COMPLEX
NCO I/QOUT
EXPLNV, RCF COEFFICIENTS
EXPOFF NUMBER OF TAPS A/BOUT
CIC2, CIC5 DECIMATE FACTOR MULTIPLEXER
PHASE DECIMATE FACTORS ADDRESS OFFSET
OFFSET fSAMP SCALE FACTORS
NCO FREQUENCY OUTPUT PARALLEL SERIAL
CLK PHASE OFFSET SCALE
DITHER FACTOR 16
A/B TIMING
SYNC MASK
CONTROL REGISTERS
RESET OUT[15:0]
INPUT MODE
REAL, DUAL, COMPLEX MICROPORT AND SCLK
FIXED OR WITH EXPONENT SERIAL ACCESS SDI
SYNC M/S PARALLEL
SYNC NCO 16 SDO
OUTPUTS
AND SDFS
SYNC CIC SYNC
SERIAL I/O SDFE
I/O JTAG MICROPROCESSOR INTERFACE
SBM
SYNC RCF WL[1:0]
TRST TCK TMS TDI TDO D[7:0] A[2:0] CS R/W DS DTACK MODE PAR/SER AD
(W/R) (R/D) (RDY) SDIV[3:0]

Figure 1. Block Diagram

–2– REV. A
 AD6620
Following CIC2 is the second fixed-coefficient decimating filter. The overall filter response for the AD6620 is the composite of
This filter, CIC5, further reduces the sample rate by a program- all three cascaded decimating filters: CIC2, CIC5, and RCF. Each
mable ratio from 1 to 32. The data rate out of CIC5, fSAMP5, is successive filter stage is capable of narrower transition band-
determined by the decimation factors of MCIC5 and MCIC2. widths but requires a greater number of CLK cycles to calculate
Each CIC stage is a FIR filter whose response is defined by the the output. More decimation in the first filter stage will minimize
decimation rate. The purpose of these filters is to reduce the overall power consumption. Data comes out via a parallel port
data rate of the incoming signal so that the final filter stage, a FIR or a serial interface.
RAM coefficient sum-of-products filter (RCF), can calculate Figure 2 illustrates the basic function of the AD6620: to select
more taps per output. As shown in Figure 1, on-chip multiplex- and filter a single channel from a wide input spectrum. The
ers allow both CIC filters to be bypassed if a multirate clock frequency translator “tunes” the desired carrier to baseband.
is used. CIC2 and CIC5 have fixed order responses; the RCF filter
The fourth stage is a sum-of-products FIR filter with program- provides the sharp transitions. More detail is provided in later
mable 20-bit coefficients, and decimation rates programmable sections of the data sheet.
from 1 to 32. The RAM Coefficient FIR Filter (RCF in Figure
1) can handle a maximum of 256 taps.

WIDEBAND INPUT SPECTRUM (–fsamp/2 TO fsamp/2)

SIGNAL OF INTEREST "IMAGE" SIGNAL OF

C' A' A C
INTEREST
B' B D
D'

–fS /2 –3fS /8 –5fS /16 –fS /4 –3fS /16 –fS /8 –fS /16 DC fS /16 fS /8 3fS /16 fS /4 5fS /16 3fS /8 fS /2

Figure 2a. Wideband Input Spectrum (e.g., 30 MHz from High-Speed ADC)

NCO "TUNES" SIGNAL TO BASEBAND

AFTER FREQUENCY TRANSLATION C C'

A A'
B B'
D D'

–fS /2 –3fS /8 –5fS /16 –fS /4 –3fS /16 –fS /8 –fS /16 DC fS /16 fS /8 3fS /16 fS /4 5fS /16 3fS /8 fS /2

Figure 2b. Frequency Translation (e.g., Single 1 MHz Channel Tuned to Baseband)

CIC2, CIC5, AND RCF

0
–10
–20
–30
–40
–50
–60
dBc

–70
–80
–90
–100
–110
–120
–130
FREQUENCY

Figure 2c. Baseband Signal is Decimated and Filtered by CIC2, CIC5, RCF

REV. A –3–
AD6620–SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
Test AD6620AS
Parameter Level Min Typ Max Unit
VDD I 3.0 3.3 3.6 V
TAMBIENT IV –40 +25 +85 °C

ELECTRICAL CHARACTERISTICS
Test AD6620AS
Parameter (Conditions) Temp Level Min Typ Max Unit
1, 2, 3, 4, 5, 6, 7
LOGIC INPUTS (NOT 5 V TOLERANT)
Logic Compatibility Full 3.3 V CMOS
Logic “1” Voltage Full I 2.0 VDD + 0.3 V
Logic “0” Voltage Full I –0.3 0.8 V
Logic “1” Current Full I 1 10 µA
Logic “0” Current Full I 1 10 µA
Input Capacitance 25°C V 4 pF
LOGIC OUTPUTS2, 4, 7, 8, 9, 10, 11
Logic Compatibility Full 3.3 V CMOS/TTL
Logic “1” Voltage (IOH = 0.5 mA) Full I 2.4 VDD – 0.2 V
Logic “0” Voltage (IOL = 1.0 mA) Full I 0.2 0.4 V
IDD SUPPLY CURRENT
CLK = 20 MHz12 Full V 52 mA
CLK = 65 MHz13 Full I 167 227 mA
Reset Mode14 Full I 1 mA
POWER DISSIPATION
CLK = 20 MHz12 Full V 170 mW
CLK = 65 MHz13 Full I 550 750 mW
Reset Mode14 Full I 3.3 mW
NOTES
1
Input-Only Pins: CLK, RESET, IN[15:0], EXP[2:0], A/B, PAR/SEL.
2
Bidirectional Pins: SYNC_NCO, SYNC_CIC, SYNC_RCF.
3
Microinterface Input Pins: DS (RD), R/W (WR), CS.
4
Microinterface Bidirectional Pins: A[2:0], D[7:0].
5
JTAG Input Pins: TRST, TCK, TMS, TDI.
6
Serial Mode Input Pins: SDI, SBM, WL[1:0], AD, SDIV[3:0].
7
Serial Mode Bidirectional Pins: SCLK, SDFS.
8
Output Pins: OUT[15:0], DV OUT, A/BOUT, I/QOUT.
9
Microinterface Output Pins: DTACK (RDY).
10
JTAG Output Pins: TDO.
11
Serial Mode Output Pins: SDO, SDFE.
12
Conditions for IDD @ 20 MHz. M CIC2 = 2, MCIC5 = 2, MRCF = 1, 4 RCF taps of alternating positive and negative full scale.
13
Conditions for IDD @ 65 MHz. M CIC2 = 2, MCIC5 = 2, MRCF = 1, 4 RCF taps of alternating positive and negative full scale.
14
Conditions for IDD in Reset (RESET = 0).
Specifications subject to change without notice.

–4– REV. A
 AD6620
TIMING CHARACTERISTICS (C LOAD = 40 pF All Outputs)
Test AD6620AS
Parameter (Conditions) Temp Level Min Typ Max Unit
CLK Timing Requirements:
tCLK CLK Period Full I 14.931 ns
tCLK CLK Period Full I 15.4 ns
tCLKL CLK Width Low Full IV 7.0 0.5 × tCLK ns
tCLKH CLK Width High Full IV 7.0 0.5 × tCLK ns
Reset Timing Requirements:
tRESL RESET Width Low Full I 30.0 ns
Input Data Timing Requirements:
tSI Input2 to CLK Setup Time Full IV –1.0 ns
tHI Input2 to CLK Hold Time Full IV 6.5 ns
Parallel Output Switching Characteristics:
tDPR CLK to OUT[15:0] Rise Delay Full IV 8.0 19.5 ns
tDPF CLK to OUT[15:0] Fall Delay Full IV 7.5 19.5 ns
tDPR CLK to DVOUT Rise Delay Full IV 6.5 19.0 ns
tDPF CLK to DVOUT Fall Delay Full IV 5.5 11.5 ns
tDPR CLK to IQOUT Rise Delay Full IV 7.0 19.5 ns
tDPF CLK to IQOUT Fall Delay Full IV 6.0 13.5 ns
tDPR CLK to ABOUT Rise Delay Full IV 7.0 19.5 ns
tDPF CLK to ABOUT Fall Delay Full IV 5.5 13.5 ns
SYNC Timing Requirements:
tSY SYNC3 to CLK Setup Time Full IV –1.0 ns
tHY SYNC3 to CLK Hold Time Full IV 6.5 ns
SYNC Switching Characteristics:
tDY CLK to SYNC4 Delay Time Full V 7.0 23.5 ns
Serial Input Timing:
tSSI SDI to SCLKt Setup Time Full IV 1.0 ns
tHSI SDI to SCLKt Hold Time Full IV 2.0 ns
tHSRF SDFS to SCLKu Hold Time Full IV 4.0 ns
tSSF SDFS to SCLKt Setup Time5 Full IV 1.0 ns
tHSF SDFS to SCLKt Hold Time5 Full IV 2.0 ns
Serial Frame Output Timing:
tDSE SCLKu to SDFE Delay Time Full IV 3.5 11.0 ns
tSDFEH SDFE Width High Full V tSCLK ns
tDSO SCLKu to SDO Delay Time Full IV 4.5 11.0 ns
SCLK Switching Characteristics, SBM = “1”:
tSCLK SCLK Period4 Full I 2 × tCLK ns
tSCLKL SCLK Width Low Full V 0.5 × tSCLK ns
tSCLKH SCLK Width High Full V 0.5 × tSCLK ns
tSCLKD CLK to SCLK Delay Time Full V 6.5 13.0 ns
Serial Frame Timing, SBM = “1”:
tDSF SCLKu to SDFS Delay Time Full IV 1.0 4.0 ns
tSDFSH SDFS Width High Full V tSCLK ns
SCLK Timing Requirements, SBM = “0”:
tSCLK SCLK Period Full I 15.4 ns
tSCLKL SCLK Width Low Full IV 0.4 × tSCLK 0.5 × tSCLK ns
tSCLKH SCLK Width High Full IV 0.4 × tSCLK 0.5 × tSCLK ns
NOTES
1
This specification valid for VDD >= 3.3 V. t CLKL and tCLKH still apply.
2
Specification pertains to: IN[15:0], EXP[2:0], A/B.
3
Specification pertains to: SYNC_NCO, SYNC_CIC, SYNC_RCF.
4
SCLK period will be ≥ 2 × tCLK when AD6620 is Serial Bus Master (SBM = 1) depending on the SDIV word.
5
SDFS setup and hold time must be met, even when configured as outputs, since internally the signal is sampled at the pad.
Specifications subject to change without notice.

REV. A –5–