Scribd
Upload
53 views

Memory Circuit3

The document discusses various types of memory circuits and decoders used in digital systems. It describes NOR and NAND decoders that are commonly used for row and column address decoding. It also shows examples of 1-bit and 3-bit domino CMOS NAND decoders and pass transistor decoders. Additionally, it discusses different types of read-only memory (ROM) circuits like static NMOS ROM, domino CMOS ROM, NAND array ROM, and how programmable ROM was introduced to allow for post-fabrication configuration. Finally, it briefly describes how reset-set flip-flops can be implemented using cross-coupled NOR or NAND gates and a D-latch circuit using transmission gates

Uploaded by

salman1992
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
53 views

Memory Circuit3

The document discusses various types of memory circuits and decoders used in digital systems. It describes NOR and NAND decoders that are commonly used for row and column address decoding. It also shows examples of 1-bit and 3-bit domino CMOS NAND decoders and pass transistor decoders. Additionally, it discusses different types of read-only memory (ROM) circuits like static NMOS ROM, domino CMOS ROM, NAND array ROM, and how programmable ROM was introduced to allow for post-fabrication configuration. Finally, it briefly describes how reset-set flip-flops can be implemented using cross-coupled NOR or NAND gates and a D-latch circuit using transmission gates

Uploaded by

salman1992
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 15

Memory circuit3

NOR Decoders
• The following figures are examples of commonly used decoders for row and
column address decoding

NMOS NOR Decoder


Jaeger/Blalock Microelectronic Circuit Design
Chap 8 - 2
10/17/03 McGraw-Hill
NAND Decoders
• The following figures are examples of commonly used decoders for row and
column address decoding

NMOS NAND Decoder


Jaeger/Blalock Microelectronic Circuit Design
Chap 8 - 3
10/17/03 McGraw-Hill
Address Decoders
One row of a 3 bit
NAND decoder in
domino CMOS logic

Jaeger/Blalock Microelectronic Circuit Design


Chap 8 - 4
10/17/03 McGraw-Hill
Address Decoders
Complete 3-bit domino
CMOS NAND decoder

Jaeger/Blalock Microelectronic Circuit Design


Chap 8 - 5
10/17/03 McGraw-Hill
Address Decoders

Data transmission through pass transistor decoder (a) 0 input data (b) 1 input data

Jaeger/Blalock Microelectronic Circuit Design


Chap 8 - 6
10/17/03 McGraw-Hill
Address Decoders

3-bit column data


selector using pass-
transistor logic

Jaeger/Blalock Microelectronic Circuit Design


Chap 8 - 7
10/17/03 McGraw-Hill
Read-Only Memory (ROM)
• ROM is often needed in digital systems such as:
• Holding the instruction set for a microprocessor
• Firmware
• Calculator plug-in modules
• Cartridge style video games

Jaeger/Blalock Microelectronic Circuit Design


Chap 8 - 8
10/17/03 McGraw-Hill
Read-Only Memory (ROM)
• The basic structure of
the NMOS static ROM
is shown in the figure
• The existence of a
NMOS means a “0” is
stored at that address
otherwise a “1” is
stored
• The major downfall to
this particular circuit is
that it dissipates a lot
of power

Jaeger/Blalock Microelectronic Circuit Design


Chap 8 - 9
10/17/03 McGraw-Hill
Read-Only Memory (ROM)
• The domino
CMOS ROM is
one technique
used to lower the
amount of power
dissipation

Jaeger/Blalock Microelectronic Circuit Design


Chap 8 - 10
10/17/03 McGraw-Hill
Read-Only Memory (ROM)
• Another ROM
option is the
NAND array
ROM which can
be directly used
with a NAND
decoder

Jaeger/Blalock Microelectronic Circuit Design


Chap 8 - 11
10/17/03 McGraw-Hill
Read-Only Memory (ROM)
• The main problem with these previous ROMs is that they must be designed at the
mask level, meaning that it was not a versatile product.
• To solve this problem, the programmable ROM (PROM) was introduced
• The standard PROM cannot be erased, so the erasable ROM (EPROM), and later,
electrically erasable ROM (EEPROM) were introduced
• High density flash memories allow for selective electrical erasure and
reprogramming of memory cells

Jaeger/Blalock Microelectronic Circuit Design


Chap 8 - 12
10/17/03 McGraw-Hill
RS Flip-Flop
• The reset-set (RS) flip-flop can be easily realized by using either two
cross-coupled NOR or NAND gates
• The RSFF has the following truth tables
RSFF using NOR gates
NOR RSFF
R S Q Q
0 0 Q Q
0 1 1 0
1 0 0 1
1 1 0 0

Jaeger/Blalock Microelectronic Circuit Design


Chap 8 - 13
10/17/03 McGraw-Hill
RS Flip-Flop

R S Q Q
0 0 Q Q
0 1 0 1
1 0 1 0
1 1 1 1

NAND RSFF
NAND RSFF

Jaeger/Blalock Microelectronic Circuit Design


Chap 8 - 14
10/17/03 McGraw-Hill
D-Latch using T-Gates
• A very important circuit of digital systems is the D-Latch which is used
for a D flip-flop
• Whenever C (clock) goes high in the below D-Latch, whatever is on D
is passed through to Q

Jaeger/Blalock Microelectronic Circuit Design


Chap 8 - 15
10/17/03 McGraw-Hill

You might also like