3.

3V Uniform Sector
Dual and Quad Serial Flash GD25Q128C

GD25Q128C

DATASHEET

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 3.3V Uniform Sector
Dual and Quad Serial Flash GD25Q128C
Contents
1. FEATURES ................................................................................................................................................................ 4

2. GENERAL DESCRIPTION ...................................................................................................................................... 5

3. MEMORY ORGANIZATION .................................................................................................................................... 7

4. DEVICE OPERATION .............................................................................................................................................. 8

5. DATA PROTECTION .............................................................................................................................................. 10

6. STATUS REGISTER ............................................................................................................................................... 13

7. COMMANDS DESCRIPTION ............................................................................................................................... 15

7.1. WRITE ENABLE (WREN) (06H) ......................................................................................................................... 19

7.2. WRITE DISABLE (WRDI) (04H) ......................................................................................................................... 19
7.3. WRITE ENABLE FOR VOLATILE STATUS REGISTER (50H) .................................................................................. 20
7.4. READ STATUS REGISTER (RDSR) (05H OR 35H OR 15H) .................................................................................. 21
7.5. WRITE STATUS REGISTER (WRSR) (01H OR 31H OR 11H) ................................................................................ 22
7.6. READ DATA BYTES (READ) (03H) .................................................................................................................... 23
7.7. READ DATA BYTES AT HIGHER SPEED (FAST READ) (0BH) .............................................................................. 23
7.8. DUAL OUTPUT FAST READ (3BH) ...................................................................................................................... 24
7.9. QUAD OUTPUT FAST READ (6BH) ..................................................................................................................... 25
7.10. DUAL I/O FAST READ (BBH) ............................................................................................................................. 26
7.11. QUAD I/O FAST READ (EBH) ............................................................................................................................. 28
7.12. QUAD I/O WORD FAST READ (E7H) .................................................................................................................. 30
7.13. SET BURST WITH WRAP (77H) ........................................................................................................................... 31
7.14. PAGE PROGRAM (PP) (02H) ............................................................................................................................... 32
7.15. QUAD PAGE PROGRAM (32H)............................................................................................................................. 34
7.16. SECTOR ERASE (SE) (20H) ................................................................................................................................. 35
7.17. 32KB BLOCK ERASE (BE) (52H) ....................................................................................................................... 36
7.18. 64KB BLOCK ERASE (BE) (D8H) ...................................................................................................................... 37
7.19. CHIP ERASE (CE) (60/C7H) ............................................................................................................................... 38
7.20. DEEP POWER-DOWN (DP) (B9H) ....................................................................................................................... 39
7.21. RELEASE FROM DEEP POWER-DOWN AND READ DEVICE ID (RDI) (ABH) ........................................................ 40
7.22. READ MANUFACTURE ID/ DEVICE ID (REMS) (90H)........................................................................................ 42
7.23. READ MANUFACTURE ID/ DEVICE ID DUAL I/O (92H)...................................................................................... 43
7.24. READ MANUFACTURE ID/ DEVICE ID QUAD I/O (94H) ..................................................................................... 44
7.25. READ IDENTIFICATION (RDID) (9FH) ................................................................................................................ 45
7.26. PROGRAM/ERASE SUSPEND (PES) (75H) ........................................................................................................... 47
7.27. PROGRAM/ERASE RESUME (PER) (7AH) ........................................................................................................... 48
7.28. ERASE SECURITY REGISTERS (44H) ................................................................................................................... 49
7.29. PROGRAM SECURITY REGISTERS (42H).............................................................................................................. 49
7.30. READ SECURITY REGISTERS (48H)..................................................................................................................... 51
7.31. INDIVIDUAL BLOCK/SECTOR LOCK (36H)/UNLOCK (39H)/READ (3DH) ........................................................... 52
7.32. GLOBAL BLOCK/SECTOR LOCK (7EH) OR UNLOCK (98H) ................................................................................. 55

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Dual and Quad Serial Flash GD25Q128C
7.33. SET READ PARAMETERS (C0H) .......................................................................................................................... 57
7.34. BURST READ WITH WRAP (0CH)........................................................................................................................ 58
7.35. ENABLE QPI (38H)............................................................................................................................................. 58
7.36. DISABLE QPI (FFH) ........................................................................................................................................... 59
7.37. ENABLE RESET (66H) AND RESET (99H) ............................................................................................................ 59
7.38. READ SERIAL FLASH DISCOVERABLE PARAMETER (5AH) ................................................................................. 60

8. ELECTRICAL CHARACTERISTICS ................................................................................................................... 66

8.1. POWER-ON TIMING ....................................................................................................................................... 66

8.2. INITIAL DELIVERY STATE ........................................................................................................................... 66
8.3. DATA RETENTION AND ENDURANCE ...................................................................................................... 66
8.4. ABSOLUTE MAXIMUM RATINGS ............................................................................................................... 67
8.5. CAPACITANCE MEASUREMENT CONDITIONS ....................................................................................... 67
8.6. DC CHARACTERISTICS................................................................................................................................. 68
8.7. AC CHARACTERISTICS................................................................................................................................. 69

9. ORDERING INFORMATION ................................................................................................................................. 72

10. PACKAGE INFORMATION ............................................................................................................................... 73

10.1. PACKAGE SOP8 208MIL ................................................................................................................................... 73

10.2. PACKAGE VSOP8 208MIL................................................................................................................................. 74
10.3. PACKAGE SOP16 300MIL.................................................................................................................................. 75
10.4. PACKAGE DIP8 300MIL .................................................................................................................................... 76
10.5. PACKAGE WSON 8 (6*5MM) ............................................................................................................................. 77
10.6. PACKAGE WSON 8 (8*6MM) ............................................................................................................................. 78
10.7. PACKAGE TFBGA-24BALL (6*4 BALL ARRAY) ................................................................................................ 79

11. REVISION HISTORY .......................................................................................................................................... 80

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Dual and Quad Serial Flash GD25Q128C
1. FEATURES

◆ 128M-bit Serial Flash ◆ Program/Erase Speed

-16384K-byte -Page Program time: 0.6ms typical
-256 bytes per programmable page -Sector Erase time: 50ms typical
-Block Erase time: 0.2/0.3s typical
◆ Standard, Dual, Quad SPI -Chip Erase time: 60s typical
-Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD#/ RESET#
-Dual SPI: SCLK, CS#, IO0, IO1, WP#, HOLD#/ RESET# ◆ Flexible Architecture
-Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3 -Sector of 4K-byte
-QPI: SCLK, CS#, IO0, IO1, IO2, IO3 -Block of 32/64k-byte

◆ Low Power Consumption

◆ High Speed Clock Frequency -20mA maximum active current
-104MHz for Standard and Dual SPI fast read with 30PF load -5uA maximum power down current
-80MHz for Quad SPI and QPI fast read with 30PF load
-Dual I/O Data transfer up to 208Mbits/s ◆ Advanced Security Features(1)
-Quad I/O Data transfer up to 320Mbits/s -3*512-Byte Security Registers With OTP Locks
-QPI Mode Data transfer up to 320Mbits/s -Discoverable parameters(SFDP) register
-Continuous Read With 8/16/32/64-byte Wrap

◆ Software/Hardware Write Protection ◆ Single Power Supply Voltage

-Write protect all/portion of memory via software -Full voltage range:2.7~3.6V
-Enable/Disable protection with WP# Pin
-Top or Bottom, Sector or Block selection ◆ Package Information
-SOP8 (208mil)
-VSOP8 (208mil)
◆ Cycling endurance -SOP16 (300mil)
-Minimum 100,000 Program/Erase Cycles -DIP8 (300mil)
-WSON8 (6*8mm)
◆ Data retention -WSON8 (6*5mm)
-20-year data retention typical -TFBGA-24(6*4 ball array)

Note: 1.Please contact GigaDevice for details.

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Dual and Quad Serial Flash GD25Q128C
2. GENERAL DESCRIPTION

The GD25Q128C (128M-bit) Serial flash supports the standard Serial Peripheral Interface (SPI), and supports the
Dual/Quad SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (WP#), and I/O3 (HOLD#/ RESET#).
The Dual I/O data is transferred with speed of 208Mbits/s and the Quad I/O & Quad output data is transferred with speed
of 320Mbits/s.

CONNECTION DIAGRAM

CS# 1 8 VCC CS# 1 8 VCC

SO 2 7 HOLD#/ SO 2 7 HOLD#/
Top View RESET# Top View RESET#

WP# 3 6 SCLK WP# 3 6 SCLK

VSS 4 5 SI VSS 4 5 SI

8–LEAD SOP/VSOP/DIP 8–LEAD WSON

Top View

4
NC VCC WP# HOLD#/ NC NC
RESET#
3
NC VSS NC SI NC NC
2
NC SCLK CS# SO NC NC
1
NC NC NC NC NC NC

A B C D E F
24-BALL TFBGA

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Dual and Quad Serial Flash GD25Q128C

HOLD# 1 16 SCLK

VCC 2 15 SI

NC 3 14 NC

NC 4 13 NC
Top View
NC 5 12 NC

NC 6 11 NC

CS# 7 10 VSS

SO 8 9 WP#

16-LEAD SOP

Note: Only for special order, Pin 3 is RESET# pin. Please contact GigaDevice for detail.

PIN DESCRIPTION
Pin Name I/O Description
CS# I Chip Select Input
SO (IO1) I/O Data Output (Data Input Output 1)
WP# (IO2) I/O Write Protect Input (Data Input Output 2)
VSS Ground
SI (IO0) I/O Data Input (Data Input Output 0)
SCLK I Serial Clock Input
HOLD#/RESET# (IO3) I/O Hold or Reset Input (Data Input Output 3)
VCC Power Supply

BLOCK DIAGRAM

WP#(IO2) Write Control

Logic

Status
Write Protect Logic
and Row Decode

Register

HOLD# Flash
High Voltage
RESET#(IO3) Memory
Generators
SPI
SCLK Command &
Control Logic Page Address
CS# Latch/Counter

SI(IO0) Column Decode And

256-Byte Page Buffer
SO(IO1)
Byte Address
Latch/Counter

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3. MEMORY ORGANIZATION

GD25Q128C
Each device has Each block has Each sector has Each page has
16M 64/32K 4K 256 bytes
64K 256/128 16 - pages
4096 16/8 - - sectors
256/512 - - - blocks

UNIFORM BLOCK SECTOR ARCHITECTURE

GD25Q128C 64K Bytes Block Sector Architecture
Block Sector Address range

4095 FFF000H FFFFFFH

255 …… …… ……
4080 FF0000H FF0FFFH
4079 FEF000H FEFFFFH
254 …… …… ……
4064 FE0000H FE0FFFH
…… …… ……
…… …… …… ……
…… …… ……
…… …… ……
…… …… …… ……
…… …… ……
47 02F000H 02FFFFH
2 …… …… ……
32 020000H 020FFFH
31 01F000H 01FFFFH
1 …… …… ……
16 010000H 010FFFH
15 00F000H 00FFFFH
0 …… …… ……
0 000000H 000FFFH

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Dual and Quad Serial Flash GD25Q128C
4. DEVICE OPERATION

SPI Mode
Standard SPI
The GD25Q128C features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#),
Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is latched on the
rising edge of SCLK and data shifts out on the falling edge of SCLK.

Dual SPI
The GD25Q128C supports Dual SPI operation when using the “Dual Output Fast Read” and “Dual I/O Fast Read”
(3BH and BBH) commands. These commands allow data to be transferred to or from the device at two times the rate of the
standard SPI. When using the Dual SPI command the SI and SO pins become bidirectional I/O pins: IO0 and IO1.

Quad SPI
The GD25Q128C supports Quad SPI operation when using the “Quad Output Fast Read”,” Quad I/O Fast Read”,
“Quad I/O Word Fast Read” (6BH, EBH, E7H) commands. These commands allow data to be transferred to or from the
device at four times the rate of the standard SPI. When using the Quad SPI command the SI and SO pins become
bidirectional I/O pins: IO0 and IO1, and WP# and HOLD#/RESET# pins become IO2 and IO3. Quad SPI commands
require the non-volatile Quad Enable bit (QE) in Status Register to be set.

QPI
The GD25Q128C supports Quad Peripheral Interface (QPI) operations only when the device is switched from
Standard/Dual/Quad SPI mode to QPI mode using the “Enable the QPI (38H)” command. The QPI mode utilizes all four IO
pins to input the command code. Standard/Dual/Quad SPI mode and QPI mode are exclusive. Only one mode can be
active at any given times. “Enable the QPI (38H)” and “Disable the QPI (FFH)” commands are used to switch between
these two modes. Upon power-up and after software reset using “”Reset (99H)” command, the default state of the device is
Standard/Dual/Quad SPI mode. The QPI mode requires the non-volatile Quad Enable bit (QE) in Status Register to be set.

Hold
The HOLD/RST bit is used to determine whether HOLD# or RESET# function should be implemented on the
hardware pin for 8-pin packages. When HOLD/RST=0, the pin7 acts as HOLD#, the HOLD# function is only available when
QE=0, If QE=1, The HOLD# functions is disabled, the pin acts as dedicated data I/O pin.
The HOLD# signal goes low to stop any serial communications with the device, but doesn’t stop the operation of write
status register, programming, or erasing in progress.
The operation of HOLD, need CS# keep low, and starts on falling edge of the HOLD# signal, with SCLK signal being
low (if SCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD condition ends on rising edge
of HOLD# signal with SCLK being low (If SCLK is not being low, HOLD operation will not end until SCLK being low).
The SO is high impedance, both SI and SCLK don’t care during the HOLD operation, if CS# drives high during HOLD
operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and
then CS# must be at low.

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Dual and Quad Serial Flash GD25Q128C
Figure1. Hold Condition

CS#

SCLK

HOLD#

HOLD HOLD

RESET
The RESET# pin allows the device to be reset by the control. For the WSON8 package, the pin7 can be configured as
a RESET# pin depending on the status register setting, which need QE=0 and HOLD/RST=1. On the SOP16 package, a
dedicated RESET# pin is provided and it is independent of QE bit setting.
The RESET# pin goes low for a period of tRLRH or longer will reset the flash. After reset cycle, the flash is at the
following states:
-Standby mode
-All the volatile bits will return to the default status as power on.
Figure2. RESET Condition

CS#

RESET#

RESET

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5. DATA PROTECTION

The GD25Q128C provide the following data protection methods:

◆ Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL bit will
return to reset by the following situation:
-Power-Up
-Write Disable (WRDI)
-Write Status Register (WRSR)
-Page Program (PP)
-Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE)
◆ Software Protection Mode:
-The Block Protect (BP4, BP3, BP2, BP1, and BP0) bits define the section of the memory array that can be read
but not change.
-Individual Block Protection bit provides the protection selection of each individual block and sectors in the top and
bottom block.
◆ Hardware Protection Mode: WP# going low to protected the BP0~BP4 bits and SRP0~1 bits.
◆ Deep Power-Down Mode: In Deep Power-Down Mode, all commands are ignored except the Release from Deep
Power-Down Mode command.
Table 5.1. GD25Q128C Protected area size (WPS=0, CMP=0)
Status Register Content Memory Content

BP4 BP3 BP2 BP1 BP0 Blocks Addresses Density Portion

X X 0 0 0 NONE NONE NONE NONE
0 0 0 0 1 252 to 255 FC0000H-FFFFFFH 256KB Upper 1/64
0 0 0 1 0 248 to 255 F80000H-FFFFFFH 512KB Upper 1/32
0 0 0 1 1 240 to 255 F00000H-FFFFFFH 1MB Upper 1/16
0 0 1 0 0 224 to 255 E00000H-FFFFFFH 2MB Upper 1/8
0 0 1 0 1 192 to 255 C00000H-FFFFFFH 4MB Upper 1/4
0 0 1 1 0 128 to 255 800000H-FFFFFFH 8MB Upper 1/2
0 1 0 0 1 0 to 3 000000H-03FFFFH 256KB Lower 1/64
0 1 0 1 0 0 to 7 000000H-07FFFFH 512KB Lower 1/32
0 1 0 1 1 0 to 15 000000H-0FFFFFH 1MB Lower 1/16
0 1 1 0 0 0 to 31 000000H-1FFFFFH 2MB Lower 1/8
0 1 1 0 1 0 to 63 000000H-3FFFFFH 4MB Lower 1/4
0 1 1 1 0 0 to 127 000000H-7FFFFFH 8MB Lower 1/2
X X 1 1 1 0 to 255 000000H-FFFFFFH 16MB ALL
1 0 0 0 1 255 FFF000H-FFFFFFH 4KB Top Block
1 0 0 1 0 255 FFE000H-FFFFFFH 8KB Top Block
1 0 0 1 1 255 FFC000H-FFFFFFH 16KB Top Block
1 0 1 0 X 255 FF8000H-FFFFFFH 32KB Top Block
1 0 1 1 0 255 FF8000H-FFFFFFH 32KB Top Block
1 1 0 0 1 0 000000H-000FFFH 4KB Bottom Block
1 1 0 1 0 0 000000H-001FFFH 8KB Bottom Block
1 1 0 1 1 0 000000H-003FFFH 16KB Bottom Block
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Dual and Quad Serial Flash GD25Q128C
1 1 1 0 X 0 000000H-007FFFH 32KB Bottom Block
1 1 1 1 0 0 000000H-007FFFH 32KB Bottom Block

Table 5.2. GD25Q128C Protected area size (WPS=0, CMP=1)

Status Register Content Memory Content

BP4 BP3 BP2 BP1 BP0 Blocks Addresses Density Portion

X X 0 0 0 0 to 255 000000H-FFFFFFH ALL ALL
0 0 0 0 1 0 to 251 000000H-FBFFFFH 16128KB Lower 63/64
0 0 0 1 0 0 to 247 000000H-F7FFFFH 15872KB Lower 31/32
0 0 0 1 1 0 to 239 000000H-EFFFFFH 15MB Lower 15/16
0 0 1 0 0 0 to 223 000000H-DFFFFFH 14MB Lower 7/8
0 0 1 0 1 0 to 191 000000H-BFFFFFH 12MB Lower 3/4
0 0 1 1 0 0 to 127 000000H-7FFFFFH 8MB Lower 1/2
0 1 0 0 1 4 to 255 040000H-FFFFFFH 16128KB Upper 63/64
0 1 0 1 0 8 to 255 080000H-FFFFFFH 15872KB Upper 31/32
0 1 0 1 1 16 to 255 100000H-FFFFFFH 15MB Upper 15/16
0 1 1 0 0 32 to 255 200000H-FFFFFFH 14MB Upper 7/8
0 1 1 0 1 64 to 255 400000H-FFFFFFH 12MB Upper 3/4
0 1 1 1 0 128 to 255 800000H-FFFFFFH 8MB Upper 1/2
X X 1 1 1 NONE NONE NONE NONE
1 0 0 0 1 0 to 255 000000H-FFEFFFH 16380KB L-4095/4096
1 0 0 1 0 0 to 255 000000H-FFDFFFH 16376KB L-2047/2048
1 0 0 1 1 0 to 255 000000H-FFBFFFH 16368KB L-1023/1024
1 0 1 0 X 0 to 255 000000H-FF7FFFH 16352KB L-511/512
1 0 1 1 0 0 to 255 000000H-FF7FFFH 16352KB L-511/512
1 1 0 0 1 0 to 255 001000H-FFFFFFH 16380KB U-4095/4096
1 1 0 1 0 0 to 255 002000H-FFFFFFH 16376KB U-2047/2048
1 1 0 1 1 0 to 255 004000H-FFFFFFH 16368KB U-1023/1024
1 1 1 0 X 0 to 255 008000H-FFFFFFH 16352KB U-511/512
1 1 1 1 0 0 to 255 008000H-FFFFFFH 16352KB U-511/512

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Dual and Quad Serial Flash GD25Q128C
Table 5.3. GD25Q128C Individual Block Protection (WPS=1)
Block Sector Address range Individual Block Lock Operation

4095 FFF000H FFFFFFH

255 …… …… ……
4080 FF0000H FF0FFFH
254 FE0000H FEFFFFH 32 Sectors(Top/Bottom)/254 Blocks
…… …… …… …… Block Lock: 36H+Address
…… …… …… …… Block Unlock: 39H+Address
…… …… …… …… Read Block Lock: 3DH+Address
2 020000H 02FFFFH Global Block Lock: 7EH
1 010000H 01FFFFH Global Block Unlock: 98H

15 00F000H 00FFFFH
0 …… …… ……
0 000000H 000FFFH

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Dual and Quad Serial Flash GD25Q128C
6. STATUS REGISTER

S23 S22 S21 S20 S19 S18 S17 S16

HOLD/RST DRV1 DRV0 Reserved Reserved WPS Reserved Reserved

S15 S14 S13 S12 S11 S10 S9 S8

SUS1 CMP LB3 LB2 LB1 SUS2 QE SRP1

S7 S6 S5 S4 S3 S2 S1 S0
SRP0 BP4 BP3 BP2 BP1 BP0 WEL WIP
The status and control bits of the Status Register are as follows:
WIP bit.
The Write in Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register progress.
When WIP bit sets to 1, means the device is busy in program/erase/write status register progress, when WIP bit sets 0,
means the device is not in program/erase/write status register progress.
WEL bit.
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal
Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or
Erase command is accepted.
BP4, BP3, BP2, BP1, BP0 bits.
The Block Protect (BP4, BP3, BP2, BP1, and BP0) bits are non-volatile. They define the size of the area to be
software protected against Program and Erase commands. These bits are written with the Write Status Register (WRSR)
command. When the Block Protect (BP4, BP3, BP2, BP1, BP0) bits are set to 1, the relevant memory area (as defined in
Table1).becomes protected against Page Program (PP), Sector Erase (SE) and Block Erase (BE) commands. The Block
Protect (BP4, BP3, BP2, BP1, and BP0) bits can be written provided that the Hardware Protected mode has not been set.
The Chip Erase (CE) command is executed, only if the Block Protect (BP2, BP1, and BP0) bits are 0 and CMP=0.
SRP1, SRP0 bits.
The Status Register Protect (SRP1 and SRP0) bits are non-volatile Read/Write bits in the status register. The SRP
bits control the method of write protection: software protection, hardware protection, power supply lock-down or one time
programmable protection.
SRP1 SRP0 #WP Status Register Description
The Status Register can be written to after a Write Enable
0 0 X Software Protected
command, WEL=1.(Default)
WP#=0, the Status Register locked and can not be written to.
0 1 0 Hardware Protected

WP#=1, the Status Register is unlocked and can be written to

0 1 1 Hardware Unprotected
after a Write Enable command, WEL=1.
Status Register is protected and can not be written to again
1 0 X Power Supply Lock-Down(1)
until the next Power-Down, Power-Up cycle.
Status Register is permanently protected and can not be
1 1 X One Time Program(2)
written to.
NOTE:
1. When SRP1, SRP0= (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to (0, 0) state.
2. This feature is available on special order. Please contact GigaDevice for details.

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Dual and Quad Serial Flash GD25Q128C
QE bit.
The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad operation. When
the QE bit is set to 0 (Default) the WP# pin and HOLD# / RESET# pin are enable. When the QE pin is set to 1, the Quad
IO2 and IO3 pins are enabled. (The QE bit should never be set to 1 during standard SPI or Dual SPI operation if the WP#
or HOLD# / RESET# pins are tied directly to the power supply or ground)
LB3, LB2, LB1, bits.
The LB3, LB2, LB1, bits are non-volatile One Time Program (OTP) bits in Status Register (S13-S11) that provide the
write protect control and status to the Security Registers. The default state of LB3-LB1 are 0, the security registers are
unlocked. The LB3-LB1 bits can be set to 1 individually using the Write Register instruction. The LB3-LB1 bits are One
Time Programmable, once its set to 1, the Security Registers will become read-only permanently.
CMP bit
The CMP bit is a non-volatile Read/Write bit in the Status Register (S14). It is used in conjunction the BP4-BP0 bits to
provide more flexibility for the array protection. Please see the Status registers Memory Protection table for details. The
default setting is CMP=0.
SUS1, SUS2 bit
The SUS1 and SUS2 bit are read only bit in the status register (S15 and S10) that are set to 1 after executing an
Program/Erase Suspend (75H) command (The Erase Suspend will set the SUS1 to 1,and the Program Suspend will set
the SUS2 to 1). The SUS1 and SUS2 bit are cleared to 0 by Program/Erase Resume (7AH) command as well as a
power-down, power-up cycle.
WPS
The WPS Bit is used to select which Write Protect scheme should be used. When WPS=0, the device will use the
combination of CMP, BP (4:0) bits to protect a specific area of the memory array. When WPS=1, the device will utilize the
Individual Block Locks to protect any individual sector or blocks. The default value for all Individual Block Lock bits is 1
upon device power on or after reset.
DRV1/DRV0
The DRV1&DRV0 bits are used to determine the output driver strength for the Read operations.
DRV1,DRV0 Driver Strength
00 100%
01 75%
10 50% (default)
11 25%

HOLD/RST
The HOLD/RST bit is used to determine whether HOLD# or RESET# function should be implemented on the hardware
pin for 8-pin packages. When HOLD/RST=0, the pin acts as HOLD#, When the HOLD/RST=1, the pin acts as RESET#.
However, the HOLD# or RESET# function are only available when QE=0, If QE=1, The HOLD# and RESET# functions are
disabled, the pin acts as dedicated data I/O pin.

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Dual and Quad Serial Flash GD25Q128C
7. COMMANDS DESCRIPTION

All commands, addresses and data are shifted in and out of the device, beginning with the most significant bit on the
first rising edge of SCLK after CS# is driven low. Then, the one-byte command code must be shifted in to the device, most
significant bit first on SI, each bit being latched on the rising edges of SCLK.
See Table 7.1., every command sequence starts with a one-byte command code. Depending on the command, this
might be followed by address bytes, or by data bytes, or by both or none. CS# must be driven high after the last bit of the
command sequence has been shifted in. For the command of Read, Fast Read, Read Status Register or Release from
Deep Power-Down, and Read Device ID, the shifted-in command sequence is followed by a data-out sequence. CS# can
be driven high after any bit of the data-out sequence is being shifted out.
For the command of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write Enable,
Write Disable or Deep Power-Down command, CS# must be driven high exactly at a byte boundary, otherwise the
command is rejected, and is not executed. That is CS# must driven high when the number of clock pulses after CS# being
driven low is an exact multiple of eight. For Page Program, if at any time the input byte is not a full byte, nothing will happen
and WEL will not be reset.
Table 7.1. Commands (Standard/Dual/Quad SPI)
Command Name Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 n-Bytes
Write Enable 06H
Write Disable 04H
Volatile SR 50H
Write Enable
Read Status Register-1 05H (S7-S0) (continuous)
Read Status Register-2 35H (S15-S8) (continuous)
Read Status Register-3 15H (S23-S16)
Write Status Register-1 01H (S7-S0)
Write Status Register-2 31H (S15-S8)
Write Status Register-3 11H (S23-S16)
Read Data 03H A23-A16 A15-A8 A7-A0 (D7-D0) (Next byte) (continuous)
Fast Read 0BH A23-A16 A15-A8 A7-A0 dummy (D7-D0) (continuous)
Dual Output 3BH A23-A16 A15-A8 A7-A0 dummy (D7-D0)(1) (continuous)
Fast Read
Dual I/O BBH A23-A8(2) A7-A0 (D7-D0)(1) (continuous)
Fast Read M7-M0(2)
Quad Output 6BH A23-A16 A15-A8 A7-A0 dummy (D7-D0)(3) (continuous)
Fast Read
Quad I/O EBH A23-A0 dummy(5) (D7-D0)(3) (continuous)
Fast Read M7-M0(4)
Quad I/O Word E7H A23-A0 dummy(6) (D7-D0)(3) (continuous)
Fast Read(7) M7-M0(4)
Page Program 02H A23-A16 A15-A8 A7-A0 (D7-D0) Next byte
Quad Page Program 32H A23-A16 A15-A8 A7-A0 (D7-D0)(3)
Sector Erase 20H A23-A16 A15-A8 A7-A0
Block Erase(32K) 52H A23-A16 A15-A8 A7-A0
Block Erase(64K) D8H A23-A16 A15-A8 A7-A0
Chip Erase C7/60
H
Enable QPI 38H
Enable Reset 66H
Reset 99H
Set Burst with Wrap 77H dummy(10)
W7-W0
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 3.3V Uniform Sector
Dual and Quad Serial Flash GD25Q128C
Program/Erase 75H
Suspend
Program/Erase Resume 7AH
Release From Deep ABH dummy dummy dummy (DID7-DID (continuous)
Power-Down, And 0)
Read Device ID
Release From Deep ABH
Power-Down
Deep Power-Down B9H
Manufacturer/ 90H dummy dummy 00H (MID7-MI (DID7-DID (continuous)
Device ID D0) 0)
Manufacturer/ (MID7-MID
Device ID by Dual I/O A7-A0, 0)
92H A23-A8 (continuous)
M7-M0 (DID7-DID
0)
Manufacturer/ dummy (11)
Device ID by Quad I/O (MID7-MI
A23-A0,
94H D0) (continuous)
M7-M0
(DID7-DID
0)
Read Identification (MID7-MID (JDID15-J (JDID7-JD (continuous)
9FH
0) DID8) ID0)
Read Serial Flash 5AH A23-A16 A15-A8 A7-A0 dummy (D7-D0) (continuous)
Discoverable Parameter
Erase Security 44H A23-A16 A15-A8 A7-A0
Registers(8)
Program Security 42H A23-A16 A15-A8 A7-A0 (D7-D0) (D7-D0)
Registers(8)
Read Security 48H A23-A16 A15-A8 A7-A0 dummy (D7-D0)
Registers(8)
Individual Block Lock 36H A23-A16 A15-A8 A7-A0
Individual Block Unlock 39H A23-A16 A15-A8 A7-A0
Read Block Lock 3DH A23-A16 A15-A8 A7-A0
Global Block Lock 7EH
Global Block Unlock 98H

Table 7.2. Commands (QPI)

Command Name Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6
Clock Number (0,1) (2,3) (4,5) (6,7) (8,9) (10,11)
Write Enable 06H
Volatile SR Write Enable 50H
Write Disable 04H
Read Status Register-1 05H (S7-S0)
Read Status Register-2 35H (S15-S8)
Read Status Register-3 15H (S23-S16)
Write Status Register-1 01H (S7-S0)
Write Status Register-2 31H (S15-S8)
Write Status Register-3 11H (S23-S16)
Page Program 02H A23-A16 A15-A8 A7-A0 (D7-D0) Next byte
Sector Erase 20H A23-A16 A15-A8 A7-A0
Block Erase(32K) 52H A23-A16 A15-A8 A7-A0
Block Erase(64K) D8H A23-A16 A15-A8 A7-A0
Chip Erase C7/60H
Program/Erase Suspend 75H
Program/Erase Resume 7AH
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Deep Power-Down B9H
Set Read Parameters C0H P7-P0
Fast Read 0BH A23-A16 A15-A8 A7-A0 dummy (D7-D0)
Burst Read with Wrap 0CH A23-A16 A15-A8 A7-A0 dummy (D7-D0)
Quad I/O Fast Read EBH A23-A16 A15-A8 A7-A0 M7-M0 (D7-D0)
Release From Deep ABH dummy dummy dummy (DID7-DID0
Power-Down, And )
Read Device ID
Manufacturer/ 90H dummy dummy 00H (MID7-MID0 (DID7-DID0)
Device ID )
Read Identification (MID7-MID0 (JDID15-JDI (JDID7-JDID
9FH
) D8) 0)
Read Serial Flash 5AH A23-A16 A15-A8 A7-A0 dummy (D7-D0)
Discoverable Parameter
Disable QPI FFH
Enable Reset 66H
Reset 99H
Individual Block Lock 36H A23-A16 A15-A8 A7-A0
Individual Block Unlock 39H A23-A16 A15-A8 A7-A0
Read Block Lock 3DH A23-A16 A15-A8 A7-A0
Global Block Lock 7EH
Global Block Unlock 98H

NOTE:
1. Dual Output data
IO0 = (D6, D4, D2, D0)
IO1 = (D7, D5, D3, D1)
2. Dual Input Address
IO0 = A22, A20, A18, A16, A14, A12, A10, A8 A6, A4, A2, A0, M6, M4, M2, M0
IO1 = A23, A21, A19, A17, A15, A13, A11, A9 A7, A5, A3, A1, M7, M5, M3, M1
3. Quad Output Data
IO0 = (D4, D0, …..)
IO1 = (D5, D1, …..)
IO2 = (D6, D2, …..)
IO3 = (D7, D3,…..)
4. Quad Input Address
IO0 = A20, A16, A12, A8, A4, A0, M4, M0
IO1 = A21, A17, A13, A9, A5, A1, M5, M1
IO2 = A22, A18, A14, A10, A6, A2, M6, M2
IO3 = A23, A19, A15, A11, A7, A3, M7, M3
5. Fast Read Quad I/O Data
IO0 = (x, x, x, x, D4, D0,…)
IO1 = (x, x, x, x, D5, D1,…)
IO2 = (x, x, x, x, D6, D2,…)
IO3 = (x, x, x, x, D7, D3,…)
6. Fast Word Read Quad I/O Data
IO0 = (x, x, D4, D0,…)
IO1 = (x, x, D5, D1,…)
IO2 = (x, x, D6, D2,…)

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Dual and Quad Serial Flash GD25Q128C
IO3 = (x, x, D7, D3,…)
7. Fast Word Read Quad I/O Data: the lowest address bit must be 0.
8. Security Registers Address:
Security Register1: A23-A16=00H, A15-A9=0001000b, A8-A0=Byte Address;
Security Register2: A23-A16=00H, A15-A9=0010000b, A8-A0=Byte Address;
Security Register3: A23-A16=00H, A15-A9=0011000b, A8-A0=Byte Address.
9. QPI Command, Address, Data input/output format:
CLK #0 1 2 3 4 5 6 7 8 9 10 11
IO0= C4, C0, A20, A16, A12, A8, A4, A0, D4, D0, D4, D0,
IO1= C5, C1, A21, A17, A13, A9, A5, A1, D5, D1, D5, D1
IO2= C6, C2, A22, A18, A14, A10, A6, A2, D6, D2, D6, D2
IO3= C7, C3, A23, A19, A15, A11, A7, A3, D7, D3, D7, D3
10. Dummy bits and Wrap Bits
IO0 = (x, x, x, x, x, x, W4,x)
IO1 = (x, x, x, x, x, x, W5, x)
IO2 = (x, x, x, x, x, x, W6, x)
IO3 = (x, x, x, x, x, x, W7, x)
11. Address, Continuous Read Mode bits, Dummy bits, Manufacture ID and Device ID
IO0 = (A20, A16, A12, A8, A4, A0, M4, M0, x, x, x, x, MID4, MID0, DID4, DID0, …)
IO1 = (A21, A17, A13, A9, A5, A1, M5, M1, x, x, x, x, MID5, MID1, DID5, DID1, …)
IO2 = (A22, A18, A14, A10, A6, A2, M6, M2, x, x, x, x, MID6, MID2, DID6, DID2, …)
IO3 = (A23, A19, A15, A11, A7, A3, M7, M3, x, x, x, x, MID7, MID3, DID7, DID3, …)

Table 7.3. Table of ID Definitions for GD25Q128C

Operation Code MID7-MID0 ID15-ID8 ID7-ID0
9FH C8 40 18
90H/92H/94H C8 17
ABH 17

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7.1. Write Enable (WREN) (06H)
The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL)
bit must be set prior to every Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE), Write Status
Register (WRSR) and Erase/Program Security Registers command. The Write Enable (WREN) command sequence: CS#
goes low  sending the Write Enable command  CS# goes high.
Figure3. Write Enable Sequence Diagram

CS#

0 1 2 3 4 5 6 7
SCLK

Command
SI
06H
High-Z
SO

Figure3a. Write Enable Sequence Diagram (QPI)

CS#
0 1
SCLK
Command
06H
IO0

IO1

IO2

IO3

7.2. Write Disable (WRDI) (04H)

The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The Write Disable command sequence:
CS# goes low Sending the Write Disable command CS# goes high. The WEL bit is reset by following condition:
Power-up and upon completion of the Write Status Register, Page Program, Sector Erase, Block Erase, Chip Erase,
Erase/Program Security Registers and Reset commands.

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 3.3V Uniform Sector
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Figure4. Write Disable Sequence Diagram

CS#

0 1 2 3 4 5 6 7
SCLK

Command
SI
04H
High-Z
SO

Figure4a. Write Disable Sequence Diagram (QPI)

CS#
0 1
SCLK
Command
04H
IO0

IO1

IO2

IO3

7.3. Write Enable for Volatile Status Register (50H)

The non-volatile Status Register bits can also be written to as volatile bits. This gives more flexibility to change the
system configuration and memory protection schemes quickly without waiting for the typical non-volatile bit write cycles or
affecting the endurance of the Status Register non-volatile bits. The Write Enable for Volatile Status Register command
must be issued prior to a Write Status Register command. The Write Enable for Volatile Status Register command will not
set the Write Enable Latch bit, it is only valid for the Write Status Register command to change the volatile Status Register
bit values.
Figure5. Write Enable for Volatile Status Register Sequence Diagram

CS#

SCLK 0 1 2 3 4 5 6 7

Command(50H)

SI

SO High-Z

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 3.3V Uniform Sector
Dual and Quad Serial Flash GD25Q128C
Figure5a. Write Enable for Volatile Status Register Sequence Diagram (QPI)

CS#
0 1
SCLK
Command
50H
IO0

IO1

IO2

IO3

7.4. Read Status Register (RDSR) (05H or 35H or 15H)

The Read Status Register (RDSR) command is for reading the Status Register. The Status Register may be read at
any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in
progress, it is recommended to check the Write in Progress (WIP) bit before sending a new command to the device. It is
also possible to read the Status Register continuously. For command code “05H” / “35H” / “15H”, the SO will output Status
Register bits S7~S0 / S15-S8 / S16-S23.
Figure6. Read Status Register Sequence Diagram

CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCLK

Command
SI
05H or 35H or 15H
Register0/1/2 Register0/1/2
SO High-Z
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
MSB MSB

Figure6a. Read Status Register Sequence Diagram (QPI)

CS#
0 1 2 3 4 5
SCLK
Command
05H/35H/15H

IO0 4 0 4 0 4

IO1 5 1 5 1 5

IO2 6 2 6 2 6

IO3 7 3 7 3 7

Register0/1/2

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 3.3V Uniform Sector
Dual and Quad Serial Flash GD25Q128C
7.5. Write Status Register (WRSR) (01H or 31H or 11H)
The Write Status Register (WRSR) command allows new values to be written to the Status Register. Before it can be
accepted, a Write Enable (WREN) command must previously have been executed. After the Write Enable (WREN)
command has been decoded and executed, the device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) command has no effect on S20, S19, S17, S16, S15, S10, S1 and S0 of the
Status Register. CS# must be driven high after the eighth of the data byte has been latched in. If not, the Write Status
Register (WRSR) command is not executed. As soon as CS# is driven high, the self-timed Write Status Register cycle
(whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may still be read
to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status
Register cycle, and is 0 when it is completed. When the cycle is completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) command allows the user to change the values of the Block Protect (BP4, BP3,
BP2, BP1, and BP0) bits, to define the size of the area that is to be treated as read-only. The Write Status Register (WRSR)
command also allows the user to set or reset the Status Register Protect (SRP1 and SRP0) bits in accordance with the
Write Protect (WP#) signal. The Status Register Protect (SRP1 and SRP0) bits and Write Protect (WP#) signal allow the
device to be put in the Hardware Protected Mode. The Write Status Register (WRSR) command is not executed once the
Hardware Protected Mode is entered.

Figure7. Write Status Register Sequence Diagram

CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCLK

Command Status Register in

SI 01H/31H/11H 7 6 5 4 3 2 1 0
MSB High-Z
SO

Figure7a. Write Status Register Sequence Diagram (QPI)

CS#
0 1 2 3
SCLK
Command

01H/31H/11H
IO0 4 0

IO1 5 1

IO2 6 2

IO3 7 3

Status Register in

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 3.3V Uniform Sector
Dual and Quad Serial Flash GD25Q128C
7.6. Read Data Bytes (READ) (03H)
The Read Data Bytes (READ) command is followed by a 3-byte address (A23-A0), each bit being latched-in during
the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a
Max frequency fR, during the falling edge of SCLK. The first byte addressed can be at any location. The address is
automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can,
therefore, be read with a single Read Data Bytes (READ) command. Any Read Data Bytes (READ) command, while an
Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.
Figure8. Read Data Bytes Sequence Diagram

CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
SCLK

Command 24-bit address

SI
03H 23 22 21 3 2 1 0
MSB Data Out1 Data Out2
SO High-Z
7 6 5 4 3 2 1 0
MSB

7.7. Read Data Bytes at Higher Speed (Fast Read) (0BH)

The Read Data Bytes at Higher Speed (Fast Read) command is for quickly reading data out. It is followed by a 3-byte
address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK. Then the memory content,
at that address, is shifted out on SO, each bit being shifted out, at a Max frequency f C, during the falling edge of SCLK. The
first byte addressed can be at any location. The address is automatically incremented to the next higher address after each
byte of data is shifted out.

Figure9. Read Data Bytes at Higher Speed Sequence Diagram

CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
SCLK

Command 24-bit address

SI
0BH 23 22 21 3 2 1 0

SO High-Z

CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Byte
SI 7 6 5 4 3 2 1 0
Data Out1 Data Out2
SO 7 6 5 4 3 2 1 0 7 6 5
MSB MSB

23
 3.3V Uniform Sector
Dual and Quad Serial Flash GD25Q128C
Fast Read (0BH) in QPI mode
The Fast Read command is also supported in QPI mode. In QPI mode, the number of dummy clocks is configured by
the “Set Read Parameters (C0H)” command to accommodate a wide range application with different needs for either
maximum Fast Read frequency or minimum data access latency. Depending on the Read Parameter Bits P[5:4] setting,
the number of dummy clocks can be configured as either 4/6/8/8.
Figure9a. Read Data Bytes at Higher Speed Sequence Diagram (QPI)

CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13
SCLK
Command IOs switch from
0BH Dummy* Input to output
A23-16 A15-8 A7-0
IO0 20 16 12 8 4 0 4 0 4 0 4 0 4

IO1 21 17 13 9 5 1 5 1 5 1 5 1 5

IO2 22 18 14 10 6 2 6 2 6 2 6 2 6

IO3 23 19 15 11 7 3 7 3 7 3 7 3 7
Byte1 Byte2

*"Set Read Parameters" Command (C0H)

can set the number of dummy clocks

7.8. Dual Output Fast Read (3BH)

The Dual Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, each bit being
latched in during the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO.
The command sequence is shown in followed Figure 10. The first byte addressed can be at any location. The address is
automatically incremented to the next higher address after each byte of data is shifted out.
Figure10. Dual Output Fast Read Sequence Diagram
CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
SCLK

Command 24-bit address

SI
3BH 23 22 21 3 2 1 0

SO High-Z

CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Clocks
SI 6 4 2 0 6 4 2 0 6
Data Out1 Data Out2
SO 7 5 3 1 7 5 3 1 7
MSB MSB

24
 3.3V Uniform Sector
Dual and Quad Serial Flash GD25Q128C
7.9. Quad Output Fast Read (6BH)
The Quad Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, each bit being
latched in during the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO3, IO2, IO1
and IO0. The command sequence is shown in followed Figure11. The first byte addressed can be at any location. The
address is automatically incremented to the next higher address after each byte of data is shifted out.

Figure11. Quad Output Fast Read Sequence Diagram

CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
SCLK

Command 24-bit address

SI(IO0) 6BH 23 22 21 3 2 1 0
SO(IO1) High-Z
WP#(IO2) High-Z
HOLD#(IO3) High-Z

CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Clocks
SI(IO0) 4 0 4 0 4 0 4 0 4

SO(IO1) 5 1 5 1 5 1 5 1 5

WP#(IO2) 6 2 6 2 6 2 6 2 6

HOLD#(IO3) 7 3 7 3 7 3 7 3 7
Byte1 Byte2 Byte3 Byte4

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 3.3V Uniform Sector
Dual and Quad Serial Flash GD25Q128C
7.10. Dual I/O Fast Read (BBH)
The Dual I/O Fast Read command is similar to the Dual Output Fast Read command but with the capability to input the
3-byte address (A23-0) and a “Continuous Read Mode” byte 2-bit per clock by SI and SO, each bit being latched in during
the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO. The command
sequence is shown in followed Figure12. The first byte addressed can be at any location. The address is automatically
incremented to the next higher address after each byte of data is shifted out.
Dual I/O Fast Read with “Continuous Read Mode”
The Dual I/O Fast Read command can further reduce command overhead through setting the “Continuous Read Mode”
bits (M7-4) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M5-4) = (1, 0), then the next Dual
I/O Fast Read command (after CS# is raised and then lowered) does not require the BBH command code. The command
sequence is shown in followed Figure12a. If the “Continuous Read Mode” bits (M5-4) do not equal (1, 0), the next
command requires the first BBH command code, thus returning to normal operation. A “Continuous Read Mode” Reset
command can be used to reset (M5-4) before issuing normal command.
Figure12. Dual I/O Fast Read Sequence Diagram (M5-4≠ (1, 0))

CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK

Command
SI(IO0) BBH 6 4 2 0 6 4 2 0 6 4 2 0 6 4

SO(IO1) 7 5 3 1 7 5 3 1 7 5 3 1 7 5
A23-16 A15-8 A7-0 M7-4 Dummy
CS#
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCLK

SI(IO0) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6

SO(IO1) 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7
Byte1 Byte2 Byte3 Byte4

26
3.3V Uniform Sector
Dual and Quad Serial Flash GD25Q128C
Figure12a. Dual I/O Fast Read Sequence Diagram (M5-4= (1, 0))

CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCLK

6 4 2 0 6 4 2 0 6 4 2 0 6 4

7 5 3 1 7 5 3 1 7 5 3 1 7 5
A23-16 A15-8 A7-0 M7-4 Dummy
CS#
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCLK

SI(IO0) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6

SO(IO1) 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7
Byte1 Byte2 Byte3 Byte4

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 3.3V Uniform Sector
Dual and Quad Serial Flash GD25Q128C
7.11. Quad I/O Fast Read (EBH)
The Quad I/O Fast Read command is similar to the Dual I/O Fast Read command but with the capability to input the 3-byte
address (A23-0) and a “Continuous Read Mode” byte and 4-dummy clock 4-bit per clock by IO0, IO1, IO2, IO3, each bit
being latched in during the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO0,
IO1, IO2, IO3. The command sequence is shown in followed Figure13. The first byte addressed can be at any location. The
address is automatically incremented to the next higher address after each byte of data is shifted out. The Quad Enable bit
(QE) of Status Register (S9) must be set to enable for the Quad I/O Fast read command.
Quad I/O Fast Read with “Continuous Read Mode”
The Quad I/O Fast Read command can further reduce command overhead through setting the “Continuous Read Mode”
bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M5-4) = (1, 0), then the next Quad
I/O Fast Read command (after CS# is raised and then lowered) does not require the EBH command code. The command
sequence is shown in followed Figure13a. If the “Continuous Read Mode” bits (M5-4) do not equal to (1, 0), the next
command requires the first EBH command code, thus returning to normal operation. A “Continuous Read Mode” Reset
command can be used to reset (M5-4) before issuing normal command.
Figure13. Quad I/O Fast Read Sequence Diagram (M5-4≠ (1, 0))

CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK

Command
SI(IO0) EBH 4 0 4 0 4 0 4 0 4 0 4 0 4

SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5

WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6

HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7
A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2

Figure13a. Quad I/O Fast Read Sequence Diagram (M5-4= (1, 0))

CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCLK

SI(IO0) 4 0 4 0 4 0 4 0 4 0 4 0 4

SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5

WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6

HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7
A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2

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 3.3V Uniform Sector
Dual and Quad Serial Flash GD25Q128C
Quad I/O Fast Read with “8/16/32/64-Byte Wrap Around” in Standard SPI mode
The Quad I/O Fast Read command can be used to access a specific portion within a page by issuing “Set Burst with Wrap”
(77H) commands prior to EBH. The “Set Burst with Wrap” (77H) command can either enable or disable the “Wrap Around”
feature for the following EBH commands. When “Wrap Around” is enabled, the data being accessed can be limited to either
an 8/16/32/64-byte section of a 256-byte page. The output data starts at the initial address specified in the command, once
it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around the beginning boundary
automatically until CS# is pulled high to terminate the command.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache
afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands. The “Set Burst with
Wrap” command allows three “Wrap Bits” W6-W4 to be set. The W4 bit is used to enable or disable the “Wrap Around”
operation while W6-W5 is used to specify the length of the wrap around section within a page.

Quad I/O Fast Read (EBH) in QPI mode

The Quad I/O Fast Read command is also supported in QPI mode. See Figure13b. In QPI mode, the number of dummy
clocks is configured by the “Set Read Parameters (C0H)” command to accommodate a wide range application with
different needs for either maximum Fast Read frequency or minimum data access latency. Depending on the Read
Parameter Bits P[5:4] setting, the number of dummy clocks can be configured as either 4/6/8/8. In QPI mode, the
“Continuous Read Mode” bits M7-M0 are also considered as dummy clocks. “Continuous Read Mode” feature is also
available in QPI mode for Quad I/O Fast Read command. “Wrap Around” feature is not available in QPI mode for Quad I/O
Fast Read command. To perform a read operation with fixed data length wrap around in QPI mode, a dedicated “Burst
Read with Wrap” (0CH) command must be used.
Figure13b. Quad I/O Fast Read Sequence Diagram (M5-4= (1, 0) QPI)

CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
SCLK
Command IOs switch from
EBH Input to output
IO0 20 16 12 8 4 0 4 4 0 4 0 4

IO1 21 17 13 9 5 1 5 5 1 5 1 5

IO2 22 18 14 10 6 2 6 6 2 6 2 6
*"Set Read Parameters"
IO3 23 19 15 11 7 3 7 7 3 7 3 7 Command (C0H) can
set the number of
A23-16 A15-8 Dummy
A7-0 M7-4* Byte1 Byte2 Byte3 dummy clocks

29
 3.3V Uniform Sector
Dual and Quad Serial Flash GD25Q128C
7.12. Quad I/O Word Fast Read (E7H)
The Quad I/O Word Fast Read command is similar to the Quad I/O Fast Read command except that the lowest address bit
(A0) must equal 0 and only 2-dummy clock. The command sequence is shown in followed Figure14. The first byte
addressed can be at any location. The address is automatically incremented to the next higher address after each byte of
data is shifted out. The Quad Enable bit (QE) of Status Register (S9) must be set to enable for the Quad I/O Word Fast
read command.
Quad I/O Word Fast Read with “Continuous Read Mode”
The Quad I/O Word Fast Read command can further reduce command overhead through setting the “Continuous Read
Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M5-4) = (1, 0), then the next
Quad I/O Word Fast Read command (after CS# is raised and then lowered) does not require the E7H command code. The
command sequence is shown in followed Figure14. If the “Continuous Read Mode” bits (M5-4) do not equal to (1, 0), the
next command requires the first E7H command code, thus returning to normal operation. A “Continuous Read Mode” Reset
command can be used to reset (M5-4) before issuing normal command.

Figure14. Quad I/O Word Fast Read Sequence Diagram (M5-4≠ (1, 0))

CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK

Command
SI(IO0) E7H 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4

SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5

WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6

HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7
A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2 Byte3

Figure14a. Quad I/O Word Fast Read Sequence Diagram (M5-4= (1, 0))

CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCLK

SI(IO0) 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4

SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5

WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6

HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7
A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2 Byte3

30
 3.3V Uniform Sector
Dual and Quad Serial Flash GD25Q128C
Quad I/O Word Fast Read with “8/16/32/64-Byte Wrap Around” in Standard SPI mode
The Quad I/O Word Fast Read command can be used to access a specific portion within a page by issuing “Set Burst with
Wrap” (77H) commands prior to E7H. The “Set Burst with Wrap” (77H) command can either enable or disable the “Wrap
Around” feature for the following E7H commands. When “Wrap Around” is enabled, the data being accessed can be limited
to either an 8/16/32/64-byte section of a 256-byte page. The output data starts at the initial address specified in the
command, once it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around the beginning
boundary automatically until CS# is pulled high to terminate the command.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache
afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands. The “Set Burst with
Wrap” command allows three “Wrap Bits” W6-W4 to be set. The W4 bit is used to enable or disable the “Wrap Around”
operation while W6-W5 is used to specify the length of the wrap around section within a page.

7.13. Set Burst with Wrap (77H)

The Set Burst with Wrap command is used in conjunction with “Quad I/O Fast Read” and “Quad I/O Word Fast Read”
command to access a fixed length of 8/16/32/64-byte section within a 256-byte page, in standard SPI mode.
The Set Burst with Wrap command sequence: CS# goes low  Send Set Burst with Wrap command  Send 24 dummy
bits  Send 8 bits “Wrap bits”  CS# goes high.
W4=0 W4=1 (default)
W6,W5
Wrap Around Wrap Length Wrap Around Wrap Length
0, 0 Yes 8-byte No N/A
0, 1 Yes 16-byte No N/A
1, 0 Yes 32-byte No N/A
1, 1 Yes 64-byte No N/A
If the W6-W4 bits are set by the Set Burst with Wrap command, all the following “Quad I/O Fast Read” and “Quad I/O Word
Fast Read” command will use the W6-W4 setting to access the 8/16/32/64-byte section within any page. To exit the “Wrap
Around” function and return to normal read operation, another Set Burst with Wrap command should be issued to set W4=1.
In QPI mode, the “Burst Read with Wrap (0CH)” command should be used to perform the Read Operation with “Wrap
Around” feature. The Wrap Length set by W5-W6 in Standard SPI mode is still valid in QPI mode and can also be
re-configured by “Set Read Parameters (C0H) command.
Figure15. Set Burst with Wrap Sequence Diagram

CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCLK

Command
SI(IO0) 77H x x x x x x 4 x

SO(IO1) x x x x x x 5 x

WP#(IO2) x x x x x x 6 x

HOLD#(IO3) x x x x x x x x
W6-W4

31
 3.3V Uniform Sector
Dual and Quad Serial Flash GD25Q128C
7.14. Page Program (PP) (02H)
The Page Program (PP) command is for programming the memory. A Write Enable (WREN) command must previously
have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program command.
The Page Program (PP) command is entered by driving CS# Low, followed by the command code, three address bytes
and at least one data byte on SI. If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes
beyond the end of the current page are programmed from the start address of the same page (from the address whose 8
least significant bits (A7-A0) are all zero). CS# must be driven low for the entire duration of the sequence. The Page
Program command sequence: CS# goes low  sending Page Program command  3-byte address on SI  at least 1
byte data on SI  CS# goes high. The command sequence is shown in Figure16. If more than 256 bytes are sent to the
device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly
within the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the requested
addresses without having any effects on the other bytes of the same page. CS# must be driven high after the eighth bit of
the last data byte has been latched in; otherwise the Page Program (PP) command is not executed.
As soon as CS# is driven high, the self-timed Page Program cycle (whose duration is t PP) is initiated. While the Page
Program cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The
Write in Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some
unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Page Program (PP) command applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0)
is not executed.
Figure16. Page Program Sequence Diagram

CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
SCLK

Command 24-bit address Data Byte 1

SI
02H 23 22 21 3 2 1 0 7 6 5 4 3 2 1 0
MSB MSB
CS#
2073

2075
2076

2078
2072

2074

2077

2079

40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCLK

Data Byte 2 Data Byte 3 Data Byte 256

SI 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
MSB MSB MSB

32
 3.3V Uniform Sector
Dual and Quad Serial Flash GD25Q128C
Figure16a. Page Program Sequence Diagram (QPI)

CS#

516
517
518
519
0 1 2 3 4 5 6 7 8 9 10 11 12 13
SCLK
Command
02H A23-16 A15-8 A7-0 Byte1 Byte2 Byte3 Byte255 Byte256
IO0 20 16 12 8 4 0 4 0 4 0 4 0 4 0 4 0

IO1 21 17 13 9 5 1 5 1 5 1 5 1 5 1 5 1

IO2 22 18 14 10 6 2 6 2 6 2 6 2 6 2 6 2

IO3 23 19 15 11 7 3 7 3 7 3 7 3 7 3 7 3

33
 3.3V Uniform Sector
Dual and Quad Serial Flash GD25Q128C
7.15. Quad Page Program (32H)
The Quad Page Program command is for programming the memory using four pins: IO0, IO1, IO2, and IO3. To use Quad
Page Program the Quad enable in status register Bit9 must be set (QE=1). A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program command. The
quad Page Program command is entered by driving CS# Low, followed by the command code (32H), three address bytes
and at least one data byte on IO pins.
The command sequence is shown in Figure17. If more than 256 bytes are sent to the device, previously latched data are
discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256
data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the
other bytes of the same page. CS# must be driven high after the eighth bit of the last data byte has been latched in;
otherwise the Quad Page Program (PP) command is not executed.
As soon as CS# is driven high, the self-timed Quad Page Program cycle (whose duration is tPP) is initiated. While the Quad
Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit.
The Write in Progress (WIP) bit is 1 during the self-timed Quad Page Program cycle, and is 0 when it is completed. At some
unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Quad Page Program command applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0)
is not executed.

Figure17.Quad Page Program Sequence Diagram

CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
SCLK

Command 24-bit address Byte1 Byte2

SI(IO0) 32H 23 22 21 3 2 1 0 4 0 4 0 4 0 4 0
MSB
SO(IO1) 5 1 5 1 5 1 5 1

WP#(IO2) 6 2 6 2 6 2 6 2

HOLD#(IO3) 7 3 7 3 7 3 7 3

CS#
537

539
540

542
536

538

541

543

40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCLK

Byte11Byte12 Byte253 Byte256

SI(IO0) 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0

SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1

WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2

HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3

34
 3.3V Uniform Sector
Dual and Quad Serial Flash GD25Q128C
7.16. Sector Erase (SE) (20H)
The Sector Erase (SE) command is erased the all data of the chosen sector. A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit. The Sector Erase (SE) command is entered by
driving CS# low, followed by the command code, and 3-address byte on SI. Any address inside the sector is a valid
address for the Sector Erase (SE) command. CS# must be driven low for the entire duration of the sequence.
The Sector Erase command sequence: CS# goes low  sending Sector Erase command  3-byte address on SI  CS#
goes high. The command sequence is shown in Figure18. CS# must be driven high after the eighth bit of the last address
byte has been latched in; otherwise the Sector Erase (SE) command is not executed. As soon as CS# is driven high, the
self-timed Sector Erase cycle (whose duration is t SE) is initiated. While the Sector Erase cycle is in progress, the Status
Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the
self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the
Write Enable Latch (WEL) bit is reset. A Sector Erase (SE) command applied to a sector which is protected by the Block
Protect (BP4, BP3, BP2, BP1, and BP0) bit is not executed.
Figure18. Sector Erase Sequence Diagram

CS#
0 1 2 3 4 5 6 7 8 9 29 30 31
SCLK

Command 24 Bits Address

SI
20H 23 22 2 1 0
MSB

Figure18a. Sector Erase Sequence Diagram (QPI)

CS#
0 1 2 3 4 5 6 7
SCLK
Command
20H A23-16 A12-8 A7-0
IO0 20 16 12 8 4 0

IO1 21 17 13 9 5 1

IO2 22 18 14 10 6 2

IO3 23 19 15 11 7 3

35
 3.3V Uniform Sector
Dual and Quad Serial Flash GD25Q128C
7.17. 32KB Block Erase (BE) (52H)
The 32KB Block Erase (BE) command is erased the all data of the chosen block. A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit. The 32KB Block Erase (BE) command is entered
by driving CS# low, followed by the command code, and three address bytes on SI. Any address inside the block is a valid
address for the 32KB Block Erase (BE) command. CS# must be driven low for the entire duration of the sequence.
The 32KB Block Erase command sequence: CS# goes low  sending 32KB Block Erase command  3-byte address on
SI  CS# goes high. The command sequence is shown in Figure19. CS# must be driven high after the eighth bit of the last
address byte has been latched in; otherwise the 32KB Block Erase (BE) command is not executed. As soon as CS# is
driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in progress,
the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1
during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset. A 32KB Block Erase (BE) command applied to a block which is
protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0) bits is not executed.
Figure19. 32KB Block Erase Sequence Diagram

CS#
0 1 2 3 4 5 6 7 8 9 29 30 31
SCLK

Command 24 Bits Address

SI
52H 23 22 2 1 0
MSB

Figure19a. 32KB Block Erase Sequence Diagram (QPI)

CS#
0 1 2 3 4 5 6 7
SCLK
Command
52H A23-16 A12-8 A7-0
IO0 20 16 12 8 4 0

IO1 21 17 13 9 5 1

IO2 22 18 14 10 6 2

IO3 23 19 15 11 7 3

36
 3.3V Uniform Sector
Dual and Quad Serial Flash GD25Q128C
7.18. 64KB Block Erase (BE) (D8H)
The 64KB Block Erase (BE) command is erased the all data of the chosen block. A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit. The 64KB Block Erase (BE) command is entered
by driving CS# low, followed by the command code, and three address bytes on SI. Any address inside the block is a valid
address for the 64KB Block Erase (BE) command. CS# must be driven low for the entire duration of the sequence.
The 64KB Block Erase command sequence: CS# goes low  sending 64KB Block Erase command  3-byte address on
SI  CS# goes high. The command sequence is shown in Figure20. CS# must be driven high after the eighth bit of the last
address byte has been latched in; otherwise the 64KB Block Erase (BE) command is not executed. As soon as CS# is
driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in progress,
the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1
during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset. A 64KB Block Erase (BE) command applied to a block which is
protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0) bits is not executed.
Figure20. 64KB Block Erase Sequence Diagram

CS#
0 1 2 3 4 5 6 7 8 9 29 30 31
SCLK

Command 24 Bits Address

SI
D8H 23 22 2 1 0
MSB

Figure20a. 64KB Block Erase Sequence Diagram (QPI)

CS#

0 1 2 3 4 5 6 7
SCLK

Command
D8H A23-16 A15-8 A7-0
IO0 20 16 12 8 4 0

IO1 21 17 13 9 5 1

IO2 22 18 14 10 6 2

IO3 23 19 15 11 7 3

37
 3.3V Uniform Sector
Dual and Quad Serial Flash GD25Q128C
7.19. Chip Erase (CE) (60/C7H)
The Chip Erase (CE) command is erased the all data of the chip. A Write Enable (WREN) command must previously have
been executed to set the Write Enable Latch (WEL) bit .The Chip Erase (CE) command is entered by driving CS# Low,
followed by the command code on Serial Data Input (SI). CS# must be driven Low for the entire duration of the sequence.
The Chip Erase command sequence: CS# goes low  sending Chip Erase command  CS# goes high. The command
sequence is shown in Figure21. CS# must be driven high after the eighth bit of the command code has been latched in;
otherwise the Chip Erase command is not executed. As soon as CS# is driven high, the self-timed Chip Erase cycle
(whose duration is tCE) is initiated. While the Chip Erase cycle is in progress, the Status Register may be read to check the
value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Chip Erase cycle, and is
0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
The Chip Erase (CE) command is executed only if all Block Protect (BP2, BP1, and BP0) bits are 0. The Chip Erase (CE)
command is ignored if one or more sectors are protected.
Figure21. Chip Erase Sequence Diagram

CS#

0 1 2 3 4 5 6 7
SCLK

Command
SI
60H or C7H

Figure21a. Chip Erase Sequence Diagram (QPI)

CS#
0 1
SCLK
Command
C7H/60H
IO0

IO1

IO2

IO3

38
 3.3V Uniform Sector
Dual and Quad Serial Flash GD25Q128C
7.20. Deep Power-Down (DP) (B9H)
Executing the Deep Power-Down (DP) command is the only way to put the device in the lowest consumption mode (the
Deep Power-Down Mode). It can also be used as an extra software protection mechanism, while the device is not in active
use, since in this mode, the device ignores all Write, Program and Erase commands. Driving CS# high deselects the device,
and puts the device in the Standby Mode (if there is no internal cycle currently in progress). But this mode is not the Deep
Power-Down Mode. The Deep Power-Down Mode can only be entered by executing the Deep Power-Down (DP)
command. Once the device has entered the Deep Power-Down Mode, all commands are ignored except the Release from
Deep Power-Down and Read Device ID (RDI) command. This releases the device from this mode. The Release from Deep
Power-Down and Read Device ID (RDI) command also allows the Device ID of the device to be output on SO.
The Deep Power-Down Mode automatically stops at Power-Down, and the device always Power-Up in the Standby Mode.
The Deep Power-Down (DP) command is entered by driving CS# low, followed by the command code on SI. CS# must be
driven low for the entire duration of the sequence.
The Deep Power-Down command sequence: CS# goes low  sending Deep Power-Down command  CS# goes high.
The command sequence is shown in Figure22. CS# must be driven high after the eighth bit of the command code has been
latched in; otherwise the Deep Power-Down (DP) command is not executed. As soon as CS# is driven high, it requires a
delay of tDP before the supply current is reduced to ICC2 and the Deep Power-Down Mode is entered. Any Deep
Power-Down (DP) command, while an Erase, Program or Write cycle is in progress, is rejected without having any effects
on the cycle that is in progress.
Figure22. Deep Power-Down Sequence Diagram

CS#

0 1 2 3 4 5 6 7 tDP
SCLK

Command Stand-by mode Deep Power-down mode

SI
B9H

Figure22a. Deep Power-Down Sequence Diagram (QPI)

CS#
tDP
0 1
SCLK

Command
B9H
IO0

IO1

IO2

IO3

Stand-by mode Deep Power-down mode

39
 3.3V Uniform Sector
Dual and Quad Serial Flash GD25Q128C
7.21. Release from Deep Power-Down and Read Device ID (RDI) (ABH)
The Release from Power-Down and Read Device ID command is a multi-purpose command. It can be used to release the
device from the Power-Down state or obtain the devices electronic identification (ID) number.
To release the device from the Power-Down state, the command is issued by driving the CS# pin low, shifting the
instruction code “ABH” and driving CS# high as shown in Figure23. Release from Power-Down will take the time duration
of tRES1 (See AC Characteristics) before the device will resume normal operation and other command are accepted. The
CS# pin must remain high during the tRES1 time duration.
When used only to obtain the Device ID while not in the Power-Down state, the command is initiated by driving the CS#
pin low and shifting the instruction code “ABH” followed by 3-dummy byte. The Device ID bits are then shifted out on the
falling edge of SCLK with most significant bit (MSB) first as shown in Figure24. The Device ID value for the GD25Q128C
is listed in Manufacturer and Device Identification table. The Device ID can be read continuously. The command is
completed by driving CS# high.
When used to release the device from the Power-Down state and obtain the Device ID, the command is the same as
previously described, and shown in Figure24, except that after CS# is driven high it must remain high for a time duration
of tRES2 (See AC Characteristics). After this time duration the device will resume normal operation and other command will
be accepted. If the Release from Power-Down / Device ID command is issued while an Erase, Program or Write cycle is
in process (when WIP equal 1) the command is ignored and will not have any effects on the current cycle.
Figure23. Release Power-Down Sequence Diagram
CS#

0 1 2 3 4 5 6 7 t RES1
SCLK

Command
SI
ABH

Deep Power-down mode Stand-by mode

Figure23a. Release Power-Down Sequence Diagram (QPI)

CS#
tRES1
0 1
SCLK

Command
ABH
IO0

IO1

IO2

IO3

Deep Power-down mode Stand-by mode

40
 3.3V Uniform Sector
Dual and Quad Serial Flash GD25Q128C
Figure24. Release Power-Down/Read Device ID Sequence Diagram

CS#
0 1 2 3 4 5 6 7 8 9 29 30 31 32 33 34 35 36 37 38
SCLK

Command 3 Dummy Bytes t RES2

SI ABH 23 22 2 1 0
MSB Device ID
SO High-Z
7 6 5 4 3 2 1 0
MSB
Deep Power-down Mode Stand-by Mode

Figure24a. Release Power-Down/Read Device ID Sequence Diagram (QPI)

CS#
tRES2
0 1 2 3 4 5 6 7 8
SCLK

Command IOs switch from

3 Dummy Bytes
ABH Input to Output
IO0 4 0

IO1 5 1

IO2 6 2

IO3 7 3
Device
ID
Deep Power-down mode Stand-by mode

41
 3.3V Uniform Sector
Dual and Quad Serial Flash GD25Q128C
7.22. Read Manufacture ID/ Device ID (REMS) (90H)
The Read Manufacturer/Device ID command is an alternative to the Release from Power-Down / Device ID command that
provides both the JEDEC assigned Manufacturer ID and the specific Device ID.
The command is initiated by driving the CS# pin low and shifting the command code “90H” followed by a 24-bit address
(A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on the falling edge of SCLK with
most significant bit (MSB) first as shown in Figure25. If the 24-bit address is initially set to 000001H, the Device ID will be
read first.
Figure25. Read Manufacture ID/ Device ID Sequence Diagram

CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
SCLK

Command 24-bit address

SI
90H 23 22 21 3 2 1 0
SO High-Z

CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK

SI

Manufacturer ID Device ID
SO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
MSB MSB

Figure25a. Read Manufacture ID/ Device ID Sequence Diagram (QPI)

CS#

0 1 2 3 4 5 6 7 8 9 10
SCLK

Command IOs switch from

A7-0
90H A23-16 A15-8 (00H) Input to Output
IO0 20 16 12 8 4 0 4 0 4 0

IO1 21 17 13 9 5 1 5 1 5 1

IO2 22 18 14 10 6 2 6 2 6 2

IO3 23 19 15 11 7 3 7 3 7 3
MID Device
ID

42
 3.3V Uniform Sector
Dual and Quad Serial Flash GD25Q128C
7.23. Read Manufacture ID/ Device ID Dual I/O (92H)
The Read Manufacturer/Device ID Dual I/O command is an alternative to the Release from Power-Down / Device ID
command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID by dual I/O.
The command is initiated by driving the CS# pin low and shifting the command code “92H” followed by a 24-bit address
(A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on the falling edge of SCLK with
most significant bit (MSB) first as shown in Figure26. If the 24-bit address is initially set to 000001H, the Device ID will be
read first.
Figure26. Read Manufacture ID/ Device ID Dual I/O Sequence Diagram

CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK

Command
SI(IO0) 92H 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0

SO(IO1) 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1
A23-16 A15-8 A7-0 M7-0
CS#
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK

SI(IO0) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0

SO(IO1) 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1
MFR ID Device ID MFR ID Device ID MFR ID Device ID
(Repeat) (Repeat) (Repeat) (Repeat)

43
 3.3V Uniform Sector
Dual and Quad Serial Flash GD25Q128C
7.24. Read Manufacture ID/ Device ID Quad I/O (94H)
The Read Manufacturer/Device ID Quad I/O command is an alternative to the Release from Power-Down / Device ID
command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID by quad I/O.
The command is initiated by driving the CS# pin low and shifting the command code “94H” followed by a 24-bit address
(A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on the falling edge of SCLK with
most significant bit (MSB) first as shown in Figure27. If the 24-bit address is initially set to 000001H, the Device ID will be
read first.
Figure27. Read Manufacture ID/ Device ID Quad I/O Sequence Diagram

CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK

Command
SI(IO0) 94H 4 0 4 0 4 0 4 0 4 0 4 0

SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1

WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2

HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3
A23-16 A15-8 A7-0 M7-0 Dummy MFR ID DID

CS#
24 25 26 27 28 29 30 31
SCLK

SI(IO0) 4 0 4 0 4 0 4 0

SO(IO1) 5 1 5 1 5 1 5 1

WP#(IO2) 6 2 6 2 6 2 6 2

HOLD#(IO3) 7 3 7 3 7 3 7 3
MFR ID DID MFR ID DID
(Repeat)(Repeat)(Repeat)(Repeat)

44
 3.3V Uniform Sector
Dual and Quad Serial Flash GD25Q128C
7.25. Read Identification (RDID) (9FH)
The Read Identification (RDID) command allows the 8-bit manufacturer identification to be read, followed by two bytes of
device identification. The device identification indicates the memory type in the first byte, and the memory capacity of the
device in the second byte. The Read Identification (RDID) command while an Erase or Program cycle is in progress is not
decoded, and has no effect on the cycle that is in progress. The Read Identification (RDID) command should not be issued
while the device is in Deep Power-Down Mode.
The device is first selected by driving CS# to low. Then, the 8-bit command code for the command is shifted in. This is
followed by the 24-bit device identification, stored in the memory, being shifted out on Serial Data Output, each bit being
shifted out during the falling edge of Serial Clock. The command sequence is shown in Figure28. The Read Identification
(RDID) command is terminated by driving CS# to high at any time during data output. When CS# is driven high, the device
is put in the Standby Mode. Once in the Standby Mode, the device waits to be selected, so that it can receive, decode and
execute commands.
Figure28. Read Identification ID Sequence Diagram

CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCLK

SI 9FH
Command Manufacturer ID
SO 7 6 5 4 3 2 1 0
MSB
CS#
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCLK

SI

SO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Memory Type Capacity
MSB JDID15-JDID8 MSB JDID7-JDID0

45
3.3V Uniform Sector
Dual and Quad Serial Flash GD25Q128C
Figure28a. Read Identification ID Sequence Diagram (QPI)

CS#
0 1 2 3 4 5 6
SCLK
Command IOs switch from
9FH Input to Output

IO0 4 0 12 8 4 0

IO1 5 1 13 9 5 1

IO2 6 2 14 10 6 2

IO3 7 3 15 11 7 3

MID JDID15 JDID7-

-JDID8 JDID0

46
 3.3V Uniform Sector
Dual and Quad Serial Flash GD25Q128C
7.26. Program/Erase Suspend (PES) (75H)
The Program/Erase Suspend command “75H”, allows the system to interrupt a page program or sector/block erase
operation and then read data from any other sector or block. The Write Status Register command (01H/31H/11H) and
Erase/Program Security Registers command (44H, 42H) and Erase commands (20H, 52H, D8H, C7H, 60H) and Page
Program command (02H / 32H) are not allowed during Program/Erase suspend. Program/Erase Suspend is valid only
during the page program or sector/block erase operation. A maximum of time of “tsus” (See AC Characteristics) is required
to suspend the program/erase operation.
The Program/Erase Suspend command will be accepted by the device only if the SUS2/SUS1 bit in the Status Register
equal to 0 and WIP bit equal to 1 while a Page Program or a Sector or Block Erase operation is on-going. If the
SUS2/SUS1 bit equal to 1 or WIP bit equal to 0, the Suspend command will be ignored by the device. The WIP bit will be
cleared from 1 to 0 within “tsus” and the SUS2/SUS1 bit will be set from 0 to 1 immediately after Program/Erase Suspend.
A power-off during the suspend period will reset the device and release the suspend state. The command sequence is
show in Figure29.
Figure29. Program/Erase Suspend Sequence Diagram

CS#

0 1 2 3 4 5 6 7 tSUS
SCLK

Command
SI
75H
High-Z
SO
Accept read command

Figure29a. Program/Erase Suspend Sequence Diagram (QPI)

CS#
tSUS
0 1
SCLK

Command
75H
IO0

IO1

IO2

IO3

Accept Read

47
 3.3V Uniform Sector
Dual and Quad Serial Flash GD25Q128C
7.27. Program/Erase Resume (PER) (7AH)
The Program/Erase Resume command must be written to resume the program or sector/block erase operation after a
Program/Erase Suspend command. The Program/Erase command will be accepted by the device only if the SUS2/SUS1
bit equal to 1 and the WIP bit equal to 0. After issued the SUS2/SUS1 bit in the status register will be cleared from 1 to 0
immediately, the WIP bit will be set from 0 to 1 within 200ns and the Sector or Block will complete the erase operation or the
page will complete the program operation. The Program/Erase Resume command will be ignored unless a Program/Erase
Suspend is active. The command sequence is show in Figure30.
Figure30. Program/Erase Resume Sequence Diagram

CS#

0 1 2 3 4 5 6 7
SCLK

Command
SI
7AH

SO Resume Erase/Program

Figure30a. Program/Erase Resume Sequence Diagram (QPI)

CS#

0 1
SCLK

Command
7AH
IO0

IO1

IO2

IO3

Resume previously suspended

program or Erase

48
 3.3V Uniform Sector
Dual and Quad Serial Flash GD25Q128C
7.28. Erase Security Registers (44H)
The GD25Q128C provides three 512-byte Security Registers which can be erased and programmed individually. These
registers may be used by the system manufacturers to store security and other important information separately from the
main memory array.
The Erase Security Registers command is similar to Sector/Block Erase command. A Write Enable (WREN) command
must previously have been executed to set the Write Enable Latch (WEL) bit.
The Erase Security Registers command sequence: CS# goes low  sending Erase Security Registers command  CS#
goes high. The command sequence is shown in Figure31. CS# must be driven high after the eighth bit of the command
code has been latched in; otherwise the Erase Security Registers command is not executed. As soon as CS# is driven high,
the self-timed Erase Security Registers cycle (whose duration is tSE) is initiated. While the Erase Security Registers cycle is
in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress
(WIP) bit is 1 during the self-timed Erase Security Registers cycle, and is 0 when it is completed. At some unspecified time
before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Security Registers Lock Bit (LB3-1) in the
Status Register can be used to OTP protect the security registers. Once the LB bit is set to 1, the Security Registers will be
permanently locked; the Erase Security Registers command will be ignored.
Address A23-16 A15-12 A11-9 A8-0
Security Register #1 00H 0001 000 Do not care
Security Register #2 00H 0010 000 Do not care
Security Register #3 00H 0011 000 Do not care
Figure31. Erase Security Registers command Sequence Diagram

CS#
0 1 2 3 4 5 6 7 8 9 29 30 31
SCLK

Command 24 Bits Address

SI 44H 23 22 2 1 0
MSB

7.29. Program Security Registers (42H)

The Program Security Registers command is similar to the Page Program command. It allows from 1 to 512 bytes Security
Registers data to be programmed. A Write Enable (WREN) command must previously have been executed to set the Write
Enable Latch (WEL) bit before sending the Program Security Registers command. The Program Security Registers
command is entered by driving CS# Low, followed by the command code (42H), three address bytes and at least one data
byte on SI. As soon as CS# is driven high, the self-timed Program Security Registers cycle (whose duration is t PP) is
initiated. While the Program Security Registers cycle is in progress, the Status Register may be read to check the value of
the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Program Security Registers cycle,
and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is
reset.
If the Security Registers Lock Bit (LB3-1) is set to 1, the Security Registers will be permanently locked. Program Security
Registers command will be ignored.
Address A23-16 A15-12 A11-9 A8-0
Security Register #1 00H 0001 000 Byte Address
Security Register #2 00H 0010 000 Byte Address
Security Register #3 00H 0011 000 Byte Address

49
 3.3V Uniform Sector
Dual and Quad Serial Flash GD25Q128C
Figure32. Program Security Registers command Sequence Diagram

CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
SCLK

Command 24-bit address Data Byte 1

SI
42H 23 22 21 3 2 1 0 7 6 5 4 3 2 1 0
MSB MSB
CS#

2073

2075
2076

2078
2072

2074

2077

2079
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCLK

Data Byte 2 Data Byte 3 Data Byte 256

SI 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
MSB MSB MSB

50
 3.3V Uniform Sector
Dual and Quad Serial Flash GD25Q128C
7.30. Read Security Registers (48H)
The Read Security Registers command is similar to Fast Read command. The command i is followed by a 3-byte address
(A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK. Then the memory content, at that
address, is shifted out on SO, each bit being shifted out, at a Max frequency f C, during the falling edge of SCLK. The first
byte addressed can be at any location. The address is automatically incremented to the next higher address after each
byte of data is shifted out. Once the A8-A0 address reaches the last byte of the register (Byte 3FFH), it will reset to 000H,
the command is completed by driving CS# high.
Address A23-16 A15-12 A11-9 A8-0
Security Register #1 00H 0001 000 Byte Address
Security Register #2 00H 0010 000 Byte Address
Security Register #3 00H 0011 000 Byte Address

Figure33. Read Security Registers command Sequence Diagram

CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
SCLK

Command 24-bit address

SI
48H 23 22 21 3 2 1 0

SO High-Z

CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Byte
SI 7 6 5 4 3 2 1 0
Data Out1 Data Out2
SO 7 6 5 4 3 2 1 0 7 6 5
MSB MSB

51
 3.3V Uniform Sector
Dual and Quad Serial Flash GD25Q128C
7.31. Individual Block/Sector Lock (36H)/Unlock (39H)/Read (3DH)
The individual block/sector lock provides an alternative way to protect the memory array from adverse Erase/Program. In
order to use the Individual Block/Sector Locks, the WPS bit in Status Register-3 must be set to 1. If WPS=0, the write
protection will be determined by the combination of CMP, BP (4:0) bits in the Status Register. The Individual Block/Sector
Lock bits are volatile bits. The default values after device power up or after a Reset are 1, so the entire memory array is
being protected.
The individual Block/Sector Lock command (36H) sequence: CS# goes low SI: Sending individual Block/Sector Lock
command SI: Sending 24bits individual Block/Sector Lock Address  CS# goes high. The command sequence is shown
in Figure34.
The individual Block/Sector Unlock command (39H) sequence: CS# goes low SI: Sending individual Block/Sector Unlock
command SI: Sending 24bits individual Block/Sector Lock Address  CS# goes high. The command sequence is shown
in Figure35.
The Read individual Block/Sector lock command (3DH) sequence: CS# goes low  SI: Sending Read individual
Block/Sector Lock command SI: Sending 24bits individual Block/Sector Lock Address  SO: The Block/Sector Lock Bit
will out CS# goes high. If the least significant bit(LSB) is1, the corresponding block/sector is locked, if the LSB is 0, the
corresponding block/sector is unlocked, Erase/Program operation can be performed. The command sequence is shown in
Figure36.
Figure34. Individual Block/Sector Lock command Sequence Diagram

CS#
0 1 2 3 4 5 6 7 8 9 29 30 31
SCLK

Command 24 Bits Address

SI
36H 23 22 2 1 0
MSB

Figure34a. Individual Block/Sector Lock command Sequence Diagram (QPI)

CS#
0 1 2 3 4 5 6 7
SCLK
Command
36H A23-16 A12-8 A7-0
IO0 20 16 12 8 4 0

IO1 21 17 13 9 5 1

IO2 22 18 14 10 6 2

IO3 23 19 15 11 7 3

52
 3.3V Uniform Sector
Dual and Quad Serial Flash GD25Q128C
Figure35. Individual Block/Sector Unlock command Sequence Diagram

CS#
0 1 2 3 4 5 6 7 8 9 29 30 31
SCLK

Command 24 Bits Address

SI
39H 23 22 2 1 0
MSB

Figure35a. Individual Block/Sector Unlock command Sequence Diagram (QPI)

CS#
0 1 2 3 4 5 6 7
SCLK
Command
39H A23-16 A12-8 A7-0
IO0 20 16 12 8 4 0

IO1 21 17 13 9 5 1

IO2 22 18 14 10 6 2

IO3 23 19 15 11 7 3

Figure36. Read Individual Block/Sector lock command Sequence Diagram

CS#
0 1 2 3 4 5 6 7 8 9 29 30 31 32 33 34 35 36 37 38
SCLK

Command 24Bits Address

SI 3DH 23 22 2 1 0
MSB Lock Value Out
SO High-Z
X X X X X X X 0
MSB

53
 3.3V Uniform Sector
Dual and Quad Serial Flash GD25Q128C
Figure36a. Read Individual Block/Sector lock command Sequence Diagram (QPI)

CS#

0 1 2 3 4 5 6 7 8 9
SCLK

Command 24Bits Address

Lock Value Out
3DH
IO0 X 0

IO1 X X

IO2 X X

IO3 X X

54
 3.3V Uniform Sector
Dual and Quad Serial Flash GD25Q128C
7.32. Global Block/Sector Lock (7EH) or Unlock (98H)
All Block/Sector Lock bits can be set to 1 by the Global Block/Sector Lock command, or can set to 0 by the Global
Block/Sector Unlock command.
The Global Block/Sector Lock command (7EH) sequence: CS# goes low SI: Sending Global Block/Sector Lock
command CS# goes high. The command sequence is shown in Figure37.
The Global Block/Sector Unlock command (98H) sequence: CS# goes low SI: Sending Global Block/Sector Unlock
command CS# goes high. The command sequence is shown in Figure38.

Figure37. The Global Block/Sector Lock Sequence Diagram

CS#

0 1 2 3 4 5 6 7
SCLK

Command
SI
7EH
High-Z
SO

Figure37a. The Global Block/Sector Lock Sequence Diagram (QPI)

CS#
0 1
SCLK
Command
7EH
IO0

IO1

IO2

IO3

Figure38. The Global Block/Sector Unlock Sequence Diagram

CS#

0 1 2 3 4 5 6 7
SCLK

Command
SI
98H
High-Z
SO

55
3.3V Uniform Sector
Dual and Quad Serial Flash GD25Q128C
Figure38a. The Global Block/Sector Unlock Sequence Diagram (QPI)

CS#
0 1
SCLK
Command
98H
IO0

IO1

IO2

IO3

56
 3.3V Uniform Sector
Dual and Quad Serial Flash GD25Q128C
7.33. Set Read Parameters (C0H)
In QPI mode the “Set Read Parameters (C0H)” command can be used to configure the number of dummy clocks for “Fast
Read (0BH)”, “Quad I/O Fast Read (EBH)” and “Burst Read with Wrap (0CH)” command, and to configure the number of
bytes of “Wrap Length” for the “Burst Read with Wrap (0CH)” command. In standard SPI mode, the “Wrap Length” is set by
W5-6 bit in the “Set Burst with Wrap (77H)” command. This setting will remain unchanged when the device is switched from
Standard SPI mode to QPI mode.
Maximum Read
P5-P4 Dummy Clocks P1-P0 Wrap Length
Freq.
00 4 60MHz 00 8-byte
01 6 80MHz 01 16-byte
10 8 80MHz 10 32-byte
11 8 80MHz 11 64-byte

Figure39. Set Read Parameters command Sequence Diagram

CS#
0 1 2 3
SCLK
Command Read
C0H Parameters

IO0 P4 P0

IO1 P5 P1

IO2 P6 P2

IO3 P7 P3

57
 3.3V Uniform Sector
Dual and Quad Serial Flash GD25Q128C
7.34. Burst Read with Wrap (0CH)
The “Burst Read with Wrap (0CH)” command provides an alternative way to perform the read operation with “Wrap Around”
in QPI mode. This command is similar to the “Fast Read (0BH)” command in QPI mode, except the addressing of the read
operation will “Wrap Around” to the beginning boundary of the “Wrap Around” once the ending boundary is reached. The
“Wrap Length” and the number of dummy clocks can be configured by the “Set Read Parameters (C0H)” command.

Figure40. Burst Read with Wrap command Sequence Diagram

CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
SCLK
Command IOs switch from
0CH Input to output
IO0 20 16 12 8 4 0 4 0 4 0 4

IO1 21 17 13 9 5 1 5 1 5 1 5

IO2 22 18 14 10 6 2 6 2 6 2 6

IO3 23 19 15 11 7 3 7 3 7 3 7
A23-16 A15-8 A7-0
Dummy* Byte1 Byte2 Byte3

*"Set Read Parameters" Command (C0H)

can set the number of dummy clocks

7.35. Enable QPI (38H)

The device support both Standard/Dual/Quad SPI and QPI mode. The “Enable QPI (38H)” command can switch the device
from SPI mode to QPI mode. See the command Table 7.2. for all support QPI commands. In order to switch the device to
QPI mode, the Quad Enable (QE) bit in Status Register-1 must be set to 1 first, and “Enable QPI (38H)” command must be
issued. If the QE bit is 0, the “Enable QPI (38H)” command will be ignored and the device will remain in SPI mode. When
the device is switched from SPI mode to QPI mode, the existing Write Enable Latch and Program/Erase Suspend status,
and the Wrap Length setting will remain unchanged.

Figure41. Enable QPI mode command Sequence Diagram

CS#

0 1 2 3 4 5 6 7
SCLK

Command
SI
38H

58
 3.3V Uniform Sector
Dual and Quad Serial Flash GD25Q128C
7.36. Disable QPI (FFH)
To exit the QPI mode and return to Standard/Dual/Quad SPI mode, the “Disable QPI (FFH)” command must be issued.
When the device is switched from QPI mode to SPI mode, the existing Write Enable Latch and Program/Erase Suspend
status, and the Wrap Length setting will remain unchanged.

Figure42. Disable QPI mode command Sequence Diagram

CS#
0 1
SCLK
Command
FFH
IO0

IO1

IO2

IO3

7.37. Enable Reset (66H) and Reset (99H)

If the Reset command is accepted, any on-going internal operation will be terminated and the device will return to its default
power-on state and lose all the current volatile settings, such as Volatile Status Register bits, Write Enable Latch status
(WEL), Program/Erase Suspend status, Read Parameter setting (P7-P0), Continuous Read Mode bit setting (M7-M0) and
Wrap Bit Setting (W6-W4).
The “Enable Reset (66H)” and the “Reset (99H)” commands can be issued in either SPI or QPI mode. The “Reset (99H)”
command sequence as follow: CS# goes low  Sending Enable Reset command  CS# goes high  CS# goes low 
Sending Reset command  CS# goes high. Once the Reset command is accepted by the device, the device will take
approximately tRST =60us to reset. During this period, no command will be accepted. Data corruption may happen if there is
an on-going or suspended internal Erase or Program operation when Reset command sequence is accepted by the device.
It is recommended to check the BUSY bit and the SUS bit in Status Register before issuing the Reset command sequence.
Figure43. Enable Reset and Reset command Sequence Diagram

CS#

0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
SCLK

Command Command
SI
66H 99H

SO High-Z

59
 3.3V Uniform Sector
Dual and Quad Serial Flash GD25Q128C
Figure44. Enable Reset and Reset command Sequence Diagram (QPI)

CS#
0 1 0 1
SCLK
Command Command
66H 99H
IO0

IO1

IO2

IO3

7.38. Read Serial Flash Discoverable Parameter (5AH)

The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional and
feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables can be
interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple
vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on CFI. SFDP is a
standard of JEDEC Standard No.216.

Figure45. Read Serial Flash Discoverable Parameter command Sequence Diagram

CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
SCLK

Command 24-bit address

SI
5AH 23 22 21 3 2 1 0

SO High-Z

CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Byte
SI 7 6 5 4 3 2 1 0
Data Out1 Data Out2
SO 7 6 5 4 3 2 1 0 7 6 5
MSB MSB

60
 3.3V Uniform Sector
Dual and Quad Serial Flash GD25Q128C
Figure45a. Read Serial Flash Discoverable Parameter command Sequence Diagram (QPI)

CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13
SCLK
Command IOs switch from
5AH Dummy* Input to output
A23-16 A15-8 A7-0
IO0 20 16 12 8 4 0 4 0 4 0 4 0 4

IO1 21 17 13 9 5 1 5 1 5 1 5 1 5

IO2 22 18 14 10 6 2 6 2 6 2 6 2 6

IO3 23 19 15 11 7 3 7 3 7 3 7 3 7
Byte1 Byte2

*"Set Read Parameters" Command (C0H)

can set the number of dummy clocks

61
 3.3V Uniform Sector
Dual and Quad Serial Flash GD25Q128C
Table 7.4. Signature and Parameter Identification Data Values
Description Comment Add(H) DW Add Data Data
(Byte) (Bit)
SFDP Signature Fixed:50444653H 00H 07:00 53H 53H
01H 15:08 46H 46H
02H 23:16 44H 44H
03H 31:24 50H 50H
SFDP Minor Revision Number Start from 00H 04H 07:00 00H 00H
SFDP Major Revision Number Start from 01H 05H 15:08 01H 01H
Number of Parameters Headers Start from 00H 06H 23:16 01H 01H
Unused Contains 0xFFH and can never be 07H 31:24 FFH FFH
changed
ID number (JEDEC) 00H: It indicates a JEDEC specified 08H 07:00 00H 00H
header
Parameter Table Minor Revision Start from 0x00H 09H 15:08 00H 00H
Number
Parameter Table Major Revision Start from 0x01H 0AH 23:16 01H 01H
Number
Parameter Table Length How many DWORDs in the 0BH 31:24 09H 09H
(in double word) Parameter table
Parameter Table Pointer (PTP) First address of JEDEC Flash 0CH 07:00 30H 30H
Parameter table 0DH 15:08 00H 00H
0EH 23:16 00H 00H
Unused Contains 0xFFH and can never be 0FH 31:24 FFH FFH
changed
ID Number It is indicates GigaDevice 10H 07:00 C8H C8H
(GigaDevice Manufacturer ID) manufacturer ID
Parameter Table Minor Revision Start from 0x00H 11H 15:08 00H 00H
Number
Parameter Table Major Revision Start from 0x01H 12H 23:16 01H 01H
Number
Parameter Table Length How many DWORDs in the 13H 31:24 03H 03H
(in double word) Parameter table
Parameter Table Pointer (PTP) First address of GigaDevice Flash 14H 07:00 60H 60H
Parameter table 15H 15:08 00H 00H
16H 23:16 00H 00H
Unused Contains 0xFFH and can never be 17H 31:24 FFH FFH
changed

62
 3.3V Uniform Sector
Dual and Quad Serial Flash GD25Q128C
Table 7.5. Parameter Table (0): JEDEC Flash Parameter Tables
Description Comment Add(H) DW Add Data Data
(Byte) (Bit)
00: Reserved; 01: 4KB erase;
Block/Sector Erase Size 10: Reserved; 01:00 01b
11: not support 4KB erase
Write Granularity 0: 1Byte, 1: 64Byte or larger 02 1b
Write Enable Instruction 0: Nonvolatile status bit
Requested for Writing to Volatile 1: Volatile status bit 03 0b
Status Registers (BP status register bit)
30H E5H
0: Use 50H Opcode,
1: Use 06H Opcode,
Write Enable Opcode Select for
Note: If target flash status register is 04 0b
Writing to Volatile Status Registers
Nonvolatile, then bits 3 and 4 must
be set to 00b.
Contains 111b and can never be
Unused 07:05 111b
changed
4KB Erase Opcode 31H 15:08 20H 20H
(1-1-2) Fast Read 0=Not support, 1=Support 16 1b
Address Bytes Number used in 00: 3Byte only, 01: 3 or 4Byte,
18:17 00b
addressing flash array 10: 4Byte only, 11: Reserved
Double Transfer Rate (DTR)
0=Not support, 1=Support 19 0b
clocking 32H F1H
(1-2-2) Fast Read 0=Not support, 1=Support 20 1b
(1-4-4) Fast Read 0=Not support, 1=Support 21 1b
(1-1-4) Fast Read 0=Not support, 1=Support 22 1b
Unused 23 1b
Unused 33H 31:24 FFH FFH
Flash Memory Density 37H:34H 31:00 07FFFFFFH
(1-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy
04:00 00100b
states Clocks) not support
38H 44H
(1-4-4) Fast Read Number of
000b:Mode Bits not support 07:05 010b
Mode Bits
(1-4-4) Fast Read Opcode 39H 15:08 EBH EBH
(1-1-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy
20:16 01000b
states Clocks) not support
3AH 08H
(1-1-4) Fast Read Number of
000b:Mode Bits not support 23:21 000b
Mode Bits
(1-1-4) Fast Read Opcode 3BH 31:24 6BH 6BH

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Dual and Quad Serial Flash GD25Q128C
Add(H) DW Add
Description Comment Data Data
(Byte) (Bit)
(1-1-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy
04:00 01000b
states Clocks) not support
3CH 08H
(1-1-2) Fast Read Number
000b: Mode Bits not support 07:05 000b
of Mode Bits
(1-1-2) Fast Read Opcode 3DH 15:08 3BH 3BH
(1-2-2) Fast Read Number 0 0000b: Wait states (Dummy
20:16 00010b
of Wait states Clocks) not support
3EH 42H
(1-2-2) Fast Read Number
000b: Mode Bits not support 23:21 010b
of Mode Bits
(1-2-2) Fast Read Opcode 3FH 31:24 BBH BBH
(2-2-2) Fast Read 0=not support 1=support 00 0b
Unused 03:01 111b
40H FEH
(4-4-4) Fast Read 0=not support 1=support 04 1b
Unused 07:05 111b
Unused 43H:41H 31:08 0xFFH 0xFFH
Unused 45H:44H 15:00 0xFFH 0xFFH
(2-2-2) Fast Read Number 0 0000b: Wait states (Dummy
20:16 00000b
of Wait states Clocks) not support
46H 00H
(2-2-2) Fast Read Number
000b: Mode Bits not support 23:21 000b
of Mode Bits
(2-2-2) Fast Read Opcode 47H 31:24 FFH FFH
Unused 49H:48H 15:00 0xFFH 0xFFH
(4-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy
20:16 00100b
states Clocks) not support
4AH 44H
(4-4-4) Fast Read Number
000b: Mode Bits not support 23:21 010b
of Mode Bits
(4-4-4) Fast Read Opcode 4BH 31:24 EBH EBH
Sector/block size=2^N bytes
Sector Type 1 Size 4CH 07:00 0CH 0CH
0x00b: this sector type don’t exist
Sector Type 1 erase Opcode 4DH 15:08 20H 20H
Sector/block size=2^N bytes
Sector Type 2 Size 4EH 23:16 0FH 0FH
0x00b: this sector type don’t exist
Sector Type 2 erase Opcode 4FH 31:24 52H 52H
Sector/block size=2^N bytes
Sector Type 3 Size 50H 07:00 10H 10H
0x00b: this sector type don’t exist
Sector Type 3 erase Opcode 51H 15:08 D8H D8H
Sector/block size=2^N bytes
Sector Type 4 Size 52H 23:16 00H 00H
0x00b: this sector type don’t exist
Sector Type 4 erase Opcode 53H 31:24 FFH FFH

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Table 7.6. Parameter Table (1): GigaDevice Flash Parameter Tables
Add(H) DW Add
Description Comment Data Data
(Byte) (Bit)
2000H=2.000V
Vcc Supply Maximum Voltage 2700H=2.700V 61H:60H 15:00 3600H 3600H
3600H=3.600V
1650H=1.650V
2250H=2.250V
Vcc Supply Minimum Voltage 63H:62H 31:16 2700H 2700H
2350H=2.350V
2700H=2.700V
HW Reset# pin 0=not support 1=support 00 1b
HW Hold# pin 0=not support 1=support 01 1b
Deep Power Down Mode 0=not support 1=support 02 1b
SW Reset 0=not support 1=support 03 1b
Should be issue Reset Enable(66H) 1001 1001b
SW Reset Opcode 65H:64H 11:04 F99FH
before Reset cmd. (99H)
Program Suspend/Resume 0=not support 1=support 12 1b
Erase Suspend/Resume 0=not support 1=support 13 1b
Unused 14 1b
Wrap-Around Read mode 0=not support 1=support 15 1b
Wrap-Around Read mode Opcode 66H 23:16 77H 77H
08H:support 8B wrap-around read
16H:8B&16B
Wrap-Around Read data length 67H 31:24 64H 64H
32H:8B&16B&32B
64H:8B&16B&32B&64B
Individual block lock 0=not support 1=support 00 1b
Individual block lock bit
0=Volatile 1=Nonvolatile 01 0b
(Volatile/Nonvolatile)
Individual block lock Opcode 09:02 36H
Individual block lock Volatile
0=protect 1=unprotect 10 0b E8D9H
protect bit default protect status 6BH:68H
Secured OTP 0=not support 1=support 11 1b
Read Lock 0=not support 1=support 12 0b
Permanent Lock 0=not support 1=support 13 1b
Unused 15:14 11b
Unused 31:16 FFH FFH

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Dual and Quad Serial Flash GD25Q128C
8. ELECTRICAL CHARACTERISTICS

8.1. POWER-ON TIMING

Figure 46. Power-on Timing Sequence Diagram

Vcc(max)
Program, Erase and Write command are ignored
Chip Selection is not allowed
Vcc(min)
tVSL Read command Device is fully
Reset is allowed accessible
State
VWI
tPUW

Time

Table 8.1. Power-Up Timing and Write Inhibit Threshold

Symbol Parameter Min Max Unit

tVSL VCC(min) To CS# Low 10 us
tPUW Time Delay Before Write Instruction 1 10 ms
VWI Write Inhibit Voltage 1 2.5 V

8.2. INITIAL DELIVERY STATE

The device is delivered with the memory array erased: all bits are set to 1(each byte contains FFH). The Status
Register bits are set to 0, except DRV1 bit (S22) is set to 1.

8.3. DATA RETENTION AND ENDURANCE

Parameter Test Condition Min Units

150℃ 10 Years
Minimum Pattern Data Retention Time
125℃ 20 Years
Erase/Program Endurance -40 to 85℃ 100K Cycles

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8.4. ABSOLUTE MAXIMUM RATINGS
Parameter Value Unit
Ambient Operating Temperature -40 to 85 ℃
Storage Temperature -65 to 150 ℃
Output Short Circuit Current 200 mA
Applied Input / Output Voltage -0.6 to VCC+0.4 V
Transient Input / Output Voltage(note: overshoot) -2.0 to VCC+2.0 V
VCC -0.6 to 4.0 V

Figure 47. Maximum Negative/positive Overshoot Diagram

Maximum Negative Overshoot Waveform Maximum Positive Overshoot Waveform

20ns 20ns
20ns
Vss
Vcc + 2.0V

Vss-2.0V
20ns Vcc
20ns 20ns

8.5. CAPACITANCE MEASUREMENT CONDITIONS

Symbol Parameter Min Typ Max Unit Conditions
CIN Input Capacitance 6 pF VIN=0V
COUT Output Capacitance 8 pF VOUT=0V
CL Load Capacitance 30 pF
Input Rise And Fall time 5 ns
Input Pulse Voltage 0.1VCC to 0.8VCC V
Input Timing Reference Voltage 0.2VCC to 0.7VCC V
Output Timing Reference Voltage 0.5VCC V

Figure48. Input Test Waveform and Measurement Level

Input timing reference level Output timing reference level

0.8VCC 0.7VCC
AC Measurement Level 0.5VCC
0.1VCC 0.2VCC

Note: Input pulse rise and fall time are <5ns

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Dual and Quad Serial Flash GD25Q128C
8.6. DC CHARACTERISTICS
(T= -40℃~85℃, VCC=2.7~3.6V)
Symbol Parameter Test Condition Min. Typ Max. Unit.
ILI Input Leakage Current ±2 μA
ILO Output Leakage Current ±2 μA
ICC1 Standby Current CS#=VCC, 15 50 μA
VIN=VCC or VSS
ICC2 Deep Power-Down Current CS#=VCC, 1 5 μA
VIN=VCC or VSS
CLK=0.1VCC / 0.9VCC
at 104MHz, 15 20 mA
Q=Open(*1 I/O)
ICC3 Operating Current (Read)
CLK=0.1VCC / 0.9VCC
at 80MHz, 13 18 mA
Q=Open(*1,*2,*4 I/O)
ICC4 Operating Current (PP) CS#=VCC 10 mA
ICC5 Operating Current(WRSR) CS#=VCC 10 mA
ICC6 Operating Current (SE) CS#=VCC 10 mA
ICC7 Operating Current (BE) CS#=VCC 10 mA
VIL Input Low Voltage 0.2VCC V
VIH Input High Voltage 0.7VCC VCC+0.4 V
VOL Output Low Voltage IOL =100uA 0.2 V
VOH Output High Voltage IOH =-100μA VCC-0.2 V

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Dual and Quad Serial Flash GD25Q128C
8.7. AC CHARACTERISTICS
(T= -40℃~85℃, VCC=2.7~3.6V, CL=30pf)
Symbol Parameter Min. Typ. Max. Unit.
fC Serial Clock Frequency For All Instructions Except Read DC. 104 MHz
fC1 Serial Clock Frequency For Quad Read Instructions (1) DC. 104/80 MHz
fC2 Serial Clock Frequency For QPI Instructions DC. 80 MHz
Serial Clock Frequency For: Read(03H), Read Manufacturer
fR DC. 80 MHz
ID/device ID(90H), Read Identification(9FH)
tCLH Serial Clock High Time 4.5 ns
tCLL Serial Clock Low Time 4.5 ns
tCLCH Serial Clock Rise Time (Slew Rate) 0.2 V/ns
tCHCL Serial Clock Fall Time (Slew Rate) 0.2 V/ns
tSLCH CS# Active Setup Time 5 ns
tCHSH CS# Active Hold Time 5 ns
tSHCH CS# Not Active Setup Time 5 ns
tCHSL CS# Not Active Hold Time 5 ns
tSHSL CS# High Time (read/write) 20 ns
tSHQZ Output Disable Time 6 ns
tCLQX Output Hold Time 1.0 ns
tDVCH Data In Setup Time 2 ns
tCHDX Data In Hold Time 2 ns
tHLCH HOLD# Low Setup Time (relative to Clock) 5 ns
tHHCH HOLD# High Setup Time (relative to Clock) 5 ns
tCHHL HOLD# High Hold Time (relative to Clock) 5 ns
tCHHH HOLD# Low Hold Time (relative to Clock) 5 ns
tHLQZ HOLD# Low To High-Z Output 6 ns
tHHQX HOLD# Low To Low-Z Output 6 ns
tCLQV Clock Low To Output Valid 6.5 ns
tWHSL Write Protect Setup Time Before CS# Low 20 ns
tSHWL Write Protect Hold Time After CS# High 100 ns
tDP CS# High To Deep Power-Down Mode 20 μs
CS# High To Standby Mode Without Electronic Signature
tRES1 30 μs
Read
tRES2 CS# High To Standby Mode With Electronic Signature Read 30 μs
tSUS CS# High To Next Command After Suspend 20 us
tRST CS# High To Next Command After Reset 60 us
tW Write Status Register Cycle Time 5 30 ms
tBP1 Byte Program Time( First Byte) 30 50 us
tBP2 Additional Byte Program Time ( After First Byte) 2.5 12 us
tPP Page Programming Time 0.6 2.4 ms
tSE Sector Erase Time 50 400 ms
tBE Block Erase Time(32K Bytes) 0.2 1.0 s

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Dual and Quad Serial Flash GD25Q128C
tBE Block Erase Time(64K Bytes) 0.3 1.2 s
tCE Chip Erase Time(GD25Q128C) 60 120 s

Note:
1. Serial Clock Frequency for Quad Read Instructions fC1 is 104MHz maximum, when operating temperature is ≤80℃.
Serial Clock Frequency for Quad Read Instructions fC1 is 80MHz maximum, when 80℃＜ operating temperature ≤
85℃ .
Figure49. Serial Input Timing

tSHSL
CS#

tCHSL tSLCH tCHSH tSHCH

SCLK
tDVCH tCHCL
tCHDX tCLCH

SI MSB LSB

SO High-Z

Figure50. Output Timing

CS#
tCLH tSHQZ
SCLK
tCLQV tCLQV tCLL
tCLQX tCLQX
SO LSB

SI
Least significant address bit (LIB) in

Figure51. Hold Timing

CS#

tCHHL tHLCH tHHCH

SCLK

tCHHH
tHLQZ tHHQX
SO

HOLD#

SI do not care during HOLD operation.

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Dual and Quad Serial Flash GD25Q128C
Figure52. RESET Timing

tRB1
CS# tRB2

RESET#

tRLRH tRHSL

Reset Timing
Symbol Parameter Setup Speed Unit.
tRLRH Reset pulse width MIN 1 us
tRHSL Reset high time before read MIN 50 ns
tRB1 Reset recovery time (For NOT busy mode) MAX 5 us
tRB2 Reset recovery time (For busy mode) MAX 60 us

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Dual and Quad Serial Flash GD25Q128C
9. ORDERING INFORMATION

GD XX X XX X X X X X
Packing Type
Y:Tray
R:Tape & Reel

Green Code
G:Pb Free & Halogen Free Green Package
Temperature Range
I:Industrial(-40℃ to +85℃)
Package Type
P: DIP8 300mil
S:SOP8 208mil
V:VSOP8 208mil
F:SOP16 300mil
W: WSON8 (6*5mm)
Y: WSON8 (8*6mm)
Z:TFBGA24(6*4 Ball Array)
Generation
A: A Version or no mark
B: B Version
C: C Version
Density
128:128Mb

Series
Q: 3V, 4KB Uniform Sector
B: 3V, 4KB Uniform Sector,
QE=1 Permanently

Product Family
25:SPI Interface Flash

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Dual and Quad Serial Flash GD25Q128C
10. PACKAGE INFORMATION

10.1. Package SOP8 208MIL

8 5 θ

E1 E

L1
L
1 4
C
D

A2 A

b A1
e

Dimensions
Symbol
A A1 A2 b C D E E1 e L L1 θ
Unit
Min 0.05 1.70 0.31 0.18 5.13 7.70 5.18 0.50 1.21 0
mm Nom 0.15 1.80 0.41 0.21 5.23 7.90 5.28 1.27 0.67 1.31 5
Max 2.16 0.25 1.91 0.51 0.25 5.33 8.10 5.38 0.85 1.41 8
Min 0.002 0.067 0.012 0.007 0.202 0.303 0.204 0.020 0.048 0
Inch Nom 0.006 0.071 0.016 0.008 0.206 0.311 0.208 0.050 0.026 0.052 5
Max 0.085 0.010 0.075 0.020 0.010 0.210 0.319 0.212 0.033 0.056 8
Note：Both package length and width do not include mold flash.

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 3.3V Uniform Sector
Dual and Quad Serial Flash GD25Q128C
10.2. Package VSOP8 208MIL
8 5 θ

E1 E

L1
L
1 4
C
D

A2 A

b A1
e

Dimensions
Symbol
A A1 A2 b D E E1 e L L1 C θ
Unit
Min - 0.05 0.75 0.35 5.18 7.70 5.18 - 0.50 0.09 0°
mm Nom - 0.10 0.80 0.42 5.28 7.90 5.28 1.27BSC 0.65 1.31REF - -
Max 1.00 0.15 0.85 0.48 5.38 8.10 5.38 - 0.80 0.2 10°
Min - 0.002 0.030 0.014 0.204 0.303 0.204 - 0.020 0.004 0°
Inch Nom - 0.004 0.031 0.017 0.208 0.311 0.208 0.050BSC 0.026 0.052REF 0 -
Max 0.04 0.006 0.033 0.019 0.212 0.319 0.212 - 0.031 0.008 10°
Note：Both package length and width do not include mold flash.

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 3.3V Uniform Sector
Dual and Quad Serial Flash GD25Q128C
10.3. Package SOP16 300MIL

16 9 θ

E1 E

L1
L
1 8
C
D

A2 A

b A1
e

Dimensions
Symbol
A A1 A2 b C D E E1 e L L1 θ
Unit
Min 2.36 0.10 2.24 0.36 0.20 10.10 10.10 7.42 0.40 1.31 0
mm Nom 2.55 0.20 2.34 0.41 0.25 10.30 10.35 7.52 1.27 0.84 1.44 5
Max 2.75 0.30 2.44 0.51 0.30 10.50 10.60 7.60 1.27 1.57 8
Min 0.093 0.004 0.088 0.014 0.008 0.397 0.397 0.292 0.016 0.052 0
Inch Nom 0.100 0.008 0.092 0.016 0.010 0.405 0.407 0.296 0.050 0.033 0.057 5
Max 0.108 0.012 0.096 0.020 0.012 0.413 0.417 0.299 0.050 0.062 8
Note：Both package length and width do not include mold flash.

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 3.3V Uniform Sector
Dual and Quad Serial Flash GD25Q128C
10.4. Package DIP8 300MIL

4 1
E
11°

E1

R0.005xDP0.020 11° 5°
C

eB
5 8

A2

L A1
b
e
b1

Dimensions
Symbol
A1 A2 b b1 C D E E1 e eB L
Unit
Min 0.38 3.00 1.27 0.38 0.20 9.05 7.62 6.12 7.62 3.04
mm Nom 0.72 3.25 1.46 0.46 0.28 9.32 7.94 6.38 2.54 8.49 3.30
Max 1.05 3.50 1.65 0.54 0.34 9.59 8.26 6.64 9.35 3.56
Min 0.015 0.118 0.05 0.015 0.008 0.356 0.300 0.242 0.333 0.12
Inch Nom 0.028 0.128 0.058 0.018 0.011 0.367 0.313 0.252 0.1 0.345 0.13
Max 0.041 0.138 0.065 0.021 0.014 0.378 0.326 0.262 0.357 0.14
Note：Both package length and width do not include mold flash.

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 3.3V Uniform Sector
Dual and Quad Serial Flash GD25Q128C
10.5. Package WSON 8 (6*5mm)

D
A2

A1
A
Top View Side View
L D1

b 1

e E1

Bottom View

Dimensions
Symbol
A A1 A2 b D D1 E E1 e y L
Unit
Min 0.70 0.19 0.35 5.90 3.25 4.90 3.85 0.00 0.50
mm Nom 0.75 0.22 0.42 6.00 3.37 5.00 3.97 1.27BSC 0.04 0.60
Max 0.80 0.05 0.25 0.48 6.10 3.50 5.10 4.10 0.08 0.75
Min 0.028 0.007 0.014 0.232 0.128 0.193 0.151 0.000 0.020
Inch Nom 0.030 0.009 0.016 0.236 0.133 0.197 0.156 0.05BSC 0.001 0.024
Max 0.032 0.002 0.010 0.019 0.240 0.138 0.201 0.161 0.003 0.030
Note:
1. Both package length and width do not include mold flash.
2. The exposed metal pad area on the bottom of the package is connected to device ground (GND pin),
so both Floating and connecting GND of exposed pad are also available.

77
 3.3V Uniform Sector
Dual and Quad Serial Flash GD25Q128C
10.6. Package WSON 8 (8*6mm)

D
A2

A1
A
Top View Side View
L D1

b 1

e E1

Bottom View

Dimensions
Symbol
A A1 A2 b D D1 E E1 e K L
Unit
Min 0.70 0.35 7.90 3.25 5.90 4.15 0.55
mm Nom 0.75 0.20BSC 0.40 8.00 3.42 6.00 4.30 1.27BSC 1.80 0.60
Max 0.80 0.05 0.45 8.10 3.50 6.10 4.40 0.65
Min 0.028 0.014 0.311 0.128 0.232 0.163 0.022
Inch Nom 0.030 0.008BSC 0.016 0.315 0.135 0.236 0.169 0.050BSC 0.071 0.024
Max 0.031 0.002 0.018 0.319 0.138 0.240 0.173 0.027
Note:
1. Both package length and width do not include mold flash.
2. The exposed metal pad area on the bottom of the package is connected to device ground (GND pin),
so both Floating and connecting GND of exposed pad are also available

78
 3.3V Uniform Sector
Dual and Quad Serial Flash GD25Q128C
10.7. Package TFBGA-24BALL (6*4 ball array)

1 2 3 4 4 3 2 1

A A
e
B B

C C
E E1
D D

E E

F F

D e
Φb D1

A1 A

A2

Dimensions
Symbol
A A1 A2 b D D1 E E1 e
Unit
Min 0.25 0.35 5.90 7.90
mm Nom 0.30 0.85 0.40 6.00 3.00 8.00 5.00 1.00
Max 1.20 0.35 0.45 6.10 8.10
Min 0.010 0.014 0.232 0.311
Inch Nom 0.012 0.033 0.016 0.236 0.120 0.315 0.200 0.039
Max 0.047 0.014 0.018 0.240 0.319
Note：Both package length and width do not include mold flash.

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Dual and Quad Serial Flash GD25Q128C
11. REVISION HISTORY

Version No Description Date

1.0 Initial Release 2013/7/25
Modify AC CHARACTERISTICS: tCLQV 7.0ns max change to 6.5ns max
1.1 2013/9/24
Modify AC CHARACTERISTICS: tCLQX 1.2ns min change to 1.0ns min
1.2 Modify SFDP table 2013/11/21
Modify OTP size and Security Register Address
1.3 2014/7/29
Modify Package WSON8 8x6mm
1.4 Modify Package SOP16 300mil 2014/10/8
1.5 Modify ELECTRICAL CHARACTERISTICS 2015-3-10

80