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Part 4 –PCB LAYOUT

RULES FOR SIGNAL
INTEGRITY

The information in this work has been obtained from sources believed to be reliable.
The author does not guarantee the accuracy or completeness of any information
presented herein, and shall not be responsible for any errors, omissions or damages
as a result of the use of this information.

Feb 2012 Fabian Kung Wai Lee 1

References
• [1] H. Johnson, M. Graham, “High-speed digital design – A handbook of black
magic”, Prentice-Hall, 1993.
• [2] D.M. Pozar, “Microwave engineering”, 2nd edition, 1998 John-Wiley & Sons.
• [3] M. I. Montrose, “EMC and printed circuit board – design theory and layout
made simple”, IEEE Press, 1999.
• [4] T. C. Edwards, “Foundations for microstrip circuit design”, 2nd edition, 1992
John-Wiley & Sons.
• [5] T. C. Edwards, “Foundations of interconnect and microstrip design”, 3rd
edition, 2000, John-Wiley & Sons.
• [6] H. Howe, “Stripline circuit design”, 1974, Artech House.
• [7] I. Bahl, P. Bhartia, “Microwave solid state circuit design”, 2nd edition, 2003,
John-Wiley & Sons.
• [8] http://pesona.mmu.edu.my/~wlkung/Master/mthesis.htm
• [9] S. H. Hall, G. W. Hall, J. A. McCall, “High-speed digital system design”,
2000, John-Wiley & Sons.
• [10] T. Williams, “EMC for product designers”, 2001, Butterworth-Heinemann.
• [11] H. W. Ott, “Noise reduction techniques in electronic systems”, 1988, John-
Wiley & Sons.
• [12] D. Brooks, “Signal integrity issues and printed circuit board design”, 2003,
Prentice Hall.

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Introduction
• By PCB layout we imply the designing the pattern or the shape of the
conducting structures on the PCB, stacking up the various layers of the
PCB, placement of components and vias.
• The purpose of a good PCB layout tends to achieve the following
objectives:
– (A) Provide a means of sending electrical energy from one
component to the other with as little ‘obstacle’ as possible.
– (B) Provide sufficient isolation such that electrical signal in
one path does not affect other, and vice versa. This means we
want to reduce electric/magnetic field coupling, and also common
impedance coupling.
• We can achieve objective A by reducing unnecessary reflections or
distortion and loading along the signal path for high-speed signal.
• We can achieve objective B by providing proper ‘grounding’ and noise
suppression on the power delivery system of the circuit (and also
sufficient spatial separation).
Feb 2012 Fabian Kung Wai Lee 3

4.1 – Introduction to the

Concept of Discontinuities
in Transmission Line Circuit

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Practical Transmission Line Design

and Discontinuities
• Discontinuities in Tline are changes in the Tline geometry to
accommodate layout and other requirements on the printed circuit
board.
• Virtually all practical distributed circuits, whether in waveguide, coaxial
cables, microstrip line etc. must inherently contains discontinuities. A
straight uninterrupted length of waveguide or Tline would be of little
engineering use.
• The following discussion consider the effect and compensation for
discontinuities in PCB layout. This discussion is restricted to TEM or
quasi-TEM propagation modes.

Feb 2012 Fabian Kung Wai Lee 5

Transmission Line Discontinuities

Found in PCB (1)
plane

bend
trace trace Here we illustrate the
gap discontinuities using
Ground plane gap microstripline. Similar
Bend ground plane
structures apply to
pad
socket
other transmission line
trace
cylinder pin configuration as well.
plane via
trace
Via
Socket-trace interconnection

Junction

Open Step Line to Component

Bend Interface
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Transmission Line Discontinuities

Found in PCB (2)
• Further examples of microstrip and co-planar line discontinuities.

Gap Pad or Stub Coupled lines

Examples of bend and via

on co-planar Tline.

Feb 2012 Fabian Kung Wai Lee 7

Discontinuities and EM Fields (1)

• Introduction of discontinuities will distort the uniform EM fields present
in the infinite length Tline. Assuming the propagation mode is TEM or
quasi-TEM, the discontinuity will create a multitude of higher modes
(such as TM11 , TM12 , TE11 , …) in its vicinity in order to fulfill the
boundary conditions (Note - there is only one type of TEM mode !!).
• Most of these induced higher order modes are evanescent or non-
propagating as their cut-off frequencies are higher than the operating
frequency of the circuit. Thus the fields of the higher order modes are
known as local fields.
• The effect of discontinuity is usually reactive (the energy stored in the
local fields is returned back to the system) since loss is negligible.
• The effect of reactive system to the voltage and current can be
modeled using LC circuits (which are reactive elements).
• For TEM or quasi-TEM mode, we can consider the discontinuity as a 2-
port network containing inductors and capacitors.

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Discontinuities and EM Fields (2)

• Modeling a discontinuity using circuit theory element such as RLCG is a
good approximation for operating frequency up to 6 -20 GHz. This upper
limit depends on substrate thickness and size of discontinuity.
• The smaller the dimension of the discontinuity as compared to the
wavelength, the higher will be the upper usable frequency.
• As a example, the 2-port model for a microstrip bend is usually accurate
up to 10 GHz.
Minimum distance See Chapter 5, T.C. Edwards, “Foundation
for microstrip circuit design” [4], or Chapter 3 [8]
A 0.25λ
A 0.25λ B

0.25λ Two port

networks
A’
B’ B A’ B’

Feb 2012 Fabian Kung Wai Lee 9

Discontinuities and EM Fields (3)

• For instance for a microstrip bend, a snapshot of the EM fields at a
particular instant in time:

Non-TEM mode *This field can be decomposed into

field here* TEM and non-TEM components

E field
H field

Direction of propagation

Quasi-TEM
field

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Methods of Obtaining Equivalent

Circuit Model for Discontinuities (1)
• 3 Typical approaches…
• Method 1: Analytical solution - see Chapter 4, reference [3] on Modal
Analysis for waveguide discontinuities.
• Method 2: Numerical methods, for example:
Agilent’s Momentum
– Method of Moments (MOM).
Ansoft’s HFSS •CST’s Microwave
– Finite Element Method (FEM).
Studio
– Finite Difference Time Domain Method (FDTD). •Sonnet
– And many others.
• Numerical methods are used to find the quasi-static EM fields of a 3D
model containing the discontinuity. The EM field in the vicinity of the
discontinuity is split into TEM and non-TEM fields. LC elements are
then associated with the non-TEM fields using formula similar to (3.1)
in Part 3.

Feb 2012 Fabian Kung Wai Lee 11

Methods of Obtaining Equivalent Circuit

Model for Discontinuities (2)
• Method 3: Fitting measurement with circuit models. By proposing an
equivalent circuit model, we can try to tune the parameters of the circuit
elements in the model so that frequency/time domain response from
theoretical analysis and measurement match.
• Measurement can be done in time domain using time-domain
reflectometry (TDR) and frequency domain measurement using a
vector network analyzer (VNA) (see Chapter 3 of Ref [4] for details).

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4.2 - Practical Stripline

Discontinuities

Feb 2012 Fabian Kung Wai Lee 13

Microstrip Line Discontinuity Models

(1)
Through hole: Ls   4h  
Ls ≅ 0.2h ln  + 1 (2.1a)
  d  

0.5Cp 0.5Cp ε hd
C p ≅ 0.056 r N (2.1b)
2 d −d
d = diameter of via or
internal pad This is the capacitance between the via and
internal plane. If there are multiple internal
conducting planes, then there should be one
GND planes
Cp corresponding to each internal plane.

d2 = diameter Ls in nH
of relief or Cp in pF
antipad h in mm
d and d2 in mm
h Cross section
εr = dielectric constant of PCB
of a Via N = number of GND planes
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Microstrip Line Discontinuity Models

(2)
90o Bend:
L L
T1
C
w

T2 See Edwards [4], Chapter 5

Approximate quasi-static expressions for L1, L2 and C:

C (14ε r +12.5) wd −(1.83ε r −2.25 ) for w <1
w
= pF/m d
w/ d (2.2a)
w
C
w
= (9.5ε r + 1.25) + 5.2ε r + 7.0 pF/m
w
d
for d
>1
εr = dielectric constant of substrate,
L = 100 4 w − 4.21 nH/m (2.2b) assume non-magnetic.
d  d 
d = thickness of dielectric in meter.

Feb 2012 Fabian Kung Wai Lee 15

Example 2.1 - Microstrip Line Bend

• For a 90o microstrip line bend, with w = 0.92mm, d = 0.51mm, εr = 4.6
(non-magnetic substrate). Find the value of L and C for the bend.

C
w
= (9.5 × 4.6 + 1.25)1.8 + 5.2 × 4.6 + 7.0
= 111.83 pF/m w = 1.834
d
⇒ C = 111.83 × 0.00092 = 0.10pF
30.0pH 30.0pH

L
d
[
= 100 4 1.8 − 4.21 = 115.66 nH/m ] 0.10pF
⇒ L ≅ 60pH
Typically the effect of bend is not
At 1GHz: important for frequency below 1 GHz.
Reactance of C Xc = 1
≅ 1592 This is also true for discontinuities like
2πfC
step and T-junction.
Reactance of L X L = 2πfL ≅ 0.38
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Microstrip Line Discontinuity Models

(3)
Step: L1 L2

T1 T2 C
w1 w2 See Edwards [4] Chapter 5
Approximate quasi-static expressions for L1, L2 and C:
w w2
C = (10.1log ε r + 2.33) w1 − 12.6 log ε r − 3.17 pF/m for ε r ≤ 10 ; 1.5 ≤
w1
≤ 10
w1w2 2

= 130 log w2  - 44 pF/m

C w w
for ε r = 9.6 ; 3.5 ≤ w2 ≤ 10
w1w2  1 1

2 (2.3a)
= 40.5 w1 − 1.0  − 75 w1 + 0.2 w1 − 1.0 
L w w w
nH/m (2.3b)
d  2  2  2 
Lm1 Lm 2 Lm1 and Lm2 are the per unit length
L1 = L L2 = L
Lm1 + Lm 2 Lm1 + Lm 2 inductance of T1 and T2 respectively.
Feb 2012 Fabian Kung Wai Lee 17

Microstrip Line Discontinuity Models

(4)
T-Junction:
T1
T1 L1 L1
T2

C1
T3
T3
L3

T2
See Edwards [4], Chapter 5
for alternative model and
further details.

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Connector Discontinuity: Coaxial -

Microstrip Line Transition (1)
• Since most microstrip line invariably leads to external connection from
the printed circuit board, an interface is needed. Usually the microstrip
line is connected to a co-axial cable.
• An adapter usually used for microstrip to co-axial transistion is the SMA
to PCB adapter, also called the SMA End-launcher.

Feb 2012 Fabian Kung Wai Lee 19

Connector Discontinuity: Coaxial -

Microstrip Line Transition (2)
• Again the coaxial-to-microstrip transition is a form of discontinuity, care
must be taken to reduce the abruptness of the discontinuity. For a
properly designed transition such as shown in the previous slide, the
operating frequency could go as high as 6 GHz for the coaxial to
microstrip line transition and 9 GHz for the coaxial to co-planar line
transition.

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Effect of Discontinuities
• Looking at the equivalent circuit models for the microstrip
discontinuities, the sharp reader will immediately notice that all these
networks can be interpreted as Low-Pass Filters. The inductor
attenuates the electrical signal at high frequency while the capacitor
shunts electrical energy at high frequency.
• Thus the effect of having too many discontinuities in a high-frequency
circuit reduces the overall bandwidth of the interconnection.
• Another consequence of discontinuities is attenuation due to radiation
from the discontinuity. |H(f)|
|H(f)|

0 f
0 f

Feb 2012 Fabian Kung Wai Lee 21

Radiation Loss from Discontinuities

• At higher frequency, say > 5 GHz, the assumption of lossless
discontinuity becomes flawed. This is because the higher order mode
EM fields can induce surface wave on the printed circuit board, this
wave radiates out so energy is loss.
• Furthermore the acceleration or deceleration of electric charge also
generates radiation.
• The losses due to radiation can be included in the equivalent circuit
model for the discontinuity by adding series resistance or shunt
conductance.

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Exercise 2.1
• What do you expect the equivalent circuit of the following discontinuity
to be ?

Feb 2012 Fabian Kung Wai Lee 23

4.3 – PCB Layout Rules for

Reducing the Effect of
Discontinuity

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Reducing the Effects of Discontinuity

(1)
• To reduce the effect of discontinuity, we must reduce the values of the
associated inductance and capacitance. This can be achieved by
decreasing the abruptness of the discontinuity, so that current flow will
not be disrupted and charge will not accumulate.

NOTE:
Generally these are not needed for frequency < 300 MHz

Chamfering of bends
W 1.42W
For 90o bend:
b
It is seen that the optimum
chamfering is b=0.57W
W (see Chapter 5, Edwards [4]) W
For further examples see
Chapter 2, Bahl [7]. W

Feb 2012 Fabian Kung Wai Lee 25

Reducing the Effects of Discontinuity

(2)

Mitering of junction Mitering of step

T1

≅ 0.7W 1
T3
T1 T2
W2
W1

T2

T1 For more details of compensation for discontinuity,

please refer to Chapter 5 of Edwards [4] and
≅ 2W 2 Chapter 2 of Bahl [7].
T3 0.5W 2 or
W2 smaller
W1 NOTE:
Generally these are not needed for frequency < 300 MHz
T2
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Reducing the Effects of Discontinuity

(3)
Reduce the length
of the via by using
inner trace layer
and remove the stub
(e.g. use buried or
Side view of a Via blind via).
A tear-drop shape pad (typically only
recommended for frequency above 1 GHz).

• The extra capacitance

of the tear-drop shape
balance the effect of
the inductance associated
with the via.
• The tear-drop shape also
improves reliability of
Top view of a Via contact between trace and
pad.

Feb 2012 Fabian Kung Wai Lee 27

Handling Stubs (1)

• Stubs are short trace segment that extend from the main trace. Most
often they connect to a solder pad and a component.

Keep branching stub and unterminated

stub short, less than 0.05λ, where λ is the
shortest wavelength encountered

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Handling Stubs (2)

Add compensation to bend

if necessary

Feb 2012 Fabian Kung Wai Lee 29

Example 3.1
• A Zc = 50Ω microstrip Tline is used to drive a resistive termination as
shown.
VIAHS VIAHS VIAHS
V3 V2 V1
D=20.0 mil D=20.0 mil D=20.0 mil
MSub H=0.8 mm H=0.8 mm H=0.0 mm
T=1.0 mil T=1.0 mil T=1.0 mil
MSUB
MSub1
H=0.8 mm
Er=4.6 R
R1
Mur=1
R=100 Ohm
Cond=5.8E+7
Hu=3.9e+034 mil
T=1.38 mil
TanD=0.02
Rough=0 mil
MLIN C
TL3 C1
MSOBND_MDS Subst="MSub1" C=0.47 pF
Bend2 W=1.45 mm R
Subst="MSub1" L=15.0 mm R2
W=1.45 mm R=100 Ohm

Example of schematic with discontinuity MLIN

TL2
Subst="MSub1"
Elements (Agilent’s ADS software) W=1.45 mm
L=10.0 mm
VIAHS
V4
VIAHS
V5
VIAHS
D=20.0 mil D=20.0 mil V6
H=0.8 mm H=0.8 mm D=20.0 mil
H=0.8 mm
T=1.0 mil T=1.0 mil
L MSOBND_MDS T=1.0 mil
Port MLIN
LSMA1 Bend1
P1 TL1
L=1.2 nH Subst="MSub1"
Num=1 Subst="MSub1"
R= W=1.45 mm
W=1.45 mm
C C L=25.0 mm
CSMA1 CSMA2
C=0.33 pF C=0.33 pF

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Example 3.2 – Photomicrographs of

PCB
• Photomicrograph of microstrip line bend and step (60X).

Bend in microstrip line

Step in microstrip line

Narrower traces
graticules in mm to BGA IC package
Feb 2012 Fabian Kung Wai Lee 31

4.4 – PCB Layout Rules for

Grounding

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The Ground (GND)

• A SINGLE conductor in the PCB or system is called the Ground (GND).
• It is assumed the GND has a stable electric potential (with respect to
infinity) and this potential is uniform throughout the conductor. This can
be enforced by using a good conductor (low impedance) and limiting the
GND conductor size to as small as practical.
• All electric potential in the PCB or system is measured with respect to
GND, and we can arbitrarily assign a value of 0V to the GND potential.
• This 0V GND conductor is what we assumed when drawing schematics.

• The process of creating the GND conductor is called Grounding. An

ideal GND is just a concept, as all real conductor has finite impedance
and we cannot ensure uniform potential throughout the GND conductor
for high frequency signals.
Feb 2012 Fabian Kung Wai Lee 33

Example of Ground - Earth and Signal

Ground
• A simplified view of typical instrument powered via mains supply.
110V /240V AC
Metal Chassis
Service
Outlet Fuse I/O
Live to other
VCC hardware
Neutral
Voltage Circuit
Earth Regulator

Step-down
transformer

Earth connection Safety Ground Signal Ground

or Earth
Note that only ONE point on the
signal ground is connected to the
chassis of the instrument
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Signal Ground
• The aims of grounding are:
– To allow electric charge and current to flow from source to load and
back to the source, i.e. provide a return path.
– For low frequency circuit, to provide a stable reference potential
(0V).
– To control electromagnetic interference due to electric and magnetic
field coupling, i.e. provide reasonable isolation. We have already
seen this in action in our discussion on multiconductor transmission
line and crosstalk in Part 3. Signal
Tx Conductor A Tx/Rx System Rx

Good layout practices on the PCB

are of utmost importance in Ground
ensuring the circuit works properly.

Feb 2012 Fabian Kung Wai Lee 35

Signal Ground: Single-Point Ground

Usually a bus-bar as in
high voltage circuits
1 2 3 1 2 3
GND

Series Ground Parallel Ground

• Series Ground System Can be signal or earth ground

- Easy to implement.
- Suffers from common-impedance coupling.
• Parallel Ground System
- Less common-impedance coupling.
- Mutual coupling (inductive and capacitive) between
ground leads should be minimised.

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Signal Ground: Multi-point Ground

1 2 3

• Uses large ground plane as common ground conductor.

• Circuits that require ground connection are connected to the nearest
available ground plane.
• Also suffer from common impedance coupling but it can be reduced
by lowering the ground-impedance.
• Typically used in multilayer PCB.

Feb 2012 Fabian Kung Wai Lee 37

Grounding Consideration: Common-

Impedance Coupling (1)
• The same GND impedance is seen by all modules.

Source V1 1 2 3
Vs
I1 I2 I3
I1+I2+I3 I2+I3 I3

Zg
Inclusive of the resistance
Vs = (I1 + I 2 + I 3 )Z g + V1
and partial inductance
of the GND
⇒ V1 = Vs − (I1 + I 2 + I 3 )Z g

Voltage across module 1 is ‘modulated’ by the changes

in other modules. This effect is also known as Ground
Bounce.
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Grounding Consideration: Common-

Impedance Coupling (2)
• Common-impedance coupling can occurs on both source (i.e. the VCC)
and return path in a PCB assembly. It is more serious in system which
uses series or multi-point ground scheme.
• Common-impedance coupling can be reduced by using low impedance
source and ground path, reduce Zg and Zp (VCC path impedance), i.e.
use power plane and ground plane instead of power and ground
traces/buses.
• Segmentation of the circuits and ground planes reduces common-
impedance coupling.
• Using decoupling capacitors and RF chokes can help filter out large
voltage fluctuations seen by a component VCC and GND terminals.
NOTE: Techniques of analyzing and reducing the supply voltage fluctuation
on a component is generally called Power Integrity (PI), as opposed to Signal
Integrity which is our concern here. The physical VCC and GND paths are usually
called the Power Distribution Network (PDN).

Feb 2012 Fabian Kung Wai Lee 39

Reducing Common-Impedance Coupling

with Decoupling Capacitors
• If common-impedance coupling is mainly due to large transient/AC
current, adding decoupling capacitors on each block will helps.
• Block here can means a group of components or an integrated circuit.

Loop for AC current

Source
Vs
1 2 3
I1 I2 I3
Putting decoupling
capacitors near
each IC in
through-hole and Zg
SMD components
Decoupling capacitor, good quality capacitor
(with low ESR, ESL) placed near the module.

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Grounding Consideration: Current Return

Path (1)
• Coupling is minimised if current returns via a path as near as possible
to the incident path (to reduce the effect of stray fields).
• Current will always follows the path with least impedance, this is a
consequent of the law of physics where the energy of a system will
tend towards lowest energy state.
• At low frequency, the resistance of a path dominates the impedance,
while at high frequency, the reactance of a path dominates. This is
best summarized as follows:
– Low frequency current flows through the path with least resistance.
– High frequency current flows through the path with least
impedance.
• Current that flows on least impedance path will create less ‘fringing’ EM
fields, thus less opportunity to interfere with other circuits.
• Least impedance path usually correspond to the signal and return path
which minimizes the loop area.

Feb 2012 Fabian Kung Wai Lee 41

Grounding Consideration: Current Return

Path (2)

Low frequency content

current

Least resistance path

Minimize the area between Least impedance

signal and return path path

High frequency content

current

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Grounding Consideration: Ground Break

Ground break

Detour for return current, more magnetic flux

linkage. This will manifest as extra inductance in
the interconnect circuit.
Furthermore the E and H fields will ‘extend’ further from
the circuit, making it easier for this circuit to interfere
and be interfered.

Feb 2012 Fabian Kung Wai Lee 43

Effect of Ground Break (1)

• A break in ground plane for transmission line is not desirable, return
current will have to flow a longer distance, this manifests as extra
inductance (because of extra magnetic field generated in the vicinity of
the break). However, from measurement, it is observed that this effect is
only important for frequencies of 2 GHz and above if a,b > 3W.
• In system where a ground plane is not possible, then the use of ground
grid is encouraged. Usage of grid provides a number of return path for
the signal current, thus allowing the return current to choose the path
that is of lowest impedance.
Top Trace
Equivalent circuit due to ground break
a
Signal current

W = width of
b
transmission line Return
current

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Effect of Ground Break (2)

• Ground break also increases coupling between traces.

Ground break

Trace 1
Trace 2

EM fields due to return signal

and return current from
Trace 1 coupled to Trace 2

Feb 2012 Fabian Kung Wai Lee 45

Example 4.1
• A numerical experiment is performed using Maxwell SV software. The
figure below shows the 2D plot of the E field magnitude for 2
conductors sandwiching a FR4 substrate.
• Top conductor has 1V potential while bottom is GND at 0V.

When the conductors are

misalligned.

If another conductor is
placed here, E field
coupling would occur.

Same argument can be shown

for H field too!

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Ground Scheme 1 - Power Distribution

and Ground on Same Layer
• The power and ground wires can be considered as a signal-ground
combination. Therefore based on previous discussion on current return
path, these must be near each other.

GND
VCC GND
VCC

Feb 2012
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Good Practice 47

Ground Scheme 2 – Using Ground Grid

• Reduce ground path impedance

• Allow shorter return path.

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Ground Scheme 3 – Using Ground

Ring

Circuit module 1
GND
trace

Circuit Circuit You can use similar

module 2 module 3 scheme for the power
distribution, the VCC
bus on another layer.
Bear in mind to keep
Circuit the traces as close as
module 4 possible.

Feb 2012 Fabian Kung Wai Lee 49

Ground Scheme 4 - Ground Plane and

Segmentation for Hybrid System
Separation of ground plane allows isolation of
each module from the effect of common-impedance
coupling.

Electromechanical
Analog
+12V

+5V

Digital
Link to maintain
This is the best scheme as it allows return current to same d.c. ground
flow directly beneath the power lines. potential
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Using Ground Plane

• To reduce common impedance coupling and promote return current to
flow as near as source current, ground plane should be used wherever
possible.
• Ground plane has much lower partial self inductance and resistance as
compared to ground trace. Thus common impedance effect is vastly
reduced.
• Source and return current near each other results in small loop area,
this in turn reduces mutual inductance between different current loop.

‘Flooded’ ground on top side and ground

plane on bottom side of PCB to
ensure return current
follows the signal current
closely. A GND plane
is on the bottom to provide
further isolation.

Feb 2012 Fabian Kung Wai Lee 51

Example 4.2 - Isolating Noisy or

Critical Current
• If there are only a few traces that carry high-speed signal, we can
control the flow of the return current by removing part of the GND
conductor.

Trace

GND

Top View

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Example 4.3 – Signal Trace Crossing

Unrelated GND Plane
Possible return
current paths,
both are equally
undesirable
Analog GND
Signal Trace
plane

IC1 IC2

Digital GND
plane

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Using Multi-Layer PCB

• The advantages:
• More trace layers for routing.
• Can minimize crosstalk by having critical traces on different trace
layers isolated by conducting planes, or having the critical traces
perpendicular to each other.
• The GND and Power planes provide the return path, return current
flows near source current.
• The planes have low self impedance.
• The planes serve to isolate traces (top and bottom trace layer).
• The planes form a good decoupling capacitor.

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Some Suggestions for Layer Stacking in

Multi-layer PCB
Top signal Power plane
trace 4 Layers Board
Internal signal
Power plane trace
VCC
Dielectric Ground plane
Ground plane 6 Layers Board Use Top and Bottom
GND traces for high-speed
signals. The planes
Bottom signal
serve to isolate the
trace
high-speed traces.
GND
These form a
good decoupling GND Internal signal Use internal signal
capacitor for the trace 1
VCC trace 1 for high-speed
power supply
GND signals. These internal
Internal signal trace acts as striplines,
trace 2 with the added benefits
8 Layers Board
of very low dispersion.
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Return Current Path for Multi-Layer PCB (1)

• For a signal trace which is sandwiched by two conducting planes, the

return current exist on both planes.

Decoupling capacitor
GND
Plane

Return current
on GND plane Vcc Plane

If we use stripline configuration with

Return current VCC and GND planes, always place
on Vcc plane sufficient decoupling capacitors near
the driver to provide an AC short
between both planes.

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Return Current Path for Multi-Layer PCB (2)

• There are occasions when the return current has to switch GND
planes.
Coupling capacitor
to AC short both GND planes
GND1
Signal current

Signal
Trace

GND2

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Example 4.4 - Minimizing Noise on Sensitive

Circuits: Preventing Unwanted GND Current
• Be careful of accidental current loop due to multi-point ground
connections.
110V /240V AC Metal Chassis
Service
I/O
Outlet Fuse Live to other
VCC hardware
Neutral
Voltage Circuit
Earth Regulator

Step-down
transformer

Signal Ground
Earth connection
Ground loop: Current can be induced
Safety Ground
in this loop by external magnetic field.
or Earth
This induced current can cause fluctuation
of GND potential and stray current to flow
into the circuit (common-mode current).
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Example 4.5 - Minimizing Noise on Sensitive

Circuits: Connecting I/O Lines to Outside World
Clean interface
Ground (a separate ground plane or metal on chasis)

Suppresion/filter
components
Break in
Critical GND plane
I/O lines
Circuits

Medium critical circuits

Low impedance Single-point link, can insert

path an RF choke
Earth or
External ground

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Grounding Rules
• Identify circuits with high rate-of-change (di/dt, dv/dt, for emissions),
e.g. clocks, bus buffers/drivers and high-power oscillators.
• Identify sensitive circuits (for susceptibility), e.g. low-level analog signal
or high-speed digital data.
• Minimize ground impedance by 1) Keeping sensitive circuits away from
the edge of the PCB, 2) Minimize loop area, 3) Use ground plane.
• Ensure that internal and external ground noise cannot couple in or out
of the system, incorporate a clean interface ground.
• Segmentation of circuits and ground.
• No crossing of signal trace from one region to another.

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Other Topics of Interests in this Part

• Here are some other topics that are deemed important but are not
covered due to time constraint:
• Power supply noise filtering and decoupling.
• Simultaneous switching noise.
• Placement and selection of capacitors for decoupling.
• Decoupling performance analysis.
• Using active voltage regulator onboard PCB.

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Key Learning of Part 4

• Concept of discontinuity in interconnect.
• Equivalent electrical circuit of discontinuity.
• Effect of discontinuity on signal propagation along interconnect.
• How to compensate for the effect of discontinuity.
• Type of ground.
• Current return path – high and low-frequency condition.
• Common-impedance coupling.
• Ground break and it’s effect.
• Ground and power distribution scheme.
• Use of multi-layer PCB and conductor layers stacking.

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