The Inverter

References:
Adapted from: Digital Integrated Circuits: A Design
Perspective, J. Rabaey, Prentice Hall © UCB
Principles of CMOS VLSI Design: A Systems Perspective,
N. H. E. Weste, K. Eshraghian, Addison Wesley
 Regions of Operation

Cutoff Non-saturated
Non saturated Saturated

Vgsp < Vtp Vgsp = Vtp

Vgsp > Vtp Vin < Vtp + VDD Vin < Vtp + VDD
p-device
Vin > Vtp + VDD Vdsp > Vgsp - Vtp Vdsp < Vgsp - Vtp
Vout > Vin - Vtp Vout < Vin - Vtp

Vggsn > Vtn Vggsn > Vtn

Vgsn < Vtn Vin > Vtn Vin > Vtn
n-device
Vin < Vtn Vdsn < Vgs - Vtn Vdsn > Vgs - Vtn
Vout < Vin - Vtn Vout > Vin - Vtn
 Digital Gates
Fundamental Parameters

• Area and Complexity

• Robustness and Reliability
• Performance
• Power Consumption
 Noise in digital Integrated Circuits
unwanted variations of voltages
g and currents at the logic
g nodes

VDD
v(t)
i (t)

(a) Inductive coupling (b) Capacitive coupling (c) Power and ground noise
 DC Operation:
V lt
Voltage T
Transfer
f Characteristic
Ch t i ti (VTC)

Vout

Vout = Vin
VOH f

VM Switching Threshold Voltage

(≠ Transistor Threshold Voltage)

VOL

VOL VOH Vin

Nominal Voltage Levels

Mapping between analog and digital signals

V(y)
VOH VOH dVout
‘1’
V1H Slope = -1 = dVin (gain)
Undefined
Region
dVout
VIL Slope = -1 = dVin
‘0’
VOL
VOL
VIL VIH V(x)

Undefined Region
(Transition width TW)
Definitaion of Noise Margins

NMH = VOH -
‘1’
1 VIH

VOH
NMH VIH
Undefined
Region
NML VI
VO
L
L
‘0’
0 NML = VIL - VOL

Gate Output Gate Input

Stage M Stage M+1
 The Regenerative Property

V V V V V V V
0 1 2 3 4 5 6

A chain of inverters

V
3 0

V
1 1
V
2

-1
0 2 4 6 8 10
 Conditions for Regeneration

Vout Vout
V3 f(v) finv(v)

V1 f(V0) V1
V3
fi ( )
finv(v)
f(v)

Vin
V2 V0 Vin V0 V2
(a) Regenerative gate (b) Non-regenerative gate
Fan-in and Fan-out

( ) Fan-out
(a) F tN

N
(b) Fan-in M
 The Ideal Gate

Vout

Ri = ∞

g = -∞ Ro = 0

Vin
 VTC of Real Inverter VDD

5.0

4.0
NML
Vout(V)

3.0

20
2.0
VM
NMH
1.0

0.0 1.0 2.0 3.0 4.0 5.0

Vin (V)
 Delayy Definitions

Vin

50%

tpHL tpLH
Voutt

90%

50%

10% t

tf tr
 Ring Oscillator

V0 V1 V2 V3 V4 V5

V0 V1 V5

T = 2 x tp x N
2Ntp >> tf + tr
 Power Dissipation

P(t) = instantaneous power

Ppeak = ipeakVsupply = max (p(t))

1 T Vsup ply T
Pav =
T ∫0
p (t )dt =
T ∫
0
isup ply (t )dt

Power-Delay Product

PDP = tp x Pav

= Energy dissipated per operation

Static Load MOS Inverters
 Static Load MOS Inverters

Rload
Ibias

Vout Vout
Vin Vin
 Basic Inverter

VDD

Vout

Vin

• Vin < Vth ; NMOS off; Vout pulled to VDD

• Vin > Vth ; NMOS on, currentt flows
fl through
th h R tto
ground
• If R is sufficientlyy large,
g Vout could be p
pulled down
well below Vth;
 St ti Load
Static L d MOS IN
INverter
t

Ids R

Vout

Vout = Vds
Ids.R = VDD-Vds
VTC of Resistive Load
 Resistive Load Device

Rload Voh = 5.0V

Vol = ???
Vout
I = (Vdd-Vol)/R
Vin

I = β.((Vdd-Vt)Vol-0.5Vol2)

(Vdd − Vol )
R=
β .((Vdd − Vt )Vol − 0.5Vol 2 )
 Sizing for VOL

(Vdd − Vol )
R=
β .((Vdd − Vt )Vol − 0.5Vol )
2

Assume: Vdd = 5.0V

Vt = 1.0V
β = 10-44A/V

Proper design: Vol < Vt

Let: Vol = 0.5V

R = 24kΩ
 Resistor and Current-Source Loads

• R
Resistance/length
i t /l th off minimum-width
i i idth lilines off various
i
connecting elements is far less than effective
resistance of the switched on MOSFET
• In some memory processes, resistors are
implemented by highly resistive undoped polysilicon
• Normally
N ll use ttransistors
i t iin CMOS tto iimplement
l t
resistor and current-source loads
• If biased for use as a resistor
resistor, called an unsaturated
load inverter
• If load transistor operates in saturation as a constant
current source, called a saturated load inverter
 Pseudo NMOS Inverter

Vout Ln = 1
Vin

VDD + Vdsp = Vout

⇒ Vdsp = Vout - VDD
⇒ Vdsp = Vout + Vgsp
∴Vdsp > Vgsp - Vtp or Vout > - Vtp
⇒ Non-saturated region
DC Transfer Characteristics
 Pseudo-NMOS Inverter

Vout
Vin

• DC current flows when the inverter is turned on unlike

CMOS inverter
• CMOS is great for low power unlike this circuit (e.g.
watch needs low power lap-tops etc)
• Need to be turned off during IDDQ (VDD Supply
Current Quiescent) testing
 PMOST Load with Constant VGS
Voh = 5.0V

Vol = ???

I = 0.5βp.(Vdd-Vtp)2

Vout I = βn.((Vdd-Vtn)Vol-0.5Vol2)
Vin
βn 0.5(Vdd − Vtp ) 2

=
β p ((Vdd − Vtn )Vol − 0.5Vol 2 )
 Sizing for VOL

βn 0.5(Vdd − Vtp ) 2

=
β p ((Vdd − Vtn )Vol − 0.5Vol 2 )

Assume: Vdd = 5.0V

Vtn = Vtp = 1.0V

Proper design: Vol < Vth

Let
Let: Vol = 0.5V
0 5V

βn
= 4.266
βp
 Sizing for Gate Threshold Voltage (Trip Point)

N-device: saturated (Vout >Vin −Vtn )

βn
Idsn = (Vin −Vtn )2
2
P-device: non-saturated
Vgsp = −VDD
(Vout − VDD ) 2
I dsp = β p [(−VDD − Vtp )(Vout − VDD ) − ]
2
Equating the two currents we obtain,

βn (Vout − VDD ) 2
(Vin − Vtn ) = − β p [(−VDD − Vtp )(Vout
2
− VDD ) − ]
2 2
 Sizing for Gate Threshold Voltage

Solving for Vout

Vout = −Vtp + (VDD + Vtp ) 2 − C

Where C = k (Vin - Vtn)2

βn
k=
βp

β n (VDD + Vtpp ) − (Vout + Vtpp )

2 2
Also
Also, =
βp (Vin − Vtn ) 2

To make g
gate threshold voltage
g = 0.5VDD
βn
= 6.11
βp
 Noise Margin

βn/βp VIL VIH VOL VOH NML NMH

2 3
3.4
4 4
4.5
5 1
1.4
4 5 2
2.0
0 0
0.5
5
4 1.8 3.3 0.6 5 1.2 2.7
6 1.4 2.8 0.35 5 1.05 3.2
8 1
1.1
1 2
2.4
4 0
0.24
24 5 0
0.86
86 3
3.6
6
100 0.5 1.1 0.00 5 0.5 3.9
VTC of Pseudo-NMOS Inverter
 Unsaturated Load Inverter

Vout

Vin

• High is n threshold down from VDD

• Used when depletion mode transistors were not
available
• Low noise margin
• Might be used in I/O structures where p-transistors
p transistors
were not wanted
VTC of Unsaturated Load Inverters

For k = 4
VOL = 0.24V
VIH = 2.2V
VOH = 3.8V
3 8V
VIL = 0.56V
 Current Source Load

Ibias

Vout Vout
Vin Vin
 Saturated Load Inverter

Vout
Vin

• Vout > Vin - Vtn ⇒ driver transistor in saturation

– When Vin is small
• Load transistor permanently in saturation
– Vdsp = Vgsp
– ∴Vdsp < Vgsp - Vtp or 0 < - Vtp ⇒ Saturated region
 When Vin is Small
β driver
I ds ,driver = (V in − V tn ) 2
2

Load in saturation:
β load
I ds ,load = − (V out − V DD − Vtp ) 2
2

Equating the currents:

Vout = VDD + Vtp + k (Vin − Vtn )

β driven
where k =
β load
VTC of Saturated Load Inverter

For k = 4
VOL = 0.24V
VIH = 2.1V
VOH = 44.4V
4V
VIL = 0.5V
 NMOS Inverter
Use depletion mode transistor as pull-up

Vtdep transistor is < 0 V

diffusion

VDD

(poly)
depletion mode transistor

Vout
Vin enhancement mode out
transistor
in

The depletion mode transistor is always ON:

gate and source connected ⇒ Vgs = 0

Vin = 0 ⇒ transistor pull down is off ⇒ Vout is high

 Vout vs Vin using Graphical Method
Ids (dep)
Ids (enh)

Vgs = 0.0
00
Vgs = -0.2 VDD

Vds (dep) VDD

Ids Ids
Ids
Vgs (dep) = 0

Vgs (dep)
VDD
Vds (dep) VDD - Vds (dep)

Vds (enh) = VDD - Vds (dep)

Vds (enh) = Vout
VDD -Vds(dep) = Vds(enh) = Vout Therefore Vout = VDD - Vds (dep)
In a steady state,
Ids of both transistors are equal
 Gate Threshold Voltage
Gate threshold voltage = Vinv
= Input voltage at which Vin = Vout
Assume that both driver and load are in saturation with input Vinv
β driver
I DS ( sat ) = (Vgs − Vt ) 2
2
β driver β load
∴ (Vinv − Vt ) = 2
(−Vdep ) 2
2 2 VDD

β load
Hence, Vinv = Vt − Vdep
β driver Vout
Vin

If βdriver is increased relative to βload then,

Vinv decreases
VTC of NMOS inverter

Sl
Slope |G| iincreases, Vinv decreases
d

increasing
β driver
β load
CMOS INVERTER
CMOS Inverters
The CMOS Inverter: A First Glance
VD
D
S

Vin
D Vout
CL

S
 Switch Model of MOS Transistor

| VGS
|

| VGS | < | VT | | VGS | > | VT |

CMOS Inverter: Steady State Response
VDD VDD

Ron VOH = VDD

VOL = 0
Vout

VM = f(Ronn, Ronp)

Vin = VDD Vin = 0

 PMOS Load Lines
Vin = VDD - VGSp
IDn
Idn = -IDP
Vout = VDD-V
VDSp

Vout
IDp IDn IDn
Vin = 0 Vin = 0

Vin = 3 Vin = 3

VDSp VDSp Vout

VGSp = -2

VGSp = -5 Vin = VDD + VGSp Vout = VDD - VDSp

IDn = - IDp
 Construction Of Inverter Curves

Ids

Vds
 Construction Of Inverter Curves

Ids

Vds
 Construction Of Inverter Curves

Ids

Vds
 CMOS Inverter Load Characteristics
In,p
Vin = 5
Vin = 0

PMOS NMOS

Vin = 1 Vin = 4

Vin = 3
Vin = 2 Vin = 3
Vin = 2
Vin = 4
Vin = 3 Vin = 2 Vin = 1
Vin = 5
Vin = 0
CMOS Inverter VTC

5.0
Vout
0.0
0.0 Vin 5.0
 Inverter Supply Current

Idnn=Idp=Isuppply
 Small Signal Model for an MOS Transistor

• Vsb = 0
• voltage-controlled current source (gm)
• output conductance (gds)
• interelectrode capacitance
D
Cgd
G

Cgs + Cgb gmVgs gds Cdb

S
 Output Conductance
• By differentiating Ids w.r.t. Vds
• In linear region 2
Vds
I ds = β [(Vgs − Vt )Vds − ]
2
1
g ds = β [(Vgs − Vt ) − Vds ] Rlinear =
β (Vgs − Vt − Vds )
• In saturation, device behaves like a current source:
the current being almost independent of Vdsd
β
I ds = [ (Vgs − Vt ) 2 ]
2
β
d[ (Vgs − Vt ) 2 ]
dI ds 2
= =0
dVds dVds
• In
I reality,
lit secondary
d effects
ff t resultlt in
i a slope
l
g ds = I ds λ
 Transconductance

• Expresses relationship between output current and

input voltage
dI ds
gm = | Vds = constant
dVgs
g m (linear
li ) = βVds
g m ( sat.) = β (Vgs − Vt )
 MOS Transistor Small Signal Model

G
+ gmvgs
vgs r0
-

gm ro
Linear kVDS [k(VGS-VT-VDS)]-1

Saturation k(V
( GS-VT) 1/λID
 CMOS Inverter
VDD
s
Vout = VDD - Vsdp
= VDD + Vdsp
d Vin = VDD - Vsgp
d = VDD + Vgsp

Vin Vout

Vin = Vgsn, Vout = Vdsn

 Regions of Operation

Cutoff Non-saturated
Non saturated Saturated

Vgsp < Vtp Vgsp = Vtp

Vgsp > Vtp Vin < Vtp + VDD Vin < Vtp + VDD
p-device
Vin > Vtp + VDD Vdsp > Vgsp - Vtp Vdsp < Vgsp - Vtp
Vout > Vin - Vtp Vout < Vin - Vtp

Vggsn > Vtn Vggsn > Vtn

Vgsn < Vtn Vin > Vtn Vin > Vtn
n-device
Vin < Vtn Vdsn < Vgs - Vtn Vdsn > Vgs - Vtn
Vout < Vin - Vtn Vout > Vin - Vtn
 Inverter Operating Regions

5.0
A: nmost off
pmost linear reg.

B: nmost saturated
pmostt linear
li reg.

C: nmost saturated

Vout
pmost saturated

D: nmost linear reg.

0.0 pmost saturated

E: nmost linear reg.

0.0 Vin
i
5.0 pmost off
p
 Inverter Operating Regions

A: nmost off
pmost linear region

B: nmost saturated
pmostt linear
li region
i out out out out outt

C: nmost saturated
pmost saturated

D: nmost linear region A B C D E

pmost saturated
Assume infinite ro
E: nmost linear region when a device is in saturation
pmost off
p
 Region A
(0 ≤ Vin ≤ Vtn)

Idsn = 0 ⇒ n-device is cut-off VDD

p-device
p device in linear region

Idsn = - Idsp = 0, as Idsn = 0

Vin Vout
Vdsp = Vout - VDD

With Vdsp = 0, Vout = VDD

 Region B
VDD
(Vtn ≤ Vin ≤ )
2

p-device in non-saturated region (Vds ≠ 0)

n-device is in saturation

Idsp
Vin = Vgsn

Vout
Idsn
 Region B

[Vin − Vtn ]2 με W
I dsn = βn ;β = n ( n )
2 tox Ln
Vgsp = (Vin - VDD) & Vdsp = (Vout - VDD)

(Vout − VDD ) 2
∴ I dsp = − β p [(Vin − VDD − Vtp )(Vout − VDD ) − ]
2
μ pt W p
βp = ( )
tox Lp

Equating Idsp = -Idsn

VDD β
Vout = (Vin − Vtp ) + (Vin − Vtp ) 2 − 2(Vin − − Vtp )VDD − n (Vi n − Vtc ) 2
2 βp
 Region D
VDD
( < Vin ≤ VDD − Vtp )
2

p : saturation
n : non-saturated Idsp

1
I dsp = − β p (Vin − VDD − Vtp ) 2 Idsn
2 Vout
2
Vout
I dsn = β n [(Vin − Vtn )Vout − ]
2
I dsp = − I dsn
βp
∴Vout = (V in−Vtn ) − (Vin − Vtn ) − 2
(Vin − VDD − Vtp ) 2
βn
Determining VIH and VIL
 R i E
Region
(Vin >= VDD - Vtp)

p: cut-off Idsp = 0
n: linear
li moded

Vgsp = Vin - VDD → more p

positive than Vtp

Vout = 0
 Region C
(B th devices
(Both d i iin S
Saturation)
t ti )

βp
I dsp = − (Vin − VDD − Vtp ) 2
2
βn
I dsn = (Vin − Vtn ) 2
2
E
Equating
ti Idsp = -IIdsn

βn
VDD + Vtp + Vtn
βp
Vin =
βn
1+
βp
 Gate Threshold Voltage
If βn = βp & Vtn = -Vtp

VDD
Vin =
2
Region
g C exists for one value of Vin

Possible values of Vout in region C

n-channel Vin - Vout < Vtn

Vout > Vin - Vtn saturation conditions
p-channel Vin - Vout > Vtp
Vout < Vin - Vtp

Vin - Vtn < Vout < Vin - Vtp

In reality, region C has a finite slope

- because in reality Ids increases slightly with Vds in saturation
Typical Parameter Values (1μm process)
μ n = 500cm 2 / V − sec
ε = 3.9 × 8.85 × 10 −14 F / cm
tox = 200A
με W
βn = ( )
tox L
500 × 3.9 × 8.85 ×10 −14 W
=
.2 ×10 −5 L
W
= 88.5 μA / V 2
L
μ p ≈ 180cm 2 / V − sec
W
∴ β p = 31.9 μA / V 2
L
βn
= 2.8 (The ratio varies from 2-3)
βp
 βn/β
βp Ratio

βn
increasing
g β
Vout p

Vin

Wn
increasing W p
Vout

Vin
 Effect of βn/β
βp Ratio
βn
Vm dependent on βp
βn
with change in β p transition still remains sharp and hence
switching performance does not deteriorate
It is desirable to have
βn
=1
βp
⇒ allows capacitance load to change and discharge in equal
times by providing equal current source & sink capability
 Gate Switching Threshold

4.0

3.0
VM

2.0

1.00.1 0.3 1.0 3.2 10.0 βp

kp/kn βn
r (VDD + Vtp ) + Vtn βp
VM = with r =
r +1 βn
 Effect of Temperature
p

• Temperature similarly affects mobility of holes and

electrons
l t
• Temperature increases ⇒ μ decreases ⇒ β
decreases
β ∝ T −1.5
• Ratio βn/βp is independent of temperature to a good
approximation
• Temperature, however, reduces threshold voltages
• Extent of region A reduces and extent of region E
increases
• VTC shifts to the left as the temperature increases
 Switching Characteristics

• Switching speed - limited by time taken to charge and

discharge, CL
• Rise
Ri titime, tr : waveform
f to
t rise
i from
f 10% tto 90% off itits
steady state value
• Fall time, tf : 90% to 10% of steady state value
• Delay time, td : time difference between input
transition (50%) and 50% output level
 CMOS Inverter: Transient Response
p

VDD
tpHL = f(RonCL)
= 0.69 RonCL

Vout

1 VDD
CL
Ron
0.5
0.36

Vin = VDD RonCL t

 CMOS
C OS Inverter
e te Propagation
opagat o Delay
e ay

VDD
C LVswing /2
t pHL =
i

I av

Vout I (Vout = VDD ) + I (Vout = VDD / 2)

I av =
2
CL
Iav β n ⎛ 7VDD
2
Vtn2 3VDDVtn ⎞
= ⎜⎜ + − ⎟⎟
2 ⎝ 8 2 2 ⎠

Vin = VDD
 Inverter Propagation Delay

• Assume n-device still in saturation at Vout = VDD/2

βn
I av = (VDD − Vtn ) 2
2
C LVDD
t pHL =
β n (VDD − Vtn ) 2
CL
≈
β nVDD
CL
t pLH ≈
β pVDD
LH

C ⎛ 1 1 ⎞
tp ≈ L ⎜ + ⎟
⎜β ⎟
2VDD ⎝ p βn ⎠
 Analysis of Fall Time

VDD
Vin(t) Vout(t)

CL

non-saturated x2
2
saturated
Ids (Vds = Vgs - Vt)

Application of step
x1 input
x3 Vout (t) VDD
 Components of Fall Time

tf = tf1 + tf2 Vout drops from Vdd - Vt to 0.1 VDD

Vout drops from 0.9Vdd to Vdd - Vt

0.9 VDD
VDD - Vt
0.1 VDD

Vin Vout
tf
 Fall Time for Saturated Region

P
Ic
Saturated, Vout ≥ VDD - Vtn Input rising
Vout
Idsn
dVout β n n CL
CL + (VDD − Vtn ) 2 = 0
dt 2
Integrating from t = t1 (corresponding to Vout = 0.9 VDD) to t = t2
(
(corresponding
di tto Vout = (VDD - Vtn))

CL 0.9VDD
tf1 = 2
β n (VDD − Vtn ) 2 ∫
VDD −Vtn
dVout

2C L (Vtn − 0.1VDD )
=
β n (VDD − Vtn ) 2
 Fall Time for Non-Saturated Region

p
Vout

n CL

Non-saturated : 0 ≤ Vout ≤ VDD - Vtn

dVout V 2 out
CL + β n [(VDD − Vtn ).Vout − ]=0
dt 2
CL 0.1VDD dVout
β n (VDD − Vtn ) ∫VDD −Vtn
tf2 =
V 2 out
− Voutt
2(VDD − Vtn )
Fall Time for Non-Saturated Region

CL 0.1VDD dVout
β n (VDD − Vtn ) ∫V
tf2 =
DD −Vtn V 2 out
− Vout
2(VDD − Vtn )
CL 19VDD − 20Vtn
= ln( )
β n (VDD − Vtn ) VDD
CL
= ln(19 − 20n)
β nVDD (1 − n)

Vtn
where n =
VDD
 Fall Time Computation

tf = tf1 + tf 2
CL ⎡ (n − 0.1) 1 ⎤
=2 ⎢ + ln(19 − 20n)⎥
β nVDD (1 − n) ⎣ (1 − n) 2 ⎦

CL
tf ≈ k
β nVDD

k = 3 ~ 4 for
f VDD = 3 ~ 5V andd Vtn = 0.5 ~ 1V
 Rise Time

CL ⎡ ( p − 0.1) 1 ⎤
tr = 2 ⎢ + ln(19 − 20 p )⎥
β pVDD (1 − p) ⎣ (1 − p) 2 ⎦
| Vtp |
with p =
VDD
CL
tr ≈ k
β pVDD
For equally sized n- and p transistors
βn ≈ 2βp

tr
tf ≈
2
 Sizing
g for Identical Rise/Fall Time

For same tf and tr

βn
=1
βp

Increase the width of p-device to

W p ≈ 2 − 3Wn
 Delay Time: First Order Approximation

• Gate delay is dominated by the output rise and fall

time
tr
t dr =
2
tf
t dff =
2
 General Delay Time Computation
• Similar to the computation of rise/fall times
– Saturation region from t = t1 (corresponding to Vout = VDD) to t
= t2 (corresponding to Vout = (VDD - Vtn))
– Linear region from t = t2 (corresponding to Vout = (VDD - Vtn))
to t = t3

CL VDD
t 2 − t1 = 2
β n (VDD − Vtn ) 2 ∫
VDD −Vtn
dVout

2C L (Vtn )
=
β n (VDD − Vtn ) 2
 Delay Time Computation

'
CL Vout dVout
β n (VDD − Vtn ) ∫V
t3 − t 2 = '2
DD −Vtn Vout
− Vout
'

2(VDD − Vtn )

CL 2VDD − 2Vtn − Vout

= ln( )
β n (VDD − Vtn ) Vout
CL 2(1 − n) − VO
= ln( )
β nVDD (1 − n) VO
Vtn Vout
where n= , VO =
VDD VDD
 Delay Time

CL
t Dn = t3 − t1 = An
β nVDD

Delay ∝ CL (optimize CL to decrease delay)

1
∝ (decrease VDD increases delay)
VDD
1
∝ (if W ↑ or L ↓,
↓ delay decreases)
β
Three major parameters for optimizing speed of CMOS
Components of CL

Cw = wiring capacitance

Cg = gate capacitance = CoxWL

 Miller Effect

• Effective voltage change over the gate-drain

capacitor is actually twice the output voltage swing
• Contribution of gate-drain capacitor should be
counted twice
 Junction Capacitance
p

• Non-linear capacitor modeled by linear capacitor with

the same change in charge for the voltage range of
interest
Ceq = K eq C j 0
− φ0m
K eq =
(Vhigh − Vlow )(1 − m)
[
(φ0 − Vhigh )1− m − (φ0 − Vlow )1− m ]
• Linearize over the interval {5V, 2.5V} for the high-to-
low transition and {0, 2.5V} for the low-to-high
low to high
transition
• Correspond to {Vhigh=-5V, Vlow=-2.5V} and {Vhigh=0,
Vlow=-2.5V}
2 5V} ffor NMOS
Delay in function of VDD
 Sizing
S goof Inverter
e te Loaded
oaded by a
an Identical
de t ca Gate

Load cap.
p of first g
gate:
CL = (Cdp1 + Cdn1) + (Cgp2 + Cgn2) + CW
where
p , Cdn1 → diffusion capacitance of first gate
Cdp1
Cgp2, Cgn2 → gate capacitance of second gate
Cw → wiring capacitance

If PMOS devices
d i are α times
ti llarger th
than th
the NMOS ones,
(W / L) p
α= (W / L) n
all transistor capacitances will scale in approximately the same way
 Sizing of Inverter
Cdp1 ≈ αCdn1
C gp 2 ≈ αC gn 2
∴ C L = (1 + α )(Cdn1 + C gn 2 ) +Cw
tr + t f C L An Ap
tp = = ( + )
2 2VDD β n β p
CL Ap β n
= ( An + )
2VDD .β n βp
CL Ap μ n (W / L) n
= ( An + . )
2VDD .β n μ p (W / L) p
CL Ap μ n
= ( An + )
2VDD .β n μ pα
 Sizing of Inverter
CL Ap μ n
tp = ( An + )
2VDD .β n μ pα
(1 + α )(Cdn1 + C gn 2 ) + CW Ap μ n
= ( An + )
2VDD .β n μ p .α
∂t p
Let = 0 to get optimal α
∂α
μ n Ap CW
α opt = (1 + )
μ p An Cdn1 +C gn 2

If CW << Cdn1 + Cgn2, Ap = An

μn
α opt ≈ ≈ 1.73 Contrast
C t t to
t 3 which
hi h iis normally
ll used
d
μp in the non-cascaded case
Impact of Rise Time on Delay

t PHL (actual ) = t 2 pHL ( step) +(t r / 2) 2

Minimum-size inverter with fanout of a single gate

 Velocity Saturation
• Under long channel model, saturation current ∝ VDD2
• In small-geometry devices, this no longer holds: Iav ∝ VDD
• Therefore, for VDD >> VT we have,
CL 1 1
tp ≈ ( + ) k n , p = κvSAT CoxWn , p
2 k p kn
• Running velocity saturated devices
at high VDD is not beneficial
f
• Lowering VDD below 2VT sharply
increases delay
 Source/Drain Resistance

• In small-geometry devices, source and drain

resistance affects switching currents
– Source of the transistor is no longer grounded
grounded, body effect
increases threshold voltage
– Vgs is also reduced
– Current is reduced
 Power Consumption

• Static Power
– Leakage current
– Sub-threshold
Sub threshold conductance
• Dynamic Power
– Capacitive
p Power due to charging/discharging
g g g g of capacitive
p
load
– Short-circuit power due to direct path currents when there is
a temporary
p y connection between p power and gground
 Static Power Consumption

VDD VDD

Vout = VDD

Diode leakage
I O = is ( e Vq / kT
− 1)
Sub-threshold current
(V gs −Vt ) q / nkT
ID = K ⋅e (1 − e
kT Vds q / kT
)

Pstatic = Ileakage. VDD

 Static Consumption
p
• Leakage current through the reverse biased diode
junctions
• For typical devices it is between 0.1nA - 0.5nA at
room temperature
• For a die with 1 million devices operated at 5 V
V, this
results in 0.5mW power consumption → not much
• Junction leakage
g current is caused by y thermally
y
generated carriers -> therefore is a strong function of
temperature
• More
M i
important
t t is
i sub-threshold
b th h ld lleakage
k when
h
threshold voltage is close to 0
 Dynamic Consumption due to CL

VDD

Vout

- low-to-high
l hi h transition
ii
- Assume 0 rise and fall times
 Dynamic Power due to CL

Vout

VDD

t
in
iVDD
CL

t
discharge
charge

Define:
EVDD : energy taken
t k from
f supplyl during
d i a ttransition
iti
EC: energy stored on capacitor at the end of transition
 Energy Consumed and Stored
∞ ∞ dVout
EVDD = ∫ iVDD (t )VDD dt = VDD ∫ CL .dt
0 0 dt
VDD
= C LVDD ∫ dVout
0

= C LVDD (= QVDD )
2

∞ ∞ dVout
EC = ∫ iVDD (t )Vout dt = ∫ CL Vout dt
0 0 dt
VDD
= C LVDD ∫ Vout dVout
0
2
C L .VDD
=
2
Half the energy is stored in Capacitor ! Other half is dissipated in
the PMOS transistor !!
For each switching cycle ( L → H & H → L), amount of energy
dissipated in CL. VDD2
 Pdynamic = CL.VDD2.f

• Example
– 1.2μ CMOS chip
– 100 MHz clock rate
– Average load capacitance of 30 fF/gate
– 5V power supply
• Power consumption/gate = 75 μW
• Design with 200,000 gates: 15W !
• Pessimistic evaluation: not all gates switch at the full rate
• H
Have tto consider
id the
th activity t α: Effective
ti it ffactor Eff ti switching
it hi
capacitance = αCL
• Reducing VDD has a quadratic effect on Pdynamic
 Direct Path Current

• inputs have finite rise and fall times

• Direct current path from VDD to GND while PMOS and
NMOS are ON simultaneously for a short period
Psc = Imean.VDD

tr tf
VDD + Vtp

Vtn

Imax
Imean
t1 t2 t3
 Symmetrical Inverter Without Load

⎡1 t2 1 t3 ⎤
I mean = 2⎢
⎣T
∫
t1
I (t )dt + ∫ I (t )dt ⎥
T t2 ⎦
If Vtn = -Vtp=VT and βn = βp = β
and that the behavior around t2 is symmetrical
2 t2 β
I mean = 2× ∫ (Vin (t ) − Vt ) 2 dt
T t1 2
VDD
with Vin (t ) = t
tr
Vt
t1 = .t r
VDD
tr
t2 =
2
t r = t f = t rf
Symmetrical Inverter Without Load
2β t rf / 2 VDD
= ∫trf VT /VDD trf ⋅ − 2
I mean ( t Vt dt
)
T
t rf / 2
2β ⎡ t rf VDD ⎤
= ⎢ ( ⋅ t − Vt ) ⎥
3

T ⎢⎣ 3VDD t rf ⎥⎦ trf VT / VDD

2t rf β VDD
= ⋅ ( − Vt ) 3
3T VDD 2
t rf β
= ⋅ (VDD − 2Vt ) 3
12T VDD

β t
Psc = (VDD − 2Vt ) 3 rf

12 T
Short Circuit Current with Loads
Output Transitions under Different Loads
CL Power vs. SC Power under Different Loads
CL Power vs. SC Power under Different Inputs
 Impact
p of Load Capacitance
p on SC Current

• Large capacitance
– Fast input transition, slow output transition
– Input moves through the transient region before output
begins
g to changeg
– Short-circuit current close to zero
• Small capacitance
– Relatively slower input transition, fast output transition
– Both devices in saturation during most of the transition
– Maximum short-circuit current
• [Veendrick84]: rise/fall times of all signals should be
kept constant within a range to keep SC power
minimal 10%~20% of total dynamic power
minimal,
Technology Evolution
Technology Scaling (1)

Minimum Feature Size

 Technology Scaling

108

107
mosfet
106
bipolar
onents/Chip
p

105
transistor
104
mesfet
Compo

103
enhancement
102 mosfet
bipolar
Transistor
101 IC

1
1950 1960 1970 1980 1990
YEAR
Number of components per chip
 Propagation
p g Delay
y Scaling
g

1n
F/O = 1
R.T. Operation
500p
e)
Gatte Delay: τDDd(sec/stage

Ref.[4]
200p 3.5V

Ref.[5]
100p 3.5V
Present Results
2.5V 3.3V Reported Results
50p Ref.[7]
2.5V

VDD VDD=5V
20p Scaling

10p
05
0.5 10
1.0 50
5.0 10 0
10.0
0.1
Channel Length : Left (μm)
 Technology Scaling Models

• Full Scaling (Constant Electrical Field)

ideal model — dimensions and voltage scale
together by the same factor S

• Fixed Voltage Scaling

most common model until recently —
only dimensions scale, voltages remain constant

• General Scaling
most realistic for todays situation —
voltages and dimensions scale with different factors
Scaling Relationships for Long channel Devices
Scaling of Short Channel Devices
 Homework Problem (due next Thursday)

• Design a static CMOS inverter with 0.4pF load capacitance. Make sure
that you have equal rise and fall times. Layout the inverter using the
Mentor tools, extract parasitics, and simulate the extracted circuit on
HSPICE tto makek sure th
thatt your d
design
i conforms
f tto th
the specification.
ifi ti
• Do the same analysis for a three input NAND gate.