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DS003-1 (v2.5 ) April 2, 2001 0 3 Product Specification

Features
• Fast, high-density Field-Programmable Gate Arrays • Supported by FPGA Foundation™ and Alliance
- Densities from 50k to 1M system gates Development Systems
- System performance up to 200 MHz - Complete support for Unified Libraries, Relationally
- 66-MHz PCI Compliant Placed Macros, and Design Manager
- Hot-swappable for Compact PCI - Wide selection of PC and workstation platforms
• Multi-standard SelectIO™ interfaces • SRAM-based in-system configuration
- 16 high-performance interface standards - Unlimited re-programmability
- Connects directly to ZBTRAM devices - Four programming modes
• Built-in clock-management circuitry • 0.22 mm 5-layer metal process
- Four dedicated delay-locked loops (DLLs) for • 100% factory tested
advanced clock control
- Four primary low-skew global clock distribution Description
nets, plus 24 secondary local clock nets The Virtex FPGA family delivers high-performance,
• Hierarchical memory system high-capacity programmable logic solutions. Dramatic
- LUTs configurable as 16-bit RAM, 32-bit RAM, increases in silicon efficiency result from optimizing the new
16-bit dual-ported RAM, or 16-bit Shift Register architecture for place-and-route efficiency and exploiting an
- Configurable synchronous dual-ported 4k-bit aggressive 5-layer-metal 0.22 mm CMOS process. These
RAMs advances make Virtex FPGAs powerful and flexible alterna-
- Fast interfaces to external high-performance RAMs tives to mask-programmed gate arrays. The Virtex family
• Flexible architecture that balances speed and density comprises the nine members shown in Table 1.
- Dedicated carry logic for high-speed arithmetic Building on experience gained from previous generations of
- Dedicated multiplier support FPGAs, the Virtex family represents a revolutionary step
- Cascade chain for wide-input functions forward in programmable logic design. Combining a wide
- Abundant registers/latches with clock enable, and variety of programmable system features, a rich hierarchy of
dual synchronous/asynchronous set and reset fast, flexible interconnect resources, and advanced process
- Internal 3-state bussing technology, the Virtex family delivers a high-speed and
- IEEE 1149.1 boundary-scan logic high-capacity programmable logic solution that enhances
design flexibility while reducing time-to-market.
- Die-temperature sensor diode

Table 1: Virtex Field-Programmable Gate Array Family Members

Maximum Block RAM Maximum
Device System Gates CLB Array Logic Cells Available I/O Bits SelectRAM+™ Bits
XCV50 57,906 16x24 1,728 180 32,768 24,576
XCV100 108,904 20x30 2,700 180 40,960 38,400
XCV150 164,674 24x36 3,888 260 49,152 55,296
XCV200 236,666 28x42 5,292 284 57,344 75,264
XCV300 322,970 32x48 6,912 316 65,536 98,304
XCV400 468,252 40x60 10,800 404 81,920 153,600
XCV600 661,111 48x72 15,552 512 98,304 221,184
XCV800 888,439 56x84 21,168 512 114,688 301,056
XCV1000 1,124,022 64x96 27,648 512 131,072 393,216

© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

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Virtex™ 2.5 V Field Programmable Gate Arrays

Virtex Architecture Xilinx thoroughly benchmarked the Virtex family. While per-
formance is design-dependent, many designs operated
Virtex devices feature a flexible, regular architecture that
internally at speeds in excess of 100 MHz and can achieve
comprises an array of configurable logic blocks (CLBs) sur-
200 MHz. Table 2 shows performance data for representa-
rounded by programmable input/output blocks (IOBs), all
tive circuits, using worst-case timing parameters.
interconnected by a rich hierarchy of fast, versatile routing
resources. The abundance of routing resources permits the Table 2: Performance for Common Circuit Functions
Virtex family to accommodate even the largest and most
complex designs. Function Bits Virtex -6

Virtex FPGAs are SRAM-based, and are customized by Register-to-Register

loading configuration data into internal memory cells. In 16 5.0 ns
some modes, the FPGA reads its own configuration data Adder
from an external PROM (master serial mode). Otherwise, 64 7.2 ns
the configuration data is written into the FPGA (Select- Pipelined Multiplier 8x8 5.1 ns
MAP™, slave serial, and JTAG modes).
16 x 16 6.0 ns
The standard Xilinx Foundation™ and Alliance Series™
Development systems deliver complete design support for Address Decoder 16 4.4 ns
Virtex, covering every aspect from behavioral and sche- 64 6.4 ns
matic entry, through simulation, automatic design transla-
16:1 Multiplexer 5.4 ns
tion and implementation, to the creation, downloading, and
readback of a configuration bit stream. Parity Tree 9 4.1 ns
18 5.0 ns
Higher Performance
36 6.9 ns
Virtex devices provide better performance than previous
generations of FPGA. Designs can achieve synchronous Chip-to-Chip
system clock rates up to 200 MHz including I/O. Virtex HSTL Class IV 200 MHz
inputs and outputs comply fully with PCI specifications, and
interfaces can be implemented that operate at 33 MHz or 66 LVTTL,16mA, fast slew 180 MHz
MHz. Additionally, Virtex supports the hot-swapping
requirements of Compact PCI.

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Virtex Device/Package Combinations and Maximum I/O

Table 3: Virtex Family Maximum User I/O by Device/Package (Excluding Dedicated Clock Pins)
Package XCV50 XCV100 XCV150 XCV200 XCV300 XCV400 XCV600 XCV800 XCV1000
CS144 94 94
TQ144 98 98
PQ240 166 166 166 166 166
HQ240 166 166 166
BG256 180 180 180 180
BG352 260 260 260
BG432 316 316 316 316
BG560 404 404 404 404
FG256 176 176 176 176
FG456 260 284 312
FG676 404 444 444
FG680 512 512 512

Virtex Ordering Information

Example: XCV300 -6 PQ 240 C

Device Type Temperature Range
C = Commercial (TJ = 0°C to +85°C)
I = Industrial (TJ = –40°C to +100°C)
Speed Grade
-4
Number of Pins
-5
-6 Package Type
BG = Ball Grid Array
FG = Fine-pitch Ball Grid Array
PQ = Plastic Quad Flat Pack
HQ = High Heat Dissipation QFP
TQ = Thin Quad Flat Pack
CS = Chip-scale Package

Figure 1: Virtex Ordering Information

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Revision History

Date Version Revision

11/98 1.0 Initial Xilinx release.
01/99 1.2 Updated package drawings and specs.
02/99 1.3 Update of package drawings, updated specifications.
05/99 1.4 Addition of package drawings and specifications.
05/99 1.5 Replaced FG 676 & FG680 package drawings.
07/99 1.6 Changed Boundary Scan Information and changed Figure 11, Boundary Scan Bit
Sequence. Updated IOB Input & Output delays. Added Capacitance info for different I/O
Standards. Added 5 V tolerant information. Added DLL Parameters and waveforms and
new Pin-to-pin Input and Output Parameter tables for Global Clock Input to Output and
Setup and Hold. Changed Configuration Information including Figures 12, 14, 17 & 19.
Added device-dependent listings for quiescent currents ICCINTQ and ICCOQ. Updated
IOB Input and Output Delays based on default standard of LVTTL, 12 mA, Fast Slew Rate.
Added IOB Input Switching Characteristics Standard Adjustments.
09/99 1.7 Speed grade update to preliminary status, Power-on specification and Clock-to-Out
Minimums additions, “0” hold time listing explanation, quiescent current listing update, and
Figure 6 ADDRA input label correction. Added TIJITCC parameter, changed TOJIT to
TOPHASE.
01/00 1.8 Update to speed.txt file 1.96. Corrections for CRs 111036,111137, 112697, 115479,
117153, 117154, and 117612. Modified notes for Recommended Operating Conditions
(voltage and temperature). Changed Bank information for VCCO in CS144 package on p.43.
01/00 1.9 Updated DLL Jitter Parameter table and waveforms, added Delay Measurement
Methodology table for different I/O standards, changed buffered Hex line info and
Input/Output Timing measurement notes.
03/00 2.0 New TBCKO values; corrected FG680 package connection drawing; new note about status
of CCLK pin after configuration.
05/00 2.1 Modified “Pins not listed ...” statement. Speed grade update to Final status.
05/00 2.2 Modified Table 18.
09/00 2.3 • Added XCV400 values to table under Minimum Clock-to-Out for Virtex Devices.
• Corrected Units column in table under IOB Input Switching Characteristics.
• Added values to table under CLB SelectRAM Switching Characteristics.
10/00 2.4 • Corrected Pinout information for devices in the BG256, BG432, and BG560 packages in
Table 18.
• Corrected BG256 Pin Function Diagram.
04/01 2.5 • Revised minimums for Global Clock Set-Up and Hold for LVTTL Standard, with DLL.
• Converted file to modularized format. See Virtex Data Sheet section.

Virtex Data Sheet

The Virtex Data Sheet contains the following modules:
• DS003-1, Virtex 2.5V FPGAs: • DS003-3, Virtex 2.5V FPGAs:
Introduction and Ordering Information (Module 1) DC and Switching Characteristics (Module 3)
• DS003-2, Virtex 2.5V FPGAs: • DS003-4, Virtex 2.5V FPGAs:
Functional Description (Module 2) Pinout Tables (Module 4)

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DS003-2 (v2.6) July 19, 2001 0 3 Product Specification

Architectural Description The output buffer and all of the IOB control signals have
independent polarity controls.
Virtex Array
The Virtex user-programmable gate array, shown in
Figure 1, comprises two major configurable elements: con- DLL IOBs DLL
figurable logic blocks (CLBs) and input/output blocks VersaRing
(IOBs).
• CLBs provide the functional elements for constructing
logic
• IOBs provide the interface between the package pins

VersaRing

VersaRing
and the CLBs

BRAMs

BRAMs

IOBs
IOBs
CLBs interconnect through a general routing matrix (GRM). CLBs
The GRM comprises an array of routing switches located at
the intersections of horizontal and vertical routing channels.
Each CLB nests into a VersaBlock™ that also provides local
routing resources to connect the CLB to the GRM.
The VersaRing™ I/O interface provides additional routing
resources around the periphery of the device. This routing VersaRing
improves I/O routability and facilitates pin locking.
IOBs
The Virtex architecture also includes the following circuits DLL DLL
that connect to the GRM.
vao_b.eps
• Dedicated block memories of 4096 bits each
• Clock DLLs for clock-distribution delay compensation Figure 1: Virtex Architecture Overview
and clock domain control
• 3-State buffers (BUFTs) associated with each CLB that All pads are protected against damage from electrostatic
drive dedicated segmentable horizontal routing discharge (ESD) and from over-voltage transients. Two
resources forms of over-voltage protection are provided, one that per-
Values stored in static memory cells control the configurable mits 5 V compliance, and one that does not. For 5 V compli-
logic elements and interconnect resources. These values ance, a Zener-like structure connected to ground turns on
load into the memory cells on power-up, and can reload if when the output rises to approximately 6.5 V. When PCI
necessary to change the function of the device. 3.3 V compliance is required, a conventional clamp diode is
connected to the output supply voltage, VCCO.
Input/Output Block Optional pull-up and pull-down resistors and an optional
The Virtex IOB, Figure 2, features SelectIO™ inputs and weak-keeper circuit are attached to each pad. Prior to con-
outputs that support a wide variety of I/O signalling stan- figuration, all pins not involved in configuration are forced
dards, see Table 1. into their high-impedance state. The pull-down resistors and
the weak-keeper circuits are inactive, but inputs can option-
The three IOB storage elements function either as edge-trig- ally be pulled up.
gered D-type flip-flops or as level sensitive latches. Each
IOB has a clock signal (CLK) shared by the three flip-flops The activation of pull-up resistors prior to configuration is
and independent clock enable signals for each flip-flop. controlled on a global basis by the configuration mode pins.
If the pull-up resistors are not activated, all the pins will float.
In addition to the CLK and CE control signals, the three Consequently, external pull-up or pull-down resistors must
flip-flops share a Set/Reset (SR). For each flip-flop, this sig- be provided on pins required to be at a well-defined logic
nal can be independently configured as a synchronous Set, level prior to configuration.
a synchronous Reset, an asynchronous Preset, or an asyn- All Virtex IOBs support IEEE 1149.1-compatible boundary
chronous Clear. scan testing.

© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
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T D Q
TCE CE
Weak
Keeper

SR

PAD
O D Q
OCE CE OBUFT

SR

IQ Q D Programmable
CE Delay
IBUF

Vref
SR

SR
CLK
ICE ds022_02_091300

Figure 2: Virtex Input/Output Block (IOB)

Table 1: Supported Select I/O Standards

Input Reference Output Source Board Termination
I/O Standard Voltage (VREF) Voltage (VCCO) Voltage (VTT) 5 V Tolerant
LVTTL 2 – 24 mA N/A 3.3 N/A Yes
LVCMOS2 N/A 2.5 N/A Yes
PCI, 5 V N/A 3.3 N/A Yes
PCI, 3.3 V N/A 3.3 N/A No
GTL 0.8 N/A 1.2 No
GTL+ 1.0 N/A 1.5 No
HSTL Class I 0.75 1.5 0.75 No
HSTL Class III 0.9 1.5 1.5 No
HSTL Class IV 0.9 1.5 1.5 No
SSTL3 Class I &II 1.5 3.3 1.5 No
SSTL2 Class I & II 1.25 2.5 1.25 No
CTT 1.5 3.3 1.5 No
AGP 1.32 3.3 N/A No

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Input Path Eight I/O banks result from separating each edge of the
FPGA into two banks, as shown in Figure 3. Each bank has
A buffer In the Virtex IOB input path routes the input signal
multiple VCCO pins, all of which must be connected to the
either directly to internal logic or through an optional input
same voltage. This voltage is determined by the output
flip-flop.
standards in use.
An optional delay element at the D-input of this flip-flop elim-
inates pad-to-pad hold time. The delay is matched to the
internal clock-distribution delay of the FPGA, and when
used, assures that the pad-to-pad hold time is zero. Bank 0 Bank 1
Each input buffer can be configured to conform to any of the GCLK3 GCLK2

Bank 7

Bank 2
low-voltage signalling standards supported. In some of
these standards the input buffer utilizes a user-supplied
threshold voltage, VREF. The need to supply VREF imposes
Virtex
constraints on which standards can used in close proximity
Device
to each other. See I/O Banking, page 3.

Bank 6

Bank 3
There are optional pull-up and pull-down resistors at each GCLK1 GCLK0

input for use after configuration. Their value is in the range Bank 5 Bank 4

50 kW – 100 kW.
X8778_b
Output Path
The output path includes a 3-state output buffer that drives Figure 3: Virtex I/O Banks

the output signal onto the pad. The output signal can be
Within a bank, output standards can be mixed only if they
routed to the buffer directly from the internal logic or through
use the same VCCO. Compatible standards are shown in
an optional IOB output flip-flop.
Table 2. GTL and GTL+ appear under all voltages because
The 3-state control of the output can also be routed directly their open-drain outputs do not depend on VCCO.
from the internal logic or through a flip-flip that provides syn-
chronous enable and disable. Table 2: Compatible Output Standards
Each output driver can be individually programmed for a VCCO Compatible Standards
wide range of low-voltage signalling standards. Each output
3.3 V PCI, LVTTL, SSTL3 I, SSTL3 II, CTT, AGP, GTL,
buffer can source up to 24 mA and sink up to 48mA. Drive
GTL+
strength and slew rate controls minimize bus transients.
In most signalling standards, the output High voltage 2.5 V SSTL2 I, SSTL2 II, LVCMOS2, GTL, GTL+
depends on an externally supplied VCCO voltage. The need 1.5 V HSTL I, HSTL III, HSTL IV, GTL, GTL+
to supply VCCO imposes constraints on which standards
can be used in close proximity to each other. See I/O Bank-
ing, page 3. Some input standards require a user-supplied threshold
voltage, VREF. In this case, certain user-I/O pins are auto-
An optional weak-keeper circuit is connected to each out- matically configured as inputs for the VREF voltage. Approx-
put. When selected, the circuit monitors the voltage on the imately one in six of the I/O pins in the bank assume this
pad and weakly drives the pin High or Low to match the role.
input signal. If the pin is connected to a multiple-source sig-
nal, the weak keeper holds the signal in its last state if all The VREF pins within a bank are interconnected internally
drivers are disabled. Maintaining a valid logic level in this and consequently only one VREF voltage can be used within
way eliminates bus chatter. each bank. All VREF pins in the bank, however, must be con-
nected to the external voltage source for correct operation.
Because the weak-keeper circuit uses the IOB input buffer
to monitor the input level, an appropriate VREF voltage must Within a bank, inputs that require VREF can be mixed with
be provided if the signalling standard requires one. The pro- those that do not. However, only one VREF voltage can be
vision of this voltage must comply with the I/O banking used within a bank. Input buffers that use VREF are not 5 V
rules. tolerant. LVTTL, LVCMOS2, and PCI 33 MHz 5 V, are 5 V
tolerant.
I/O Banking The VCCO and VREF pins for each bank appear in the device
Some of the I/O standards described above require VCCO Pinout tables and diagrams. The diagrams also show the
and/or VREF voltages. These voltages externally and con- bank affiliation of each I/O.
nected to device pins that serve groups of IOBs, called Within a given package, the number of VREF and VCCO pins
banks. Consequently, restrictions exist about which I/O can vary depending on the size of device. In larger devices,
standards can be combined within a given bank.

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more I/O pins convert to VREF pins. Since these are always of five or six inputs. Consequently, when estimating the
a superset of the VREF pins used for smaller devices, it is number of system gates provided by a given device, each
possible to design a PCB that permits migration to a larger CLB counts as 4.5 LCs.
device if necessary. All the VREF pins for the largest device
anticipated must be connected to the VREF voltage, and not
Look-Up Tables
used for I/O. Virtex function generators are implemented as 4-input
In smaller devices, some VCCO pins used in larger devices look-up tables (LUTs). In addition to operating as a function
do not connect within the package. These unconnected pins generator, each LUT can provide a 16 x 1-bit synchronous
can be left unconnected externally, or can be connected to RAM. Furthermore, the two LUTs within a slice can be com-
the VCCO voltage to permit migration to a larger device if bined to create a 16 x 2-bit or 32 x 1-bit synchronous RAM,
necessary. or a 16x1-bit dual-port synchronous RAM.
The Virtex LUT can also provide a 16-bit shift register that is
In TQ144 and PQ/HQ240 packages, all VCCO pins are
ideal for capturing high-speed or burst-mode data. This
bonded together internally, and consequently the same
mode can also be used to store data in applications such as
VCCO voltage must be connected to all of them. In the
Digital Signal Processing.
CS144 package, bank pairs that share a side are intercon-
nected internally, permitting four choices for VCCO. In both Storage Elements
cases, the VREF pins remain internally connected as eight
The storage elements in the Virtex slice can be configured
banks, and can be used as described previously.
either as edge-triggered D-type flip-flops or as level-sensi-
tive latches. The D inputs can be driven either by the func-
Configurable Logic Block
tion generators within the slice or directly from slice inputs,
The basic building block of the Virtex CLB is the logic cell bypassing the function generators.
(LC). An LC includes a 4-input function generator, carry
In addition to Clock and Clock Enable signals, each Slice
logic, and a storage element. The output from the function
has synchronous set and reset signals (SR and BY). SR
generator in each LC drives both the CLB output and the D
forces a storage element into the initialization state speci-
input of the flip-flop. Each Virtex CLB contains four LCs,
fied for it in the configuration. BY forces it into the opposite
organized in two similar slices, as shown in Figure 4.
state. Alternatively, these signals can be configured to oper-
Figure 5 shows a more detailed view of a single slice. ate asynchronously. All of the control signals are indepen-
In addition to the four basic LCs, the Virtex CLB contains dently invertible, and are shared by the two flip-flops within
logic that combines function generators to provide functions the slice.

COUT COUT

YB YB
Y Y
G4 G4
G3 SP G3 SP
LUT Carry & D Q YQ LUT Carry & D Q YQ
G2 Control G2 Control
EC EC
G1 G1

RC RC
BY BY
XB XB
X X
F4 F4
F3 SP F3 SP
LUT Carry & LUT Carry & D Q XQ
D Q XQ F2
F2 Control Control
EC EC
F1 F1

RC RC
BX BX
Slice 1 Slice 0

slice_b.eps
CIN CIN

Figure 4: 2-Slice Virtex CLB

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COUT

YB
CY

G4 I3 Y
G3 I2 O
G2 I1
LUT INIT
G1 I0 D Q YQ
WE DI
0 EC

1 REV
BY
XB
F5IN
F6

CY
F5 F5

CK WSO BY DG
WE X
A4 WSH BX DI
INIT
D Q XQ
BX EC

I3 WE DI
F4
F3 I2 O REV
F2 I1 LUT
F1 I0

1
SR
CLK
CE

CIN
viewslc4.eps

Figure 5: Detailed View of VIrtex Slice

Additional Logic Block SelectRAM
The F5 multiplexer in each slice combines the function gen- Virtex FPGAs incorporate several large Block SelectRAM
erator outputs. This combination provides either a function memories. These complement the distributed LUT Selec-
generator that can implement any 5-input function, a 4:1 tRAMs that provide shallow RAM structures implemented in
multiplexer, or selected functions of up to nine inputs. CLBs.
Similarly, the F6 multiplexer combines the outputs of all four Block SelectRAM memory blocks are organized in columns.
function generators in the CLB by selecting one of the All Virtex devices contain two such columns, one along
F5-multiplexer outputs. This permits the implementation of each vertical edge. These columns extend the full height of
any 6-input function, an 8:1 multiplexer, or selected func- the chip. Each memory block is four CLBs high, and conse-
tions of up to 19 inputs. quently, a Virtex device 64 CLBs high contains 16 memory
Each CLB has four direct feedthrough paths, one per LC. blocks per column, and a total of 32 blocks.
These paths provide extra data input lines or additional local Table 3 shows the amount of Block SelectRAM memory that
routing that does not consume logic resources. is available in each Virtex device.
Arithmetic Logic
Table 3: Virtex Block SelectRAM Amounts
Dedicated carry logic provides fast arithmetic carry capabil-
Device # of Blocks Total Block SelectRAM Bits
ity for high-speed arithmetic functions. The Virtex CLB sup-
ports two separate carry chains, one per Slice. The height XCV50 8 32,768
of the carry chains is two bits per CLB.
XCV100 10 40,960
The arithmetic logic includes an XOR gate that allows a
1-bit full adder to be implemented within an LC. In addition, XCV150 12 49,152
a dedicated AND gate improves the efficiency of multiplier
XCV200 14 57,344
implementation.
The dedicated carry path can also be used to cascade func- XCV300 16 65,536
tion generators for implementing wide logic functions. XCV400 20 81,920
BUFTs XCV600 24 98,304
Each Virtex CLB contains two 3-state drivers (BUFTs) that
XCV800 28 114,688
can drive on-chip busses. See Dedicated Routing, page 7.
Each Virtex BUFT has an independent 3-state control pin XCV1000 32 131,072
and an independent input pin.

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Each Block SelectRAM cell, as illustrated in Figure 6, is a

Table 4: Block SelectRAM Port Aspect Ratios
fully synchronous dual-ported 4096-bit RAM with indepen-
dent control signals for each port. The data widths of the Width Depth ADDR Bus Data Bus
two ports can be configured independently, providing 1 4096 ADDR<11:0> DATA<0>
built-in bus-width conversion.
2 2048 ADDR<10:0> DATA<1:0>
4 1024 ADDR<9:0> DATA<3:0>
RAMB4_S#_S#
8 512 ADDR<8:0> DATA<7:0>
WEA
ENA 16 256 ADDR<7:0> DATA<15:0>
RSTA DOA[#:0]
CLKA
ADDRA[#:0] The Virtex Block SelectRAM also includes dedicated rout-
DIA[#:0] ing to provide an efficient interface with both CLBs and
other Block SelectRAMs.
WEB
ENB Programmable Routing Matrix
RSTB DOB[#:0]
CLKB It is the longest delay path that limits the speed of any
ADDRB[#:0] worst-case design. Consequently, the Virtex routing archi-
DIB[#:0] tecture and its place-and-route software were defined in a
single optimization process. This joint optimization mini-
xcv_ds_006
mizes long-path delays, and consequently, yields the best
Figure 6: Dual-Port Block SelectRAM system performance.
The joint optimization also reduces design compilation
Table 4 shows the depth and width aspect ratios for the times because the architecture is software-friendly. Design
Block SelectRAM. cycles are correspondingly reduced due to shorter design
iteration times.

To Adjacent
GRM

To Adjacent To Adjacent
GRM GRM GRM

To Adjacent
GRM

Direct Connection Direct Connection

To Adjacent CLB To Adjacent
CLB CLB

X8794b

Figure 7: Virtex Local Routing

Local Routing • Internal CLB feedback paths that provide high-speed

The VersaBlock provides local routing resources, as shown connections to LUTs within the same CLB, chaining
in Figure 7, providing the following three types of connec- them together with minimal routing delay
tions. • Direct paths that provide high-speed connections
between horizontally adjacent CLBs, eliminating the
• Interconnections among the LUTs, flip-flops, and GRM delay of the GRM.

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General Purpose Routing • 12 Longlines are buffered, bidirectional wires that

distribute signals across the device quickly and
Most Virtex signals are routed on the general purpose rout-
efficiently. Vertical Longlines span the full height of the
ing, and consequently, the majority of interconnect
device, and horizontal ones span the full width of the
resources are associated with this level of the routing hier-
device.
archy. The general routing resources are located in horizon-
tal and vertical routing channels associated with the rows I/O Routing
and columns CLBs. The general-purpose routing resources
Virtex devices have additional routing resources around
are listed below.
their periphery that form an interface between the CLB array
• Adjacent to each CLB is a General Routing Matrix and the IOBs. This additional routing, called the VersaRing,
(GRM). The GRM is the switch matrix through which facilitates pin-swapping and pin-locking, such that logic
horizontal and vertical routing resources connect, and redesigns can adapt to existing PCB layouts. Time-to-mar-
is also the means by which the CLB gains access to ket is reduced, since PCBs and other system components
the general purpose routing. can be manufactured while the logic design is still in
• 24 single-length lines route GRM signals to adjacent progress.
GRMs in each of the four directions.
Dedicated Routing
• 72 buffered Hex lines route GRM signals to another
GRMs six-blocks away in each one of the four Some classes of signal require dedicated routing resources
directions. Organized in a staggered pattern, Hex lines to maximize performance. In the Virtex architecture, dedi-
can be driven only at their endpoints. Hex-line signals cated routing resources are provided for two classes of sig-
can be accessed either at the endpoints or at the nal.
midpoint (three blocks from the source). One third of • Horizontal routing resources are provided for on-chip
the Hex lines are bidirectional, while the remaining 3-state busses. Four partitionable bus lines are
ones are uni-directional. provided per CLB row, permitting multiple busses
within a row, as shown in Figure 8.
• Two dedicated nets per CLB propagate carry signals
vertically to the adjacent CLB.

Tri-State
Lines

CLB CLB CLB CLB

buft_c.eps

Figure 8: BUFT Connections to Dedicated Horizontal Bus Lines

Global Routing • The secondary local clock routing resources consist of

Global Routing resources distribute clocks and other sig- 24 backbone lines, 12 across the top of the chip and 12
nals with very high fanout throughout the device. Virtex across bottom. From these lines, up to 12 unique
devices include two tiers of global routing resources signals per column can be distributed via the 12
referred to as primary global and secondary local clock rout- longlines in the column. These secondary resources
ing resources. are more flexible than the primary resources since they
are not restricted to routing only to clock pins.
• The primary global routing resources are four
dedicated global nets with dedicated input pins that are Clock Distribution
designed to distribute high-fanout clock signals with Virtex provides high-speed, low-skew clock distribution
minimal skew. Each global clock net can drive all CLB, through the primary global routing resources described
IOB, and block RAM clock pins. The primary global above. A typical clock distribution net is shown in Figure 9.
nets can only be driven by global buffers. There are
Four global buffers are provided, two at the top center of the
four global buffers, one for each global net.
device and two at the bottom center. These drive the four
primary global nets that in turn drive any clock pin.

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Four dedicated clock pads are provided, one adjacent to selected either from these pads or from signals in the gen-
each of the global buffers. The input to the global buffer is eral purpose routing.

GCLKPAD3 GCLKPAD2
Global Clock Rows GCLKBUF3 GCLKBUF2 Global Clock Column

Global Clock Spine

GCLKBUF1 GCLKBUF0
GCLKPAD1 GCLKPAD0
gclkbu_2.eps

Figure 9: Global Clock Distribution Network

Delay-Locked Loop (DLL) Boundary Scan

Associated with each global clock input buffer is a fully digi- Virtex devices support all the mandatory boundary-scan
tal Delay-Locked Loop (DLL) that can eliminate skew instructions specified in the IEEE standard 1149.1. A Test
between the clock input pad and internal clock-input pins Access Port (TAP) and registers are provided that imple-
throughout the device. Each DLL can drive two global clock ment the EXTEST, INTEST, SAMPLE/PRELOAD, BYPASS,
networks.The DLL monitors the input clock and the distrib- IDCODE, USERCODE, and HIGHZ instructions. The TAP
uted clock, and automatically adjusts a clock delay element. also supports two internal scan chains and configura-
Clock edges reach internal flip-flops one to four clock peri- tion/readback of the device.The TAP uses dedicated pack-
ods after they arrive at the input. This closed-loop system age pins that always operate using LVTTL. For TDO to
effectively eliminates clock-distribution delay by ensuring operate using LVTTL, the VCCO for Bank 2 should be 3.3 V.
that clock edges arrive at internal flip-flops in synchronism Otherwise, TDO switches rail-to-rail between ground and
with clock edges arriving at the input. VCCO.
In addition to eliminating clock-distribution delay, the DLL Boundary-scan operation is independent of individual IOB
provides advanced control of multiple clock domains. The configurations, and unaffected by package type. All IOBs,
DLL provides four quadrature phases of the source clock, including un-bonded ones, are treated as independent
can double the clock, or divide the clock by 1.5, 2, 2.5, 3, 4, 3-state bidirectional pins in a single scan chain. Retention of
5, 8, or 16. the bidirectional test capability after configuration facilitates
The DLL also operates as a clock mirror. By driving the out- the testing of external interconnections.
put from a DLL off-chip and then back on again, the DLL can Table 5 lists the boundary-scan instructions supported in
be used to de-skew a board level clock among multiple Vir- Virtex FPGAs. Internal signals can be captured during
tex devices. EXTEST by connecting them to un-bonded or unused IOBs.
In order to guarantee that the system clock is operating cor- They can also be connected to the unused outputs of IOBs
rectly prior to the FPGA starting up after configuration, the defined as unidirectional input pins.
DLL can delay the completion of the configuration process Before the device is configured, all instructions except
until after it has achieved lock. USER1 and USER2 are available. After configuration, all
See DLL Timing Parameters, page 20 of Module 3, for fre- instructions are available. During configuration, it is recom-
quency range information. mended that those operations using the boundary-scan
register (SAMPLE/PRELOAD, INTEST, EXTEST) not be
performed.

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In addition to the test instructions outlined above, the The FPGA supports up to two additional internal scan
boundary-scan circuitry can be used to configure the chains that can be specified using the BSCAN macro. The
FPGA, and also to read back the configuration data. macro provides two user pins (SEL1 and SEL2) which are
Figure 10 is a diagram of the Virtex Series boundary scan decodes of the USER1 and USER2 instructions respec-
logic. It includes three bits of Data Register per IOB, the tively. For these instructions, two corresponding pins (TDO1
IEEE 1149.1 Test Access Port controller, and the Instruction and TDO2) allow user scan data to be shifted out of TDO.
Register with decodes. Likewise, there are individual clock pins (DRCK1 and
DRCK2) for each user register. There is a common input pin
Instruction Set (TDI) and shared output pins that represent the state of the
The Virtex Series boundary scan instruction set also TAP controller (RESET, SHIFT, and UPDATE).
includes instructions to configure the device and read back
configuration data (CFG_IN, CFG_OUT, and JSTART). The Bit Sequence
complete instruction set is coded as shown in Table 5. The order within each IOB is: In, Out, 3-State. The
input-only pins contribute only the In bit to the boundary
Data Registers scan I/O data register, while the output-only pins contributes
The primary data register is the boundary scan register. For all three bits.
each IOB pin in the FPGA, bonded or not, it includes three
From a cavity-up view of the chip (as shown in EPIC), start-
bits for In, Out, and 3-State Control. Non-IOB pins have
ing in the upper right chip corner, the boundary scan
appropriate partial bit population if input-only or output-only.
data-register bits are ordered as shown in Figure 11.
Each EXTEST CAPTURED-OR state captures all In, Out,
and 3-state pins. BSDL (Boundary Scan Description Language) files for Vir-
tex Series devices are available on the Xilinx web site in the
The other standard data register is the single flip-flop
File Download area.
BYPASS register. It synchronizes data being passed
through the FPGA to the next downstream boundary scan
device.
DATA IN

IOB.T 0
1 sd
D Q D Q 1
0

IOB IOB IOB IOB IOB LE

IOB IOB sd
1
D Q D Q
0
IOB IOB
LE

IOB IOB
1
IOB.I
0
IOB IOB

1 sd
IOB IOB D Q D Q
0

LE
IOB IOB
1
0
IOB IOB IOB.Q
BYPASS
REGISTER
IOB.T 0
M TDO
U 1 sd
INSTRUCTION REGISTER D Q D Q 1
TDI
X 0

LE

1 sd
D Q D Q
0

LE

1
IOB.I
0

DATAOUT UPDATE EXTEST

SHIFT/ CLOCK DATA
CAPTURE REGISTER
X9016

Figure 10: Virtex Series Boundary Scan Logic

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Identification Registers
Bit 0 ( TDO end) Right half of Top-edge IOBs (Right-to-Left)
Bit 1 The IDCODE register is supported. By using the IDCODE,
Bit 2 GCLK2
GCLK3 the device connected to the JTAG port can be determined.
Left half of Top-edge IOBs (Right-to-Left) The IDCODE register has the following binary format:
Left-edge IOBs (Top-to-Bottom) vvvv:ffff:fffa:aaaa:aaaa:cccc:cccc:ccc1
M1
M0 where
M2
v = the die version number
Left half of Bottom-edge IOBs (Left-to-Right)
f = the family code (03h for Virtex family)
GCLK1
GCLK0
a = the number of CLB rows (ranges from 010h for XCV50
Right half of Bottom-edge IOBs (Left-to-Right) to 040h for XCV1000)
DONE
PROG
c = the company code (49h for Xilinx)
Right-edge IOBs (Bottom -to-Top) The USERCODE register is supported. By using the USER-
(TDI end) CCLK CODE, a user-programmable identification code can be
990602001 loaded and shifted out for examination. The identification
Figure 11: Boundary Scan Bit Sequence code is embedded in the bitstream during bitstream gener-
ation and is valid only after configuration.

Table 6: IDCODEs Assigned to Virtex FPGAs

Table 5: Boundary Scan Instructions
Boundary-Scan Binary FPGA IDCODE
Command Code(4:0) Description XCV50 v0610093h
EXTEST 00000 Enables boundary-scan XCV100 v0614093h
EXTEST operation
XCV150 v0618093h
SAMPLE/PRELOAD 00001 Enables boundary-scan
SAMPLE/PRELOAD XCV200 v061C093h
operation
XCV300 v0620093h
USER 1 00010 Access user-defined
register 1 XCV400 v0628093h
USER 2 00011 Access user-defined XCV600 v0630093h
register 2
XCV800 v0638093h
CFG_OUT 00100 Access the configuration
bus for read operations. XCV1000 v0640093h

CFG_IN 00101 Access the configuration

bus for write operations. Including Boundary Scan in a Design
INTEST 00111 Enables boundary-scan Since the boundary scan pins are dedicated, no special ele-
INTEST operation ment needs to be added to the design unless an internal
data register (USER1 or USER2) is desired.
USERCODE 01000 Enables shifting out
USER code If an internal data register is used, insert the boundary scan
symbol and connect the necessary pins as appropriate.
IDCODE 01001 Enables shifting out of ID
Code
Development System
HIGHZ 01010 3-states output pins while
enabling the Bypass
Virtex FPGAs are supported by the Xilinx Foundation and
Register Alliance CAE tools. The basic methodology for Virtex design
consists of three interrelated steps: design entry, imple-
JSTART 01100 Clock the start-up mentation, and verification. Industry-standard tools are
sequence when used for design entry and simulation (for example, Synop-
StartupClk is TCK
sys FPGA Express), while Xilinx provides proprietary archi-
BYPASS 11111 Enables BYPASS tecture-specific tools for implementation.
RESERVED All other Xilinx reserved The Xilinx development system is integrated under the Xil-
codes instructions inx Design Manager (XDM™) software, providing designers

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with a common user interface regardless of their choice of design, thus allowing the most convenient entry method to
entry and verification tools. The XDM software simplifies the be used for each portion of the design.
selection of implementation options with pull-down menus
and on-line help. Design Implementation
Application programs ranging from schematic capture to The place-and-route tools (PAR) automatically provide the
Placement and Routing (PAR) can be accessed through the implementation flow described in this section. The parti-
XDM software. The program command sequence is gener- tioner takes the EDIF net list for the design and maps the
ated prior to execution, and stored for documentation. logic into the architectural resources of the FPGA (CLBs
and IOBs, for example). The placer then determines the
Several advanced software features facilitate Virtex design. best locations for these blocks based on their interconnec-
RPMs, for example, are schematic-based macros with rela- tions and the desired performance. Finally, the router inter-
tive location constraints to guide their placement. They help connects the blocks.
ensure optimal implementation of common functions.
The PAR algorithms support fully automatic implementation
For HDL design entry, the Xilinx FPGA Foundation develop- of most designs. For demanding applications, however, the
ment system provides interfaces to the following synthesis user can exercise various degrees of control over the pro-
design environments. cess. User partitioning, placement, and routing information
• Synopsys (FPGA Compiler, FPGA Express) is optionally specified during the design-entry process. The
• Exemplar (Spectrum) implementation of highly structured designs can benefit
• Synplicity (Synplify) greatly from basic floor planning.

For schematic design entry, the Xilinx FPGA Foundation The implementation software incorporates Timing Wizard®
and alliance development system provides interfaces to the timing-driven placement and routing. Designers specify tim-
following schematic-capture design environments. ing requirements along entire paths during design entry.
The timing path analysis routines in PAR then recognize
• Mentor Graphics V8 (Design Architect, QuickSim II) these user-specified requirements and accommodate them.
• Viewlogic Systems (Viewdraw)
Timing requirements are entered on a schematic in a form
Third-party vendors support many other environments. directly relating to the system requirements, such as the tar-
A standard interface-file specification, Electronic Design geted clock frequency, or the maximum allowable delay
Interchange Format (EDIF), simplifies file transfers into and between two registers. In this way, the overall performance
out of the development system. of the system along entire signal paths is automatically tai-
lored to user-generated specifications. Specific timing infor-
Virtex FPGAs supported by a unified library of standard
mation for individual nets is unnecessary.
functions. This library contains over 400 primitives and mac-
ros, ranging from 2-input AND gates to 16-bit accumulators,
Design Verification
and includes arithmetic functions, comparators, counters,
data registers, decoders, encoders, I/O functions, latches, In addition to conventional software simulation, FPGA users
Boolean functions, multiplexers, shift registers, and barrel can use in-circuit debugging techniques. Because Xilinx
shifters. devices are infinitely reprogrammable, designs can be veri-
fied in real time without the need for extensive sets of soft-
The “soft macro” portion of the library contains detailed
ware simulation vectors.
descriptions of common logic functions, but does not con-
tain any partitioning or placement information. The perfor- The development system supports both software simulation
mance of these macros depends, therefore, on the and in-circuit debugging techniques. For simulation, the
partitioning and placement obtained during implementation. system extracts the post-layout timing information from the
design database, and back-annotates this information into
RPMs, on the other hand, do contain predetermined parti-
the net list for use by the simulator. Alternatively, the user
tioning and placement information that permits optimal
can verify timing-critical portions of the design using the
implementation of these functions. Users can create their
TRACE® static timing analyzer.
own library of soft macros or RPMs based on the macros
and primitives in the standard library. For in-circuit debugging, the development system includes
a download and readback cable. This cable connects the
The design environment supports hierarchical design entry,
FPGA in the target system to a PC or workstation. After
with high-level schematics that comprise major functional
downloading the design into the FPGA, the designer can
blocks, while lower-level schematics define the logic in
single-step the logic, readback the contents of the flip-flops,
these blocks. These hierarchical design elements are auto-
and so observe the internal logic state. Simple modifica-
matically combined by the implementation tools. Different
tions can be downloaded into the system in a matter of min-
design entry tools can be combined within a hierarchical
utes.

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Configuration After Virtex devices are configured, unused IOBs function

as 3-state OBUFTs with weak pull downs. For a more
Virtex devices are configured by loading configuration data
detailed description than that given below, see the
into the internal configuration memory. Some of the pins
XAPP138, Virtex Configuration and Readback.
used for this are dedicated configuration pins, while others
can be re-used as general purpose inputs and outputs once Configuration Modes
configuration is complete.
Virtex supports the following four configuration modes.
The following are dedicated pins:
• Slave-serial mode
• Mode pins (M2, M1, M0)
• Master-serial mode
• Configuration clock pin (CCLK)
• SelectMAP mode
• PROGRAM pin
• Boundary-scan mode
• DONE pin
The Configuration mode pins (M2, M1, M0) select among
• Boundary-scan pins (TDI, TDO, TMS, TCK)
these configuration modes with the option in each case of
Depending on the configuration mode chosen, CCLK can having the IOB pins either pulled up or left floating prior to
be an output generated by the FPGA, or it can be generated configuration. The selection codes are listed in Table 7.
externally and provided to the FPGA as an input.
Configuration through the boundary-scan port is always
Note that some configuration pins can act as outputs. For available, independent of the mode selection. Selecting the
correct operation, these pins can require a VCCO of 3.3 V to boundary-scan mode simply turns off the other modes. The
permit LVTTL operation. All the pins affected are in banks 2 three mode pins have internal pull-up resistors, and default
or 3. to a logic High if left unconnected.

Table 7: Configuration Codes

Configuration Mode M2 M1 M0 CCLK Direction Data Width Serial Dout Configuration Pull-ups
Master-serial mode 0 0 0 Out 1 Yes No
Boundary-scan mode 1 0 1 N/A 1 No No
SelectMAP mode 1 1 0 In 8 No No
Slave-serial mode 1 1 1 In 1 Yes No
Master-serial mode 1 0 0 Out 1 Yes Yes
Boundary-scan mode 0 0 1 N/A 1 No Yes
SelectMAP mode 0 1 0 In 8 No Yes
Slave-serial mode 0 1 1 In 1 Yes Yes

Slave-Serial Mode The change of DOUT on the rising edge of CCLK differs
In slave-serial mode, the FPGA receives configuration data from previous families, but does not cause a problem for
in bit-serial form from a serial PROM or other source of mixed configuration chains. This change was made to
serial configuration data. The serial bitstream must be setup improve serial configuration rates for Virtex-only chains.
at the DIN input pin a short time before each rising edge of Figure 12 shows a full master/slave system. A Virtex device
an externally generated CCLK. in slave-serial mode should be connected as shown in the
third device from the left.
For more information on serial PROMs, see the PROM data
sheet at http://www.xilinx.com/partinfo/ds026.pdf. Slave-serial mode is selected by applying <111> or <011>
to the mode pins (M2, M1, M0). A weak pull-up on the mode
Multiple FPGAs can be daisy-chained for configuration from
pins makes slave-serial the default mode if the pins are left
a single source. After a particular FPGA has been config-
unconnected. Figure 13 shows slave-serial configuration
ured, the data for the next device is routed to the DOUT pin.
timing.
The data on the DOUT pin changes on the rising edge of
CCLK. Table 8 provides more detail about the characteristics
shown in Figure 13. Configuration must be delayed until the
INIT pins of all daisy-chained FPGAs are High.

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Table 8: Master/Slave Serial Mode Programming Switching

Figure
Description References Symbol Values Units
DIN setup/hold, slave mode 1/2 TDCC/TCCD 5.0 / 0 ns, min
DIN setup/hold, master mode 1/2 TDSCK/TCKDS 5.0 / 0 ns, min
DOUT 3 TCCO 12.0 ns, max
High time 4 TCCH 5.0 ns, min
CCLK
Low time 5 TCCL 5.0 ns, min
Maximum Frequency FCC 66 MHz, max
Frequency Tolerance, master mode with +45%
respect to nominal –30%

3.3V V
CC

M0 M1 4.7 K M0 M1
M2 M2

DOUT DIN DOUT

CCLK
VIRTEX
MASTER XC1701L VIRTEX,
SERIAL XC4000XL,
CCLK CLK SLAVE
Optional Pull-up DIN DATA

Resistor on Done
1 PROGRAM CE CEO PROGRAM
DONE INIT RESET/OE DONE INIT

(Low Reset Option Used)

PROGRAM

Note 1: If none of the Virtex FPGAs have been selected to drive DONE, an external pull-up resistor of 330 Ω should be added to the common DONE line.

xcv_12_091499

Figure 12: Master/Slave Serial Mode Circuit Diagram

DIN

1 TDCC 2 TCCD 5 TCCL

CCLK

4 TCCH

3 TCCO

DOUT
(Output)

X5379_a

Figure 13: Slave-Serial Mode Programming Switching Characteristics

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Master-Serial Mode daisy-chained FPGAs are fast enough to support the clock
rate.
In master-serial mode, the CCLK output of the FPGA drives
a Xilinx Serial PROM that feeds bit-serial data to the DIN On power-up, the CCLK frequency is 2.5 MHz. This fre-
input. The FPGA accepts this data on each rising CCLK quency is used until the ConfigRate bits have been loaded
edge. After the FPGA has been loaded, the data for the next when the frequency changes to the selected ConfigRate.
device in a daisy-chain is presented on the DOUT pin after Unless a different frequency is specified in the design, the
the rising CCLK edge. default ConfigRate is 4 MHz.
The interface is identical to slave-serial except that an inter- Figure 12 shows a full master/slave system. In this system,
nal oscillator is used to generate the configuration clock the left-most device operates in master-serial mode. The
(CCLK). A wide range of frequencies can be selected for remaining devices operate in slave-serial mode. The
CCLK which always starts at a slow default frequency. Con- SPROM RESET pin is driven by INIT, and the CE input is
figuration bits then switch CCLK to a higher frequency for driven by DONE. There is the potential for contention on the
the remainder of the configuration. Switching to a lower fre- DONE pin, depending on the start-up sequence options
quency is prohibited. chosen.
The CCLK frequency is set using the ConfigRate option in Figure 14 shows the timing of master-serial configuration.
the bitstream generation software. The maximum CCLK fre- Master-serial mode is selected by a <000> or <100> on the
quency that can be selected is 60 MHz. When selecting a mode pins (M2, M1, M0). Table 8 shows the timing informa-
CCLK frequency, ensure that the serial PROM and any tion for Figure 14.

CCLK
(Output)

TCKDS 2

1 TDSCK

Serial Data In

Serial DOUT
(Output)
DS022_44_071201

Figure 14: Master-Serial Mode Programming Switching Characteristics

At power-up, VCC must rise from 1.0 V to VCC min in less In the SelectMAP mode, multiple Virtex devices can be
than 50 ms, otherwise delay configuration by pulling chained in parallel. DATA pins (D7:D0), CCLK, WRITE,
PROGRAM Low until VCC is valid. BUSY, PROGRAM, DONE, and INIT can be connected in
The sequence of operations necessary to configure a Virtex parallel between all the FPGAs. Note that the data is orga-
FPGA serially appears in Figure 15. nized with the MSB of each byte on pin DO and the LSB of
each byte on D7. The CS pins are kept separate, insuring
SelectMAP Mode that each FPGA can be selected individually. WRITE should
The SelectMAP mode is the fastest configuration option. be Low before loading the first bitstream and returned High
Byte-wide data is written into the FPGA with a BUSY flag after the last device has been programmed. Use CS to
controlling the flow of data. select the appropriate FPGA for loading the bitstream and
sending the configuration data. at the end of the bitstream,
An external data source provides a byte stream, CCLK, a deselect the loaded device and select the next target FPGA
Chip Select (CS) signal and a Write signal (WRITE). If by setting its CS pin High. A free-running oscillator or other
BUSY is asserted (High) by the FPGA, the data must be externally generated signal can be used for CCLK. The
held until BUSY goes Low. BUSY signal can be ignored for frequencies below 50 MHz.
Data can also be read using the SelectMAP mode. If For details about frequencies above 50 MHz, see
WRITE is not asserted, configuration data is read out of the XAPP138, Virtex Configuration and Readback. Once all the
FPGA as part of a readback operation. devices have been programmed, the DONE pin goes High.

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Apply Power
FPGA starts to clear
configuration memory.
Set PROGRAM = High

FPGA makes a final

clearing pass and releases
If used to delay
INIT when finished. Release INIT configuration

Low
INIT?
High

Load a Configuration Bit

Once per bitstream,

FPGA checks data using CRC
and pulls INIT Low on error. No
End of
Bitstream?

If no CRC errors found, Yes

FPGA enters start-up phase
causing DONE to go High. Configuration Completed

ds003_154_111799

Figure 15: Serial Configuration Flowchart

After configuration, the pins of the SelectMAP port can be Multiple Virtex FPGAs can be configured using the Select-
used as additional user I/O. Alternatively, the port can be MAP mode, and be made to start-up simultaneously. To
retained to permit high-speed 8-bit readback. configure multiple devices in this way, wire the individual
Retention of the SelectMAP port is selectable on a CCLK, Data, WRITE, and BUSY pins of all the devices in
design-by-design basis when the bitstream is generated. If parallel. The individual devices are loaded separately by
retention is selected, PROHIBIT constraints are required to asserting the CS pin of each device in turn and writing the
prevent the SelectMAP-port pins from being used as user appropriate data. See Table 9 for SelectMAP Write Timing
I/O. Characteristics.
.

Table 9: SelectMAP Write Timing Characteristics

Description Symbol Units
D0-7 Setup/Hold 1/2 TSMDCC/TSMCCD 5.0 / 1.7 ns, min
CS Setup/Hold 3/4 TSMCSCC/TSMCCCS 7.0 / 1.7 ns, min
WRITE Setup/Hold 5/6 TSMCCW/TSMWCC 7.0 / 1.7 ns, min
CCLK
BUSY Propagation Delay 7 TSMCKBY 12.0 ns, max
Maximum Frequency FCC 66 MHz, max
Maximum Frequency with no handshake FCCNH 50 MHz, max

Write 1. Assert WRITE and CS Low. Note that when CS is

Write operations send packets of configuration data into the asserted on successive CCLKs, WRITE must remain
FPGA. The sequence of operations for a multi-cycle write either asserted or de-asserted. Otherwise an abort will
operation is shown below. Note that a configuration packet be initiated, as described below.
can be split into many such sequences. The packet does 2. Drive data onto D[7:0]. Note that to avoid contention,
not have to complete within one assertion of CS, illustrated the data source should not be enabled while CS is Low
in Figure 16. and WRITE is High. Similarly, while WRITE is High, no
more that one CS should be asserted.

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3. At the rising edge of CCLK: If BUSY is Low, the data is 5. De-assert CS and WRITE.
accepted on this clock. If BUSY is High (from a previous A flowchart for the write operation appears in Figure 17.
write), the data is not accepted. Acceptance will instead Note that if CCLK is slower than fCCNH, the FPGA never
occur on the first clock after BUSY goes Low, and the asserts BUSY. In this case, the above handshake is unnec-
data must be held until this has happened. essary, and data can simply be entered into the FPGA every
4. Repeat steps 2 and 3 until all the data has been sent. CCLK cycle.

CCLK

CS 3 4

WRITE 5 6

1 2

DATA[7:0]

7
BUSY

Write Write No Write Write

ds003_16_102199

Figure 16: Write Operations

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Apply Power
FPGA starts to clear
configuration memory.
Set PROGRAM = High

FPGA makes a final

clearing pass and releases
If used to delay
INIT when finished. Release INIT configuration

Low
INIT?

High

Set WRITE = Low

Enter Data Source

Sequence A

Set CS = Low On first FPGA

Apply Configuration Byte

Once per bitstream,

FPGA checks data using CRC
and pulls INIT Low on error. High
Busy?
Low

No
End of Data?
If no errors, Yes
first FPGAs enter start-up phase
releasing DONE.
Set CS = High On first FPGA

If no errors, Repeat Sequence A For any other FPGAs

later FPGAs enter start-up phase
releasing DONE.

Disable Data Source

Set WRITE = High

When all DONE pins
are released, DONE goes High
and start-up sequences complete. Configuration Completed
ds003_17_111799

Figure 17: SelectMAP Flowchart for Write Operation

Abort aries, and the FPGA requires a new synchronization word

prior to accepting any new packets.
During a given assertion of CS, the user cannot switch from
a write to a read, or vice-versa. This action causes the cur- To initiate an abort during a write operation, de-assert
rent packet command to be aborted. The device will remain WRITE. At the rising edge of CCLK, an abort is initiated, as
BUSY until the aborted operation has completed. Following shown in Figure 18.
an abort, data is assumed to be unaligned to word bound-

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The power-up timing of configuration signals is shown in

Figure 19. The corresponding timing characteristics are
listed in Table 10. .
CCLK

Vcc TPOR
CS

WRITE PROGRAM
TPI
DATA[7:0]
INIT

BUSY
TICCK

CCLK OUTPUT or INPUT

Abort
X8797_c

M0, M1, M2
Figure 18: SelectMAP Write Abort Waveforms (Required)
VALID

Boundary-Scan Mode 98122302

In the boundary-scan mode, no non-dedicated pins are Figure 19: Power-Up Timing Configuration Signals
required, configuration being done entirely through the
IEEE 1149.1 Test Access Port. Table 10: Power-up Timing Characteristics
Configuration through the TAP uses the CFG_IN instruc- Description Symbol Value Units
tion. This instruction allows data input on TDI to be con-
verted into data packets for the internal configuration bus. Power-on Reset TPOR 2.0 ms, max
The following steps are required to configure the FPGA Program Latency TPL 100.0 ms, max
through the boundary-scan port (when using TCK as a
CCLK (output) Delay TICCK 0.5 ms, min
start-up clock).
1. Load the CFG_IN instruction into the boundary-scan 4.0 ms, max
instruction register (IR) Program Pulse Width TPROGRAM 300 ns, min
2. Enter the Shift-DR (SDR) state
3. Shift a configuration bitstream into TDI Delaying Configuration
4. Return to Run-Test-Idle (RTI) INIT can be held Low using an open-drain driver. An
5. Load the JSTART instruction into IR open-drain is required since INIT is a bidirectional
6. Enter the SDR state open-drain pin that is held Low by the FPGA while the con-
figuration memory is being cleared. Extending the time that
7. Clock TCK through the startup sequence
the pin is Low causes the configuration sequencer to wait.
8. Return to RTI Thus, configuration is delayed by preventing entry into the
Configuration and readback via the TAP is always available. phase where data is loaded.
The boundary-scan mode is selected by a <101> or 001>
Start-Up Sequence
on the mode pins (M2, M1, M0).
The default Start-up sequence is that one CCLK cycle after
Configuration Sequence DONE goes High, the global 3-state signal (GTS) is released.
This permits device outputs to turn on as necessary.
The configuration of Virtex devices is a three-phase pro-
cess. First, the configuration memory is cleared. Next, con- One CCLK cycle later, the Global Set/Reset (GSR) and Glo-
figuration data is loaded into the memory, and finally, the bal Write Enable (GWE) signals are released. This permits
logic is activated by a start-up process. the internal storage elements to begin changing state in
response to the logic and the user clock.
Configuration is automatically initiated on power-up unless
it is delayed by the user, as described below. The configura- The relative timing of these events can be changed. In addi-
tion process can also be initiated by asserting PROGRAM. tion, the GTS, GSR, and GWE events can be made depen-
The end of the memory-clearing phase is signalled by INIT dent on the DONE pins of multiple devices all going High,
going High, and the completion of the entire process is sig- forcing the devices to start in synchronism. The sequence
nalled by DONE going High. can also be paused at any stage until lock has been
achieved on any or all DLLs.

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Data Stream Format Readback

Virtex devices are configured by sequentially loading The configuration data stored in the Virtex configuration
frames of data. Table 11 lists the total number of bits memory can be readback for verification. Along with the
required to configure each device. For more detailed infor- configuration data it is possible to readback the contents all
mation, see application note XAPP151 “Virtex Configura- flip-flops/latches, LUTRAMs, and block RAMs. This capabil-
tion Architecture Advanced Users Guide”. ity is used for real-time debugging.

Table 11: Virtex Bit-Stream Lengths For more detailed information, see application note
XAPP138, Virtex FPGA Series Configuration and Read-
Device # of Configuration Bits back.
XCV50 559,200
XCV100 781,216
XCV150 1,040,096
XCV200 1,335,840
XCV300 1,751,808
XCV400 2,546,048
XCV600 3,607,968
XCV800 4,715,616
XCV1000 6,127,744

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Revision History
Date Version Revision
11/98 1.0 Initial Xilinx release.
01/99 1.2 Updated package drawings and specs.
02/99 1.3 Update of package drawings, updated specifications.
05/99 1.4 Addition of package drawings and specifications.
05/99 1.5 Replaced FG 676 & FG680 package drawings.
07/99 1.6 Changed Boundary Scan Information and changed Figure 11, Boundary Scan Bit
Sequence. Updated IOB Input & Output delays. Added Capacitance info for different I/O
Standards. Added 5 V tolerant information. Added DLL Parameters and waveforms and
new Pin-to-pin Input and Output Parameter tables for Global Clock Input to Output and
Setup and Hold. Changed Configuration Information including Figures 12, 14, 17 & 19.
Added device-dependent listings for quiescent currents ICCINTQ and ICCOQ. Updated
IOB Input and Output Delays based on default standard of LVTTL, 12 mA, Fast Slew Rate.
Added IOB Input Switching Characteristics Standard Adjustments.
09/99 1.7 Speed grade update to preliminary status, Power-on specification and Clock-to-Out
Minimums additions, “0” hold time listing explanation, quiescent current listing update, and
Figure 6 ADDRA input label correction. Added TIJITCC parameter, changed TOJIT to TOPHASE.
01/00 1.8 Update to speed.txt file 1.96. Corrections for CRs 111036,111137, 112697, 115479,
117153, 117154, and 117612. Modified notes for Recommended Operating Conditions
(voltage and temperature). Changed Bank information for VCCO in CS144 package on p.43.
01/00 1.9 Updated DLL Jitter Parameter table and waveforms, added Delay Measurement
Methodology table for different I/O standards, changed buffered Hex line info and
Input/Output Timing measurement notes.
03/00 2.0 New TBCKO values; corrected FG680 package connection drawing; new note about status
of CCLK pin after configuration.
05/00 2.1 Modified “Pins not listed ...” statement. Speed grade update to Final status.
05/00 2.2 Modified Table 18.
09/00 2.3 • Added XCV400 values to table under Minimum Clock-to-Out for Virtex Devices.
• Corrected Units column in table under IOB Input Switching Characteristics.
• Added values to table under CLB SelectRAM Switching Characteristics.
10/00 2.4 • Corrected Pinout information for devices in the BG256, BG432, and BG560 packages in
Table 18.
• Corrected BG256 Pin Function Diagram.
04/01 2.5 • Revised minimums for Global Clock Set-Up and Hold for LVTTL Standard, with DLL.
• Updated SelectMAP Write Timing Characteristics values in Table 9.
• Converted file to modularized format. See the Virtex Data Sheet section.
07/01 2.6 • Made minor edits to text under Configuration.

Virtex Data Sheet

The Virtex Data Sheet contains the following modules:
• DS003-1, Virtex 2.5V FPGAs: • DS003-3, Virtex 2.5V FPGAs:
Introduction and Ordering Information (Module 1) DC and Switching Characteristics (Module 3)
• DS003-2, Virtex 2.5V FPGAs: • DS003-4, Virtex 2.5V FPGAs:
Functional Description (Module 2) Pinout Tables (Module 4)

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DS003-3 (v3.0) February 1, 2002 0 3 Product Specification

Virtex Electrical Characteristics

Definition of Terms
Electrical and switching characteristics are specified on a Table 1 correlates the current status of each Virtex device
per-speed-grade basis and can be designated as Advance, with a corresponding speed file designation.
Preliminary, or Production. Each designation is defined as
follows: Table 1: Virtex Device Speed Grade Designations
Advance: These speed files are based on simulations only Speed Grade Designations
and are typically available soon after device design specifi-
Device Advance Preliminary Production
cations are frozen. Although speed grades with this desig-
nation are considered relatively stable and conservative, XCV50 –6, –5, –4
some under-reporting might still occur.
XCV100 –6, –5, –4
Preliminary: These speed files are based on complete ES
(engineering sample) silicon characterization. Devices and XCV150 –6, –5, –4
speed grades with this designation are intended to give a XCV200 –6, –5, –4
better indication of the expected performance of production
silicon. The probability of under-reporting delays is greatly XCV300 –6, –5, –4
reduced as compared to Advance data. XCV400 –6, –5, –4
Production: These speed files are released once enough XCV600 –6, –5, –4
production silicon of a particular device family member has
been characterized to provide full correlation between XCV800 –6, –5, –4
speed files and devices over numerous production lots. XCV1000 –6, –5, –4
There is no under-reporting of delays, and customers
receive formal notification of any subsequent changes. Typ- All specifications are subject to change without notice.
ically, the slowest speed grades transition to Production
before faster speed grades.
All specifications are representative of worst-case supply
voltage and junction temperature conditions. The parame-
ters included are common to popular designs and typical
applications. Contact the factory for design considerations
requiring more detailed information.

© 2001-2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

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Virtex DC Characteristics
Absolute Maximum Ratings

Symbol Description(1) Units

VCCINT Supply voltage relative to GND (2) –0.5 to 3.0 V
VCCO Supply voltage relative to GND (2) –0.5 to 4.0 V
VREF Input Reference Voltage –0.5 to 3.6 V
Input voltage relative to GND (3) Using VREF –0.5 to 3.6 V
VIN
Internal threshold –0.5 to 5.5 V
VTS Voltage applied to 3-state output –0.5 to 5.5 V
VCC Longest Supply Voltage Rise Time from 1V-2.375V 50 ms
TSTG Storage temperature (ambient) –65 to +150 °C
TJ Junction temperature(4) Plastic Packages +125 °C
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings can cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time can affect device reliability.
2. Power supplies can turn on in any order.
3. For protracted periods (e.g., longer than a day), VIN should not exceed VCCO by more than 3.6 V.
4. For soldering guidelines and thermal considerations, see the Device Packaging infomation on the Xilinx website.

Recommended Operating Conditions

Symbol Description Min Max Units
Input Supply voltage relative to GND, TJ = 0 °C to +85°C Commercial 2.5 – 5% 2.5 + 5% V
VCCINT (1)
Input Supply voltage relative to GND, TJ = –40°C to +100°C Industrial 2.5 – 5% 2.5 + 5% V
Supply voltage relative to GND, TJ = 0 °C to +85°C Commercial 1.4 3.6 V
VCCO (4)
Supply voltage relative to GND, TJ = –40°C to +100°C Industrial 1.4 3.6 V
TIN Input signal transition time 250 ns
Notes:
1. Correct operation is guaranteed with a minimum VCCINT of 2.375 V (Nominal VCCINT –5%). Below the minimum value, all delay
parameters increase by 3% for each 50-mV reduction in VCCINT below the specified range.
2. At junction temperatures above those listed as Operating Conditions, delay parameters do increase. Please refer to the TRCE report.
3. Input and output measurement threshold is ~50% of VCC.
4. Min and Max values for VCCO are I/O Standard dependant.

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DC Characteristics Over Recommended Operating Conditions

Symbol Description Device Min Max Units

Data Retention VCCINT Voltage
VDRINT All 2.0 V
(below which configuration data can be lost)
Data Retention VCCO Voltage
VDRIO All 1.2 V
(below which configuration data can be lost)
ICCINTQ Quiescent VCCINT supply current (1,3) XCV50 50 mA
XCV100 50 mA
XCV150 50 mA
XCV200 75 mA
XCV300 75 mA
XCV400 75 mA
XCV600 100 mA
XCV800 100 mA
XCV1000 100 mA
ICCOQ Quiescent VCCO supply current (1) XCV50 2 mA
XCV100 2 mA
XCV150 2 mA
XCV200 2 mA
XCV300 2 mA
XCV400 2 mA
XCV600 2 mA
XCV800 2 mA
XCV1000 2 mA
IREF VREF current per VREF pin All 20 m A
IL Input or output leakage current All –10 +10 m A
CIN Input capacitance (sample tested) BGA, PQ, HQ, packages All 8 pF
IRPU Pad pull-up (when selected) @ Vin = 0 V, VCCO = 3.3 V (sample
All Note (2) 0.25 mA
tested)
IRPD Pad pull-down (when selected) @ Vin = 3.6 V (sample tested) Note (2) 0.15 mA
Notes:
1. With no output current loads, no active input pull-up resistors, all I/O pins 3-stated and floating.
2. Internal pull-up and pull-down resistors guarantee valid logic levels at unconnected input pins. These pull-up and pull-down resistors
do not guarantee valid logic levels when input pins are connected to other circuits.
3. Multiply ICCINTQ limit by two for industrial grade.

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Power-On Power Supply Requirements

Xilinx FPGAs require a certain amount of supply current during power-on to insure proper device operation. The actual
current consumed depends on the power-on ramp rate of the power supply. This is the time required to reach the nominal
power supply voltage of the device (1) from 0 V. The current is highest at the fastest suggested ramp rate (0 V to nominal
voltage in 2 ms) and is lowest at the slowest allowed ramp rate (0 V to nominal voltage in 50 ms).

Product Description (2) Current Requirement (1,3)

Virtex Family, Commercial Grade Minimum required current supply 500 mA
Virtex Family, Industrial Grade Minimum required current supply 2A
Notes:
1. Ramp rate used for this specification is from 0 - 2.7 VDC. Peak current occurs on or near the internal power-on reset threshold and
lasts for less than 3 ms.
2. Devices are guaranteed to initialize properly with the minimum current available from the power supply as noted above.
3. Larger currents can result if ramp rates are forced to be faster.

DC Input and Output Levels

Values for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed output currents over the
recommended operating conditions at the VOL and VOH test points. Only selected standards are tested. These are chosen
to ensure that all standards meet their specifications. The selected standards are tested at minimum VCCO for each standard
with the respective VOL and VOH voltage levels shown. Other standards are sample tested.

VIL VIH VOL VOH IOL IOH

Input/Output
Standard V, min V, max V, min V, max V, Max V, Min mA mA
LVTTL (1) – 0.5 0.8 2.0 5.5 0.4 2.4 24 –24
LVCMOS2 – 0.5 .7 1.7 5.5 0.4 1.9 12 –12
PCI, 3.3 V – 0.5 44% VCCINT 60% VCCINT VCCO + 0.5 10% VCCO 90% VCCO Note 2 Note 2

PCI, 5.0 V – 0.5 0.8 2.0 5.5 0.55 2.4 Note 2 Note 2

GTL – 0.5 VREF – 0.05 VREF + 0.05 3.6 0.4 n/a 40 n/a
GTL+ – 0.5 VREF – 0.1 VREF + 0.1 3.6 0.6 n/a 36 n/a
HSTL I (3) – 0.5 VREF – 0.1 VREF + 0.1 3.6 0.4 VCCO – 0.4 8 –8
HSTL III – 0.5 VREF – 0.1 VREF + 0.1 3.6 0.4 VCCO – 0.4 24 –8
HSTL IV – 0.5 VREF – 0.1 VREF + 0.1 3.6 0.4 VCCO – 0.4 48 –8
SSTL3 I – 0.5 VREF – 0.2 VREF + 0.2 3.6 VREF – 0.6 VREF + 0.6 8 –8
SSTL3 II – 0.5 VREF – 0.2 VREF + 0.2 3.6 VREF – 0.8 VREF + 0.8 16 –16
SSTL2 I – 0.5 VREF – 0.2 VREF + 0.2 3.6 VREF – 0.61 VREF + 0.61 7.6 –7.6
SSTL2 II – 0.5 VREF – 0.2 VREF + 0.2 3.6 VREF – 0.80 VREF + 0.80 15.2 –15.2
CTT – 0.5 VREF – 0.2 VREF + 0.2 3.6 VREF – 0.4 VREF + 0.4 8 –8
AGP – 0.5 VREF – 0.2 VREF + 0.2 3.6 10% VCCO 90% VCCO Note 2 Note 2

Notes:
1. VOL and VOH for lower drive currents are sample tested.
2. Tested according to the relevant specifications.
3. DC input and output levels for HSTL18 (HSTL I/O standard with VCCO of 1.8 V) are provided in an HSTL white paper on the Xilinx
website.

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Virtex Switching Characteristics

Testing of switching parameters is modeled after testing by the static timing analyzer (TRCE in the Xilinx Develop-
methods specified by MIL-M-38510/605. All devices are ment System) and back-annotated to the simulation net list.
100% functionally tested. Internal timing parameters are All timing parameters assume worst-case operating condi-
derived from measuring internal test patterns. Listed below tions (supply voltage and junction temperature). Values
are representative values. For more specific, more precise, apply to all Virtex devices unless otherwise noted.
and worst-case guaranteed data, use the values reported

IOB Input Switching Characteristics

Input delays associated with the pad are specified for LVTTL levels. For other standards, adjust the delays with the values
shown in , page 6.

Speed Grade
Description Device Symbol Min -6 -5 -4 Units
Propagation Delays
Pad to I output, no delay All TIOPI 0.39 0.8 0.9 1.0 ns, max
Pad to I output, with delay XCV50 TIOPID 0.8 1.5 1.7 1.9 ns, max
XCV100 0.8 1.5 1.7 1.9 ns, max
XCV150 0.8 1.5 1.7 1.9 ns, max
XCV200 0.8 1.5 1.7 1.9 ns, max
XCV300 0.8 1.5 1.7 1.9 ns, max
XCV400 0.9 1.8 2.0 2.3 ns, max
XCV600 0.9 1.8 2.0 2.3 ns, max
XCV800 1.1 2.1 2.4 2.7 ns, max
XCV1000 1.1 2.1 2.4 2.7 ns, max
Pad to output IQ via transparent All TIOPLI 0.8 1.6 1.8 2.0 ns, max
latch, no delay
Pad to output IQ via transparent XCV50 TIOPLID 1.9 3.7 4.2 4.8 ns, max
latch, with delay
XCV100 1.9 3.7 4.2 4.8 ns, max
XCV150 2.0 3.9 4.3 4.9 ns, max
XCV200 2.0 4.0 4.4 5.1 ns, max
XCV300 2.0 4.0 4.4 5.1 ns, max
XCV400 2.1 4.1 4.6 5.3 ns, max
XCV600 2.1 4.2 4.7 5.4 ns, max
XCV800 2.2 4.4 4.9 5.6 ns, max
XCV1000 2.3 4.5 5.1 5.8 ns, max
Sequential Delays
Clock CLK to output IQ All TIOCKIQ 0.2 0.7 0.7 0.8 ns, max
Setup and Hold Times with respect to Clock CLK at IOB input Setup Time / Hold Time
register (1)
Pad, no delay All TIOPICK/TIOICKP 0.8 / 0 1.6 / 0 1.8 / 0 2.0 / 0 ns, min

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Speed Grade
Description Device Symbol Min -6 -5 -4 Units
Pad, with delay XCV50 TIOPICKD/TIOICKPD 1.9 / 0 3.7 / 0 4.1 / 0 4.7 / 0 ns, min
XCV100 1.9 / 0 3.7 / 0 4.1 / 0 4.7 / 0 ns, min
XCV150 1.9 / 0 3.8 / 0 4.3 / 0 4.9 / 0 ns, min
XCV200 2.0 / 0 3.9 / 0 4.4 / 0 5.0 / 0 ns, min
XCV300 2.0 / 0 3.9 / 0 4.4 / 0 5.0 / 0 ns, min
XCV400 2.1 / 0 4.1 / 0 4.6 / 0 5.3 / 0 ns, min
XCV600 2.1 / 0 4.2 / 0 4.7 / 0 5.4 / 0 ns, min
XCV800 2.2 / 0 4.4 / 0 4.9 / 0 5.6 / 0 ns, min
XCV1000 2.3 / 0 4.5 / 0 5.0 / 0 5.8 / 0 ns, min
ICE input All TIOICECK/TIOCKICE 0.37/ 0 0.8 / 0 0.9 / 0 1.0 / 0 ns, max
Set/Reset Delays
SR input (IFF, synchronous) All TIOSRCKI 0.49 1.0 1.1 1.3 ns, max
SR input to IQ (asynchronous) All TIOSRIQ 0.70 1.4 1.6 1.8 ns, max
GSR to output IQ All TGSRQ 4.9 9.7 10.9 12.5 ns, max
Notes:
1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed "best-case", but
if a "0" is listed, there is no positive hold time.
2. Input timing for LVTTL is measured at 1.4 V. For other I/O standards, see Table 3.

IOB Input Switching Characteristics Standard Adjustments

Speed Grade
Description Symbol Standard (1) Min -6 -5 -4 Units
Data Input Delay Adjustments
Standard-specific data input delay TILVTTL LVTTL 0 0 0 0 ns
adjustments
TILVCMOS2 LVCMOS2 –0.02 –0.04 –0.04 –0.05 ns
TIPCI33_3 PCI, 33 MHz, 3.3 V –0.05 –0.11 –0.12 –0.14 ns
TIPCI33_5 PCI, 33 MHz, 5.0 V 0.13 0.25 0.28 0.33 ns
TIPCI66_3 PCI, 66 MHz, 3.3 V –0.05 –0.11 –0.12 –0.14 ns
TIGTL GTL 0.10 0.20 0.23 0.26 ns
TIGTLP GTL+ 0.06 0.11 0.12 0.14 ns
TIHSTL HSTL 0.02 0.03 0.03 0.04 ns
TISSTL2 SSTL2 –0.04 –0.08 –0.09 –0.10 ns
TISSTL3 SSTL3 –0.02 –0.04 –0.05 –0.06 ns
TICTT CTT 0.01 0.02 0.02 0.02 ns
TIAGP AGP –0.03 –0.06 –0.07 –0.08 ns
Notes:
1. Input timing for LVTTL is measured at 1.4 V. For other I/O standards, see Table 3.

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IOB Output Switching Characteristics

Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust
the delays with the values shown in IOB Output Switching Characteristics Standard Adjustments, page 8.

Speed Grade
Description Symbol Min -6 -5 -4 Units
Propagation Delays
O input to Pad TIOOP 1.2 2.9 3.2 3.5 ns, max
O input to Pad via transparent latch TIOOLP 1.4 3.4 3.7 4.0 ns, max
3-State Delays
T input to Pad high-impedance (1) TIOTHZ 1.0 2.0 2.2 2.4 ns, max
T input to valid data on Pad TIOTON 1.4 3.1 3.3 3.7 ns, max
T input to Pad high-impedance via
TIOTLPHZ 1.2 2.4 2.6 3.0 ns, max
transparent latch (1)
T input to valid data on Pad via
TIOTLPON 1.6 3.5 3.8 4.2 ns, max
transparent latch
GTS to Pad high impedance (1) TGTS 2.5 4.9 5.5 6.3 ns, max
Sequential Delays
Clock CLK to Pad delay with OBUFT
TIOCKP 1.0 2.9 3.2 3.5 ns, max
enabled (non-3-state)
Clock CLK to Pad high-impedance
TIOCKHZ 1.1 2.3 2.5 2.9 ns, max
(synchronous) (1)
Clock CLK to valid data on Pad delay, plus
TIOCKON 1.5 3.4 3.7 4.1 ns, max
enable delay for OBUFT
Setup and Hold Times before/after Clock CLK (2) Setup Time / Hold Time
O input TIOOCK/TIOCKO 0.51 / 0 1.1 / 0 1.2 / 0 1.3 / 0 ns, min
OCE input TIOOCECK/TIOCKOCE 0.37 / 0 0.8 / 0 0.9 / 0 1.0 / 0 ns, min
SR input (OFF) TIOSRCKO/TIOCKOSR 0.52 / 0 1.1 / 0 1.2 / 0 1.4 / 0 ns, min
3-State Setup Times, T input TIOTCK/TIOCKT 0.34 / 0 0.7 / 0 0.8 / 0 0.9 / 0 ns, min
3-State Setup Times, TCE input TIOTCECK/TIOCKTCE 0.41 / 0 0.9 / 0 0.9 / 0 1.1 / 0 ns, min
3-State Setup Times, SR input (TFF) TIOSRCKT/TIOCKTSR 0.49 / 0 1.0 / 0 1.1 / 0 1.3 / 0 ns, min
Set/Reset Delays
SR input to Pad (asynchronous) TIOSRP 1.6 3.8 4.1 4.6 ns, max
SR input to Pad high-impedance
TIOSRHZ 1.6 3.1 3.4 3.9 ns, max
(asynchronous) (1)
SR input to valid data on Pad
TIOSRON 2.0 4.2 4.6 5.1 ns, max
(asynchronous)
GSR to Pad TIOGSRQ 4.9 9.7 10.9 12.5 ns, max
Notes:
1. 3-state turn-off delays should not be adjusted.
2. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but
if a "0" is listed, there is no positive hold time.

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IOB Output Switching Characteristics Standard Adjustments

Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust
the delays by the values shown.

Speed Grade
Unit
Description Symbol Standard (1) Min -6 -5 -4 s
Output Delay Adjustments
Standard-specific adjustments for TOLVTTL_S2 LVTTL, Slow, 2 mA 4.2 14.7 15.8 17.0 ns
output delays terminating at pads
TOLVTTL_S4 4 mA 2.5 7.5 8.0 8.6 ns
(based on standard capacitive load,
Csl) TOLVTTL_S6 6 mA 1.8 4.8 5.1 5.6 ns
TOLVTTL_S8 8 mA 1.2 3.0 3.3 3.5 ns
TOLVTTL_S12 12 mA 1.0 1.9 2.1 2.2 ns
TOLVTTL_S16 16 mA 0.9 1.7 1.9 2.0 ns
TOLVTTL_S24 24 mA 0.8 1.3 1.4 1.6 ns
TOLVTTL_F2 LVTTL, Fast, 2mA 1.9 13.1 14.0 15.1 ns
TOLVTTL_F4 4 mA 0.7 5.3 5.7 6.1 ns
TOLVTTL_F6 6 mA 0.2 3.1 3.3 3.6 ns
TOLVTTL_F8 8 mA 0.1 1.0 1.1 1.2 ns
TOLVTTL_F12 12 mA 0 0 0 0 ns
TOLVTTL_F16 16 mA –0.10 –0.05 –0.05 –0.05 ns
TOLVTTL_F24 24 mA –0.10 –0.20 –0.21 –0.23 ns
TOLVCMOS2 LVCMOS2 0.10 0.10 0.11 0.12 ns
TOPCI33_3 PCI, 33 MHz, 3.3 V 0.50 2.3 2.5 2.7 ns
TOPCI33_5 PCI, 33 MHz, 5.0 V 0.40 2.8 3.0 3.3 ns
TOPCI66_3 PCI, 66 MHz, 3.3 V 0.10 –0.40 –0.42 –0.46 ns
TOGTL GTL 0.6 0.50 0.54 0.6 ns
TOGTLP GTL+ 0.7 0.8 0.9 1.0 ns
TOHSTL_I HSTL I 0.10 –0.50 –0.53 –0.5 ns
TOHSTL_III HSTL III –0.10 –0.9 –0.9 –1.0 ns
TOHSTL_IV HSTL IV –0.20 –1.0 –1.0 –1.1 ns
TOSSTL2_I SSTL2 I –0.10 –0.50 –0.53 –0.5 ns
TOSSLT2_II SSTL2 II –0.20 –0.9 –0.9 –1.0 ns
TOSSTL3_I SSTL3 I –0.20 –0.50 –0.53 –0.5 ns
TOSSTL3_II SSTL3 II –0.30 –1.0 –1.0 –1.1 ns
TOCTT CTT 0 –0.6 –0.6 –0.6 ns
TOAGP AGP 0 –0.9 –0.9 –1.0 ns
Notes:
1. Output timing is measured at 1.4 V with 35 pF external capacitive load for LVTTL. For other I/O standards and different loads, see
Table 2 and Table 3.

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Calculation of Tioop as a Function of For other capacitive loads, use the formulas below to calcu-
Capacitance late the corresponding Tioop.

Tioop is the propagation delay from the O Input of the IOB to Tioop = Tioop + Topadjust + (Cload – Csl) * fl
the pad. The values for Tioop were based on the standard Where:
capacitive load (Csl) for each I/O standard as listed in
Table 2. Topadjust is reported above in the Output Delay
Adjustment section.

Table 2: Constants for Calculating Tioop Cload is the capacitive load for the design.

Csl fl
Standard (pF) (ns/pF) Table 3: Delay Measurement Methodology
LVTTL Fast Slew Rate, 2mA drive 35 0.41 Meas. VREF
LVTTL Fast Slew Rate, 4mA drive 35 0.20 Standard VL (1) VH (1) Point Typ (2)
LVTTL Fast Slew Rate, 6mA drive 35 0.13 LVTTL 0 3 1.4 -
LVTTL Fast Slew Rate, 8mA drive 35 0.079 LVCMOS2 0 2.5 1.125 -
LVTTL Fast Slew Rate, 12mA drive 35 0.044 PCI33_5 Per PCI Spec -
LVTTL Fast Slew Rate, 16mA drive 35 0.043
PCI33_3 Per PCI Spec -
LVTTL Fast Slew Rate, 24mA drive 35 0.033
PCI66_3 Per PCI Spec -
LVTTL Slow Slew Rate, 2mA drive 35 0.41
GTL VREF –0.2 VREF +0.2 VREF 0.80
LVTTL Slow Slew Rate, 4mA drive 35 0.20
GTL+ VREF –0.2 VREF +0.2 VREF 1.0
LVTTL Slow Slew Rate, 6mA drive 35 0.100
LVTTL Slow Slew Rate, 8mA drive 35 0.086 HSTL Class I VREF –0.5 VREF +0.5 VREF 0.75

LVTTL Slow Slew Rate, 12mA drive 35 0.058 HSTL Class III VREF –0.5 VREF +0.5 VREF 0.90
LVTTL Slow Slew Rate, 16mA drive 35 0.050 HSTL Class IV VREF –0.5 VREF +0.5 VREF 0.90
LVTTL Slow Slew Rate, 24mA drive 35 0.048 SSTL3 I & II VREF –1.0 VREF +1.0 VREF 1.5
LVCMOS2 35 0.041
SSTL2 I & II VREF –0.75 VREF +0.75 VREF 1.25
PCI 33MHz 5V 50 0.050
CTT VREF –0.2 VREF +0.2 VREF 1.5
PCI 33MHZ 3.3 V 10 0.050
AGP VREF – VREF + VREF Per
PCI 66 MHz 3.3 V 10 0.033 AGP
(0.2xVCCO) (0.2xVCCO)
GTL 0 0.014 Spec
GTL+ 0 0.017 Notes:
HSTL Class I 20 0.022 1. Input waveform switches between VLand VH.
2. Measurements are made at VREF (Typ), Maximum, and
HSTL Class III 20 0.016 Minimum. Worst-case values are reported.
HSTL Class IV 20 0.014 3. I/O parameter measurements are made with the capacitance
values shown in Table 2. See Xilinx Application Note
SSTL2 Class I 30 0.028 XAPP133 for appropriate terminations.
SSTL2 Class II 30 0.016 4. I/O standard measurements are reflected in the IBIS model
information except where the IBIS format precludes it.
SSTL3 Class I 30 0.029
SSTL3 Class II 30 0.016
CTT 20 0.035
AGP 10 0.037
Notes:
1. I/O parameter measurements are made with the capacitance
values shown above. See Xilinx Application Note XAPP133
for appropriate terminations.
2. I/O standard measurements are reflected in the IBIS model
information except where the IBIS format precludes it.

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Clock Distribution Guidelines

Speed Grade
Description Device Symbol -6 -5 -4 Units
Global Clock Skew (1)
Global Clock Skew between IOB Flip-flops XCV50 TGSKEWIOB 0.10 0.12 0.14 ns, max
XCV100 0.12 0.13 0.15 ns, max
XCV150 0.12 0.13 0.15 ns, max
XCV200 0.13 0.14 0.16 ns, max
XCV300 0.14 0.16 0.18 ns, max
XCV400 0.13 0.13 0.14 ns, max
XCV600 0.14 0.15 0.17 ns, max
XCV800 0.16 0.17 0.20 ns, max
XCV1000 0.20 0.23 0.25 ns, max
Notes:
1. These clock-skew delays are provided for guidance only. They reflect the delays encountered in a typical design under worst-case
conditions. Precise values for a particular design are provided by the timing analyzer.

Clock Distribution Switching Characteristics

Speed Grade
Description Symbol Min -6 -5 -4 Units
GCLK IOB and Buffer
Global Clock PAD to output. TGPIO 0.33 0.7 0.8 0.9 ns, max
Global Clock Buffer I input to O output TGIO 0.34 0.7 0.8 0.9 ns, max

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I/O Standard Global Clock Input Adjustments

Speed Grade
Description Symbol Standard (1) Min -6 -5 -4 Units
Data Input Delay Adjustments
Standard-specific global clock input TGPLVTTL LVTTL 0 0 0 0 ns,
delay adjustments max
TGPLVCMOS LVCMOS2 –0.02 –0.04 –0.04 –0.05 ns,
2 max
TGPPCI33_3 PCI, 33 MHz, 3.3 –0.05 –0.11 –0.12 –0.14 ns,
V max
TGPPCI33_5 PCI, 33 MHz, 5.0 0.13 0.25 0.28 0.33 ns,
V max
TGPPCI66_3 PCI, 66 MHz, 3.3 –0.05 –0.11 –0.12 –0.14 ns,
V max
TGPGTL GTL 0.7 0.8 0.9 0.9 ns,
max
TGPGTLP GTL+ 0.7 0.8 0.8 0.8 ns,
max
TGPHSTL HSTL 0.7 0.7 0.7 0.7 ns,
max
TGPSSTL2 SSTL2 0.6 0.52 0.51 0.50 ns,
max
TGPSSTL3 SSTL3 0.6 0.6 0.55 0.54 ns,
max
TGPCTT CTT 0.7 0.7 0.7 0.7 ns,
max
TGPAGP AGP 0.6 0.54 0.53 0.52 ns,
max
Notes:
1. Input timing for GPLVTTL is measured at 1.4 V. For other I/O standards, see Table 3.

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CLB Switching Characteristics

Delays originating at F/G inputs vary slightly according to the input used. The values listed below are worst-case. Precise
values are provided by the timing analyzer.

Speed Grade
Description Symbol Min -6 -5 -4 Units
Combinatorial Delays
4-input function: F/G inputs to X/Y outputs TILO 0.29 0.6 0.7 0.8 ns, max
5-input function: F/G inputs to F5 output TIF5 0.32 0.7 0.8 0.9 ns, max
5-input function: F/G inputs to X output TIF5X 0.36 0.8 0.8 1.0 ns, max
6-input function: F/G inputs to Y output via F6 MUX TIF6Y 0.44 0.9 1.0 1.2 ns, max
6-input function: F5IN input to Y output TF5INY 0.17 0.32 0.36 0.42 ns, max
Incremental delay routing through transparent latch TIFNCTL 0.31 0.7 0.7 0.8 ns, max
to XQ/YQ outputs
BY input to YB output TBYYB 0.27 0.53 0.6 0.7 ns, max
Sequential Delays
FF Clock CLK to XQ/YQ outputs TCKO 0.54 1.1 1.2 1.4 ns, max
Latch Clock CLK to XQ/YQ outputs TCKLO 0.6 1.2 1.4 1.6 ns, max
Setup and Hold Times before/after Clock CLK (1) Setup Time / Hold Time
4-input function: F/G Inputs TICK/TCKI 0.6 / 0 1.2 / 0 1.4 / 0 1.5 / 0 ns, min
5-input function: F/G inputs TIF5CK/TCKIF5 0.7 / 0 1.3 / 0 1.5 / 0 1.7 / 0 ns, min
6-input function: F5IN input TF5INCK/TCKF5IN 0.46 / 0 1.0 / 0 1.1 / 0 1.2 / 0 ns, min
6-input function: F/G inputs via F6 MUX TIF6CK/TCKIF6 0.8 / 0 1.5 / 0 1.7 / 0 1.9 / 0 ns, min
BX/BY inputs TDICK/TCKDI 0.30 / 0 0.6 / 0 0.7 / 0 0.8 / 0 ns, min
CE input TCECK/TCKCE 0.37 / 0 0.8 / 0 0.9 / 0 1.0 / 0 ns, min
SR/BY inputs (synchronous) TRCKTCKR 0.33 / 0 0.7 / 0 0.8 / 0 0.9 / 0 ns, min
Clock CLK
Minimum Pulse Width, High TCH 0.8 1.5 1.7 2.0 ns, min
Minimum Pulse Width, Low TCL 0.8 1.5 1.7 2.0 ns, min
Set/Reset
Minimum Pulse Width, SR/BY inputs TRPW 1.3 2.5 2.8 3.3 ns, min
Delay from SR/BY inputs to XQ/YQ outputs TRQ 0.54 1.1 1.3 1.4 ns, max
(asynchronous)
Delay from GSR to XQ/YQ outputs TIOGSRQ 4.9 9.7 10.9 12.5 ns, max
Toggle Frequency (MHz) (for export control) FTOG (MHz) 625 333 294 250 MHz
Notes:
1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed "best-case", but
if a "0" is listed, there is no positive hold time.

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CLB Arithmetic Switching Characteristics

Setup times not listed explicitly can be approximated by decreasing the combinatorial delays by the setup time adjustment
listed. Precise values are provided by the timing analyzer.

Speed Grade
Description Symbol Min -6 -5 -4 Units
Combinatorial Delays
F operand inputs to X via XOR TOPX 0.37 0.8 0.9 1.0 ns, max
F operand input to XB output TOPXB 0.54 1.1 1.3 1.4 ns, max
F operand input to Y via XOR TOPY 0.8 1.5 1.7 2.0 ns, max
F operand input to YB output TOPYB 0.8 1.5 1.7 2.0 ns, max
F operand input to COUT output TOPCYF 0.6 1.2 1.3 1.5 ns, max
G operand inputs to Y via XOR TOPGY 0.46 1.0 1.1 1.2 ns, max
G operand input to YB output TOPGYB 0.8 1.6 1.8 2.1 ns, max
G operand input to COUT output TOPCYG 0.7 1.3 1.4 1.6 ns, max
BX initialization input to COUT TBXCY 0.41 0.9 1.0 1.1 ns, max
CIN input to X output via XOR TCINX 0.21 0.41 0.46 0.53 ns, max
CIN input to XB TCINXB 0.02 0.04 0.05 0.06 ns, max
CIN input to Y via XOR TCINY 0.23 0.46 0.52 0.6 ns, max
CIN input to YB TCINYB 0.23 0.45 0.51 0.6 ns, max
CIN input to COUT output TBYP 0.05 0.09 0.10 0.11 ns, max
Multiplier Operation
F1/2 operand inputs to XB output via AND TFANDXB 0.18 0.36 0.40 0.46 ns, max
F1/2 operand inputs to YB output via AND TFANDYB 0.40 0.8 0.9 1.1 ns, max
F1/2 operand inputs to COUT output via AND TFANDCY 0.22 0.43 0.48 0.6 ns, max
G1/2 operand inputs to YB output via AND TGANDYB 0.25 0.50 0.6 0.7 ns, max
G1/2 operand inputs to COUT output via AND TGANDCY 0.07 0.13 0.15 0.17 ns, max
Setup and Hold Times before/after Clock CLK (1) Setup Time / Hold Time
CIN input to FFX TCCKX/TCKCX 0.50 / 0 1.0 / 0 1.2 / 0 1.3 / 0 ns, min
CIN input to FFY TCCKY/TCKCY 0.53 / 0 1.1 / 0 1.2 / 0 1.4 / 0 ns, min
Notes:
1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but
if a "0" is listed, there is no positive hold time.

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Product Specification 1-800-255-7778 13
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CLB SelectRAM Switching Characteristics

Speed Grade
Description Symbol Min -6 -5 -4 Units
Sequential Delays
Clock CLK to X/Y outputs (WE active) 16 x 1 mode TSHCKO16 1.2 2.3 2.6 3.0 ns, max
Clock CLK to X/Y outputs (WE active) 32 x 1 mode TSHCKO32 1.2 2.7 3.1 3.5 ns, max
Shift-Register Mode
Clock CLK to X/Y outputs TREG 1.2 3.7 4.1 4.7 ns, max
Setup and Hold Times before/after Clock CLK (1) Setup Time / Hold Time
F/G address inputs TAS/TAH 0.25 / 0 0.5 / 0 0.6 / 0 0.7 / 0 ns, min
BX/BY data inputs (DIN) TDS/TDH 0.34 / 0 0.7 / 0 0.8 / 0 0.9 / 0 ns, min
CE input (WE) TWS/TWH 0.38 / 0 0.8 / 0 0.9 / 0 1.0 / 0 ns, min
Shift-Register Mode
BX/BY data inputs (DIN) TSHDICK 0.34 0.7 0.8 0.9 ns, min
CE input (WS) TSHCECK 0.38 0.8 0.9 1.0 ns, min
Clock CLK
Minimum Pulse Width, High TWPH 1.2 2.4 2.7 3.1 ns, min
Minimum Pulse Width, Low TWPL 1.2 2.4 2.7 3.1 ns, min
Minimum clock period to meet address write cycle TWC 2.4 4.8 5.4 6.2 ns, min
time
Shift-Register Mode
Minimum Pulse Width, High TSRPH 1.2 2.4 2.7 3.1 ns, min
Minimum Pulse Width, Low TSRPL 1.2 2.4 2.7 3.1 ns, min
Notes:
1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but
if a "0" is listed, there is no positive hold time.

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Block RAM Switching Characteristics

Speed Grade
Description Symbol Min -6 -5 -4 Units
Sequential Delays
Clock CLK to DOUT output TBCKO 1.7 3.4 3.8 4.3 ns, max
Setup and Hold Times before/after Clock CLK (1) Setup Time / Hold Time
ADDR inputs TBACK/TBCKA 0.6 / 0 1.2 / 0 1.3 / 0 1.5 / 0 ns, min
DIN inputs TBDCK/TBCKD 0.6 / 0 1.2 / 0 1.3 / 0 1.5 / 0 ns, min
EN input TBECK/TBCKE 1.3 / 0 2.6 / 0 3.0 / 0 3.4 / 0 ns, min
RST input TBRCK/TBCKR 1.3 / 0 2.5 / 0 2.7 / 0 3.2 / 0 ns, min
WEN input TBWCK/TBCKW 1.2 / 0 2.3 / 0 2.6 / 0 3.0 / 0 ns, min
Clock CLK
Minimum Pulse Width, High TBPWH 0.8 1.5 1.7 2.0 ns, min
Minimum Pulse Width, Low TBPWL 0.8 1.5 1.7 2.0 ns, min
CLKA -> CLKB setup time for different ports TBCCS 3.0 3.5 4.0 ns, min
Notes:
1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but
if a "0" is listed, there is no positive hold time.

TBUF Switching Characteristics

Speed Grade
Description Symbol Min -6 -5 -4 Units
Combinatorial Delays
IN input to OUT output TIO 0 0 0 0 ns, max
TRI input to OUT output high-impedance TOFF 0.05 0.09 0.10 0.11 ns, max
TRI input to valid data on OUT output TON 0.05 0.09 0.10 0.11 ns, max

JTAG Test Access Port Switching Characteristics

Speed Grade
Description Symbol -6 -5 -4 Units
TMS and TDI Setup times before TCK TTAPTCK 4.0 4.0 4.0 ns, min
TMS and TDI Hold times after TCK TTCKTAP 2.0 2.0 2.0 ns, min
Output delay from clock TCK to output TDO TTCKTDO 11.0 11.0 11.0 ns, max
Maximum TCK clock frequency FTCK 33 33 33 MHz, max

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Virtex Pin-to-Pin Output Parameter Guidelines

Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Listed below are representative values for typical pin locations and normal clock loading. Values are
expressed in nanoseconds unless otherwise noted.

Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, with DLL

Speed Grade
Description Symbol Device Min -6 -5 -4 Units
LVTTL Global Clock Input to Output Delay using TICKOFDLL XCV50 1.0 3.1 3.3 3.6 ns, max
Output Flip-flop, 12 mA, Fast Slew Rate, with DLL.
XCV100 1.0 3.1 3.3 3.6 ns, max
For data output with different standards, adjust
delays with the values shown in Output Delay XCV150 1.0 3.1 3.3 3.6 ns, max
Adjustments.
XCV200 1.0 3.1 3.3 3.6 ns, max
XCV300 1.0 3.1 3.3 3.6 ns, max
XCV400 1.0 3.1 3.3 3.6 ns, max
XCV600 1.0 3.1 3.3 3.6 ns, max
XCV800 1.0 3.1 3.3 3.6 ns, max
XCV1000 1.0 3.1 3.3 3.6 ns, max
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Output timing is measured at 1.4 V with 35 pF external capacitive load for LVTTL. The 35 pF load does not apply to the Min values.
For other I/O standards and different loads, see Table 2 and Table 3.
3. DLL output jitter is already included in the timing calculation.

Global Clock Input-to-Output Delay for LVTTL, 12 mA, Fast Slew Rate, without DLL

Speed Grade
Description Symbol Device Min -6 -5 -4 Units
LVTTL Global Clock Input to Output Delay using TICKOF XCV50 1.5 4.6 5.1 5.7 ns, max
Output Flip-flop, 12 mA, Fast Slew Rate, without DLL.
XCV100 1.5 4.6 5.1 5.7 ns, max
For data output with different standards, adjust
delays with the values shown in Input and Output XCV150 1.5 4.7 5.2 5.8 ns, max
Delay Adjustments.
XCV200 1.5 4.7 5.2 5.8 ns, max
For I/O standards requiring VREF, such as GTL,
GTL+, SSTL, HSTL, CTT, and AGO, an additional XCV300 1.5 4.7 5.2 5.9 ns, max
600 ps must be added.
XCV400 1.5 4.8 5.3 6.0 ns, max
XCV600 1.6 4.9 5.4 6.0 ns, max
XCV800 1.6 4.9 5.5 6.2 ns, max
XCV1000 1.7 5.0 5.6 6.3 ns, max
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Output timing is measured at 1.4 V with 35 pF external capacitive load for LVTTL. The 35 pF load does not apply to the Min values.
For other I/O standards and different loads, see Table 2 and Table 3.

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Minimum Clock-to-Out for Virtex Devices

With DLL Without DLL

I/O Standard All Devices V50 V100 V150 V200 V300 V400 V600 V800 V1000 Units
*LVTTL_S2 5.2 6.0 6.0 6.0 6.0 6.1 6.1 6.1 6.1 6.1 ns
*LVTTL_S4 3.5 4.3 4.3 4.3 4.3 4.4 4.4 4.4 4.4 4.4 ns
*LVTTL_S6 2.8 3.6 3.6 3.6 3.6 3.7 3.7 3.7 3.7 3.7 ns
*LVTTL_S8 2.2 3.1 3.1 3.1 3.1 3.1 3.1 3.2 3.2 3.2 ns
*LVTTL_S12 2.0 2.9 2.9 2.9 2.9 2.9 2.9 3.0 3.0 3.0 ns
*LVTTL_S16 1.9 2.8 2.8 2.8 2.8 2.8 2.8 2.9 2.9 2.9 ns
*LVTTL_S24 1.8 2.6 2.6 2.7 2.7 2.7 2.7 2.7 2.7 2.8 ns
*LVTTL_F2 2.9 3.8 3.8 3.8 3.8 3.8 3.8 3.9 3.9 3.9 ns
*LVTTL_F4 1.7 2.6 2.6 2.6 2.6 2.6 2.6 2.7 2.7 2.7 ns
*LVTTL_F6 1.2 2.0 2.0 2.0 2.1 2.1 2.1 2.1 2.1 2.2 ns
*LVTTL_F8 1.1 1.9 1.9 1.9 1.9 2.0 2.0 2.0 2.0 2.0 ns
*LVTTL_F12 1.0 1.8 1.8 1.8 1.8 1.9 1.9 1.9 1.9 1.9 ns
*LVTTL_F16 0.9 1.7 1.8 1.8 1.8 1.8 1.8 1.8 1.9 1.9 ns
*LVTTL_F24 0.9 1.7 1.7 1.7 1.8 1.8 1.8 1.8 1.8 1.9 ns
LVCMOS2 1.1 1.9 1.9 1.9 2.0 2.0 2.0 2.0 2.0 2.1 ns
PCI33_3 1.5 2.4 2.4 2.4 2.4 2.4 2.4 2.5 2.5 2.5 ns
PCI33_5 1.4 2.2 2.2 2.3 2.3 2.3 2.3 2.3 2.3 2.4 ns
PCI66_3 1.1 1.9 1.9 2.0 2.0 2.0 2.0 2.0 2.1 2.1 ns
GTL 1.6 2.5 2.5 2.5 2.5 2.5 2.5 2.6 2.6 2.6 ns
GTL+ 1.7 2.5 2.5 2.6 2.6 2.6 2.6 2.6 2.6 2.7 ns
HSTL I 1.1 1.9 1.9 1.9 1.9 2.0 2.0 2.0 2.0 2.0 ns
HSTL III 0.9 1.7 1.7 1.8 1.8 1.8 1.8 1.8 1.8 1.9 ns
HSTL IV 0.8 1.6 1.6 1.6 1.7 1.7 1.7 1.7 1.7 1.8 ns
SSTL2 I 0.9 1.7 1.7 1.7 1.7 1.8 1.8 1.8 1.8 1.8 ns
SSTL2 II 0.8 1.6 1.6 1.6 1.6 1.7 1.7 1.7 1.7 1.7 ns
SSTL3 I 0.8 1.6 1.7 1.7 1.7 1.7 1.7 1.7 1.8 1.8 ns
SSTL3 II 0.7 1.5 1.5 1.6 1.6 1.6 1.6 1.6 1.6 1.7 ns
CTT 1.0 1.8 1.8 1.8 1.9 1.9 1.9 1.9 1.9 2.0 ns
AGP 1.0 1.8 1.8 1.9 1.9 1.9 1.9 1.9 1.9 2.0 ns
*S = Slow Slew Rate, F = Fast Slew Rate
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Input and output timing is measured at 1.4 V for LVTTL. For other I/O standards, see Table 3. In all cases, an 8 pF external capacitive
load is used.

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Virtex Pin-to-Pin Input Parameter Guidelines

Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Listed below are representative values for typical pin locations and normal clock loading. Values are
expressed in nanoseconds unless otherwise noted

Global Clock Set-Up and Hold for LVTTL Standard, with DLL

Speed Grade
Description Symbol Device Min -6 -5 -4 Units
Input Setup and Hold Time Relative to Global Clock Input Signal for LVTTL Standard. For data input with different
standards, adjust the setup time delay by the values shown in Input Delay Adjustments.
No Delay TPSDLL/TPHDLL XCV50 0.40 / –0.4 1.7 /–0.4 1.8 /–0.4 2.1 /–0.4 ns,
Global Clock and IFF, with DLL min
XCV100 0.40 /–0.4 1.7 /–0.4 1.9 /–0.4 2.1 /–0.4 ns,
min
XCV150 0.40 /–0.4 1.7 /–0.4 1.9 /–0.4 2.1 /–0.4 ns,
min
XCV200 0.40 /–0.4 1.7 /–0.4 1.9 /–0.4 2.1 /–0.4 ns,
min
XCV300 0.40 /–0.4 1.7 /–0.4 1.9 /–0.4 2.1 /–0.4 ns,
min
XCV400 0.40 /–0.4 1.7 /–0.4 1.9 /–0.4 2.1 /–0.4 ns,
min
XCV600 0.40 /–0.4 1.7 /–0.4 1.9 /–0.4 2.1 /–0.4 ns,
min
XCV800 0.40 /–0.4 1.7 /–0.4 1.9 /–0.4 2.1 /–0.4 ns,
min
XCV1000 0.40 /–0.4 1.7 /–0.4 1.9 /–0.4 2.1 /–0.4 ns,
min
IFF = Input Flip-Flop or Latch
Notes:
1. Set-up time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
2. DLL output jitter is already included in the timing calculation.
3. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but
if a "0" is listed, there is no positive hold time.

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Global Clock Set-Up and Hold for LVTTL Standard, without DLL

Speed Grade
Description Symbol Device Min -6 -5 -4 Units
Input Setup and Hold Time Relative to Global Clock Input Signal for LVTTL Standard. (2) For data input with different
standards, adjust the setup time delay by the values shown in Input Delay Adjustments.
Full Delay TPSFD/TPHFD XCV50 0.6 / 0 2.3 / 0 2.6 / 0 2.9 / 0 ns,
Global Clock and IFF, without min
DLL XCV100 0.6 / 0 2.3 / 0 2.6 / 0 3.0 / 0 ns,
min
XCV150 0.6 / 0 2.4 / 0 2.7 / 0 3.1 / 0 ns,
min
XCV200 0.7 / 0 2.5 / 0 2.8 / 0 3.2 / 0 ns,
min
XCV300 0.7 / 0 2.5 / 0 2.8 / 0 3.2 / 0 ns,
min
XCV400 0.7 / 0 2.6 / 0 2.9 / 0 3.3 / 0 ns,
min
XCV600 0.7 / 0 2.6 / 0 2.9 / 0 3.3 / 0 ns,
min
XCV800 0.7 / 0 2.7 / 0 3.1 / 0 3.5 / 0 ns,
min
XCV1000 0.7 / 0 2.8 / 0 3.1 / 0 3.6 / 0 ns,
min
IFF = Input Flip-Flop or Latch
Notes: Notes:
1. Set-up time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
2. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but
if a "0" is listed, there is no positive hold time.

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DLL Timing Parameters

Switching parameters testing is modeled after testing methods specified by MIL-M-38510/605; all devices are 100 percent
functionally tested. Because of the difficulty in directly measuring many internal timing parameters, those parameters are
derived from benchmark timing patterns. The following guidelines reflect worst-case values across the recommended
operating conditions.

Speed Grade
-6 -5 -4
Description Symbol Min Max Min Max Min Max Units
Input Clock Frequency (CLKDLLHF) FCLKINHF 60 200 60 180 60 180 MHz
Input Clock Frequency (CLKDLL) FCLKINLF 25 100 25 90 25 90 MHz
Input Clock Pulse Width (CLKDLLHF) TDLLPWHF 2.0 - 2.4 - 2.4 - ns
Input Clock Pulse Width (CLKDLL) TDLLPWLF 2.5 - 3.0 3.0 - ns
Notes:
1. All specifications correspond to Commercial Operating Temperatures (0°C to + 85°C).

DLL Clock Tolerance, Jitter, and Phase Information

All DLL output jitter and phase specifications determined through statistical measurement at the package pins using a clock
mirror configuration and matched drivers.

CLKDLLHF CLKDLL
Description Symbol FCLKIN Min Max Min Max Units
Input Clock Period Tolerance TIPTOL - 1.0 - 1.0 ns
Input Clock Jitter Tolerance (Cycle to Cycle) TIJITCC - ± 150 - ± 300 ps
Time Required for DLL to Acquire Lock TLOCK > 60 MHz - 20 - 20 m s
50 - 60 MHz - - - 25 m s
40 - 50 MHz - - - 50 m s
30 - 40 MHz - - - 90 m s
25 - 30 MHz - - - 120 m s
Output Jitter (cycle-to-cycle) for any DLL Clock Output (1) TOJITCC ± 60 ± 60 ps
Phase Offset between CLKIN and CLKO (2) TPHIO ± 100 ± 100 ps
Phase Offset between Clock Outputs on the DLL (3) TPHOO ± 140 ± 140 ps
Maximum Phase Difference between CLKIN and
TPHIOM ± 160 ± 160 ps
CLKO (4)
Maximum Phase Difference between Clock Outputs on
TPHOOM ± 200 ± 200 ps
the DLL (5)
Notes:
1. Output Jitter is cycle-to-cycle jitter measured on the DLL output clock, excluding input clock jitter.
2. Phase Offset between CLKIN and CLKO is the worst-case fixed time difference between rising edges of CLKIN and CLKO,
excluding Output Jitter and input clock jitter.
3. Phase Offset between Clock Outputs on the DLL is the worst-case fixed time difference between rising edges of any two DLL
outputs, excluding Output Jitter and input clock jitter.
4. Maximum Phase Difference between CLKIN an CLKO is the sum of Output Jitter and Phase Offset between CLKIN and CLKO,
or the greatest difference between CLKIN and CLKO rising edges due to DLL alone (excluding input clock jitter).
5. Maximum Phase DIfference between Clock Outputs on the DLL is the sum of Output JItter and Phase Offset between any DLL
clock outputs, or the greatest difference between any two DLL output rising edges sue to DLL alone (excluding input clock jitter).
6. All specifications correspond to Commercial Operating Temperatures (0°C to +85°C).

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Period Tolerance: the allowed input clock period change in nanoseconds.

TCLKIN TCLKIN +_ TIPTOL

Output Jitter: the difference between an ideal Phase Offset and Maximum Phase Difference
reference clock edge and the actual design.

Ideal Period

Actual Period
+ Jitter

+/- Jitter

+ Maximum
Phase Difference

+ Phase Offset

ds003_20c_110399

Figure 1: Frequency Tolerance and Clock Jitter

Revision History
Date Version Revision
11/98 1.0 Initial Xilinx release.
01/99 1.2 Updated package drawings and specs.
02/99 1.3 Update of package drawings, updated specifications.
05/99 1.4 Addition of package drawings and specifications.
05/99 1.5 Replaced FG 676 & FG680 package drawings.
07/99 1.6 Changed Boundary Scan Information and changed Figure 11, Boundary Scan Bit
Sequence. Updated IOB Input & Output delays. Added Capacitance info for different I/O
Standards. Added 5 V tolerant information. Added DLL Parameters and waveforms and
new Pin-to-pin Input and Output Parameter tables for Global Clock Input to Output and
Setup and Hold. Changed Configuration Information including Figures 12, 14, 17 & 19.
Added device-dependent listings for quiescent currents ICCINTQ and ICCOQ. Updated
IOB Input and Output Delays based on default standard of LVTTL, 12 mA, Fast Slew Rate.
Added IOB Input Switching Characteristics Standard Adjustments.
09/99 1.7 Speed grade update to preliminary status, Power-on specification and Clock-to-Out
Minimums additions, "0" hold time listing explanation, quiescent current listing update, and
Figure 6 ADDRA input label correction. Added TIJITCC parameter, changed TOJIT to TOPHASE.
01/00 1.8 Update to speed.txt file 1.96. Corrections for CRs 111036,111137, 112697, 115479,
117153, 117154, and 117612. Modified notes for Recommended Operating Conditions
(voltage and temperature). Changed Bank information for VCCO in CS144 package on p.43.

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Date Version Revision

01/00 1.9 Updated DLL Jitter Parameter table and waveforms, added Delay Measurement
Methodology table for different I/O standards, changed buffered Hex line info and
Input/Output Timing measurement notes.
03/00 2.0 New TBCKO values; corrected FG680 package connection drawing; new note about status
of CCLK pin after configuration.
05/00 2.1 Modified "Pins not listed ..." statement. Speed grade update to Final status.
05/00 2.2 Modified Table 18.
09/00 2.3 • Added XCV400 values to table under Minimum Clock-to-Out for Virtex Devices.
• Corrected Units column in table under IOB Input Switching Characteristics.
• Added values to table under CLB SelectRAM Switching Characteristics.
10/00 2.4 • Corrected Pinout information for devices in the BG256, BG432, and BG560 packages in
Table 18.
• Corrected BG256 Pin Function Diagram.
04/02/01 2.5 • Revised minimums for Global Clock Set-Up and Hold for LVTTL Standard, with DLL.
• Converted file to modularized format. See the Virtex Data Sheet section.
04/19/01 2.6 • Clarified TIOCKP and TIOCKON IOB Output Switching Characteristics descriptors.

07/19/01 2.7 • Under Absolute Maximum Ratings, changed (TSOL) to 220 °C .

07/26/01 2.8 • Removed TSOL parameter and added footnote to Absolute Maximum Ratings table.

10/29/01 2.9 • Updated the speed grade designations used in data sheets, and added Table 1, which
shows the current speed grade designation for each device.
02/01/02 3.0 • Added footnote to DC Input and Output Levels table.

Virtex Data Sheet

The Virtex Data Sheet contains the following modules:
• DS003-1, Virtex 2.5V FPGAs: • DS003-3, Virtex 2.5V FPGAs:
Introduction and Ordering Information (Module 1) DC and Switching Characteristics (Module 3)
• DS003-2, Virtex 2.5V FPGAs: • DS003-4, Virtex 2.5V FPGAs:
Functional Description (Module 2) Pinout Tables (Module 4)

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Field Programmable Gate Arrays
DS003-4 (v2.7) July 19, 2001 0 3 Product Specification

Virtex Pin Definitions

Table 1: Special Purpose Pins
Dedicated
Pin Name Pin Direction Description
GCK0, GCK1, Yes Input Clock input pins that connect to Global Clock Buffers. These pins become
GCK2, GCK3 user inputs when not needed for clocks.
M0, M1, M2 Yes Input Mode pins are used to specify the configuration mode.
CCLK Yes Input or The configuration Clock I/O pin: it is an input for SelectMAP and
Output slave-serial modes, and output in master-serial mode. After configuration,
it is input only, logic level = Don’t Care.
PROGRAM Yes Input Initiates a configuration sequence when asserted Low.
DONE Yes Bidirectional Indicates that configuration loading is complete, and that the start-up
sequence is in progress. The output can be open drain.
INIT No Bidirectional When Low, indicates that the configuration memory is being cleared. The
(Open-drain) pin becomes a user I/O after configuration.
BUSY/ No Output In SelectMAP mode, BUSY controls the rate at which configuration data
DOUT is loaded. The pin becomes a user I/O after configuration unless the
SelectMAP port is retained.
In bit-serial modes, DOUT provides header information to downstream
devices in a daisy-chain. The pin becomes a user I/O after configuration.
D0/DIN, No Input or In SelectMAP mode, D0 - D7 are configuration data pins. These pins
D1, D2, Output become user I/Os after configuration unless the SelectMAP port is
D3, D4, retained.
D5, D6, In bit-serial modes, DIN is the single data input. This pin becomes a user
D7 I/O after configuration.
WRITE No Input In SelectMAP mode, the active-low Write Enable signal. The pin becomes
a user I/O after configuration unless the SelectMAP port is retained.
CS No Input In SelectMAP mode, the active-low Chip Select signal. The pin becomes
a user I/O after configuration unless the SelectMAP port is retained.
TDI, TDO, Yes Mixed Boundary-scan Test-Access-Port pins, as defined in IEEE 1149.1.
TMS, TCK
DXN, DXP Yes N/A Temperature-sensing diode pins. (Anode: DXP, cathode: DXN)
VCCINT Yes Input Power-supply pins for the internal core logic.
VCCO Yes Input Power-supply pins for the output drivers (subject to banking rules)
VREF No Input Input threshold voltage pins. Become user I/Os when an external
threshold voltage is not needed (subject to banking rules).
GND Yes Input Ground

© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

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Virtex Pinout Information

Pinout Tables
See the Xilinx WebLINX web site (http://www.xilinx.com/partinfo/databook.htm) for updates or additional Pinout
information. For convenience, Table 2, Table 3 and Table 4 list the locations of special-purpose and power-supply pins. Pins
not listed are either user I/Os or not connected, depending on the device/package combination. See the Pinout Diagrams
starting on page 17 for any pins not listed for a particular part/package combination.

Table 2: Virtex Pinout Tables (Chip-Scale and QFP Packages)

Pin Name Device CS144 TQ144 PQ/HQ240
GCK0 All K7 90 92
GCK1 All M7 93 89
GCK2 All A7 19 210
GCK3 All A6 16 213
M0 All M1 110 60
M1 All L2 112 58
M2 All N2 108 62
CCLK All B13 38 179
PROGRAM All L12 72 122
DONE All M12 74 120
INIT All L13 71 123
BUSY/DOUT All C11 39 178
D0/DIN All C12 40 177
D1 All E10 45 167
D2 All E12 47 163
D3 All F11 51 156
D4 All H12 59 145
D5 All J13 63 138
D6 All J11 65 134
D7 All K10 70 124
WRITE All C10 32 185
CS All D10 33 184
TDI All A11 34 183
TDO All A12 36 181
TMS All B1 143 2
TCK All C3 2 239
VCCINT All A9, B6, C5, G3, 10, 15, 25, 57, 84, 94, 16, 32, 43, 77, 88, 104,
G12, M5, M9, N6 99, 126 137, 148, 164, 198,
214, 225

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Table 2: Virtex Pinout Tables (Chip-Scale and QFP Packages) (Continued)

Pin Name Device CS144 TQ144 PQ/HQ240
VCCO All Banks 0 and 1: No I/O Banks in this No I/O Banks in this
A2, A13, D7 package: package:
Banks 2 and 3: 1, 17, 37, 55, 73, 92, 15, 30, 44, 61, 76, 90,
B12, G11, M13 109, 128 105, 121, 136, 150, 165,
180, 197, 212, 226, 240
Banks 4 and 5:
N1, N7, N13
Banks 6 and 7:
B2, G2, M2
VREF, Bank 0 XCV50 C4, D6 5, 13 218, 232
(VREF pins are listed XCV100/150 ... + B4 ... + 7 ... + 229
incrementally. Connect
all pins listed for both XCV200/300 N/A N/A ... + 236
the required device XCV400 N/A N/A ... + 215
and all smaller devices
listed in the same XCV600 N/A N/A ... + 230
package.) XCV800 N/A N/A ... + 222
Within each bank, if
input reference voltage
is not required, all
VREF pins are general
I/O.
VREF, Bank 1 XCV50 A10, B8 22, 30 191, 205
(VREF pins are listed XCV100/150 ... + D9 ... + 28 ... + 194
incrementally. Connect
all pins listed for both XCV200/300 N/A N/A ... + 187
the required device XCV400 N/A N/A ... + 208
and all smaller devices
listed in the same XCV600 N/A N/A ... + 193
package.) XCV800 N/A N/A ... + 201
Within each bank, if
input reference voltage
is not required, all
VREF pins are general
I/O.
VREF, Bank 2 XCV50 D11, F10 42, 50 157, 171
(VREF pins are listed XCV100/150 ... + D13 ... + 44 ... + 168
incrementally. Connect
all pins listed for both XCV200/300 N/A N/A ... + 175
the required device XCV400 N/A N/A ... + 154
and all smaller devices
listed in the same XCV600 N/A N/A ... + 169
package.) XCV800 N/A N/A ... + 161
Within each bank, if
input reference voltage
is not required, all
VREF pins are general
I/O.

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Table 2: Virtex Pinout Tables (Chip-Scale and QFP Packages) (Continued)

Pin Name Device CS144 TQ144 PQ/HQ240
VREF, Bank 3 XCV50 H11, K12 60, 68 130, 144
(VREF pins are listed XCV100/150 ... + J10 ... + 66 ... + 133
incrementally. Connect
all pins listed for both XCV200/300 N/A N/A ... + 126
the required device XCV400 N/A N/A ... + 147
and all smaller devices
listed in the same XCV600 N/A N/A ... + 132
package.) XCV800 N/A N/A ... + 140
Within each bank, if
input reference voltage
is not required, all
VREF pins are general
I/O.
VREF, Bank 4 XCV50 L8, L10 79, 87 97, 111
(VREF pins are listed XCV100/150 ... + N10 ... + 81 ... + 108
incrementally. Connect
all pins listed for both XCV200/300 N/A N/A ... + 115
the required device XCV400 N/A N/A ... + 94
and all smaller devices
listed in the same XCV600 N/A N/A ... + 109
package.) XCV800 N/A N/A ... + 101
Within each bank, if
input reference voltage
is not required, all
VREF pins are general
I/O.
VREF, Bank 5 XCV50 L4, L6 96, 104 70, 84
(VREF pins are listed XCV100/150 ... + N4 ... + 102 ... + 73
incrementally. Connect
all pins listed for both XCV200/300 N/A N/A ... + 66
the required device XCV400 N/A N/A ... + 87
and all smaller devices
listed in the same XCV600 N/A N/A ... + 72
package.) XCV800 N/A N/A ... + 80
Within each bank, if
input reference voltage
is not required, all
VREF pins are general
I/O.

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Table 2: Virtex Pinout Tables (Chip-Scale and QFP Packages) (Continued)

Pin Name Device CS144 TQ144 PQ/HQ240
VREF, Bank 6 XCV50 H2, K1 116, 123 36, 50
(VREF pins are listed XCV100/150 ... + J3 ... + 118 ... + 47
incrementally. Connect
all pins listed for both XCV200/300 N/A N/A ... + 54
the required device XCV400 N/A N/A ... + 33
and all smaller devices
listed in the same XCV600 N/A N/A ... + 48
package.) XCV800 N/A N/A ... + 40
Within each bank, if
input reference voltage
is not required, all
VREF pins are general
I/O.
VREF, Bank 7 XCV50 D4, E1 133, 140 9, 23
(VREF pins are listed XCV100/150 ... + D2 ... + 138 ... + 12
incrementally. Connect
all pins listed for both XCV200/300 N/A N/A ... + 5
the required device XCV400 N/A N/A ... + 26
and all smaller devices
listed in the same XCV600 N/A N/A ... + 11
package.) XCV800 N/A N/A ... + 19
Within each bank, if
input reference voltage
is not required, all
VREF pins are general
I/O.
GND All A1, B9, B11, C7, 9, 18, 26, 35, 46, 54, 64 1, 8, 14, 22, 29, 37, 45, 51,
D5, E4, E11, F1, 120, 129, 136, 144, 59, 69, 75, 83, 91, 98, 106,
G10, J1, J12, L3, 112, 119, 129, 135, 143,
L5, L7, L9, N12 151, 158, 166, 172, 182,
190, 196, 204, 211, 219,
227, 233

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Table 3: Virtex Pinout Tables (BGA)

Pin Name Device BG256 BG352 BG432 BG560
GCK0 All Y11 AE13 AL16 AL17
GCK1 All Y10 AF14 AK16 AJ17
GCK2 All A10 B14 A16 D17
GCK3 All B10 D14 D17 A17
M0 All Y1 AD24 AH28 AJ29
M1 All U3 AB23 AH29 AK30
M2 All W2 AC23 AJ28 AN32
CCLK All B19 C3 D4 C4
PROGRAM All Y20 AC4 AH3 AM1
DONE All W19 AD3 AH4 AJ5
INIT All U18 AD2 AJ2 AH5
BUSY/DOUT All D18 E4 D3 D4
D0/DIN All C19 D3 C2 E4
D1 All E20 G1 K4 K3
D2 All G19 J3 K2 L4
D3 All J19 M3 P4 P3
D4 All M19 R3 V4 W4
D5 All P19 U4 AB1 AB5
D6 All T20 V3 AB3 AC4
D7 All V19 AC3 AG4 AJ4
WRITE All A19 D5 B4 D6
CS All B18 C4 D5 A2
TDI All C17 B3 B3 D5
TDO All A20 D4 C4 E6
TMS All D3 D23 D29 B33
TCK All A1 C24 D28 E29
DXN All W3 AD23 AH27 AK29
DXP All V4 AE24 AK29 AJ28

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Table 3: Virtex Pinout Tables (BGA) (Continued)

Pin Name Device BG256 BG352 BG432 BG560
VCCINT XCV50/100 C10, D6, N/A N/A N/A
Notes: D15, F4,
• Superset includes all pins, F17, L3,
including the ones in bold L18, R4,
type. Subset excludes pins in R17, U6,
bold type. U15, V10
• In BG352, for XCV300 all the
XCV150/200/300 Same as A20, C14, A10, A17, B23, N/A
VCCINT pins in the superset
above D10, J24, C14, C19, K3,
must be connected. For
K4, P2, P25, K29, N2, N29,
XCV150/200, VCCINT pins in
V24, W2, T1, T29, W2,
the subset must be
AC10, AE14, W31, AB2,
connected, and pins in bold
type can be left unconnected AE19, AB30, AJ10,
(these unconnected pins B16, D12, AJ16, AK13,
cannot be used as user I/O.) L1, L25, AK19, AK22,
• In BG432, for R23, T1, B26, C7, F1,
XCV400/600/800 all VCCINT AF11, AF16 F30, AE29, AF1,
pins in the superset must be AH8, AH24
connected. For XCV300,
VCCINT pins in the subset XCV400/600/800/1000 N/A N/A Same as above A21, B14, B18,
must be connected, and pins B28, C24, E9,
in bold type can be left E12, F2, H30,
unconnected (these J1, K32, N1,
unconnected pins cannot be N33, U5, U30,
used as user I/O.) Y2, Y31, AD2,
• In BG560, for XCV800/1000 AD32, AG3,
all VCCINT pins in the AG31, AK8,
superset must be connected. AK11, AK17,
For XCV400/600, VCCINT AK20, AL14,
pins in the subset must be AL27, AN25,
connected, and pins in bold
type can be left unconnected
B12, C22, M3,
(these unconnected pins N29, AB2,
cannot be used as user I/O.) AB32, AJ13,
AL22
VCCO, Bank 0 All D7, D8 A17, B25, A21, C29, D21 A22, A26, A30,
D19 B19, B32
VCCO, Bank 1 All D13, D14 A10, D7, A1, A11, D11 A10, A16, B13,
D13 C3, E5
VCCO, Bank 2 All G17, H17 B2, H4, K1 C3, L1, L4 B2, D1, H1, M1,
R2
VCCO, Bank 3 All N17, P17 P4, U1, Y4 AA1, AA4, AJ3 V1, AA2, AD1,
AK1, AL2
VCCO, Bank 4 All U13, U14 AC8, AE2, AH11, AL1, AM2, AM15,
AF10 AL11 AN4, AN8, AN12
VCCO, Bank 5 All U7, U8 AC14, AC20, AH21, AJ29, AL31, AM21,
AF17 AL21 AN18, AN24,
AN30
VCCO, Bank 6 All N4, P4 U26, W23, AA28, AA31, W32, AB33,
AE25 AL31 AF33, AK33,
AM32

DS003-4 (v2.7) July 19, 2001 www.xilinx.com Module 4 of 4

Product Specification 1-800-255-7778 7
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Table 3: Virtex Pinout Tables (BGA) (Continued)

Pin Name Device BG256 BG352 BG432 BG560
VCCO, Bank 7 All G4, H4 G23, K26, A31, L28, L31 C32, D33, K33,
N23 N32, T33
VREF, Bank 0 XCV50 A8, B4 N/A N/A N/A
(VREF pins are listed XCV100/150 ... + A4 A16,C19, N/A N/A
incrementally. Connect all C21
pins listed for both the
XCV200/300 ... + A2 ... + D21 B19, D22, D24, N/A
required device and all
D26
smaller devices listed in the
same package.) XCV400 N/A N/A ... + C18 A19, D20,
Within each bank, if input D26, E23, E27
reference voltage is not
XCV600 N/A N/A ... + C24 ... + E24
required, all VREF pins are
general I/O. XCV800 N/A N/A ... + B21 ... + E21
XCV1000 N/A N/A N/A ... + D29
VREF, Bank 1 XCV50 A17, B12 N/A N/A N/A
(VREF pins are listed XCV100/150 ... + B15 B6, C9, N/A N/A
incrementally. Connect all
C12
pins listed for both the
required device and all XCV200/300 ... + B17 ... + D6 A13, B7, N/A
smaller devices listed in the C6, C10
same package.)
XCV400 N/A N/A ... + B15 A6, D7,
Within each bank, if input
reference voltage is not D11, D16, E15
required, all VREF pins are XCV600 N/A N/A ... + D10 ... + D10
general I/O.
XCV800 N/A N/A ... + B12 ... + D13
XCV1000 N/A N/A N/A ... + E7
VREF, Bank 2 XCV50 C20, J18 N/A N/A N/A
(VREF pins are listed XCV100/150 ... + F19 E2, H2, N/A N/A
incrementally. Connect all
M4
pins listed for both the
required device and all XCV200/300 ... + G18 ... + D2 E2, G3, N/A
smaller devices listed in the J2, N1
same package.)
XCV400 N/A N/A ... + R3 G5, H4,
Within each bank, if input
reference voltage is not L5, P4, R1
required, all VREF pins are XCV600 N/A N/A ... + H1 ... + K5
general I/O.
XCV800 N/A N/A ... + M3 ... + N5
XCV1000 N/A N/A N/A ... + B3

Module 4 of 4 www.xilinx.com DS003-4 (v2.7) July 19, 2001

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Virtex™ 2.5 V Field Programmable Gate Arrays

Table 3: Virtex Pinout Tables (BGA) (Continued)

Pin Name Device BG256 BG352 BG432 BG560
VREF, Bank 3 XCV50 M18, V20 N/A N/A N/A
(VREF pins are listed XCV100/150 ... + R19 R4, V4, Y3 N/A N/A
incrementally. Connect all
XCV200/300 ... + P18 ... + AC2 V2, AB4, AD4, N/A
pins listed for both the
AF3
required device and all
smaller devices listed in the XCV400 N/A N/A ... + U2 V4, W5,
same package.) AD3, AE5, AK2
Within each bank, if input
XCV600 N/A N/A ... + AC3 ... + AF1
reference voltage is not
required, all VREF pins are XCV800 N/A N/A ... + Y3 ... + AA4
general I/O. XCV1000 N/A N/A N/A ... + AH4
VREF, Bank 4 XCV50 V12, Y18 N/A N/A N/A
(VREF pins are listed XCV100/150 ... + W15 AC12, AE5, N/A N/A
incrementally. Connect all AE8,
pins listed for both the
XCV200/300 ... + V14 ... + AE4 AJ7, AL4, AL8, N/A
required device and all
AL13
smaller devices listed in the
same package.) XCV400 N/A N/A ... + AK15 AL7, AL10,
Within each bank, if input AL16, AM4,
reference voltage is not AM14
required, all VREF pins are XCV600 N/A N/A ... + AK8 ... + AL9
general I/O.
XCV800 N/A N/A ... + AJ12 ... + AK13
XCV1000 N/A N/A N/A ... + AN3
VREF, Bank 5 XCV50 V9, Y3 N/A N/A N/A
(VREF pins are listed XCV100/150 ... + W6 AC15, AC18, N/A N/A
incrementally. Connect all
AD20
pins listed for both the
required device and all XCV200/300 ... + V7 ... + AE23 AJ18, AJ25, N/A
smaller devices listed in the AK23, AK27
same package.)
XCV400 N/A N/A ... + AJ17 AJ18, AJ25,
Within each bank, if input AL20, AL24,
reference voltage is not AL29
required, all VREF pins are
general I/O. XCV600 N/A N/A ... + AL24 ... + AM26
XCV800 N/A N/A ... + AH19 ... + AN23
XCV1000 N/A N/A N/A ... + AK28
VREF, Bank 6 XCV50 M2, R3 N/A N/A N/A
(VREF pins are listed XCV100/150 ... + T1 R24, Y26, N/A N/A
incrementally. Connect all AA25,
pins listed for both the
XCV200/300 ... + T3 ... + AD26 V28, AB28, N/A
required device and all
AE30, AF28
smaller devices listed in the
same package.) XCV400 N/A N/A ... + U28 V29, Y32, AD31,
Within each bank, if input AE29, AK32
reference voltage is not XCV600 N/A N/A ... + AC28 ... + AE31
required, all VREF pins are
XCV800 N/A N/A ... + Y30 ... + AA30
general I/O.
XCV1000 N/A N/A N/A ... + AH30

DS003-4 (v2.7) July 19, 2001 www.xilinx.com Module 4 of 4

Product Specification 1-800-255-7778 9
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Virtex™ 2.5 V Field Programmable Gate Arrays

Table 3: Virtex Pinout Tables (BGA) (Continued)

Pin Name Device BG256 BG352 BG432 BG560
VREF, Bank 7 XCV50 G3, H1 N/A N/A N/A
(VREF pins are listed XCV100/150 ... + D1 D26, G26, N/A N/A
incrementally. Connect all
L26
pins listed for both the
required device and all XCV200/300 ... + B2 ... + E24 F28, F31, N/A
smaller devices listed in the J30, N30
same package.)
Within each bank, if input
reference voltage is not XCV400 N/A N/A ... + R31 E31, G31, K31,
required, all VREF pins are P31, T31
general I/O. XCV600 N/A N/A ... + J28 ... + H32
XCV800 N/A N/A ... + M28 ... + L33
XCV1000 N/A N/A N/A ... + D31
GND All C3, C18, A1, A2, A5, A2, A3, A7, A9, A1, A7, A12,
D4, D5, A8, A14, A14, A18, A23, A14, A18, A20,
D9, D10, A19, A22, A25, A29, A30, A24, A29, A32,
D11, A25, A26, B1, B2, B30, A33, B1, B6, B9,
D12, B1, B26, E1, B31, C1, C31, B15, B23, B27,
D16, E26, H1, D16, G1, G31, B31, C2, E1,
D17, E4, H26, N1, J1, J31, P1, P31, F32, G2, G33,
E17, J4, P26, W1, T4, T28, V1, J32, K1, L2,
J17, K4, W26, AB1, V31, AC1, AC31, M33, P1, P33,
K17, L4, AB26, AE1, AE1, AE31, R32, T1, V33,
L17, M4, AE26, AF1, AH16, AJ1, W2, Y1, Y33,
M17, T4, AF2, AF5, AJ31, AK1, AK2, AB1, AC32,
T17, U4, AF8, AF13, AK30, AK31, AD33, AE2,
U5, U9, AF19, AF22, AL2, AL3, AL7, AG1, AG32,
U10, AF25, AF26 AL9 AL14, AL18 AH2, AJ33,
U11, AL23, AL25, AL32, AM3,
U12, AL29, AL30 AM7, AM11,
U16, AM19, AM25,
U17, V3, AM28, AM33,
V18 AN1, AN2, AN5,
AN10, AN14,
AN16, AN20,
AN22, AN27,
AN33
GND (1) All J9, J10, N/A N/A N/A
J11, J12,
K9, K10,
K11, K12,
L9, L10,
L11, L12,
M9, M10,
M11, M12
No Connect All N/A N/A N/A C31, AC2, AK4,
AL3
Notes:
1. 16 extra balls (grounded) at package center.

Module 4 of 4 www.xilinx.com DS003-4 (v2.7) July 19, 2001

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Virtex™ 2.5 V Field Programmable Gate Arrays

Table 4: Virtex Pinout Tables (Fine-Pitch BGA)

Pin Name Device FG256 FG456 FG676 FG680
GCK0 All N8 W12 AA14 AW19
GCK1 All R8 Y11 AB13 AU22
GCK2 All C9 A11 C13 D21
GCK3 All B8 C11 E13 A20
M0 All N3 AB2 AD4 AT37
M1 All P2 U5 W7 AU38
M2 All R3 Y4 AB6 AT35
CCLK All D15 B22 D24 E4
PROGRAM All P15 W20 AA22 AT5
DONE All R14 Y19 AB21 AU5
INIT All N15 V19 Y21 AU2
BUSY/DOUT All C15 C21 E23 E3
D0/DIN All D14 D20 F22 C2
D1 All E16 H22 K24 P4
D2 All F15 H20 K22 P3
D3 All G16 K20 M22 R1
D4 All J16 N22 R24 AD3
D5 All M16 R21 U23 AG2
D6 All N16 T22 V24 AH1
D7 All N14 Y21 AB23 AR4
WRITE All C13 A20 C22 B4
CS All B13 C19 E21 D5
TDI All A15 B20 D22 B3
TDO All B14 A21 C23 C4
TMS All D3 D3 F5 E36
TCK All C4 C4 E6 C36
DXN All R4 Y5 AB7 AV37
DXP All P4 V6 Y8 AU35

DS003-4 (v2.7) July 19, 2001 www.xilinx.com Module 4 of 4

Product Specification 1-800-255-7778 11
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Virtex™ 2.5 V Field Programmable Gate Arrays

Table 4: Virtex Pinout Tables (Fine-Pitch BGA) (Continued)

Pin Name Device FG256 FG456 FG676 FG680
VCCINT All C3, C14, D4, E5, E18, F6, G7, G20, H8, H19, AD5, AD35,
D13, E5, F17, G7, G8, G9, J9, J10, J11, J16, AE5, AE35, AL5,
E12, M5, G14, G15, G16, J17, J18, K9, K18, AL35, AM5,
M12, N4, H7, H16, J7, L9, L18, T9, T18, AM35, AR8,
N13, P3, J16, P7, P16, U9, U18, V9, V10, AR9, AR15,
P14 R7, R16, T7, T8, V11, V16, V17, AR16, AR24,
T9, T14, T15, V18, W8, W19, Y7, AR25, AR31,
T16, U6, U17, Y20 AR32, E8, E9,
V5, V18 E15, E16, E24,
E25, E31, E32,
H5, H35, J5,
J35, R5, R35,
T5, T35
VCCO, Bank 0 All E8, F8 F7, F8, F9, F10 H9, H10, H11, E26, E27, E29,
G10, G11 H12, J12, J13 E30, E33, E34
VCCO, Bank 1 All E9, F9 F13, F14, F15, H15, H16, H17, E6, E7, E10,
F16, G12, G13 H18, J14, J15 E11, E13, E14
VCCO, Bank 2 All H11, H12 G17, H17, J17, J19, K19, L19, F5, G5, K5, L5,
K16, K17, L16 M18, M19, N18 N5, P5
VCCO, Bank 3 All J11, J12 M16, N16, N17, P18, R18, R19, AF5, AG5, AN5,
P17, R17, T17 T19, U19, V19 AK5, AJ5, AP5
VCCO, Bank 4 All L9. M9 T12, T13, U13, V14, V15, W15, AR6, AR7,
U14, U15, U16, W16, W17, W18 AR10, AR11,
AR13, AR14
VCCO, Bank 5 All L8, M8 T10, T11, U7, V12, V13, AR26, AR27,
U8, U9, U10 W9,W10, W11, AR29, AR30,
W12 AR33, AR34
VCCO, Bank 6 All J5, J6 M7, N6, N7, P6, P9, R8, R9, T8, AF35, AG35,
R6, T6 U8, V8 AJ35, AK35,
AN35, AP35
VCCO, Bank 7 All H5, H6 G6, H6, J6, K6, J8, K8, L8, M8, F35, G35, K35,
K7, L7 M9, N9 L35, N35, P35
VREF, Bank 0 XCV50 B4, B7 N/A N/A N/A
(VREF pins are listed XCV100/150 ... + C6 A9, C6, E8 N/A N/A
incrementally. Connect
all pins listed for both XCV200/300 ... + A3 ... + B4 N/A N/A
the required device and XCV400 N/A N/A A12, C11, D6, E8,
all smaller devices G10
listed in the same
package.) XCV600 N/A N/A ... + B7 A33, B28, B30,
C23, C24, D33
Within each bank, if
input reference voltage XCV800 N/A N/A ... + B10 ... + A26
is not required, all VREF XCV1000 N/A N/A N/A ... + D34
pins are general I/O.

Module 4 of 4 www.xilinx.com DS003-4 (v2.7) July 19, 2001

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Table 4: Virtex Pinout Tables (Fine-Pitch BGA) (Continued)

Pin Name Device FG256 FG456 FG676 FG680
VREF, Bank 1 XCV50 B9, C11 N/A N/A N/A
(VREF pins are listed XCV100/150 ... + E11 A18, B13, E14 N/A N/A
incrementally. Connect
all pins listed for both XCV200/300 ... + A14 ... + A19 N/A N/A
the required device and XCV400 N/A N/A A14, C20, C21, N/A
all smaller devices D15, G16
listed in the same
package.) XCV600 N/A N/A ... + B19 B6, B8, B18,
D11, D13, D17
Within each bank, if
input reference voltage XCV800 N/A N/A ... + A17 ... + B14
is not required, all VREF XCV1000 N/A N/A N/A ... + B5
pins are general I/O.
VREF, Bank 2 XCV50 F13, H13 N/A N/A N/A
(VREF pins are listed XCV100/150 ... + F14 F21, H18, K21 N/A N/A
incrementally. Connect
all pins listed for both XCV200/300 ... + E13 ... + D22 N/A N/A
the required device and XCV400 N/A N/A F24, H23, K20, N/A
all smaller devices M23, M26
listed in the same
package.) XCV600 N/A N/A ... + G26 G1, H4, J1, L2,
V5, W3
Within each bank, if
input reference voltage XCV800 N/A N/A ... + K25 ... + N1
is not required, all VREF XCV1000 N/A N/A N/A ... + D2
pins are general I/O.
VREF, Bank 3 XCV50 K16, L14 N/A N/A N/A
(VREF pins are listed XCV100/150 ... + L13 N21, R19, U21 N/A N/A
incrementally. Connect
all pins listed for both XCV200/300 ... + M13 ... + U20 N/A N/A
the required device and XCV400 N/A N/A R23, R25, U21, N/A
all smaller devices W22, W23
listed in the same
package.) XCV600 N/A N/A ... + W26 AC1, AJ2, AK3,
AL4, AR1, Y1
Within each bank, if
input reference voltage XCV800 N/A N/A ... + U25 ... + AF3
is not required, all VREF XCV1000 N/A N/A N/A ... + AP4
pins are general I/O.

DS003-4 (v2.7) July 19, 2001 www.xilinx.com Module 4 of 4

Product Specification 1-800-255-7778 13
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Table 4: Virtex Pinout Tables (Fine-Pitch BGA) (Continued)

Pin Name Device FG256 FG456 FG676 FG680
VREF, Bank 4 XCV50 P9, T12 N/A N/A N/A
(VREF pins are listed XCV100/150 ... + T11 AA13, AB16, N/A N/A
incrementally. Connect AB19
all pins listed for both
the required device and XCV200/300 ... + R13 ... + AB20 N/A N/A
all smaller devices XCV400 N/A N/A AC15, AD18, N/A
listed in the same AD21, AD22,
package.) AF15
Within each bank, if XCV600 N/A N/A ... + AF20 AT19, AU7,
input reference voltage AU17, AV8,
is not required, all VREF AV10, AW11
pins are general I/O.
XCV800 N/A N/A ... + AF17 ... + AV14
XCV1000 N/A N/A N/A ... + AU6
VREF, Bank 5 XCV50 T4, P8 N/A N/A N/A
(VREF pins are listed XCV100/150 ... + R5 W8, Y10, AA5 N/A N/A
incrementally. Connect
all pins listed for both XCV200/300 ... + T2 ... + Y6 N/A N/A
the required device and XCV400 N/A N/A AA10, AB8, AB12, N/A
all smaller devices AC7, AF12
listed in the same
package.) XCV600 N/A N/A ... + AF8 AT27, AU29,
AU31, AV35,
Within each bank, if AW21, AW23
input reference voltage
is not required, all VREF XCV800 N/A N/A ... + AE10 ... + AT25
pins are general I/O. XCV1000 N/A N/A N/A ... + AV36
VREF, Bank 6 XCV50 J3, N1 N/A N/A N/A
(VREF pins are listed XCV100/150 ... + M1 N2, R4, T3 N/A N/A
incrementally. Connect
all pins listed for both XCV200/300 ... + N2 ... + Y1 N/A N/A
the required device and XCV400 N/A N/A AB3, R1, R4, U6, N/A
all smaller devices V5
listed in the same
package.) XCV600 N/A N/A ... + Y1 AB35, AD37,
AH39, AK39,
Within each bank, if AM39, AN36
input reference voltage
is not required, all VREF XCV800 N/A N/A ... + U2 ... + AE39
pins are general I/O. XCV1000 N/A N/A N/A ... + AT39

Module 4 of 4 www.xilinx.com DS003-4 (v2.7) July 19, 2001

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Virtex™ 2.5 V Field Programmable Gate Arrays

Table 4: Virtex Pinout Tables (Fine-Pitch BGA) (Continued)

Pin Name Device FG256 FG456 FG676 FG680
VREF, Bank 7 XCV50 C1, H3 N/A N/A N/A
(VREF pins are listed XCV100/150 ... + D1 E2, H4, K3 N/A N/A
incrementally. Connect
all pins listed for both XCV200/300 ... + B1 ... + D2 N/A N/A
the required device and XCV400 N/A N/A F4, G4, K6, M2, N/A
all smaller devices M5
listed in the same
package.) XCV600 N/A N/A ... + H1 E38, G38, L36,
N36, U36, U38
Within each bank, if
input reference voltage XCV800 N/A N/A ... + K1 ... + N38
is not required, all VREF XCV1000 N/A N/A N/A ... + F36
pins are general I/O.
GND All A1, A16, B2, A1, A22, B2, A1, A26, B2, B9, A1, A2, A3, A37,
B15, F6, F7, B21, C3, C20, B14, B18, B25, A38, A39, AA5,
F10, F11, J9, J10, J11, C3, C24, D4, D23, AA35, AH4,
G6, G7, G8, J12, J13, J14, E5, E22, J2, J25, AH5, AH35,
G9, G10, K9, K10, K11, K10, K11, K12, AH36, AR5,
G11, H7, K12, K13, K14, K13, K14, K15, AR12, AR19,
H8, H9, H10, L9, L10, L11, K16, K17, L10, AR20, AR21,
J7, J8, J9, L12, L13, L14, L11, L12, L13, AR28, AR35,
J10, K6, K7, M9, M10, M11, L14, L15, L16, AT4, AT12, AT20,
K8, K9, K10, M12, M13, M14, L17, M10, M11, AT28, AT36,
K11, L6, L7, N9, N10, N11, M12, M13, M14, AU1, AU3, AU20,
L10, L11, N12, N13, N14, M15, M16, M17, AU37, AU39,
R2, R15, T1, P9, P10, P11, N2, N10, N11, AV1, AV2, AV38,
T16 P12, P13, P14, N12, N13, N14, AV39, AW1,
Y3, Y20, AA2, N15, N16, N17, AW2, AW3,
AA21, AB1, P10, P11, P12, AW37, AW38,
AB22 P13, P14, P15, AW39, B1, B2,
P16, P17, P25, B38, B39, C1,
R10, R11, R12, C3, C20, C37,
R13, R14, R15, C39, D4, D12,
R16, R17, T10, D20, D28, D36,
T11, T12, T13, E5, E12, E19,
T14, T15, T16, E20, E21, E28,
T17, U10, U11, E35, M4, M5,
U12, U13, U14, M35, M36, W5,
U15, U16, U17, W35, Y3, Y4, Y5,
V2, V25, AB5, Y35, Y36, Y37
AB22, AC4, AC23,
AD3, AD24, AE2,
AE9, AE13, AE18,
AE25, AF1, AF26

DS003-4 (v2.7) July 19, 2001 www.xilinx.com Module 4 of 4

Product Specification 1-800-255-7778 15
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Table 4: Virtex Pinout Tables (Fine-Pitch BGA) (Continued)

Pin Name Device FG256 FG456 FG676 FG680
No Connect XCV800 N/A N/A A2, A3, A15, A25, N/A
(No-connect pins are B1, B6, B11, B16,
listed incrementally. All B21, B24, B26,
pins listed for both the C1, C2, C25, C26,
required device and all F2, F6, F21, F25,
larger devices listed in L2, L25, N25, P2,
the same package are T2, T25, AA2,
no connects.) AA6, AA21, AA25,
AD1, AD2, AD25,
AE1, AE3, AE6,
AE11, AE14,
AE16, AE21,
AE24, AE26, AF2,
AF24, AF25
XCV600 N/A N/A same as above N/A
XCV400 N/A N/A ... + A9, A10, A13, N/A
A16, A24, AC1,
AC25, AE12,
AE15, AF3, AF10,
AF11, AF13,
AF14, AF16,
AF18, AF23, B4,
B12, B13, B15,
B17, D1, D25,
H26, J1, K26, L1,
M1, M25, N1, N26,
P1, P26, R2, R26,
T1, T26, U26, V1
XCV300 N/A D4, D19, W4, N/A N/A
W19
XCV200 N/A ... + A2, A6, A12, N/A N/A
B11, B16, C2,
D1, D18, E17,
E19, G2, G22,
L2, L19, M2,
M21, R3, R20,
U3, U18, Y22,
AA1, AA3, AA11,
AA16, AB7,
AB12, AB21,
XCV150 N/A ... + A13, A14, N/A N/A
C8, C9, E13,
F11, H21, J1, J4,
K2, K18, K19,
M17, N1, P1, P5,
P22, R22, W13,
W15, AA9,
AA10, AB8,
AB14

Module 4 of 4 www.xilinx.com DS003-4 (v2.7) July 19, 2001

16 1-800-255-7778 Product Specification
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Virtex™ 2.5 V Field Programmable Gate Arrays

Pinout Diagrams
The following diagrams, CS144 Pin Function Diagram, Table 5: Pinout Diagram Symbols (Continued)
page 17 through FG680 Pin Function Diagram, page 27, Symbol Pin Function
illustrate the locations of special-purpose pins on Virtex
FPGAs. Table 5 lists the symbols used in these diagrams. ❿, ❶, ❷ M0, M1, M2
The diagrams also show I/O-bank boundaries. ➉, ➀, ➁, D0/DIN, D1, D2, D3, D4, D5, D6, D7
➂,
Table 5: Pinout Diagram Symbols
➃, ➄, ➅, ➆
Symbol Pin Function
B DOUT/BUSY
✳ General I/O
D DONE
❄ Device-dependent general I/O, n/c on
smaller devices P PROGRAM
V VCCINT I INIT
v Device-dependent VCCINT, n/c on smaller K CCLK
devices
W WRITE
O VCCO
S CS
R VREF
T Boundary-scan Test Access Port
r Device-dependent VREF, remains I/O on
+ Temperature diode, anode
smaller devices
– Temperature diode, cathode
G Ground
n No connect
Ø, 1, 2, 3 Global Clocks

CS144 Pin Function Diagram

Bank 0 Bank 1
1
2
3
4
5
6
7
8
9
10
11
12
13

A GO✳ ✳✳ 3 2 ✳ V R T T O A
B T O✳ r ✳ V ✳RG✳GO K B
Bank 7 C ✳ ✳ T R V ✳ G ✳ ✳W B ➉ ✳ C Bank 2
D ✳ r ✳RGRO✳ r S R✳ r D
E R ✳✳G ➀G➁✳ E
F G ✳ ✳ ✳ CS144 R ➂ ✳ ✳ F
G ✳ O V ✳(Top view) G O V ✳ G
H ✳R✳✳ ✳ R➃ ✳ H
J G✳ r ✳ r ➅ G➄ J
K R ✳✳✳✳✳Ø✳✳ ➆✳R✳ K
Bank 6 L ✳ ❶GRGRGR GR ✳ P I L Bank 3
M ❿O✳✳ V ✳ 1 ✳ V ✳✳DO M
N O❷ ✳ r ✳ V O✳✳ r ✳GO N
1
2
3
4
5
6
7
8
9
10
11
12
13

Bank 5 Bank 4
Figure 1: CS144 Pin Function Diagram

DS003-4 (v2.7) July 19, 2001 www.xilinx.com Module 4 of 4

Product Specification 1-800-255-7778 17
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Virtex™ 2.5 V Field Programmable Gate Arrays

TQ144 Pin Function Diagram

144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
G T ✳✳R ✳ r ✳G✳✳R ✳✳✳GO✳ V ✳✳R ✳✳G✳ r ✳R ✳✳✳ ❶G ❿O
1 O ❷ 108
2 T ✳ 107
3 ✳ Bank 7 Bank 6 ✳ 106
4 ✳ ✳ 105
5 R R 104
6 ✳ ✳ 103
7 r r 102
8 ✳ ✳ 101
9 G G 100
10 V Bank 0 Bank 5 V 99
11 ✳ ✳ 98
12 ✳ ✳ 97
13 R R 96
14 ✳ ✳ 95
15 V V 94
16 3 TQ144 1 93
17 O O 92
18 G (Top view) G 91
19 2 Ø 90
20 ✳ ✳ 89
21 ✳ ✳ 88
22 R R 87
23 ✳ ✳ 86
24 ✳ ✳ 85
25 V V 84
26 G Bank 1 Bank 4 G 83
27 ✳ ✳ 82
28 r r 81
29 ✳ ✳ 80
30 R R 79
31 ✳ ✳ 78
32 W ✳ 77
33 S ✳ 76
34 T Bank 2 Bank 3 G 75
35 G D 74
36 T O 73
O K B ➉ ✳ R ✳ r ➀ G ➁ ✳ ✳ R ➂ ✳ ✳ G O ✳ V ✳➃ R ✳ ✳ ➄ G ➅ r ✳ R ✳ ➆ I P
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72

Figure 2: TQ144 Pin Function Diagram

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18 1-800-255-7778 Product Specification
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Virtex™ 2.5 V Field Programmable Gate Arrays

PQ240/HQ240 Pin Function Diagram

233

223

213

203

193

183
239

229

219

209

199

189
235

225

215

205

195

185
231

221

211

201

191

181
237

227

217

207

197

187
T ✳ ✳ G ✳ r G V ✳ ✳ G ✳ r 3 G ✳ ✳ R ✳ r ✳ O ✳ r R ✳ r W T T
O ✳ r ✳ R r ✳ O ✳ r ✳ R ✳ V O 2 r ✳ G ✳ ✳ V G r ✳ G ✳ ✳ S G

1 G Bank 0 Bank 1 O
T K 179
3 ✳ B
✳ ➉ 177
5 r ✳
✳ r 175
7 ✳ ✳
G ✳ 173
9 R G
✳ R 171
11 r ✳
r r 169
13 ✳ r
G ➀ 167
15 O Bank 7 Bank 2 G
V O 165
17 ✳ V
✳ ➁ 163
19 r ✳
✳ r 161
21 ✳ ✳
G ✳ 159
23 R G
✳ PQ240/HQ240 R 157
25 ✳ ➂
r (Top view) ✳ 155
27 ✳ r
✳ ✳ 153
29 G ✳
O
Pins are shown staggered G 151
31 ✳ O
V for readability ✳ 149
33 r V
✳ r 147
35 ✳ ✳
R ➃ 145
37 G R
✳ G 143
39 ✳ ✳
r ✳ 141
41 ✳ r
✳ Bank 6 Bank 3 ✳ 139
43 V ➄
O V 137
45 G O
✳ G 135
47 r ➅
r r 133
49 ✳ r
R ✳ 131
51 G R
✳ G 129
53 ✳ ✳
r ✳ 127
55 ✳ r
✳ ✳ 125
57 ✳ ➆
❶ Bank 5 Bank 4 I 123
59 G P
❿ O 121
❷ ✳ r ✳ R r ✳ O ✳ r ✳ R ✳ V O Ø r ✳ G ✳ ✳ V G r ✳ G ✳ ✳ ✳ D
O ✳ ✳ ✳ G ✳ r G V ✳ ✳ G ✳ r 1 G ✳ ✳ R ✳ r ✳ O ✳ r R ✳ r ✳ G
63

73

83

93

103

113
67

77

87

97

107

117
61

71

81

91

101

111
65

75

85

95

105

115
69

79

89

99

109

119

Figure 3: PQ240/HQ240 Pin Function Diagram

DS003-4 (v2.7) July 19, 2001 www.xilinx.com Module 4 of 4

Product Specification 1-800-255-7778 19
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Virtex™ 2.5 V Field Programmable Gate Arrays

BG256 Pin Function Diagram

10
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
8
9
A T r ✳ r ✳ ✳ ✳ R✳ 2 ✳ ✳ ✳ ✳ ✳ ✳ R ✳ W T A
B ✳ r ✳ R ✳ ✳ ✳ ✳ ✳ 3 ✳ R✳ ✳ r ✳ r S K✳ B
C ✳ ✳ G ✳ ✳ ✳ ✳ ✳ ✳ V ✳ ✳ ✳ ✳ ✳ ✳ T G ➉ R C
D r ✳ T G G V O O G G G G O O V G G B ✳ ✳ D
E ✳ ✳ ✳ G Bank 0 Bank 1 G ✳ ✳ ➀ E
F ✳ ✳ ✳ V V ✳ r ✳ F
G ✳ ✳ R O BG256 O r ➁✳ G
H R ✳ ✳ O Bank 7 Bank 2 O ✳ ✳ ✳ H
J ✳ ✳ ✳ G G G G G G R ➂✳ J
K ✳ ✳ ✳ G G G G G G ✳ ✳ ✳ K
L ✳ ✳ V G G G G G G V ✳ ✳ L
M ✳ R ✳ G G G G G G R ➃✳ M
N ✳ ✳ ✳ O Bank 6 Bank 3 O ✳ ✳ ✳ N
P ✳ ✳ ✳ O (Top View) O r ➄✳ P
R ✳ ✳ R V V ✳ r ✳ R
T r ✳ r G Bank 5 Bank 4 G ✳ ✳ ➅ T
U ✳ ✳ ❶ G G V O O G G G G O O V G G I ✳ ✳ U
V ✳ ✳ G + ✳ ✳ r ✳ R V ✳ R✳ r ✳ ✳ ✳ G ➆ R V
W ✳ ❷ – ✳ ✳ r ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ r ✳ ✳ ✳ D✳ W
Y ❿ ✳ R ✳ ✳ ✳ ✳ ✳ ✳ 1 Ø ✳ ✳ ✳ ✳ ✳ ✳ R ✳ P Y
10
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
8
9

DS003_18_100300

Figure 4: BG256 Pin Function Diagram

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20 1-800-255-7778 Product Specification
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Virtex™ 2.5 V Field Programmable Gate Arrays

BG352 Pin Function Diagram

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
1
2
3
4
5
6
7
8
9
A G G ✳ ✳ G ✳ ✳ G ✳ O ✳ ✳ ✳ G ✳ R O ✳ G V ✳ G ✳ ✳ G G A
B G O T ✳ ✳ R ✳ ✳ ✳ ✳ ✳ ✳ ✳ 2 ✳ V ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ O G B
C ✳ ✳ K S✳ ✳ ✳ ✳ R ✳ ✳ R ✳ V ✳ ✳ ✳ ✳ R ✳ R ✳ ✳ T ✳ ✳ C
D ✳ r ➉ T W r O ✳ ✳ V ✳ V O 3 ✳ ✳ ✳ ✳ O ✳ r ✳ T ✳ ✳ R D
E G R ✳ B ✳ r ✳ G E
F ✳ ✳ ✳ ✳ Bank 1 Bank 0 ✳ ✳ ✳ ✳ F
G ➀✳ ✳ ✳ O ✳ ✳ R G
H G R ✳ O ✳ ✳ ✳ G H
J ✳ ✳ ➁✳ ✳ V ✳ ✳ J
K O ✳ ✳V Bank 2 Bank 7 ✳ ✳ ✳ O K
L V ✳ ✳ ✳ ✳ ✳ V R L
M ✳ ✳ ➂R ✳ ✳ ✳ ✳ M
N G ✳ ✳ ✳ BG352 O ✳ ✳ ✳ N
P ✳V ✳ O (Top View) ✳ ✳ V G P
R ✳ ✳ ➃R V R ✳ ✳ R
T V ✳ ✳ ✳ ✳ ✳ ✳ ✳ T
U O ✳ ✳ ➄ Bank 3 Bank 6 ✳ ✳ ✳ O U
V ✳ ✳ ➅R ✳ V ✳ ✳ V
W GV ✳ ✳ O ✳ ✳ G W
Y ✳ ✳ R O ✳ ✳ ✳ R Y
AA ✳ ✳ ✳ ✳ Bank 4 Bank 5 ✳ ✳ R ✳ AA
AB G ✳ ✳ ✳ ❶ ✳ ✳ G AB
AC ✳ r ➆P ✳ ✳ ✳ O ✳ V ✳ R ✳ O R ✳ ✳ R ✳ O ✳ ✳ ❷ ✳ ✳ ✳ AC
AD ✳ I D ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ R ✳ ✳ – ❿ ✳ r AD
AE G O ✳ r R ✳ ✳ R ✳ ✳ ✳ ✳ Ø V ✳ ✳ ✳ ✳ V ✳ ✳ ✳ r + O G AE
AF G G ✳ ✳ G ✳ ✳ G ✳ O V ✳ G 1 ✳ V O ✳ G ✳ ✳ G ✳ ✳ G G AF
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
1
2
3
4
5
6
7
8
9

DS003_19_100600

Figure 5: BG352 Pin Function Diagram

DS003-4 (v2.7) July 19, 2001 www.xilinx.com Module 4 of 4

Product Specification 1-800-255-7778 21
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Virtex™ 2.5 V Field Programmable Gate Arrays

BG432 Pin Function Diagram

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
1
2
3
4
5
6
7
8
9
A O G G ✳ ✳ ✳ G ✳ G V O ✳ R G ✳ 2 V G ✳ ✳ O ✳ G ✳ G ✳ ✳ ✳ G G O A
B G G T W ✳ ✳ R ✳ ✳ ✳ ✳ r ✳ ✳ r ✳ ✳ ✳ R ✳ r ✳ V ✳ ✳ V ✳ ✳ ✳ G G B
C G ➉ O T ✳ R V ✳ ✳ R ✳ ✳ ✳ V ✳ ✳ ✳ r V ✳ ✳ ✳ ✳ r ✳ ✳ ✳ ✳ O ✳ G C
D ✳ ✳ B K S ✳ ✳ ✳ ✳ r O ✳ ✳ ✳ ✳ G 3 ✳ ✳ ✳ O R ✳ R ✳ R ✳ T T ✳ ✳ D
E ✳ R ✳ ✳ ✳ ✳ ✳ ✳ E
F V ✳ ✳ ✳ Bank 1 Bank 0 R ✳ V R F
G G ✳ R ✳ ✳ ✳ ✳ G G
H r ✳ ✳ ✳ ✳ ✳ ✳ ✳ H
J G R ✳ ✳ r ✳ R G J
K ✳ ➁ V ➀ Bank 2 Bank 7 ✳ V ✳ ✳ K
L O ✳ ✳ O O ✳ ✳ O L
M ✳ ✳ r ✳ r ✳ ✳ ✳ M
N R V ✳ ✳ ✳ V R ✳ N
P G ✳ ✳ ➂ ✳ ✳ ✳ G P
R ✳ ✳ r ✳ BG432 ✳ ✳ ✳ r R
T V ✳ ✳ G (Top View) G V ✳ ✳ T
U ✳ r ✳ ✳ r ✳ ✳ ✳ U
V G R ✳ ➃ R ✳ ✳ G V
W ✳ V ✳ ✳ ✳ ✳ ✳ V W
Y ✳ ✳ r ✳ ✳ ✳ r ✳ Y
AA O ✳ ✳ O O ✳ ✳ O AA
AB ➄ V ➅ R Bank 3 Bank 6 R ✳ V ✳ AB
AC G ✳ r ✳ r ✳ ✳ G AC
AD ✳ ✳ ✳ R ✳ ✳ ✳ ✳ AD
AE G ✳ ✳ ✳ ✳ V R G AE
AF V ✳ R ✳ Bank 4 Bank 5 R ✳ ✳ ✳ AF
AG ✳ ✳ ✳ ➆ ✳ ✳ ✳ ✳ AG
AH ✳ ✳ P D ✳ ✳ ✳ V ✳ ✳ O ✳ ✳ ✳ ✳ G ✳ ✳ r ✳ O ✳ ✳ V ✳ ✳ – ❿ ❶ ✳ ✳ AH
AJ G I O ✳ ✳ ✳ R ✳ ✳ V ✳ r ✳ ✳ ✳ V r R ✳ ✳ ✳ ✳ ✳ ✳ R ✳ ✳ ❷ O ✳ G AJ
AK G G ✳ ✳ ✳ ✳ ✳ r ✳ ✳ ✳ ✳ V ✳ r 1 ✳ ✳ V ✳ ✳ V R ✳ ✳ ✳ R ✳ + G G AK
AL O G G R ✳ ✳ G R G ✳ O ✳ R G ✳ Ø ✳ G ✳ ✳ O ✳ G r G ✳ ✳ ✳ G G O AL
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
1
2
3
4
5
6
7
8
9

DS003_21_100300

Figure 6: BG432 Pin Function Diagram

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22 1-800-255-7778 Product Specification
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Virtex™ 2.5 V Field Programmable Gate Arrays

BG560 Pin Function Diagram

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
1
2
3
4
5
6
7
8
9
A G S ✳ ✳ ✳ R G ✳ ✳ O ✳ G ✳ G ✳ O 3 G R G V O ✳ G ✳ O ✳ ✳ G O ✳ G G A
B G O r ✳ ✳ G ✳ ✳ G ✳ ✳ V O V G ✳ ✳ V O ✳ ✳ ✳ G ✳ ✳ ✳ G V ✳ ✳ G O T B
C ✳ G OK ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ V ✳V ✳ ✳ ✳ ✳ ✳ ✳ n O ✳ C
D O ✳ ✳ B T W R ✳ ✳ r R ✳ r ✳ ✳ R 2 ✳ ✳ R ✳ ✳ ✳ ✳ ✳ R ✳ ✳ r ✳ r ✳ O D
E G ✳ ✳ ➉O T r ✳V ✳ ✳ V ✳ ✳ R ✳ ✳ ✳ ✳ ✳ r ✳ R r ✳ ✳ R ✳ T ✳ R ✳ ✳ E
F ✳ V ✳ ✳ ✳ Bank 1 Bank 0 ✳ ✳ ✳ G ✳ F
G ✳ G ✳ ✳ R ✳ ✳ R ✳ G G
H O ✳ ✳ R ✳ ✳ V ✳ r ✳ H
J V ✳ ✳ ✳ ✳ ✳ ✳ ✳ G ✳ J
K G ✳ ➀✳ r Bank 2 Bank 7 ✳ ✳ R V O K
L ✳ G ✳ ➁R ✳ ✳ ✳ ✳ r L
M O ✳ V ✳ ✳ ✳ ✳ ✳ ✳ G M
N V ✳ ✳ ✳ r V ✳ ✳ O V N
P G ✳ ➂R ✳ ✳ ✳ R ✳ G P
R R O ✳ ✳ ✳ BG560 ✳ ✳ ✳ G ✳ R
T G ✳ ✳ ✳ ✳ (Top View) ✳ ✳ R ✳ O T
U ✳ ✳ ✳ ✳V ✳ V ✳ ✳ ✳ U
V O ✳ ✳ R ✳ R ✳ ✳ ✳ G V
W ✳ G ✳ ➃R ✳ ✳ ✳ O ✳ W
Y G V ✳ ✳ ✳ ✳ ✳ V R G Y
AA ✳ O ✳ r ✳ ✳ r ✳ ✳ ✳ AA
AB G V ✳ ✳ ➄ ✳ ✳ ✳ V O AB
AC ✳ n ✳ ➅ ✳ Bank 3 Bank 6 ✳ ✳ ✳ G ✳ AC
AD O V R ✳ ✳ ✳ ✳ R V G AD
AE ✳ G ✳ ✳ R R ✳ r ✳ ✳ AE
AF r ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ O AF
AG G ✳ V ✳ ✳ Bank 4 Bank 5 ✳ ✳ V G ✳ AG
AH ✳ G ✳ r I ✳ r ✳ ✳ ✳ AH
AJ ✳ ✳ ✳ ➆D ✳ ✳ ✳ ✳ ✳ ✳ ✳ V ✳ ✳ ✳ 1 R ✳ ✳ ✳ ✳ ✳ ✳ R ✳ ✳ + ❿ ✳ ✳ ✳ G AJ
AK O R ✳ n ✳ ✳ ✳V ✳ ✳V ✳ r ✳ ✳ ✳ V ✳ ✳ V ✳ ✳ ✳ ✳ ✳ ✳ ✳ r – ❶ ✳ R O AK
AL ✳ O n ✳ ✳ ✳ R ✳ r R ✳ ✳ ✳ V ✳ R Ø ✳ ✳ R ✳ V ✳ R ✳ ✳ V ✳ R ✳ O G ✳ AL
AM P O G R ✳ ✳ G ✳ ✳ ✳ G ✳ ✳ R O ✳ ✳ ✳ G ✳ O ✳ ✳ ✳ G r ✳ G ✳ ✳ ✳ O G AM
AN G G r O G ✳ ✳ O ✳ G ✳ O ✳ G ✳ G ✳ O ✳ G ✳ G r O V ✳ G ✳ ✳ O ✳ ❷ G AN
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
1
2
3
4
5
6
7
8
9

DS003_22_100300

Figure 7: BG560 Pin Function Diagram

DS003-4 (v2.7) July 19, 2001 www.xilinx.com Module 4 of 4

Product Specification 1-800-255-7778 23
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Virtex™ 2.5 V Field Programmable Gate Arrays

FG256 Pin Function Diagram

Bank 0 Bank 1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A G✳ r ✳✳✳✳✳✳✳✳✳✳ r T G A
B r G✳R✳✳R 3 R✳✳✳S T G✳ B
C R ✳ V T ✳ r ✳ ✳ 2 ✳ R ✳W V B ✳ C
Bank 7 D r ✳ T V ✳✳✳✳✳✳✳✳V ➉ K ✳ D Bank 2
E ✳✳✳✳ V ✳✳OO✳ r V r ✳✳ ➀ E
F ✳✳✳✳✳GGOOGG✳R r ➁ ✳ F
G ✳✳✳✳✳GGGGGG✳✳✳✳➂ G
H ✳✳R ✳OOGGGGOOR ✳✳✳ H
J ✳ ✳ R ✳ O O G G G G O O ✳ ✳ ✳➃ J
K ✳✳✳✳✳GGGGGG✳✳✳✳R K
L ✳✳✳✳✳GGOOGG✳ r R ✳✳ L
M r ✳✳✳ V ✳✳OO✳✳ V r ✳✳➄ M
Bank 6 N R r ❿ V ✳✳✳Ø✳✳✳✳ V ➆ I ➅ N Bank 3
P ✳❶ V + ✳✳✳RR✳✳✳✳V P ✳ P
R ✳G❷ – r ✳✳ 1 ✳✳✳✳ r DG✳ R
T G r ✳R ✳✳✳✳✳✳ r R ✳✳✳G T
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

Bank 5 Bank 4

FG256
(Top view)
Figure 8: FG256 Pin Function Diagram

Module 4 of 4 www.xilinx.com DS003-4 (v2.7) July 19, 2001

24 1-800-255-7778 Product Specification
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Virtex™ 2.5 V Field Programmable Gate Arrays

FG456 Pin Function Diagram

Bank 0 Bank 1

1
2
3
4
5
6
7
8
9
10
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12
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14
15
16
17
18
19
20
21
22
A G❅ ✳✳✳❅ ✳✳R ✳ 2 ❅ ❅ ❅ ✳✳✳R r WT G A
B ✳G✳ r ✳✳✳✳✳✳❅ ✳R ✳✳❅ ✳✳✳ T G K B
C ✳❅G T ✳R✳❅ ❅ ✳ 3 ✳✳✳✳✳✳✳SGB ✳ C
Bank 7 D ❅ r T n ✳✳✳✳✳✳✳✳✳✳✳✳✳❅ n ➉ ✳ r D Bank 2
E ✳R✳✳V ✳✳R✳✳✳✳❅ R✳✳❅ V ❅ ✳✳✳ E
F ✳✳✳✳✳ V OOOO❅ ✳OOOO V ✳✳✳R ✳ F
G ✳❅ ✳✳✳O V V V OOOO V V V O✳✳✳✳❅ G
H ✳✳✳R ✳O V VOR✳➁❅ ➀ H
J ❅ ✳✳❅ ✳O V GGGGGG V O✳✳✳✳✳ J
K ✳❅ R ✳✳OO GGGGGG OO❅ ❅ ➂ R ✳ K
L ✳❅ ✳✳✳✳O GGGGGG O✳✳❅ ✳✳✳ L
M ✳❅ ✳✳✳✳O GGGGGG O❅ ✳✳✳❅ ✳ M
N ❅ R ✳✳✳OO GGGGGG OO✳✳✳ R➃ N
P ❅ ✳✳✳❅ O V GGGGGG V O✳✳✳✳❅ P
R ✳✳❅ R ✳O V VO✳R❅➄ ❅ R
T ✳✳R ✳✳O V V V OOOO V V V O✳✳✳✳➅ T
U ✳✳❅ ✳ ❶V OOOO✳✳OOOO V ❅ ✳ r R ✳ U
V ✳✳✳✳V + ✳✳✳✳✳✳✳✳✳✳✳V I ✳✳✳ V
Bank 6 W ✳✳✳n ✳✳✳R ✳✳✳Ø❅ ✳❅ ✳✳✳n P ✳✳ W Bank 3
Y r ✳G❷ – r ✳✳✳R 1 ✳✳✳✳✳✳✳DG ➆❅ Y
AA ❅ G ❅ ✳ R ✳ ✳ ✳ ❅ ❅ ❅ ✳ R ✳ ✳ ❅ ✳ ✳ ✳ ✳ G ✳ AA
AB G ❿ ✳ ✳ ✳ ✳ ❅ ❅ ✳ ✳ ✳ ❅ ✳ ❅ ✳ R ✳ ✳ R r ❅ G AB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22 Bank 5 Bank 4

FG456
(Top view)

Figure 9: FG456 Pin Function Diagram

Notes:
Packages FG456 and FG676 are layout compatible.

DS003-4 (v2.7) July 19, 2001 www.xilinx.com Module 4 of 4

Product Specification 1-800-255-7778 25
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Virtex™ 2.5 V Field Programmable Gate Arrays

FG676 Pin Function Diagram

Bank 0 Bank 1

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
1
2
3
4
5
6
7
8
9
A G n n ✳ ✳ ✳ ✳ ✳ ❄ ❄ ✳ R ❄ R n ❄ r ✳ ✳ ✳ ✳ ✳ ✳ ❄ n G A
B n G ✳ ❄ ✳ n r ✳ G r n ❄ ❄ G ❄ n ❄ G r ✳ n ✳ ✳ n G n B
C n n G ✳ ✳ ✳ ✳ ✳ ✳ ✳ R ✳ 2 ✳ ✳ ✳ ✳ ✳ ✳ R R W T G n n C
D ❄ ✳ ✳ G ✳ R ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ R ✳ ✳ ✳ ✳ ✳ ✳ T G K ❄ ✳ D
E ✳ ✳ ✳ ✳ G T ✳ R ✳ ✳ ✳ ✳ 3 ✳ ✳ ✳ ✳ ✳ ✳ ✳ S G B ✳ ✳ ✳ E
Bank 7 F ✳ n ✳ R T n ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ n ➉ ✳ R n ✳ F Bank 2
G ✳ ✳ ✳ R ✳ ✳ V ✳ ✳ R ✳ ✳ ✳ ✳ ✳ R ✳ ✳ ✳ V ✳ ✳ ✳ ✳ ✳ r G
H r ✳ ✳ ✳ ✳ ✳ ✳ V O O O O ✳ ✳ O O O O V ✳ ✳ ✳ R ✳ ✳ ❄ H
J ❄ G ✳ ✳ ✳ ✳ ✳ O V V V O O O O V V V O ✳ ✳ ✳ ✳ ✳ G ✳ J
K r ✳ ✳ ✳ ✳ R ✳ O V G G G G G G G G V O R ✳ ➁ ✳ ➀ r ❄ K
L ❄ n ✳ ✳ ✳ ✳ ✳ O V G G G G G G G G V O ✳ ✳ ✳ ✳ ✳ n ✳ L
M ❄ R ✳ ✳ R ✳ ✳ O O G G G G G G G G O O ✳ ✳ ➂ R ✳ ❄ R M
N ❄ G ✳ ✳ ✳ ✳ ✳ ✳ O G G G G G G G G O ✳ ✳ ✳ ✳ ✳ ✳ n ❄ N
P ❄ n ✳ ✳ ✳ ✳ ✳ ✳ O G G G G G G G G O ✳ ✳ ✳ ✳ ✳ ✳ G ❄ P
R R ❄ ✳ R ✳ ✳ ✳ O O G G G G G G G G O O ✳ ✳ ✳ ➃
R R ❄ R
T ❄ n ✳ ✳ ✳ ✳ ✳ O V G G G G G G G G V O ✳ ✳ ✳ ✳
✳ n ❄ T
U ✳ r ✳ ✳ ✳ R ✳ O V G G G G G G G G V O ✳ R ✳ ➄ ✳ r ❄ U
V ❄ G ✳ ✳ R ✳ ✳ O V V V O O O O V V V O ✳ ✳ ✳ ✳ ➅ G ✳ V
Bank 6 W ✳ ✳ ✳ ✳ ✳ ✳ ❶ V O O O O ✳ ✳ O O O O V ✳ ✳ R R ✳ ✳ r W Bank 3
Y r ✳ ✳
✳ ✳ ✳ V + ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ V I ✳ ✳ ✳ ✳ ✳ Y
AA ✳ n ✳
✳ ✳ n ✳ ✳ ✳ R ✳
✳ ✳ 0 ✳ ✳ ✳ ✳ ✳ ✳ n P ✳ ✳ n ✳ AA
AB ✳ ✳ G ❷
✳ R - R ✳ ✳ ✳
R 1 ✳ ✳ ✳ ✳ ✳ ✳ ✳ D G ➆ ✳ ✳ ✳ AB
AC ❄ ✳ ✳
G ✳ ✳ R ✳ ✳ ✳ ✳
✳ ✳ ✳ R ✳ ✳ ✳ ✳ ✳ ✳ ✳ G ✳ ❄ ✳ AC
AD n n G ❿ ✳ ✳ ✳ ✳ ✳ ✳ ✳
✳ ✳ ✳ ✳ ✳ ✳ R ✳ ✳ R R ✳ G n ✳ AD
AE n G n ✳ ✳ n ✳ ✳ G r n ❄ G n ❄ n ✳ G ✳ ✳ n ✳ ✳ n G n AE
AF G n ❄ ✳ ✳ ✳ ✳ r ✳ ❄ ❄ R ❄ ❄ R ❄ r ❄ ✳ r ✳ ✳ ❄ n n G AF
10
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18
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22
23
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25
26
1
2
3
4
5
6
7
8
9

Bank 5 Bank 4

FG676
(Top view)
fg676a

Figure 10: FG676 Pin Function Diagram

Notes:
Packages FG456 and FG676 are layout compatible.

Module 4 of 4 www.xilinx.com DS003-4 (v2.7) July 19, 2001

26 1-800-255-7778 Product Specification
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Virtex™ 2.5 V Field Programmable Gate Arrays

FG680 Pin Function Diagram

Bank 1 Bank 0

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
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30
31
32
33
34
35
36
37
38
39
1
2
3
4
5
6
7
8
9
A G G G ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ 3 ✳ ✳ ✳ ✳ ✳ r ✳ ✳ ✳ ✳ ✳ ✳ R ✳ ✳ ✳ G G G A
B G G T W r R ✳ R ✳ ✳ ✳ ✳ ✳ r ✳ ✳ ✳ R ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ R ✳ R ✳ ✳ ✳ ✳ ✳ ✳ ✳ G G B
C G ➉ G T ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ G ✳ ✳ R R ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ T G ✳ G C
D ✳ r ✳ G S ✳ ✳ ✳ ✳ ✳ R G R ✳ ✳ ✳ R ✳ ✳ G 2 ✳ ✳ ✳ ✳ ✳ ✳ G ✳ ✳ ✳ ✳ R r ✳ G ✳ ✳ ✳ D
E ✳ ✳ B K G O O V V O O G O O V V ✳ ✳ G G G ✳ ✳ V V O O G O O V V O O G T ✳ R ✳ E
Bank 2 F ✳ ✳ ✳ ✳ O O r ✳ ✳ ✳ F Bank 7
G R ✳ ✳ ✳ O O ✳ ✳ R ✳ G
H ✳ ✳ ✳ R V V ✳ ✳ ✳ ✳ H
J R ✳ ✳ ✳ V V ✳ ✳ ✳ ✳ J
K ✳ ✳ ✳ ✳ O O ✳ ✳ ✳ ✳ K
L ✳ R ✳ ✳ O O R ✳ ✳ ✳ L
M ✳ ✳ ✳ G G G G ✳ ✳ ✳ M
N r ✳ ✳ ✳ O O R ✳ r ✳ N
P ✳ ✳ ➁ ➀ O O ✳ ✳ ✳ ✳ P
R ➂ ✳ ✳ ✳ V V ✳ ✳ ✳ ✳ R
T ✳ ✳ ✳ ✳ V V ✳ ✳ ✳ ✳ T
U ✳ ✳ ✳ ✳ ✳ ✳ R ✳ R ✳ U
V ✳ ✳ ✳ ✳ R ✳ ✳ ✳ ✳ ✳ V
W ✳ ✳ R ✳ G G ✳ ✳ ✳ ✳ W
Y R ✳ G G G FG680 G G G ✳ ✳ Y
AA ✳ ✳ ✳ ✳ G G ✳ ✳ ✳ ✳ AA
( Top View)
AB ✳ ✳ ✳ ✳ ✳ R ✳ ✳ ✳ ✳ AB
✳ ✳ ✳ ✳
Bank 7 ✳ ✳ ✳ ✳ ✳
AC R Bank 2 AC
AD ✳ ✳ ➃ ✳ V V ✳ R ✳ ✳ AD
AE ✳ ✳ ✳ ✳ V V ✳ ✳ ✳ r AE
AF ✳ ✳ r ✳ O O ✳ ✳ ✳ ✳ AF
AG ✳ ➄ ✳ ✳ O O ✳ ✳ ✳ ✳ AG
AH ➅ ✳ ✳ G G G G ✳ ✳ R AH
AJ ✳ R ✳ ✳ O O ✳ ✳ ✳ ✳ AJ
AK ✳ ✳ R ✳ O O ✳ ✳ ✳ R AK
AL ✳ ✳ ✳ R V V ✳ ✳ ✳ ✳ AL
AM ✳ ✳ ✳ ✳ V V ✳ ✳ ✳ R AM
AN ✳ ✳ ✳ ✳ O O R ✳ ✳ ✳ AN
Bank 3 AP ✳ ✳ ✳ r O O ✳ ✳ ✳ ✳ AP Bank 6
AR R ✳ ✳ ➆ G O O V V O O G O O V V ✳ ✳ G G G ✳ ✳ V V O O G O O V V O O G ✳ ✳ ✳ ✳ AR
AT ✳ ✳ ✳ G P ✳ ✳ ✳ ✳ ✳ ✳ G ✳ ✳ ✳ ✳ ✳ ✳ R G ✳ ✳ ✳ ✳ r ✳ R G ✳ ✳ ✳ ✳ ✳ ✳ ❷ G ❿ ✳ r AT
AU G I G ✳ D r R ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ R ✳ ✳ G ✳ 1 ✳ ✳ ✳ ✳ ✳ ✳ R ✳ R ✳ ✳ ✳ + ✳ G ❶ G AU
AV G G ✳ ✳ ✳ ✳ ✳ R ✳ R ✳ ✳ ✳ r ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ R r G G - AV
AW G G G ✳ ✳ ✳ ✳ ✳ ✳ ✳ R ✳ ✳ ✳ ✳ ✳ ✳ ✳ 0 ✳ R ✳ R ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ ✳ G G G AW
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
1
2
3
4
5
6
7
8
9

Bank 4 Bank 5

fg680_12a
Note: AA3, AA4, and AB2 are in Bank 2 Note: AA37 is in Bank 7

Figure 11: FG680 Pin Function Diagram

DS003-4 (v2.7) July 19, 2001 www.xilinx.com Module 4 of 4

Product Specification 1-800-255-7778 27
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Virtex™ 2.5 V Field Programmable Gate Arrays

Revision History
Date Version Revision
11/98 1.0 Initial Xilinx release.
01/99 1.2 Updated package drawings and specs.
02/99 1.3 Update of package drawings, updated specifications.
05/99 1.4 Addition of package drawings and specifications.
05/99 1.5 Replaced FG 676 & FG680 package drawings.
07/99 1.6 Changed Boundary Scan Information and changed Figure 11, Boundary Scan Bit
Sequence. Updated IOB Input & Output delays. Added Capacitance info for different I/O
Standards. Added 5 V tolerant information. Added DLL Parameters and waveforms and
new Pin-to-pin Input and Output Parameter tables for Global Clock Input to Output and
Setup and Hold. Changed Configuration Information including Figures 12, 14, 17 & 19.
Added device-dependent listings for quiescent currents ICCINTQ and ICCOQ. Updated
IOB Input and Output Delays based on default standard of LVTTL, 12 mA, Fast Slew Rate.
Added IOB Input Switching Characteristics Standard Adjustments.
09/99 1.7 Speed grade update to preliminary status, Power-on specification and Clock-to-Out
Minimums additions, "0" hold time listing explanation, quiescent current listing update, and
Figure 6 ADDRA input label correction. Added TIJITCC parameter, changed TOJIT to TOPHASE.
01/00 1.8 Update to speed.txt file 1.96. Corrections for CRs 111036,111137, 112697, 115479,
117153, 117154, and 117612. Modified notes for Recommended Operating Conditions
(voltage and temperature). Changed Bank information for VCCO in CS144 package on p.43.
01/00 1.9 Updated DLL Jitter Parameter table and waveforms, added Delay Measurement
Methodology table for different I/O standards, changed buffered Hex line info and
Input/Output Timing measurement notes.
03/00 2.0 New TBCKO values; corrected FG680 package connection drawing; new note about status
of CCLK pin after configuration.
05/00 2.1 Modified "Pins not listed ..." statement. Speed grade update to Final status.
05/00 2.2 Modified Table 18.
09/00 2.3 • Added XCV400 values to table under Minimum Clock-to-Out for Virtex Devices.
• Corrected Units column in table under IOB Input Switching Characteristics.
• Added values to table under CLB SelectRAM Switching Characteristics.
10/00 2.4 • Corrected pinout info for devices in the BG256, BG432, and BG560 pkgs in Table 18.
• Corrected BG256 Pin Function Diagram.
04/02/01 2.5 • Revised minimums for Global Clock Set-Up and Hold for LVTTL Standard, with DLL.
• Converted file to modularized format. See section Virtex Data Sheet, below.
04/19/01 2.6 • Corrected pinout information for FG676 device in Table 4. (Added AB22 pin.)

07/19/01 2.7 • Clarified VCCINT pinout information and added AE19 pin for BG352 devices in Table 3.
• Changed pinouts listed for BG352 XCV400 devices in banks 0 thru 7.

Virtex Data Sheet

The Virtex Data Sheet contains the following modules:
• DS003-1, Virtex 2.5V FPGAs: • DS003-3, Virtex 2.5V FPGAs:
Introduction and Ordering Information (Module 1) DC and Switching Characteristics (Module 3)
• DS003-2, Virtex 2.5V FPGAs: • DS003-4, Virtex 2.5V FPGAs:
Functional Description (Module 2) Pinout Tables (Module 4)

Module 4 of 4 www.xilinx.com DS003-4 (v2.7) July 19, 2001

28 1-800-255-7778 Product Specification