EE341 - Lecture 3
EE341 - Lecture 3
Microelectronic Design
Lecture 3
25th Jan. 2021
1
Example
2
Example
3
Current Sources
5
CS Stage with Current-Source Load
11
CS Stage with Degeneration
VDD
RD
R1
Vout
C1
Vin Vx
M1
R2
CS Core with Biasing
VDD
RD
R1
Vout
Vin RG C1
Vx
M1
R2 Rs
23
CS Core with Biasing
VDD
RD
R1
Vout
Vin RG C1
Vx
M1
R2 Rs
Rin C2
24
CS Core with Biasing
27
Signal Levels in CG Stage
Voltage Headroom
29
Example
30
I/O Impedances of CG Stage
37
Example of CG Stage