04/11/2018

VHDL
Very High-Speed Integrated Circuits
FPGA & Hardware
programmation Description
VHDL Software
Language
Dr. Mustapha BELARBI Programming
Maître de Conférences A
Département de génie électrique please think Language
Université Ibn Khaldoun de Tiaret
Hardware
2018-2019

VHDL Invariants:
developed by the US department of defense in 1980 1. Case Sensitivity
Dout <= A and B;
doUt <= a AnD b;
standardised by IEEE in the standard 1076 in 1987
3. Comments
first significant revision has been released in 1993 Comments in VHDL begin with “--“ (two consecutive
dashes). The VHDL synthesizer ignores anything after the
two minor revision has been released in 2000 and 2002 introducing
two dashes and up to the end of the line in which the
the use of protected type then relaxing the rules related to the ports dashes appear.

major revision was released on 2009 => IEEE 1076-2008

2. White Space nQ <= In_a or In_b;

nQ <= in_a OR in_b; Entity definition
ENTITY: the entity is the VHDL basic building block.
All the VHDL designs are implemented by entity.
You can imagine the entity as a black box with input
and output ports.

entity my_entity is
port (
input_1 : in std_logic ; input_1 output_1
input_2 : in std_logic ; my_entity
input_2 output_2

output_1 : out std_logic ;

output_2 : out std_logic ;
);
end entity my_entity ;

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Entity example Entity example

entity Flip_Flop_D is
A D
C port ( D : in std_logic ;
B AND_2 CLK : in std_logic ; CLK Q
Flip_Flop_D
RST : in std_logic ;
Q : out std_logic ) ; RST
end entity Flip_Flop_D ;
entity AND_2 is
port ( A : in std_logic ;
B : in std_logic ; entity Flip_Flop_D is
C : out std_logic ) ; port ( D, CLK, RST : in std_logic ;
end entity AND_2 ; Q : out std_logic ) ;
end entity Flip_Flop_D ;

Entity example Entity / Architecture pair

ENTITY: Formalise the interface.
A(7:0)
M(15:0) ARCHITECTURE: describe the functionality.
B(0:7) Multiplier
entity AND2 is
A
port ( A, B : in std_logic ; C
C : out std_logic ) ; B AND2
entity Multiplier is
end entity AND2 ;
port ( A : in std_logic_vector ( 7 downto 0 ) ;
B : in std_logic_vector ( 0 to 7 ) ;
architecture arch_AND2 of AND2 is
C : out std_logic_vector ( 15 downto 0 ) ) ;
begin
end entity Multiplier ;
C <= A and B ;
end architecture arch_AND2 ;

Entity / double architecture Entity / architecture golden rule

ONLY one entity/architecture pair.
architecture behave_AND2 of AND2 is
begin
C <= A and B after 3 ns ; put the architecture description code in the same file
end architecture behave_AND2 ; where is present the entity.
entity AND2 is
port ( A : in std_logic ; architecture struct_AND2 of AND2 is one file per entity/architecture pair.
B : in std_logic ; component lut_and2 is
C : out std_logic ) ; port ( X, Y : in std_logic ; File name equal to entity name.
end entity AND2 ; Z : out std_logic ) ;
end component AND2 ;
begin
U0: lut_and2 entity AND2 is
port map ( X => A , port ( A : in std_logic ;
Y => B , B : in std_logic ; File name: AND2.vhd
Z => C ) ; C : out std_logic ) ;
end architecture struct_AND2 ; end entity AND2 ;

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Concurrency Concurrency Example

entity Example is A E
In typical programming languages such as C++ or Visual Basic, the port ( A : in std_logic ; B AND2
code is executed sequentially following the order of the statement B : in std_logic ; G
in the source files. C : in std_logic ; C OR2
D : in std_logic ;
D AND2
Inside a VHDL architecture there is no specified order in the G : out std_logic ) ; F
end entity Example ;
assignment statement. this means that if you exchange the order of
two assignments the results is the same. G = (A and B) or (C and D)
architecture arch1 of Example is architecture arch2 of Example is
the VHDL is a hardware description language, the statements are signal E : std_logic ; signal E : std_logic ;
implementation of a combinatorial or sequential logic signal F : std_logic ; signal F : std_logic ;
begin begin
E <= A and B ; -- E assignment G <= E or F ; -- G assignment
the order of execution is defined only by event occurring on the
F <= C and D ; -- F assignment F <= C and D ; -- F assignment
signals that the assignments are sensitive to G <= E or F ; -- G assignment E <= A and B ; -- E assignment
end architecture arch1 ; end architecture arch2 ;

Coding styles Coding styles

Behavioural: is the highest level of abstraction

provided by the VHDL.
Architecture 1 Data flow An ENTITY can be implemented in terms of the
desired design algorithm without concern the
Entity

Architecture 2 Behavioural hardware implementation details.

Design at this level is very similar to a
programming language (C++ or Visual Basic).
Architecture 3 Structural This coding style is typical of test benches

Architecture 4 Hybrid

Coding styles Coding styles

Data Flow RTL: at this level, the entity is Structural: at this level the entity is
designed by specifying the data flow. implemented in terms of logic gate depending
The designer is aware of how data flows on the chosen technology.
between hardware registers and how the data is Design at this level is similar to describing a
processed in the design. design in terms of gate level logic diagram.
RTL (Register Transfer Logic) modelling is quite It is strongly technology dependent.
technology independent description. it is very similar to an assembly language.

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Coding styles Structural modelling

Behavioural

Data Flow RTL

Complex
Structural
Design

Structural modelling Structural modelling: Hierarchy

Simple Design 1
TOP LEVEL ENTITY
Complex Simple Design 2 Simple Design 1 Simple Design 2
Design
Simple Design 3 Sub-desing 1 Sub-design 3
Simple Design … Sub-design 2 Sub-design 4

Structural Design Declaration Structural Design Declaration Example

in the declarative part of the architecture, declare the components A
U1:
E
B AND2
instance the component in the architecture statement section U3: G
entity entity_name is C OR2
-- entity declaration U2:
[generic] ( … )
D AND2 F
port (
port_name : port_direction port_type ; component component_identifier
… ); -- component declaration entity AND2 is entity OR2 is
end entity entity_name ; [generic] ( … ) port ( input1 : in std_logic ; port ( input1 : in std_logic ;
port ( … ) ; input2 : in std_logic ; input2 : in std_logic ;
architecture arch_name of entity_name is end component ;
-- architecture declarative part
output : out std_logic ) ; output : out std_logic ) ;
begin end entity AND2 ; end entity OR2 ;
-- architecture statement part Instance_name: component_identifier
end architecture arch_name ; [generic map] ( … ) architecture arch_AND2 of AND2 is architecture arch_OR2 of OR2 is
port map ( begin begin
port_name => signal_name , output <= input1 and input2 ; output <= input1 or input2 ;
… end architecture arch_AND2 ; end architecture arch_OR2 ;
);

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Structural Design entity Example is

port ( A, B, C, D : in std_logic ;
Structural Design entity Example is
port ( A, B, C, D : in std_logic ;
Declaration Example G : out std_logic ) ; Declaration Example G : out std_logic ) ;
A end entity Example ; A end entity Example ;
U1:
E architecture arch of Example is U1:
E architecture arch of Example is
B AND2 -- architecture declarative part B AND2 -- architecture declarative part
U3: G signal E : std_logic ; U3: G ...
C OR2 signal F : std_logic ; C OR2 begin
U2: U2:
D component AND2 is D -- architecture statement part
AND2 F AND2 F
port ( input1 : in std_logic ; U1: AND2
input2 : in std_logic ; port map ( input1 => A ,
entity AND2 is output : out std_logic ) ; entity AND2 is input2 => B ,
port ( input1 : in std_logic ; port ( input1 : in std_logic ;
end component AND2 ; output => E ) ;
input2 : in std_logic ; component OR2 is input2 : in std_logic ;
U2: AND2
output : out std_logic ) ; port ( input1 : in std_logic ; output : out std_logic ) ; port map ( input1 => C ,
end entity AND2 ; end entity AND2 ;
input2 : in std_logic ; input2 => D ,
output : out std_logic ) ; output => F ) ;
entity OR2 is end component OR2 ; entity OR2 is U3: OR2
port ( input1 : in std_logic ; begin port ( input1 : in std_logic ; port map ( input1 => E ,
input2 : in std_logic ; -- architecture statement part input2 : in std_logic ; input2 => F ,
output : out std_logic ) ; … output : out std_logic ) ; output => G ) ;
end entity OR2 ; end architecture arch ; end entity OR2 ; end architecture arch ;