REV-7 Vo034 "HANDBOOK OF SOLID-STATE LOGIC" By Members of the Training Department AMPEX CORPORATIONLt 1.2 3.2 3.2.1 SECTION I: NUMBERING SYSTEMS This first section of the AMPEX Training Department logic handbook may seem at first to have no bearing on Television Tape Recorders, But the material is fundamental to what follows. Some reference is made to electronic circuits - particulary counters - which are not discussed until Sections IV and V. ‘This handbook is intended to supplement similar material available in technical libraries and book stores. The format is outline in nature, is based on lectures given during various training seminars, and is oriented toward "logic" used in AMPEX equipment, ‘Man has always had some means of designating quantities - even if it was as elementary as none, one, or many ~ and the "none" was sometimes ignored in counting systems ~ after all, if there weren't any, why worry about it? Probably at the time that early man began to worry about how many, feet were unshod, Therefore a system based on twenty units of measure seems logical and at least one historical civilization found it 50. Using only ten fingers, eleven events or quantities can be enumerated, if the absence of any events (zero) is considered a valid happening. The ROMAN numbering system had no discrete symbol for zero ‘Man needed to count , and a record of that count became desireable - how else to remember unpaid bills? So notation was developed . ‘One easy way, which you probably have used at one time or another involves drawing sticks on paper, in sand, or clay, or whatever. 1 2 3 4 5 6 7 8 Low Wh THE AIM AHHH A slight advance was special symbols to reduce the fatigue of counting "dashes" or "sticks". 12 3 4 5 6 7 8 9 10 WN HE | Hom Uh ar From the above- a special symbol " }H{ " represents 5 events or quantities,EEE ier | 3.2.2 3.8 3.3.1 3.3.2 3.3.3 3.3.4 ‘Two was shown as "" = " to show one posibility for development of the symbol = ‘The "ROMAN" system carried it further using the letters of the alphabet to designate specific quantities. Pel L = 50 v=5 c 1100 ("C" Note) w =10 D 500 M = 1000 ‘The symbol for 1000 is sometimes chiselled CID or 09 similar to our "infinity" - indicating how values - or taxes - have changed. ‘The notation was additive, the quantity was the sum of the values of the symbols, with very few exceptions which probably were introduced later into the systems, Roman numerals are still occassionally used, motion pictures are one example, In the brief time the date is flashed on the screen, it is difficult to determine when the picture was produced, Computation was difficult, but not impossible, a, Addition D ccL. XX vu 17 + cc x VI 216 D cccocn XXX vit 993 xm) 500 + (1004100+100+100+50) + (10+10410) + (LOH14141) b, Subtraction D eeu xx WL 177 - ee x wa 216 D L x I 561 500 + 50 + 10 + 1 c, Multiplication was a process of continuous addition, roughly the same method still used by 20th century computers. Vv TIMESV =V+V + V+V +V = XXV x x41 4.1 412 4.2.1 4.2.2 d, Division was a practice, of continuous subtraction, How many V's in XXV XXV - Vv XX 1 xX - Vv xXVV-V=XV 2 xV-VvVoo= x 3 vv -VvVoo2 Vv 4 v-v ___{no symbol for zero) 5 Some where in history ~ probably India ~ a new concept arose, It included a symbol for zero, and the quantities 1 through 9, There were no more symbols. The Symbols o-1-2-83-4-5-6-7-8-9 9+1 = 0, carry 1 to next position. ‘Thus arises the concept of position - the place relation of the ten digits available. 1 9 99 +1 +1 er carry 1 T00 carry 1 —— {carry 2 ‘The numbers on the right move from 0 to 9; then the next column moves from 0 to 9, and so on for as many "places" as necessary, ‘The number on the right is the least significant with respect to the overall quantity represented. ‘The decimal system is based of powers of ten, 10°, 101, 107, 10%, representing numerical value of 1,.10, 100, 1000, Any number raised to zero power equals 1, ‘The system is referred to as a Base ten, or Radix 10 system. 1-34.2.3 4,3 4.3.1 44, 4.4.1 ‘A decimal can be broken down as follows. ‘Most Significant Character ‘The BASE, or RADIX, of the system defines the number of permissable discrete Least (LSC). 7x10° Significant Character 0.x 10! =0 x 10 = 0000 1x10" =1x 100 = 0100 3x10° x 1 = 0007 = 3 x 1000 = 3000 SUM 3107 Lsc Msc symbols, and power of that decimal number define the weight of the symbols. ‘A BASE 8 system uses power of 8: 8°, 8!, 8%, 8°, (1,864,512). a, The only permitted characters are 0,1,2,3,4,5,6,7. A binary numbering system, Base 2 or Radix 2, uses the chargcters."1" and "9", with placement determined by power of 2: 29(1), 21(2), 22(4), 23(6),24(16), 25 (32), etc. EVENT DECIMAL 00 02 03 04 05 06 08 09 10 cry 12 13 14 15 1-4 3 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 o 1 0 1 0 1 0 1 0 1 0 1 0 1 0 144,2 4.4.3 ‘This is a 4 bit system, with 24(16) possible combinations, which can represent the decimal values from 0 to 15. 101, 107, 10% could represent a, An equivalent 4 place decimal system 10° decimal values from 0 to 9999, Decimals in a binary system, as in a decimal system use negative exponents, EVENT DECIMAL FRACTION BINARY 10° 107 1 20 7h 9-2 9-3 @) /2)€/4)(1/8) 1 0,000 0 0,000 2 0,125 1/8 0,001 3 01250 aa olo10 4 0,375 3/8 o,o11 5 0.500 1/2 0,100 6 01625 5/8 ol101 1 01750 3/4 oli10 8 0,875 1/8 o,ilil 9 1,000 1 1,000 ‘Numbers in the base 10 system can be rapidly converted to numbers expressed to another RADIX by dividing the Base number by the new BASE or RADIX, a, Base 10 to base 10, 10 1075 Remainder 10 107 5 LSD 10 10 7 -1075 (10) w [a ° 0 1 MSD b. Base 10 to base 16, (Hexadecimal) 16 [a 16 67 3 LSD 433(12) 16 4 3 0 4 MSD¢, Base 10 to base 8, (Octal) 8 1075 134 2063 (8) woaw MSD d, Base 10 to base 2. LsD 10000 110011 (2) 2 2 2 2 2 2 2 2 2 2 2 MsD 4.6 To convert back to RADIX 10 from another system, each digit is multiplied by the correct Radix raised to the appropriate power. a, Base 10 to base 10 (1075, 4). Bx 25x t= 5 7x w= 7x 1 = 7 0 x 17 = 0 x 100 = 000 1 x 10% = 1 x 1000 = 1000 107549 1-6b © d, e Base 16 to base 10 (433, 4) 0 3x 1!=3x 1 3 wlesx 16 = 48 4x 16=4 x 256 = 1024, 1075 y9 Base 8 to base 10 (2063,). sx asx 1 8 6x st=6x 8= 48 ox @=0x 64 = 000 2x 8° = 2x 512 = 10 10754, Base 2 to base 10 (10000110011,). 1x dx 1s 2 ax 2=1x 2= 2 ox P=0x 4= 0 ox ®=0x 8 ° ix 2=1x w= 16 ax ®s1x s2= a2 ox ®=o0x b= 0 ox 2 =0x 128= 0 ox 2 =0 x 256 0 ox ® sox siz ° ax 2224 x 1024 = 1024 1075, 5 ‘There is a conversion system which is more adaptable to use on the hand held calculator. It has been called synthetic division, or where used in binary to decimal conversion, "double babble", (@) Bring down the MSD and MULTIPLY it by the radix of the system; ADD this to the next MSD and MULTIPLY this sum by the radix, ete. until reaching the LSD. Adding the product obtained from the next LSD to the LSD gives the base 10 equivalent number. (2) Binary to decimal (10000110011,). 1 0 0 0 0 4 21 0 0 1 1 40 42 +4 48 HG 482 466 4134 1268 4536 HO74 1 2 4 8 16 33 67 184 268 537 107544 (3) 1-74,7 4.8 (4) | Hexadecimal to decimal, (433, 6) 4 3 3 40 464 sive 4 67 1075, When one of the hexadecimal symbols A through F is present, substitute its decimal value of ten through 15 in the calculation, ABs = 1010 1011, 253, A Big i ou 2 6 3 +0 160 He s6s To “Thy 2 21 “Ty, RADIX 8 and RADIX 2 enjoy a peculiar relationship because 8 is the cube of 2. a, Divide the binary version of 1075 into groups of 3, starting from LSD, and convert each of these groups into an equivalent base 10 digit. b. 010 000 110 oul, 2 107549 2 0 6 3, 107545 ‘The hexadecimal system, Radix 16 (24) is also used, primarily as shorthand for large binary numbers. It employs sixteen digits; 0,1,2,3,4,5,6,7, 8,9, A,B,C,D,E,and F, In addition, 9+1=A;F +1=10, ‘To convert from bin~ ary to hexadecimal, divide the binary numbers, starting at the least sig- nificant bit, into groups of 4. o100 oot oot, = 1075,, 16" ist 16° 4 3 3 Base 16) ‘The hexadecimal A B,, would represent the binary number AB 1010 1011 Can 1075 = 5701? It can if the least significant digit is clearly defined, Msp 1sD Msp 81075 st0 In binary counters, the schematic is usually drawn in such a way that the least significant digit is on the left, Operations in Numbering Systems ‘Table 6.1 gives the values from one to 32, of digits to bases 10,12,8,4,3,and 2, Note that a system based on 8 uses only the decimal numbers "0" through "7 the system with Base 2 uses only "0" and "1", however for a Base 16 system it is necessary to invent new symbols, represented by "A","B","C","D","E", and "EF",TABLE 6.1 NUMBERING SYSTEMS BASE 10 BASE 16 BASE 8 BASE 2 af ah g8 hal a0 00 10” 00 16° oo 8° Sse 28 on o1 o 000001 oz oz 02 00010 03 03 03 ooo011 ot ot os ooo100 2” 05 05 05 ooor01 06 06 06 ooo110 o7 o7 07 00111 08 08 10 st oo1000 2° 09 09 Fry oo1001 io 10 oA 12 001010 u oB. 13 oovo1t 2 oc u 001100 13 > 15 oo1t01 u 0 16 oo1110 15 oF 1 oii 16 10 161 20 10000 24 ru ct at 010001 18 12 22 o10010 19 43 23 o10011 20 u 24 010100 21 15 25 o1o101 22 16 26 010110 23 a 27 oro 24 18 30 011000 25 19 a1 o11001 26 A 82 o11010 27 1B 33 o11011 28 1c 34 011100 29 w 35 o101 30 1B 36 oun0 2° aL F 37 oui 32 20 40 100000 1-9OE BEE J} 6.2 6.2.1 6.3 TL 12 12.1 1.3 1.3.1 Of particular interest is the Base 2 system, since it is especially applicable to electronic systems. The "0" and "1" can readily be represented by switches or relays, and more importantly, by a voltage level shift from, for example, ground to #5 volts, Such a signal can be generated by changing the state of a transistor from conducting to saturation to a non-conducting (off) state. Note that the 2° column counts 0,1,0,1 - ‘There is an analogy in the familiar 2 frequency divider where an input signal is reversing a bistable multi- vibrator (or flip flop) at a regular rate. a, If the first frequency divider drives a second one , dividing the input, frequency by four, it will follow the pattern of the 2° column, ‘This method of counting electronically is covered more completely in section IV, which discusses binary counters, Since this handbook is primarily concerned with so called "logic" circuits, only operations with binary numbers will be covered. ‘The following rules of addition apply: Performing addition 1 ig carry 1 50 1 2 of 2 82416 2 = 50 Integrated circuits are available whose inputs are A,B, and carry in, They produce a SUM and CARRY output that follow the rules of addition, ‘The other basic arithmetic operation is subtraction, such as 305 - 196 = 109, Step 1, borrow 1 from most significant digit and add it to 10 column, 10” ro 10 10? aot 10° io 0 5 2 10 5 1 9 6 OR 1 9 6 1-107.8.2 Step 2, borrow 1 from the 10° column for the 10° column, 107 sot 10° 2 Gy 78 = 20 ws <1 9 6 19 6 10 9 7.3.3 Obviously, most of us do most of these computations automatically. 7.3.4 Subtraction in a binary system can be done in the same way. at 28 2 2 2 roo { OOO 20 o 0 Tl Oo 1 1 - 16 1 1 5 0 0 1 0 1 7.3.5 Integrated circuits are available which perform the operation X-Y, and that have a borrow IN and a borrow OUT. 7.4 There is another method of binary subtraction using the adding process, While the mathematical explanation is fairly complicated it results in an electronically simple circuit, It is sometimes called the "15 Complement", or more simply subtraction by complementing. It also produces a most significant bit which indicates whether the answer is positive or negative. 7.4.1 The equivalent in the decimal system is called the "9's complement”, in an octal system the "7's complement", a, The complement is obtained by subtracting a number from one less than the Radix of the system, the number is subtracted from 9 (or 99, or 999), 7 (or 63, or SIL), or 1 Or 11,111, or 1111), 9 99 999 10'-1 1071 63 sa wu1A 1.4.2 TA 1.44 b, Typical complements Basel0 5. from 9 4 8 5 7 2 2 101 au o10 ¢. Note the ease of obtaining the complement in the Base 2 system - the 1's and 0's are inverted. Inversion is electronically simple, and two state devices such as flip flips have two outputs which are the complement of each other. Algebraically it consists of adding the same member to both sides of an equation. a, In decimal (5-4 =x) 5-4+9=x49 101 - 100 + 111 =x + 111 10=x 49 101 + O11 =x +111 10- 9=1 1000 - 111 =x 001 =x Obviously any constant would work, In a binary system the constant chosen is ‘one which can be easily developed electronicaily ,just change all the zero's to ones, the ones to zero's, DECIMAL BINARY COMPLEMENT DECIMAL CODE 1 01 110 6 2 o10 101 5 3 oun 100 4 4 100 ou 3 5 101 010 2 6 110 oor 1 Additionally, the answer contains a 1 or 0 in the most significant bit position which indicates whether the answer is positive or negative, It will be 1 when the answer is positive, and the answer is obtained by adding that 1 to the least significant bit which is called "end around carry", If the MSB is zero, the answer must be complemented again, While it sounds complicated, electronically it is accomplished relatively easily. Typical examples complement 25 11001 11001 MINUEND -13 ~ 01101 #10010 SUBTRAHEND 1011 ¥___1._ ond around carry o1i00 13 o1toL 01101 225 = 11001 + 00110 TO0IL One complement result, answer negative. 12 1-127.5 Power of 2 to 24? 256 512 1024 2048 4096 8192 16 384 32 768 65 536 131 072 262 144 524 288 1048 576 2097 152 4194 304 8 388 608 16 777 216 33 554 432 67 108 864 134 217 728 268 435 456 536 870 912 1073 741 824 2147 483 648 4 294 967 296 8 589 934 592 17 179 869 184 34 359 738 368 68 719 776 736 137 438 953 472 274 87 906 944 549 755 813 888 1 099 511 627 776 1-18 0 1 2 3B some 10 i 12 13 14 15 16 17 18 19 20 21 22, 23 24 25 26 28 30 31 32 33 34 35 36 38 39 408. ‘The only problem with the binary code discussed so far is that it is difficult to display. 8.1 A display for more than a few binary bits must be done in terms of the decimal system, using nixie or LED numeric display units. 8.1.1 The AVR-1 buffer test panel lamps 1,2,4,8,16, and 32 is a displayed binary code which represents the time in microseconds between demod video syne and station horizontal syne. 1ea oOo ez 8.1.2 In a binary code the next value is obtained, as it is in the decimal system, by simply adding 1; 1+7=8, or 1 +111 = 1000, 8.2 One alternate if the Binary Coded Decimal . 8.2.1 Each digit of a decimal number from the least to the most significant character is converted into a binary number, which can carry a decimal weight of from zero to nine, a. Since no single decimal character can exceed 9, a maximum of four binary bits are required. b, Its most common use in AMPEX television equipment is to represent time either real time or tape travel in terms of time. HEXA EVENTS DECIMAL BINARY CODED DECIMAL BINARY OCTAL | DECIMAL 10" 10° TENS UNITS st 8° het 16° 421 8421 32168421 1 00 000 0000 000000 0 ofo 0 2 o1 000 0001 000001 0 1/0 12 3 02 000 oo10 000010 0 2/0 2 4 03 000 oo1t 000011 0 3/0 3 5 04 000 0100 000100 0 4/0 4 6 05 000 o101 000101 0 5/0 5 7 06 000 o110 000110 0 6/0 6 8 07 000 o111 000111 o 7/0 7 9 08 000 1000 001000 10/0 8 10 09 000 1001 001001 11/0 9 uw 10 001 0000 oo1010 1 2/0 a 2 ce 001 0001 oo1011 1 3/0 B 13 wz 001 0010 001100 1 4/0 G 14 13 oo1 0011 001101 1 5/0 Dd 15 4 001, 0100 001110 1 6/0 & 16 15 001 0101 001111 1 7/0 F 21 20 010 0000 010100 2 4/1 4 31 30 o1t 0000 011110 38 6/1 & 41 40 100 0000 101000 5 0/2 8 60 59 101 1001 z11011 7 3/3 B 61 00 (arry1) 000 0000 111100 7 4/3 ¢ 1-14EES ier] 8.3 A typical example would be the "seconds" display, which must count from 0 to 59 seconds. 60 seconds represents 1 minute, and any electronic circuit used would have to generate a “carry” as the "seconds" moved from 59 to 00. 8.4 To represent complete 24 hour time up to 23 hours, 59 minutes, 59 seconds, and 29 frames (24 on 625) would require, HOURS MINUTES SECONDS FRAMES TENS unITs | TENS uNirs | TENS UNITS | TENS UNITS Hyg Hy Mo = My SiS Fo Fy BCD VALUE 21 6421 421 8421 421 8421 21 8421 0-28 0-59 0-59 0-29 Ohours 00 0000 | 000 0000 000 0000 00 ©0000 23:59:50:29 10 0011 | 101 1001 101 1001 10 1001 XN. J 26 "bits" 8.4.1 24 hours represents some 2,592,000 frames, ‘The 22 Bit Binary Code for that: g2t 20 p19 g18 g17 016 915 914 518 912 911 510 49 48 97 96 95 94 93 52 yl 40 ocTAL 2 1 o 6 4 0 o BINARY1 00 10 1 2 170 0 01 1 0100000000 HEXA- 2 7 3 D 0 0 DECIMAL 8,5. The SMPTE proposed 80 bit time and control code which is used in several editing systems is a binary coded decimal. 8.5.1 When recorded on video tape on Audio No, 2 Track (Cue Track), one complete "'Time/Control word requires one frame to complete, or approximately 1/2 inch of tape, or 34 ms (525) or 40 ms (625) in time, a, Each "bit" represents 417 sec (525) or 500 sec (625). b, The 80 time periods (slots) are utilized: 26 24 hour time code 82 8 four bit control "words" used in the ACR-25 for tape control 16 Synchronizing word identifies end of "time word" and tape direction 5 Unassigned address bits _1 "Drop Frame" Identifies whether real time or "color time'' was recorded, 80 1-158.6 Format [2 [2 [9] 4]5]6] 7] 8]o [20] 11] 12 [13] 14] 15] 16 [17 [18 [19]]20] 21 | 22 [23 2 |4 [a2 |2]4| sfiol2o|40] so ifa[ ata Least 10's Second Units of Units of signif. of Binary Seconds ord Frames “i Binary Digit’ Frames Group ‘crue of ‘i spares" AL Unassigned ("Spares") Word 525 Color (st binary ‘skip bit!” group) 24-26 Tens of seconds (1,2, 4) 27 Unassigned (0) 28-31 4th binary group 382-35 Units of minutes (1,2,4,8) 36-89 5th binary group 40 - 42 Tens of minutes (1,2,4) 43 Unassigned (0) 44-47 Sixth binary group 48-51 Units of hours (1,2, 4,8) 52-55 Seventh binary group 56-57 Tens of hours (1,2) 58-59 Unassigned (zero) 60 [61] 62[63]64|65]66]67] 68 [oo [70] 71] 72| 73] 74] 75] 76] 77] 78] 79)0]1|2]3 |4]5]e ofofafalajafafafafafzfafafzye Oh es : 12 ONE'S Sth Binary} (cannot occur in message") group (spares) 4p Units Ist of Binary Frames Group Synchronizing "word" used for forward/reverse identification 1-168.6.1 8.6.2 8.6.3 8.7 8.7.1 Real time is defined as the time elapsed during the scanning of 60 fields in an ideal television system at a vertical field rate of exactly 60 fields per second, Time and control code locked to the signal will represent real time. Color time is defined as the time elapsed during the scanning of 60 fields (or any multiple there of) in a color television system at a vertical rate of approximately 59, 94 fields per second. Straight forward counting at 30 frames per second (60 fields per second) will yield an error of + 108 frames, equivalent to +3,6 seconds timing error in one hour of running time, Time code using the 59,94 reference is running in the "uncompensated" mode. In this mode, bit 10 of the code is "zero". A "compensated" mode can be used to resolve the “color time" error, When used, bit 10 is made a binary "one", a, The first two frame numbers (0,1) at the start of each minute, except minutes 0,10,20,30,40, and 50 shall be omitted from the count. ‘MINUTES SECONDS FRAME 1 59 29 2 00 02 2 59 29 3 00 02 9 59 29 10 00 00 10 00 o1 10 59 29 i 00 02 ete, ‘The modulation is such that a transition occurs at the beginning of every bit period - every 417 usec (525) or 500 usec (625). A binary "one" is represented by a second transition 1/2 bit period later (208.5/250 usec) when a binary "zero" occurs, there is no transition within the 417/500 usec bit period. FS Ur Ff cultlile f et fle a, Circuitry to accomplish this is discussed elsewhere, When carrying on arithmetic operations with Binary Coded Decimals certain difficulties arise. 1-179.1.2 9.1.8 9.1.4 ‘One method of obtaining valid answers is subtraction, For example, if as a result of an addition the frame column exceeds 29, then subtract 30 until the number is 29 or less, Each time 30 is subtracted, 1 sec is added to the "seconds" column (it generates a carry). Division of the number by 30 would accomplish this end - but in general computer type operations are always going to add or subtract; multiplication is continuous addition a specified number of times: 5x4=4+4 +4444 455+5+5+5=20 ) GE & Ga @ @ and division is subtraction repeated continuously, the answer being the number of times the numbers were subtracted, (@) answer Since we prefer addition , or at least the computer considers it the basic operation , the frames problem above can be solved by addition, a. The column is restricted to 29, but has a possibility of generating values to 99 without a spillover to the 10” place value, The frames & seconds represented by values greater than 29 can be obtained by adding 70 (99-29). ° b. In the case of the seconds & minutes column, the "magic" number is 99-59, or 40, & in the case of hours it is 99 - 23, or 76, HOURS MINUTES: SECONDS FRAMES 59 59 29 61 61 31 + "magic no." 40 40 70 In using Binary Coded decimals a similar problem exists, The 4 bit BCD cannot exceed a decimal value of 9 - 1001, In addition, the binary bits in the answer may exceed this limit, a. TENS UNITS 421 8421, 1001 +1001 10010 1-18HEE eer | . The answer, 18 is correct, however, the most significant bit has no meaning. Saying that it is in the TENS column, "1", produces a BCD of 12, obviously not correct, cc, One "out" is to subtract 10 (1010) whenever the units column exceed 9 (1001) and for each subtraction, put a 1 in the TENS position. TENS UNITS 421 8421 ‘000 Loot 4_1001 T0010 +1 =_1010 oon 1000 The correct answer of BCD 18 is obtained, 9.2.2 Again, addition is the preferred method, ‘The 4 bit code is restricted to 0 - 9, 0000 to 1001, however the maximum 4 bit number possible is 15 (1111). If 1111-1001, or 0110 (6) is added whenever the value exceeds 1001, the correct answer is obtained. (This is the complement of nine.) ioot +1001, carry ——— T0010 + 0110 1 “T000 9.2.8 The complement method can be used for binary coded decimal subtraction as well, However, in this case the "9's" complement of the subtrahend is taken, uo ou 29 oxo oor 0010 1002 215 0001 0101 +1000 0100 14 0001 ©=— 0100, TOO © T101 #0110010 Toooo 10011 Qi ot Cl a a, Again, the operations are complicated on paper; however integrated circuits are available which can produce the 9's complement of a binary coded decimal or pass the signal straight through. 10, Another code used is the ASCII. A seven bit binary code is used for a total of 128 characters, Some examples: ASCII BINARY BITS CHARACTER 765 4321 A 100 0001 NUL 000 ©0000 4 o11 0100 1-19‘Table 10-1. American Standard Code for Information Interchange (ASCII) BIT POSITION 765| 765| 765|765 res [nas 765 [765 ooo|oo1/ 010/011 ]100 [101 fito fiai [4321 nut | pre | sP 0 é@ P i p__|ofofofo] sou | DCL 1 1 A @ a a [ofofofa stx | pez " 2 B R b r__fololzlo ETx | pos | # 3 c s e s_ fofoliz gor | pes | $ 4 D T a t__[olifolo ENQ | NAK | & 5 E u e a fofifofi ack | syn | & 6 F v t v__fofz[afo BEL | ETB y 7 G Ww g w_jofafalt ps | can | ( 8 H x h x |ifololo ut | EM ) 9 I ¥ y__|alolola Lr | suB * : z Zz ij z__|alol1fo vr | Esc + K t k { 1fofafa FF | FS . L \ 1 [1] }olo cr | os = M ] m }_[afafola so | Rs : > N A n ~__[afafafo SL us / 2 ° _ ° DEL |1/1/1|1 NUL Null, or alll zeros DC1 Device control 1 SOH Start of heading DG2 Device control 2 STX Start of text DC3 Device control 3 ETX End of text DC4 Device control 4 EOT End of transmission NAK Negative adknowledge ENQ Enquiry SYN Synchronous idle ACK Acknowledge ETB End of transmission block BEL Bell, or alarm CAN Cancel BS Backspace EM End of mediam HT Horizontal tabulation SUB Substitute LF Line feed ESC Escape VE Vertical tabulation FS File separator FF Form feed GS Group separator CR Carriage return RS Record separator SO Shift out US Unit separator SI Shift in SP Space DLE Data link escape DEL Delete 1-2010.1 10.2 Characters may be given another meaning. In the Automation Data Accessory (ADA) for the ACR-25, for example, if the ADA sends ENQ to the computer, it is requesting a play list of cassettes to be played when the computer sends, STX to ADA, indicating a Play command. However, if the computer sends EN@ to ADA, the computer is requesting a Table of Contents - what tapes are where in the ACR-25. ‘The ASCII format is used on punched paper tape, a serially oriented medium. Each column of holes represents one ASCII character. There are eight bits in each column, of which seven are information, The eighth is a parity bit which is added or omitted from each character to ‘Xeep the sum of "1's" even or odd, In Figure 10-2 odd parity is shown, BIT No. AD ASPU SES SPAS CII Oo 0 0000 00000 o_o oo Oo Oo °9O ©8©000000000000 00 0 o °° ° ° 200 0000 00000 000 00 0 00 COLUMN re Figure 10-2. 8-Level 1-Inch Tape Coded in ASCII Format with Odd Parity FEED OR SPROCKET HOLE oon CHANNELS OR LEVELS PARITY 1-21Er eB tere } aa 1.2 1.3 21 y-0008 REV.7 SECTION I: GATING LOGIC The first section dealt with a special numbering scheme - the binary system - in terms only of manipulation of those numbers. The very attractive feature of the binary system is the use of only two values ~ zero and one ~ with respect to electronic circuits. A switch or relay is a binary device. When open, or off, it may represent "zero", Closed, or on, it may have a value of "one", Solid state devices - such as the transistor also adapt easily since they can be biased so that a small change in base bias can cause it to be either OFF - practically no current flow - or ON, and conducting at saturation, a. The circuit can be arranged, for example, so that in the off condition, the collector is near +5V; when the transistor is conducting the collector will be at about 40.7 volts, These voltage values could represent, respectively, "ONE" and "ZERO", Circuits where this type of change occurs, with no allowance for intermediate state (unless a fault exists), are usually referred to as LOGIC or DIGITAL circuitry. a, An ANALOG circuit is one where the input and output signals may vary smoothly over some voltage range. b, The composite television signal could also be considered composite in terms of the above definitions, where the syne portion is essentially digital, while the 53 microseconds of continuously varying picture infor- mation is an analog signal. ‘The explosive growth of mathematics, and particularly algebra, with its precise equations to explain complex functions during the nineteenth century led an Englishman, Boole, to develop a system whereby the written word could be handled as precisely. It was based on the assumption that a statement could be reduced to alphabetical letter designations which represented either trath or falsity (ONE or ZERO). The system he developed is called Boolean Algebra, and has a set of rules which allow manipulation for simplification, One of its first applications in electronic circuits was in the design of large switching networks used to select signal paths, Rather than follow a complicated schematic, it was possible to write equations, simplify them, and then design the hardware. ‘The system found an obvious application in computer circuits which are designed around the binary, or two state system,3.1 3.2 3.3 In designing "logic" circuits, such as for the control of a video tape recorder functions, equations can be used initially, and manipulated to get them in their simplest form, In some cases it may be desirable to have redundant circuits for protection, rather than to try and eliminate them, It is only when the equations become hardware that voltage levels become important, Because it is a two valued system the notation "1" and "0" are sometimes used. Particularly in control circuits this does not really carry a numerical value, Where arithmetic operations are not involved "HIGH" (A) and "LOW" (L) are just as valid. When the terms "1" and "0" are used in electronic circuits then some logic level_ assignment must be made, Binary ZERO is used as a reference, a. There are, electronically, two systems used - called respectively POSITIVE and NEGATIVE logic, to express the relationship between ONE and ZERO. Using ZERO as a reference POSITIVE logic refers to a system where binary "1" is positive with respect to binary "0", The voltage values below are from typical AMPEX equipment, BINARY ZERO POSITIVE BINARY ONE GROUND ae +5V -5.2V GROUND -1.7V -0.7V -12v sv OPEN CIRCUIT 424V (RELAY LOGIC) oY NEGATIVE aay BINARY ONE LOGIC BINARY ZERO In negative logic the "1" is negative with respect to "0". In equipment and particularly in control circuits the important thing is the active condition - the voltage level which accomplishes the desired result. a, In such a system zero does not indicate that nothing is being performed. ~A shift from +5V to ground might indicate a system command to change from 525 line standards to 625 line standards. This might be shown on schematics as OR 525(+) 625(-) oiled 625—_ _ _ a Eee 3.4 4,1 V-0008 ‘The important thing from a trouble shooting standpoint is what is to be expected on the primary trouble shooting instrument - the oscilloscope, a. A word of caution is necessary, as far as use of oscilloscope voltage scales when trouble shooting integrated circuits. When moving from point to point in circuitry, make certain the scope voltage scale is relevant, In a circuit where the acceptable swing is from +0,8V to 42,5V, a defective circuit may show a voltage shift if the scope voltage scale is expanded, but the swing will be insufficient to affect following circuits. av av iv .1V ov 0 1v/em .1Vem An integrated logic circuit can be considered a "black box" which performs certain functions. A table of combinations, or logic list describes the input and output conditions of such a device, Its complexity depends on the number of variables ~ the inputs - involved. It is frequently called a TRUTH TABLE. Only two possible conditions are considered, "0" and "1", or more practically, LOW (L) or HIGH (H). a. in_| our BLACK, aA |x A—™| BOX }™ x a | Lf b, Obviously from the Logic List, the device does not change the relative polarities of the signal, input to output, Trivial case would be a piece of wire from A to X. More practically, it would probably indicate an emitter follower or common base amplifier. ©. It could also indicate a logic level converter ~ a device to convert from one "family" of integrated circuits to another with different voltage requirements. One system, to be discussed in more detail later, swings from -0.7 to -1.7V, an other system swings from +0.7 to HV. -0.7 -1.7V This satisfies the logic list. Although there has been a level shift, there is no inversion of the signal. I-83V-0008 d. The logic symbol for this function is a triangle. INPUT OUTPUT A x X=A It is sometimes referred to as a non-inverting buffer, 4,2 The trath table for an inverting buffer: a aly BLACK HI L A —| Box |ey L|# The logic diagram symbol: A f- y oR A > c, The small circle, sometimes called a "low level designator", indicates that the device inverts the applied signal, In the case of the signal input device, the circle can be placed at either the input or the output. d. A convention sometimes followed is "circle match", Where several inverters are used in series, it can make the signal polarity more obvious from input to output, €, The "bar" (A) over the equation indicates the inversion. Note that with two bars, double inversion, the signal returns to its original state. 1, The equation for the inverters would indicate that input "A" equals output "A", there has been no inversion, Schematically the four inverters could be replaced by a piece of wire. A oa m-4er} V-0008 g. The piece of wire, however, would not indicate propagation delay - the time that it takes the output to react to a change on the input, (1) If the signal being processed had a frequency of 250Hz ~ a 4ms period - than the propagation delay of approximately 8 nanoseconds per unit - a total delay of 32 nanoseconds would probably be ignored. (2) For an input signal at 10MHZ - a 100ns period - this would represent a phase shift of about 115°, which could not be ignored. The units may be deliberately inserted in the signal path to obtain delay. 4.3 Conside* the following voltage level logic list or truth table, which has two inpat variables: IN our ale ¥ at n| a BLACK i Lia Box Ty L x] 4 a L ufo L a, The output is high only when both inputs are at a high level - "A" and "'B" must both be high for output "Y" to be high. This indicates that a high level AND function is being performed, The standard logic symbol: A T>- Y =A + B=AB= (AB) =A)" @) B ————> DIRECTION OF SIGNAL FLOW SWITCH ANALOGY - SERIES SWITCHES Fo = x = =o sv 0 swircn BQ HAP SWITCH A b, In the equation, the algebraic symbol for multiplication is used to indicate the AND function, but is read as A and B, (1) If more than three inputs are used, the symbol is modified: A = Y = (A)(B)(C)D)E) moow (2) The symbol still indicates that all inputs must be high for the outpat to be high; if any one or more of the inputs is low, the output is low, m-544 4.5 08 Consider the following voltage level logic list: IN our Als ¥ L|o A) BLack L alo Box [-Y H L/ a Bo Hq u|a H a, The output is high when any input is high - "A" or "B" or both, This indicates that a high level OR function is being performed. The standard logic symbol is: A Y=A+B B ———® DIRECTION OF SIGNAL FLOW SWITCH ANALOGY : PARALLEL SWITCHES. oO A = sv LOAD —o 3 = b. In the logic equation, the algebraic symbol for addition is used, but is read as A or B, (@) If more than two or three inputs are used, the symbol is drawn: A-\ B c D E r= (2) The symbol still indicates that if one or more of the inputs is high, the output is high. Y=A+B+C+D+E+F The MIL STD 806B, which specifies the symbols used, defines the two functions without reference to voltage levels. a. AND: Circuit element whose output is active (doos something) when all of its inputs are active. Any non-active input will produce a non- active output. b. OR: — Circuit element whose output is active when any one or more inputs is active. 1-6‘y-0008 4,6 In light of the previous page definitions examine the truth tables or logic lists. a A[sly nial aH myn) HIGH LEVEL LOW LEVEL uiulu CONSIDERED CONSIDERED ‘ACTIVE ACTIVE b, If the low level isconsideredthe ACTIVE state-the one that lights a lamp, for example - then the OR function better describes the condition, ‘The output is low when any or both inputs are low, but the output is HIGH when both inputs are high, The OR is the complement of the AND function, e. A | Bly tiula H/L|H HUH |S HIGH LEVEL LOW LEVEL uiuia ‘ACTIVE ACTIVE d, A high level AND gate also functions as a low level OR gate, and a high level OR gate performs a low level AND function. €, To obtain the new symbol the level designators on input and output were changed - or complemented, In the equation this represents doing the same thing to both side of the equality sign. Y = A+B High level equation = K+4B__ Low level equation Y= AtB AYB = (2) The complement of Y,A, and B is ¥, A, B, read as BAR Y, BAR A, BAR B,or more usually NOT Y, NOT A, NOT B, The complement of the AND indicator is the OR symbol, the complement of the OR indicator is the AND symbol - the equation follows the logic symbols.V-0008 4.7 The following combination logic is NOT the same as was done in paragraph 4.6. ABAByYY¥ HHLULG LHHLLE HLUHLAE LLWHHHL Note that the truth table indicates that a high level OR function is being performed. GATE OUTPUT EQUATION Rew b, Simplified Symbol: A ¥ B c, Similarly write the logic list and equations for: >I wl “4 Pt cme mt > Beem GATE OUTPUT EQUATION 4 SIMPLIFIED SYMBOLv-0008 4.8 A large variety of integrated circuits designated NAND or NOR (NOT AND or NOT OR) are available from manufacturers. a, NAND A|BIX wpa ly Liu la * D> « -B-K45 H/ LH u {ula (1) Note that this is equivalent to an AND gate followed by an inverter. A = X B @) Itcan also be drawn: A x B ‘The output is high when either or both inputs are low, NOR AlBI[x | ufafe A H/ L/L Joe x =KFB= @@) Liu}. B tfula (2) It is equivalent to an OR gate followed by an inverter, >D-b* AFB = Aw) (2) Itcan also be drawn, functionally, as »‘Vv-0008 4.9 Another gate frequently found in AMPEX equipment, particularly in control logic, is the WIRED GATE, using two or more inverters to accomplish the logic fanetion, a, It is necessary to know the logic levels associated with the integrated circuit used. Using DTL or TTL logic. (1) sav HIGH A a BY L GND Low HOH OL u _. ¥ LHL HL L B LoL ds (2) The equivalent logic symbol: A A B B (3) More than two inverters may be tied together. ‘The tie point may not be on a common circuit card, but in the interconnect, a gate symbol is sometimes drawn around the tie point, D4 B 7 b, Another system of integrated cireuits Emitter Coupled Logic, ECL has different levels associated with it, @ A BY > A Tr |. 7(HIGH) LH OW 1. 7V (LOW) y uu e LoL a B HOH OL (2) The equivalent logic symbol: y = y=A+B eS B m-10‘v-0008 4,10 Table Il-I covers the various possible combinations of gates with their voltage truth tables and high and low level equations, a, In general the circuits available from manufacturers are limited to AND, OR, NAND, and NOR. The other combinations will include an external inverter, For example: 4,11 One other gate, now available as an integrated circuit, was in the past frequently fabricated from gates and inverters. It is called the Exclusive OR. The OR gate previously discussed had a high output if one or both inputs were high. The exclusive OR has an output only when both inputs are different. a A = A BY a HOH OL Lt * LoL. HL H LoH OH (AB) (AB) = (A +B) (A +B) b, ‘The equation can be expanded by cross multiplying, as in mathematical algebra. A+B a+p)-Aa+ Ap +aB+Bp (1) The expressions AA and BB imply the following, and are therefore Zero ~ always low. A AR (2) Therefore, the equation reduces to AB + AB - The output is high only when or B is high, but not both. (3) The equation is sometimes written A (2) B, the symbol e indicating exclusive OR, m-1-0 g1aVvi v-0008 w|>| |ol>| jol>| Lolo} ole) lol>}| jola| fol> 2 = 2 E> * x * x = x |B = b> | jel} fml>} fol! lo l>| fof | jol>| jol> 3 ey $ x = x » ~ x = x cess|ress|eces|peesleces|eeee |pees less > > Se > 5 = = 2 z z z Se S Se S + Ss & & = = Fo) zi o 0 " " eS Ss s Ss " x x > EE S > > oa > Be S Sa z z z et = = ‘eB Ss eS " « " o £ m-12‘Vv-0008 ‘The Exclusive NOR cc, Another version: = (A) (AB) ‘ A BY HOH H 7 Lou HOLL 7 Low. (B&B, () ¥ = @)@B) AAB) = @+AB) A +AB) = AB + ABB + AAB + AB AB ~ Since BB and AA in the two middle terms are zero, they can be ignored, - The express ABAB implies : cS [a | - The equation reduces to AB + AB - the output is high when both inputs are equal, (2) This frequently is used as, and called, a comparator, For example the A input is from an electronic tape timer, the B input from switches, with output going high when the preset switch time is the same as the tape timer display. d. Where these two circuits are available as integrated circuits, their symbols: ‘7 AB+ AB 8 De 8 B B Exclusive OR Exclusive NOR e. The Exclusive OR can be programmed to act as either inverting or non inverting in the signal path, a SIGNAL CONTROL LOW, SIGNAL ON A NOT INVERTED = CONTROL HIGH, SIGNAL ON A ALWAYS re CONTROL INVERTED 1-134,12 4,13 BAL 5.2 V-0008 ‘Typical circuits used to accomplish the logic functions discussed are covered in APPENDIX B to Section II, Emitter Coupled Logic is covered in Section IX of the Logic Handbook, ‘The rules behind the equations written so far have not been discussed, but are based on some basic axioms and theorems derived from them, that form the rules for Boolean Algebra, ‘The basic axioms are as follows. These are not rules for addition of binary numbers, a. 0° 0 read zero AND zero equals zero read one AND one equals one 0 read one AND zero equals zero d. 0+0=0 read zero OR zero equals zero e. 14#0=0+1=1 read one OR zero equals one f, 1+1=1 read one OR one equals one ‘Theorems derived from these, and circuits which satisfy the conditions. : Dp a. (0) (A) 4 > + 1) (A) (1) When NAND logic is used to implement the circuit, this configuration will be found because unused inputs may be tied to voltage, or an inverter may be desired, “ K a . A ce. At1=1 — +5 M-14‘V-0008 a. © A (A) A) ay e. At a +Ay=A + AA =A Again with NOR or NAND circuits the A + A or (A) (A) equation can arise where the integrated circuit is being used as an inverter. “De - D> OR Fa > ‘This circuit is used in the digital time base corrector as a pulse former, It is a case where the equation does not adequately describe the circuit, (10MH2) Y= AA) DELAY 10ns A pe 10075 = K -{ 80s he —[]= 20ns y 1-15ENS en ‘Vv-0008 f. (A) + @) = HIGH = A HIGH x g. The commutative rule is obvious: A+B=BHA A 3 B T> AB) = B) (A) B > Ag A 3 pi 3 h, The associative rule is also obvious and will arise when several gates are used, (ap) (C) = A (BC) = (A) (B) (C) c A+B+C =(A+B)+C=A4+@B+C) ‘The Distributive rule is similar to algebraic factoring, AB + AC = A @+C) B AB B —> Bic me . A = c Ac (1) Notice that the number of gates required had been reduced. 1-16B V-0008 i m. ‘The absortive rule essentially involves expansion by cross multiplication, (A + B)(A + C) = AA + AC + AB + BC = A + BC A AA TD : A+B c AB . ac A A4+C ote c BC Since the expanded equation has AA as one of the OR TERMS, and A+ A then the output is high whenever A is present, and the terms AC and AB are redundant. A+AB=A (1 +B)=A A A+ABEA ‘AB A(A+B)=AA+AB=A+AB=A G43) =A A B If A is high then the OR function A + B is satisfied, and the AND gate is satisfied. A+KB=A+B “Tp De : B alt as I-175.8 ‘Vy-0008 n, (A) (A +B) = AA + AB = AB A A+B Probably the most useful is DeMorgan's Theorem, which covers what happens when an entire expression is inverted, or "NOTTED", a. ABC = b. A¥B¥C c. The example given is fairly straight forward, However "A", "B", and "C" can represent more complex terms, @) @ FB CFD) = AFB) + CFD Note that thé equation suggests three ways to implement the equation with hardware, (A +B)(C+D) (AFBCFD) vow > @FB) + @FD) va o> Pl ol + al oO n-18rr V-0008 @) ABFOD - GB - @ = A+B: C +d) = 86+ + BC+ BD Vw A B 5.4 Manipulation of logic equations is of obvious value in equipment design. In the case of a computer, the "schematic" could be just a list of logic equations. a, In AMPEX products frequently writing the equation can simplify the process of finding out what is happening. b, Here is a circuit used in controlling the reference to the Capstan Servo in the AVR-1 video tape recorder. Y iB) (CDE) (H+ FG) (AB) (CDE) (H + FG) (A + B)(CDE)(H + FG) Y= Gq =H + Fo Hl i SE FRAMER TO GET VERTICAL AND FRAME COINCIDENCE ¥ = CAPSTAN USING RECORD REFERENCE (2) Definition of terms [— A = CAPSTAN FRAME LOCKED (30HZ COINCIDENCE) (— B=VERTICAL COINCIDENCE (60HZ) a [— C=RFON TAPE ct -norF f— D-= CONTROL TRACK ON TAPE pH m-19SEE8.n -}—— V-0008 in E=VERTICAL SYNC RECORDED ON TAPE F “L G 1 EDITOR INSERT F-EDITOR ON ;DITOR ASSEMBLE bes RECORD MODE X=CAPSTAN USE 30HZ REFERENCE TO ACHIEVE "FRAME LOCK" Y=CAPSTAN USE RECORD REFERENCES (3) The X then says, in words: Frame or Vertical coincidence not achieved; and RF on tape, control track on tape, and vertical syne recorded on tape; and VTR not in video record mode or EDITOR is on and insert mode selected. (4) Since ¥ was defined as Capstan record, then the Y expression must be also "NOTTED" to find the record signal, which will be a low, Y= @FFS = @ w+ H - fr + ae whieh says: Record and EDITOR OFF OR RECORD and Editor in ASSEMBLE mode, 6 Examples of gating logic. 6.1 One circuit frequently found is basically an electronic switch. Al: MC846P, Quad ‘two input gateVv-0008 b, When, the control signal, is high, the signal at A appears at the output, inverted, when C is low, then the signal at B appears inverted at the output. In one case where this is used the A signal is reference syne, the syne signal at B is stripped off of modulator video, and C is the EDITOR Bus, which moves low when the EDITOR is turned on, . On some simplified blocks this circuit is shown as a switch, N.C, AL ct) “ S Y B 8 N.O. c (2) The use of the negative level indicator on the C input says that when C is low the switch will move to the N.O, (normally open) position, The bubble on the output indicates that the switch inverts the signal, (8) The switch could also be simplified. With a positive indicator on C input, saying that when C is high, the switch moves to the N.O, position, now designated the A input, c x.o, &% At A ay 3 B Nc In the AVR-2 and digital time base correctors TBC-800 and TBC-900 an SN 7451 is frequently used to perform this function, It is called a dual two wide two input AND/OR/INVERT. 1@) 13(3) a 8(6) 94) 10(6) Pins in () are the input/output of second half. b. Ina typical circuit, it performs the same switching function, coo 1EE Beier Vv~0008 ¢. The RCA CD 4016AE is a quad (4 units per chip) COS/MOs bilateral switch which will handle either digital or analog signals. A similar digital electronic switch is the Fairchild FC 9309 Dual four inpat multiplexer. 49 43 19 9 4567 a Moos 204 b, Internally, one section is a series of gates. c. The input signal Ig, 1y, Ip, or Ig to appear at Z selected by the control signals So and $1. SO Sl BINARY NUMBER OUTPUT Z FOLLOWS LoL 0 Ig HOL 1 by Lo 2 bey H OOH 3 Is 1-22V-0008 d, One application is the EDITOR where timing is dependent on the standard. It replaces relays that were used in earlier multiple standard EDITORS. so st COMMAND LoL 525, 1dips HOO” 525, 7.5ips Lo 625, 15ips HOH 625, 7.5ips e. The Fairchild FC 9312 is an eight input multiplexer which follows similar rules. 1 2 345678 416 In this case, if pin 10, the enable, is high, Z remains low, and Z high, With the enable low, the binary number represented at $0,81,82 determines which input,10 through 17, that Z will follow. 8, 8, 8, 2 FOLLOWS bobo. lp HOLL \ L oH OL L HOH OL 1 xy a HOH 4H 1, £, The 3 input H bit digital multiplexer Signetics N 826 3 is slightly different, a 456 1 2 3 23 22 21 20 19 18 17 16 11-23(2) In this case f0 follows AQ, BO, or CO, as selected by $0 and SI, {1 follows A1, B1, or Cl etc, ‘If pin 15 is high the digital infor mation is inverted; when it is low there is no inversion, so sl fn FOLLOWS HOH An Lon Bn HOO” Cn LoL — When $1 and $0 are both low, the f outputs are fixed low if pin 15 is low, and fixed high if pin 15 is high, 6.4 A similar function is performed by the FC 9311 one of 16 decoder, which essentially converts a four bit binary number into a decimal equivalent. a, 18 19 1 2 3 4 5 6 7 8 9 10 1113 14 15 16 17 b, As long as El or E2 are high, all outputs are high, With both Enable inputs low, then which output is low is determined by the 4 bit binary number at AO, Al, A2, A3, AQ] AL Az AB PIN LOW L L LoL 1@ H L LoL 2a Lo oH LoL 3@ HoH oH 4H at 5) 1-24v-0008 6.5 The Texas Instruments SN 7442 performs a similar function for a binary coded decimal. a. ah a? 22 A BC D__ PINLOW LLLUL ow HLLL 2 HOL LH ou LH L H_ NONE HOH LH NONE LoL H H_ NONE HL H MH NONE L oH H H_ NONE HOH HH NONE b. Notice that the cireuit rejects binary numbers between 10 and 7 ‘The earlier paragraph covering the Exclusive OR did not cover their very important application of ADDING binary numbers, 7.1 The exclusive OR gate performs 1/4 of the job of adding a pair of binary numbers. AB Y_ BINARY ADD A LoL Lb o+020 : HL HW 1+0-1 B Lo oH WH O#L=1 HoH OL itiso In the last step the correct answer was obtained for a pair of binary numbers, but no carry to the next higher stage was generated. 7.2 Ahalf adder will generate the sum and a carry to the next stage. 4 AB SUM CARRY ) >- suM LL L L Be HL Hu L CARRY LE u u HOH L H 11-25‘V-0008 7.3 A full adder must have the capability of a two bit plus carry input, and a sUM _ _ (ABc + ABC) CARRY IN A Bo CARRY OUT =AB + ABC + ABC A BC sUM CARRY ABC HOH H H ABC H L+14+1= 1, carry LoL H Bec L O+0O+141 HLL H ABC L 1+o+o= 1 LHL H ABC L Or1+0=s 1 HOL H L ABC H 1+0+41= 0, carry LoH OH L ABC H O+141= 0, carry TA ‘The FC 9304 is a dual full adder. 2 8 4 w ow 18 ra | I | | 9 1 WW Note that the "2°" half has a negative out when a carry is present, but also that"2!" requires the carry in to be active low, Also SUM and SUM are available as outputs. 11-26V-0008 7,5 The Texas Instruments SN 7483 is a 4 bit binary full adder, 1011 8 7 3 4 116 A, + By + Cy > and C, (internal) rt > and C, (internal) 2 Ag + Bg + Cy = > and C, (internal) Cy A; By A, BL A, By Ay By 21 Ye Dis Qsce Ay +B, +, 3 9 6 2 15 1 Ag* Bat Cg = and C4 4 8, Similar to adders are magnitude comparators such as the Fairchild FC 9324 and ‘Texas Instruments SN 7485. The logic for a two bit comparator is shown, A LESS THAN B ACB A MORE THAN B A> B (BY AB) 1-27—_—S__ nh Sinton: | 9.1 v-0008 ‘Typical gates and special function integrated circuits using gates have been shown, Basically, however, all circuits can be fabricated using the three basic gates ~ the inverter, the AND, and the OR, The section of flip-flops which follows this will start with a bistable built from these basie building blocks, Decoding of counters, which has been briefly covered uses the basic functions, Several gating circuits are drawn below. The student should write the equations for the gates. For the most part, they are drawn from AMPEX equipments, ‘Two to 1 of 4 Decoder, Mc846 AQ-8= A3-6= 11-28rr] SECTION Il, APPENDIX A MH, ‘This appendix is a summary of MIL STD 806, which establishes graphic symbols for use in logic diagrams for systems of two state devices. A, The standard also references the following documents: 1, MIL-STD-12 Abbreviations for use on drawings. 2, USAS-Y32.2 Graphical symbols for Electrical and Electronic diagrams. 3, USAS-Y82.16 Electrical and Electronic reference designation, Section 3 covers presentation techniques, A. Symbol orientation weight of line or symbol size do not affect the meaning of the symbol (3.1,3.2, 3.3). 1, Relative sizes of symbols are covered in section 7 of the standard, B. The identification code specified is in general not used on AMPEX drawings (3-4). C. Logic diagrams indicate direction of signal flow by symbol orientation, Arrows indicating signal flow are desirable , Signals leaving the logic diagram shall be terminated with a signal arrow. 1, The standard specifically forbids arrows immediately adjacent to any graphic symbol input or output, 2, Stylized waveforms, duration of delays, input and outpat pin numbers, and polarity notations should be used. Section 4 covers definitions, A, A LOGIC SYMBOL is the graphic representation of the aggregate of all the parts implementing a logic function, (para, 4.1) B, A LOGIC FUNCTION is a combinational, storage, delay, or sequential function expressing a relationship between variable signal inputs to a system or device and the resultant output(s), (para, 4.2) C, A BASIC LOGIC DIAGRAM depicts logic functions with no reference to physical inplementation, It should depict all logic relationships as simply as possible, (para, 4,3) D. A DETAILED LOGIC DIAGRAM depicts all logic and non-logic functions, Spocket locations, pin numbers, test points, and other physical elements necessary to describe the logic. It is used primarily to facilitate the rapid diagnosis and localization of malfunctions. (para, 4.4) E, A TABLE OF COMBINATIONS describes the active input/output conditions of the basic logic functions, (para. 4.5) 1, HIGH (H) more positive and LOW (L) relatively less positive. II-Al—. FEE 228006} IV, Section 5 designated LOGIC SYMBOLS. The following summary includes details from Section 6, PRACTICE; Section 7 , MECHANICAL AID; APPENDIX B, ASSIGNMENT OF LOGIC LEVELS TO BINARY LOGIC ELEMENTS. A. Logic devices are basically two state devices with inputs and outputs High or Low, regardless of actual voltages involved. 1, In one device, +5V on the input causes the output to go to ground, whereas ground on the input causes the output to swing to -2 volts. a, Or, with a HIGH (+5V) in, the output is high (Ground), b, With a LOW (Ground) in, the outpat is LOW (-2V). 2, The ACTIVE STATE (input or output) is indicated by the presence or absence of a small circle, which is never drawn by itself on a diagram (para. 5.3). It does not necessarily refer to a logic "1" or logic "0", or electrical reference states (app B, 20.1), a, Active inputs or outputs of a function may be logical 1 in either the more positive state -HIGH (Hl) or the less positive LOW (L) state; or a logical zero either High or Low. b. A small circle at the inputs(s) indicates that a relatively LOW input signal activates the signal, The absence of the circle indicates that a relatively HIGH input activates the device, ¢. A circle on the output side indicates the active state output is LOW; its absence indicates the active output is HIGH. d. The presence of an indicated active output does not necessarily provide a useful input to other elements, It may prevent the operation of some and enable others, B, The AND function is an clement whose output is active when all its inputs are active, ‘Any "non-active" input will produce a non-active output, (App, A,20,1) 1, The symbol below represents the AND function, INPUT SIDE OUTPUT SIDE ok ‘t Lt T1-A2A IN [OUT 1D BER B LILI ACTIVE OUTPUT uj Ht H|HIH 2, Use in logic diagrams Outpat high if and only if all the inputs are high (para, 5.1.) c jour x fe tx D u|ula active ourpur ||} # Low x f[tio Palen ‘Output low if and only if all inputs high (para. 5.4) usually called NAND GATE, (although STD does not use this terminology), 3, Multiple inputs to @ single AND function (para, 6.1). 4, Where a circuit is used to add inputs to another AND circuit, and the connection to this second circuit to the first is made at other than a normal input or output of the first cireuit the connection will be as shown below (para, 6.4) and will be labled E to indicate an extension, 1, ‘The E is omitted on AMPEX drawings. I1-A3 LOCATION 1 1 5 2 344 4 14 2H LOCATION 2 APPENDIX A FIG. 73. Multiple inputs to a single OR function (para. 6.1) amOmm DOW > D. The symbol shown below represents the EXCLUSIVE OR function (para. 5.6) 0.15 > INPUT SIDE j OUTPUT SIDE 1, The output is high (H) if and only if any one input is high and all other inputs are low, fweur | F ® bb |b Lou | uot | a woH [oo T-A4 = A@H) and B(L) or B (H) and A(L)5, The letter R, when shown adjacent to a symbol, indicates that the output resistor is adjacent to or in the vicinity of the hardwares physical location described by the internal tagging of that symbol (para, 6.4), It is not used on AMPEX drawings. 6. When the AND function is performed by two functions if their outputs are connected, the branched connection be enveloped by a smaller sized AND symbol (para. 6.3). A B F c DOT "AND" D C. The OR function is considered an element whose output is "active" when anyone or more inputs is “active'’. All OR inputs "non-active" will produce a "non-active" output (app. B, para 20,1). 1, The symbol below represents the INCLUSIVE OR function (para, 5.2, 7.1). eee! So = 0.8 INPUT SIDE 0,8 OUTPUT SIDE a kefos | 2, Use in logie diagrams INPUT [OUTPUT Inpur [ourpuT| = A[B| F “ A[B| F B F B F tf{t] LiL] a ti[u| 8 Lia] ui[t| # ui[t] oo ui[u[ # fal oo Output high (ff) if and only if one or more of ‘The output is low (L) if and only if the inputs are high (H) (para, 5.2.1) any one or more inputs are high (H) (para, 5,5). Usually called NOR gate, although MIL STD 806 does not use this terminology. II-AS2, Appendix A figure 11 shows another representation, 1 2 1 = > D> or E. Appendix B covers assignment of logic levels to binary logic elements, Paragraph 20.3 and 20.4 indicates that logic value "one" is assigned to presence signals for devices that are in their electrically active high or low input/output prescribed active states, Two examples are given. 1, Consider a device whose active output (F) is a function of two input signals (A,B) which follows the activity tables shown, Electrical Truth Table Activity Combinations A If the +2V is considered the activating level and is assigned logic value 1 and the -3V is considered the inactive level with logic value 0, an AND function is indicated, AND Funetion Activity States, T>- FP inpuT_ | ouTpuT B ees corny oro ny coomn b, If the -3¥V level is considered ACTIVE, and assigned logic level 1, an OR function results; the active level indicators (small circles) must be used, OR Function A D> States 3B F 0 1 1 1 LI-A62, Consider a different device which follows the Electrical Truth table as follows (para 20,3a). ELECTRICAL TRUTH TABLES A INPUTS OUTPUTS INPUTS. OUTPUTS B AB F A B F -3V 0 -3V Vv L L H -3V RV 3 L H L sav 3 3 H L L RV RV -3V H H L ~if any input is high the output will be low, a, If input (A,B) ~3V levels are considered activating inputs, and there- fore assigned the logic value "1" and the +2V output level (F) considered the activated output (logic value "1"), the AND function results, ‘The symbol combines the AND function symbol with input level indicators (electrically less positive than F), AND TRUTH TABLE A IN our F 1 1 1 B 1 0 0 0 1 0 0 0 0 =The device performs the AND function and an inverting funetion, b. If input (A,B) #2V levels are considering activating inputs (logic value 1), and the -3V output level (F) considered the activated output (logic value 1), the OR function is performed. The symbol combines the OR symbol with an output level indicator (electrically less positive than A,B). OR TRUTH TABLE A IN ouT F 0 0 0 0 1 1 1 0 1 1 1 1 ~The device performs the OR logic function plus inversion, I1-A7F. Paragraph 20,5 further defines the notation system. A given signal must be con- sidered and when necessary notated in terms of three independently variable parameters for every point in the logic network. 1, Logical state presence ("1") or absence ("0"), 2. Electrical state, high or low. 3. Activity state, signal line condition, noted by graphic representation (presence or absence of small circles) or English notations (line name high or low). a, Current AMPEX practice uses a waveform symbology rather than the terms HIGH (H) or LOW (L) which indicate active level for "English" notation, or the designation (+) or (-) or READY (-) READY = Indicates "1" condition (H or L) as defined by MIL STD 806, = SD rT 4, The paragraph demonstrates that the non-active (zero state) may be used to activate advice. a. Given the following Table: or 525 (+) Activity Device States State wv 3 BH) 1 0 P a) 1 0 Ty 0 1 x @) 0 1 YH) 1 0 Ba) x) X=(B+P)L BQ) or Pdi) or both BH) and PH) P(e) yan ¥=(B.T) (a) TL) P(L) and T(L) b, Line signal P is active or inactive in terms of previous definitions depending on what point in a logical network is being considered. II-A8G. Paragraph 5,8 defines a FLIP-FLOP as a device which stores a single bit of information with three possible inputs, set (S), clear (reset) (C), and toggle (trigger) (T) and two possible outputs, 1 and 0, 1, ‘The two outputs are normally of opposite polarity, A'L" is stored in the flip-flop when the "1" output level is active and the "0" output level is inactive, A "0" is stored when the condition is reversed. 2. The Flip-Flop assumes the "1" state when an active signal appears at the "S" input regardless of the original state, and the "0" state when an active signal appears at the "C" input. It reverses its state when an active signal appears at the ""T" input, "S" input shall be in proximity of the "1" output. T 1.0 FF s oT C¢ OR 1 *F s c 1 0 [ 1,75 _.| a, It should be noted that the state of the art has produced a much wider variation in flip-flop nomenclature than is specified in MIL STD 806. 3, Multiple flip-flop inputs may be physically integral with the FF function or physically separated, 4, Appendix A, Figures 12 and 13 illustrate equaivalent diagrams. EQUIVALENT II-A9BEAL} H, The binary register is a group of flip-flops used in parallel to store a number of characters (bits) (para. 5.9). 4 OR 2.5 Ratio 2. :1 or greater) I. The Shift Register symbol represents a binary register with provision for displacing or shifting the content of the register one stage at a time by means of the "shift" input, Ratio of symbol is 2.5:1 or greater (para 5.10). shat fmt Right Lett " Shift Parallel Input Shift Input. Parallel Input Input co wrallel Input shit seria |S 8 § R § RS R serial Serial Serial Input Output Input Outpat Parallel Output Parallel Output 1, Current practice is to use "Q" for "1" and "Q" for "0" counter and shift registers. The MIL STD does not mention these designators, J, The Single Shot ($8) (sometimes called One Shot-OS-or mono-stable multivibrator), when actuated, reverses state for the active time of the device, Unactuated state may be zero or one, Aspect ratio 8s 88 OR TIME |0} — 1, Current practice puts a bubble on the output which is low when the devise is active, II-A10K, The Schmitt Trigger (ST) is actuated when the input signal crosses a certain threshold, Output characteristics are determined by the circuit characteristics, not the input signal, Unactuated state may be "zero" or "one" when actuated it reverses state as long as the input exceeds the threshold value, Ampex ratio is 1:1. (para 5.12) st sT oR 1 ‘TIME TIME 1. The Operational amplifier voltage comparator is now frequently used, and not usually drawn as a ST, This is not covered by MIL STD 806. 40.5 ST ov 4 OR b 0.5 10.2 Time when input exceeded 40.2 . The amplifier symbol represents alinear or non-linear current or voltage amplifier, with one or more stages which may or may not produce gain or inversion, It includes level changers, inverters, pulse amplifiers, emitter followers, cathode followers, relay pullers, lamp drivers, ete, (para 5,14) 1, MIL STD 806 does not cover the operational amplifier, which may or may not invert, depending on which of two inputs is used, NON-INVER TING INPUT OUTPUT INVERTING INPUT TI-Al]M. The Time delay symbol 0.47 Input Output Input Side Side Side’ N, A general logic symbol is used for functions not otherwise specified in MIL STD 806, Aspect ratio is 2:1 or greater, (para 5.13) Lt] O. Paragraph 6.6 covers stylized waveforms. P. Appendix C, 30 or 7 shows the symbols for magnetic heads, (from MIL STD-15-1, item 61) WRITE READ ERASE READ/WRITE ONLY ONLY ONLY Q. Not presently referenced by the MIL STD 806 is USAS Y32.14, graphical symbols for logic stds. TI-A12REV, ¢ v-0001 THE BISTABLE MULTIVIBRATOR (FLIP/FLOP) ‘The basie gates discussed in Section Il - "INVERTER", "AND", "OR" ~ can be used to develop all other logic Units. One of the most dsefal cireuits In logic design is the bistable multivibrator, It Is usually called "FLIP~ FLOP". ‘The transistorized version was used in the AMPEX 1021 Intersyne, the MK IIT Editor and other accessories for the VR-1200/VR-2000 Videotape Reconders. +12v “TION VIL ~ PULSE FORMERS) which produced a narrow a, $1 and $2 were usually RC differentiators positive pulse b. If 81 is pressed, QI confucts, putting the junction of RS and RA near ground, and the base of Q3 at a similar potential, causing the collector of QS to move toward the -12V supply. (1) Through R6, R7, and RS the base of Q2 is put at a positive potential, so that when SI is released the static condition remains with output #1 low and output #2 high, (2) Pressing $2 will reverse the flip-flop, c, If both switches are pressed simultaneously, both outputs will be low. ‘The final state of the device wit depend ‘on which button is released first. Q1/Q2 and Q3/Q4 are two "shunt" NOR gates, similar to the Fairchild 914C two input gate used in the Model 1090 Velocity Compensator (VR-1200/VR-2000), it could then be drawn LOGIC LIST pur [| Att | ats | art] are ourpur mat FAL in w ich [| Low | Low | nicH r a _[ nich ovreur LL£0"_[ ice [incr [Low #2 tow | Low | No CHANGE uron_[ mcr | cow | Low ‘An even simpler version is used in the AVR-1 control logic to minimize swith bounce, As a switch moves from its normally closed (N.C.) position to the normally open (N.O.), it first bounces several times off the N.C. contact, then move to and bounces off of the N.O, position, urlAPPROXIMATELY APPROXIMATELY isms) ———> K—@ ome - Nc. conracr | 1 _transistion mime = 8.0. contact 1 LI le_cowracr BGURGH»|——} oe INITIAL INITIAL PUSH BUTTON PUSH BUTTON ACTIVATION RELEASE 2.3 ‘The baste flip-flop, usually called R-S flip-flop, or simply a "latch", can also be constructed using NAND gates, such as the MC 857 LOGIC LisT ovreur INPUT OUTPUT a ai [ars | as | ar row [| micn | HIGH | LOW nich | tow | vow | mon ourpur [auch [aica [xo crance, row | Low | micn | wich A, When Al-1 is low (S1 pressed) the output A1~3 is forced high, ‘This puts two highs at A1-5 and A1-6, so that A1~4 goes low, When the switch is released the low out of Al-4 keeps AI~3 high, b. Pressing $2 reverses the lateh, c. The state of the latch when both inputs are higgh will depend on which awitch was released last, 4, The state when both inputs are low and both outputs high is sometimes called "NOT ALLOWED" or "UN- DEFINED", ‘The above circuit may also be shown: ~oR~24 ‘The R-S flip-flop 1s usually made up of two NAND gates, and on the logic schematic may not always be drawn. In the familiar cross-coupled form, ‘The AVR-1 servo has one application where the eireuit functions as both a latch and a gate, ‘The RS A1-8/11 will also have two high outputs at times. 240K 15KHe ALA (60 2) 18.6 Ma) | 1-8 @240 Ha) (4.2 Ma) A1=19 (15 KHT2) (69.5 800) Lit 111 ats =| —- ave ALal Li 11 LL b, If the output, Al-11, drives an electronic counter (SECTION 1V) then the time between the GOH pulse and the 240H2 pulse canbe measured in increments of 63.5 see. Except in the ambiguous, or "UNDEFINED" state, the outputs of the R-S latch are always 180° out of phase. ‘When shown on logle schematics as cross coupled gates the outputs are given no further designation, However when it is supplied as an integrated eireuit with the cross coupling Internal, or on the simplified AMPEX ‘TRAINING DEPARTMENT simplified diagrams then output #1 Is usually designated by the letter "Q", and out ut #2 a8 "Q", where the input (Sl) Is called the SET input, and the other (52) the RESET input, However other designations are sometimes seen, particularly in older equipments, ouTPUT 1 ourpur 2 Remarks @ a Preferred 1 a Counter applications 1 T TRUE FALSE 8 R s FUNCTION(RECORD) FUNCTION (RECORD) PRESET (PR) ‘AR (CL) ms2.6 ‘The control inputs are defined in terms of the effect of the output, 8, The SET input is a level or pulse of the proper polarity ~ negative for NAND logie, positive for NOR logie ~ which places the Q output ina binary 1 state, With positive logic Q will be igh . ‘The RESET inpat is a level or palse of proper polarity to put the Q output in a binary zero condition ~ or a low in positive logic ‘The MIL STD 806B (SECTION I, Appendix A) symbol for an RS latch, and flip-flops in general i 9 INAND NOR 2.7. In the VR-1200 relay control, the "PLAY" latch used relay logic, FAST REWIND FORWARD PLAY RECORD K3A, Ki Kal Ki TAPE (TION wo SENSOR SWITCH 2a STOP SWITCH nav NO BEARING AIR D RECORD ‘Tape v3. Fig, 2.261 TENSION vipeo VE 1200 switch onthe, RELAY Logic z fs SiuPLinieDy a, To activate the play relay, K4, STOP relay K6 could not be energized, Through normally closed contacts of KS (Rewind), K2 (Fast Forward), K4 (PLAY), the tape motion sensor switch, the PLAY switch, aod KS (Record), '24V is supplied to the K4 (PLAY) relay coil, Contacts K4A keep the relay energized, b. Note that an equation for the STOP LAMP would say (1) (PLAY) (FF) REWIND) BTOP) crape LoapeD) 2) This would be useful to the remote operator. 2,8 Figure 2,81 is a simplified logic schematic for the AVR-2 control logic which performs the same function, a, To "SET" the "PLAY PEI MIT" latch AG-8/A18-6, putting AG~8 high, gate 17-6 must go low. (1) PLAY switch pressed, @) A18-8 high. ‘This condition is satisfied if the tape tension switeh is closed, or the Video Head Optimiz~ (VHO) mode has heen initiated, - the VHO mode eannot be initiated until after PLAY PERMIT latch k been SET, and the PLAY LATCH AS2-8/A32-1 set (82-8 low), m4L LLC RECORD 2 LLC PLAY “2 ~~e-{iie TAPE TENSION PLAY LATCH LOCKOUT Toews f TO F/F RWD LATCHES INPUTS FF ave-2 CONTROL LOGIC m52.9 (9) Gate A25-12 bigh. = The STOP bution must not be pressed ~ STOP takes precedence over PLAY. = ‘The HEAD AIR switch must be closed, indicating that there is sufficient high pressure air to support the Video Head air bearings. = Note that whenever A25-12 is low the STOP latch A13-8/A1-12 will be SET. b, Satisfying gate A17-6 puts A6-8 (PLAY PERMIT) high, and, through AG=11 goes to the reset inputs of STOP, FAST FORWARD, and REWIND latches to terminate whichever of those modules were present, ©. However, to transmit the PLAY PERMIT command PLAY latch A32-8/I1, A18-6 must go low, with all of its’ inputs high, (1) Two inputs - that the STOP COMMAND is not present (A12-6 high) and FAST FORWARD or REWIND command not present (A14~3 high) should be satisfied, since the PLAY bution put AG~8 high and A6-11 low, resetling the other modes, (2) The combination of R1/C1 is a "WAKE-UP" circuit to make certain that when power is wrned on the control logie puts the machine in STOP, ‘The function of PLAY latch A32-8/11 is to delay the transmission of the PLAY command when going from Past Forward or Rewind to Play until tape motion has stopped. (1) IEF or RW modes had been present prior to initiating PLAY, AL4-3 and AS1-2 had been low, and MOTION MEMORY LATCH A22-6/11 as "SET", and A22-11 Tigh, (2) When PLAY PERMIT LATCH AG-8/A18-6 is set, the "R” input to PLAY PERMIT latch A22-8 goes high. Bat the "S" input is still high, and the latch does not change state. (8) AS1-2 is high, since FF or RW mode was cancelled by PLAY PERMIT latch A6-8/A18-6, (4) When the Electronic Motion Sense Input to MOTION MEMORY LATCH goes low indication that tape hhas stopped on the transport. = 422-3 goes high and 422-11 low, = Play Permit latch AS2-8/11 reverses, In some of the training block diagrams, the NAND latch has been simplified to a block with no S,R, Q, or Q designations, ‘The PLAY lateh (Fig, 2.81) would be shown: prey No ‘MOTION, 1 ‘The SET-RESET-TRIGGER, oF RST fllp-flop Is a variation of the basic RS fli-flop which can be operated synchronously ~ the output will change state not only on the basis of its Set/Reset inputs but of a clock pulse lew. change. < Logie List ste t [om [To a a [ow W w_|_a_| nor perine: + af. # w|i. Lf nf. [a a Lf. n_| an R x [x i [an "x" DON'T CARE a, The expression Qn+] indicates the condition after the elock transition in this ease from a low to a high. b, The "X"" in the "S" and "R" columns is a commonly used symbol to indicate that the state of the " "R" inputs is immaterfal as long as the "T" input is low. cc. The "T" input is more of a control input and is sometimes used that way. and u-6d, Some versions require a negative level to enable. 8 @ STR a 8 a R 3.1 The operation ean be shown with a eireuit from the AVR-I buffer, using the MC12141, RST which requires « positive level, and the MCI2I51L, which requires a negative level to change state, "C''for "clock Is used Instead of "", cLock IN 5. ASE 1 case 2 2-6 aN) [ig a a / voc yF LELI r ane 7 t » i 7 1 Ana2 ‘ ' a i aie $ a3 ys 1 aig + t ” rr sec ysec 1 a, RST A2-2 goes positive as goon as the input goes positive, since the clock input is permanently low. b, RST A2-12 changes state at the same time as 2-2 In Case 1, where the clock is low when the input pulse arrives, Inease 2 the input pulse arrives when the clock is high, and A2-12 does not change state until the clock goes low. 4, The buffered store RS flip-flop is sometimes called a delay flip-flop, or "D Latch". 4,1 One version is the SN 7475, a, Symbol and logie listae a | a fu fe uf L u fu da clita b, With the clook input high, the latch is "Transparent Input is high, (1) With the "D" input Low, Gate 9 output is low and Gate 2high, Gate 4 output is low, and the two lows Into Gate 5 keep its output high, = the @ output follows the D as long as the control (C) (2) With the D inpat tigh, Gate 2 output is low and Gate $ output high, placing pin 16, the @ output, high, + When the Control Inout, pin 19 is low, the state of the output latch is frozen, since both Gate 2 and Gate 3 hhave low outputs. ‘The state of the Q output is a Memory of the level at the 1) ingstt before the control input went low, 4.2 One application in the AVR~1/ACR-25 makes use of the "memory" capabitity of the "D" latch, F sy ota a 0 I oo 22 7 Toate ive = Convtweren kx b t 7 ue wacnenc nmeaon ue RELAY 2, The relay is x special memory type with permanent magnets in the coil assembly. Th acts like an RS flip-flop. “A ground supplied by LLC #2 and with 24 volts momentarily applied by the switch and the relay would move to the lower position, b. As drawn above the Control input of latch 5 ls enabled, Since the D input is at ground, the @ output is low, ©. When S1 is pressed, the control input is placed tow, and the latch is frozen with the Q output low. Gates 3 fand 4 are enabled by the high out of Logic Level Converter 7. Since the Q output of the latch Is high, the high ut of Gate 4 turns on LLC 2 and supplies a ground return to KI-B, which has #24 volts appled from switch $1. () When the switeh is released, the control input to the latch ig again High and it is transparent, The +5V from the relay pute the @ output high. (2) The circuit is used to provide a memory, even with power off of the command, in this case 7.6 or 16 ips tape speed. It is used in the AVR-I and ACR-25, 4.3. The Texas Instruments SN 7474 Dual D Type edge triggered flip-flop is similar, However, the Q output follows the "D” input only after a positive transition on the clock input, Additionally it has PRESET and CLEAR inputa which over ride the D and Cp inputs. Logic ust 2 pen px] ct] p [co [qn [Gua I 5 i a-dor Pe cpp-is PEPE IX |x} ef on a lg Lfa|x|xfs [ot TE TT 2 wf olx |x] ae [ie | orperiven uf uta [FT L ufut{i [rt i H "R= DON'T CARI urs4, Instoad of the notation "Cp" or "clock" to indicate edge triggered devices, the AMPEX Training Department is using the notation" pd" to indieate that the device changes slate only on & positive transistion. Tre symbol" -G, ‘*indieates a change of state on a negative transistion, b. ‘The expression "Qn#1" denotes the state of the Q output after a positive transistion of the Clock Pulse (Cp) Input, ¢. Internally each D type latch consists of three NAND gate cross coupled R-S Mlip-flops, — HicH — 1ow DEPENDS PR — bon's caRE ON STATE OF Co INPUT. qs Q cp cp DEPENDS ON STATE OF Cp INPUT D CLEAR 4d, Logie List for typical Data Transfer. See > [|e [9 [ee] [oe] a a fo dada fo fa fe] e | mmarsrare arten penser moves nich @ fofofofr fr ]r}rlo| o-x0w @ fofafofafrafofa] 2 -mecn w |r fafofafofrfola wo |i fofrta]afofols ow [tifa fo}sfofrfo ©. This edge triggered latch is widely aed in the time base corrector TRC800/TBC-800, andthe AVR-2 digital time base corrector (€) Diviae by two a ce 8 2) Reclocking, oF time quantizer eo LI od a f. Its use as a short term storage device-memory- will be covered later, ‘The last flip-flop to be discussed Is the type generally referred to as a "J-K" flip-flop. It uses a combination of R-S flip-flops and gating so that the outputs change state only when the input clock makes a transition~ usually from positive to negative. It Is similar to the RST flip-flop (para, 3) it is essentially two RST flip-flops a MASTER, which is usually set-up when the clock goes high and a SLAVE output RS flip-flop, which usually takes the state of the MASTER F/F when the clock moves low. u1-9cL oGie LIST pr [or [3 | & [ep [ant [ana Lu x [x [a [| x=powr care a fe [x x [ula wf [x [x [x [a [oe | sorantowen H a a Hl HfL a Fo Ts #2 u tute [e [fl ][ en NO CHANGE a, When PR (PRESET) or CL (CLEAR) input is low, the logie list is the same as that for an RS flip-flop ~ the J, K, and Cp inputs are inhibited. b, When both J and K Inputs are low, then the flip-flop remains in a stable, inhibited state, If both J and K are high it divides by two = or reverses on every negative tr When "I" ts high and "K"" low, "Q" will go high, When "K"" is high and "J" low, "Q" will go low on the negative clock transistion, stion of the clock, It can be connected so that {t operates as a D type edge triggered lateh, eo JUUUUUUUUUUUU UIUULULILUU owl LF Here is a cireuit, similar to one in the AVR-1, Work out the timing diagram. It will reach a stable repeati sequence after several clock pulses regardless of what initial states the three JK flip-flops are in. oP PPP EPR e Pee xa StH cll cela 345678 9 10 evock JULI A B © ut-10BEsaWrMenT REV 5 ‘y0002/V0012~ SECTION V (obs) CTION IV COUNTERS 1, One very important uge of the flip flop is its use in binary counters. They can be used to generate binary numbers or binary coded decimals, the measure time to count events, and act as frequency dividers. ‘The counters may be made up of individual flip flops usually the J-K type, or come as a single integrated cir~ cuit, usually of four stages per circuit, 2, ‘The basic binary counter is usually designated a "ripple" counter. PRESET CLEAR sv eer 12 3 4 5 6 7 8 9 1011 1213 14 15 16 17 FREQ PERIOD cuock PULP noo 5004s ° ofrfo fr fofr ofa Lops [ofa [ofr fo fr fo fr 1L000Hz 1 o oft to ofr ito ofr ipo offtoof 5 2 ooo oft ito oo offriipo 250 [ooo cove offitiiiiipo 125 8 ms 2.1 This simple 4bit counter has divided 2000H down to 125K; the four outputs generate the binary numbers from one to sixteen; the 2° stage defines a time period of 8 milliseconds. a, Note that a four stage counter defines the binary numbers from zero to fifteen, or 2" -1; in this case 244 = 16-1 = 15, It is called a ripple counter because the effect of the input clock is passed through each stage to the next, and the propagation delays ~ the time after the clock goes low that the Q output changes state ~ adds at each succeeding stage. a, The MC 852P has a typical propagation delay of 40 nanoseconds, Tn the above counter this would not have caused any problems and would be difficult to measure b, If the clock frequency were SMHz, with a period of 200 nanoseconds, the effect would be quite noticeable, especially when all stages were changing at the same time, such as when the counter moves from binary 7 to binary 8, or 15 t0 0. 1-1fe 20008 y to Wns TI 10 ° 7 of I Io | a Lol ot \ 1 H iI Lol 1 1 i Lieot ig ' it T o! it $ 1 1 ol Fis oo ©. At SMHz decoding would have to be done very carefully to avoid ambiguous results, However because of its simplicity, it is still useful, 2.3 Either the Q or Q outputs of the counter may be used, In one application, where an MC 858 is used preser cuock preset — coos UUUUUUUUU 1-5) 0 Loft Lo fi lof Lo] alat-s) 0 ofi ajo ofi to oo 0 oft 1 ao will be shown later. ° —_ 7 = “ 2.4 The MC 890 feu monolith divide-by-sixteen counter which i guaranteed lo operate up (0 16MII2. IL hhas 4 outputs, a single Cp (Clear Direct), four Sp Set Direct) Inputs, one for each of the four stages. Tt clocks on negative transitions, A, To preset a given number into the counter, first a low is applied to the Cp input, then a low to selected §,, inputs. W-22,5 The ripple counter ean be set up to provide a Binary coded decimal (8421 code) output. The SN 74196 is capable of being wired externally to divide by ten in a BCD format or in a bl-quinary, format, where a symmetrical + 10 square wave is obtained, Binary Coded decimal connection (simplified-Clear, load not shown). 9 2 2 56 a 8o-d> ~ FREQ. PER e UU UU ToMnz 1 wsee aa of lof lof left lof Loft loS saz 2 see ap ooo ofi tjoof tooo ac ooococeofitiipoe @ Tijooooovoofiijo iz — tusce ging High mgIg IgM MgHnNgIgimgT }+—— 1 see ———>] b. Conneetion for "bi-quinary", or sym 6 roMz, ap ofr loft Lo _ofo Jo fro o fro fi loo ac o oft tLo oof oloo oft 10 0 L_ ao oo 0 oft]oo o ofifo o o oftfo aa Triiijoooo ofti11ijo 1 MHZ2.6 ‘The SN 74197 is the binary, or divide by sixteen version, It can also be used as 4D type latehes, DATA A DATA B DATA C DATA D yeuse 4 10 a i count Loom 13 1 [16 Aan [tame hen ut ‘To obtain a divide by 16, QA is connected to clock 2, and the input clock applied to clock 1 The Count/Load input is used in conjunction with the data inputs for D latch operation, "The Clear input, when low pats all outputs low, ‘The Count/Load input can also be used to Preset the counter to a starting point other than zero, that counter also has Although not shown in the simplified drawing of the 74196 in paragraph 2, the count/Ioad, Data, and CLEAR inputs, ‘The synchronous counter is used where the delay of the ripple counter is not acceptable, ‘The syne ~ hronous counter uses gating, and allows all stages to clock simultaneously, on the same clock edge. =A) (@B)(QC) =(Q4) QB) TO ADDITION STAGES (QA) (QB) CHAD) Qa eB ac ap ) ey @) ey) weaa oP PLP eM Ly L ao oft ao oft t]o 0 a e000 oft trio @ o cs "Tho SN 74193 SYNCHRONOUS 4 BIT UP/DOWN COUNTER is logically similar to the above example, a, Logie Block: b. Logie: 5 _[uoap cuEaR 7 ° —Pounrue —— 4 —{gounr-pown PATA INPUTS Qa gp ged BORROW 2a te 2a) 2500) Low Input to LOAD (11) sets QA “A, QB = B, QC=C, QD =D High input to CLEAR (14) sets @A = QB ~ QC = QD = LOW CLEAR (14) overrides LOAD. Clocks on positive transitions, Clocks should not be applied to COUNT UP (8) and COUNT DOWN (4) simultaneously, Clock not in use should be held high, CARRY Is negative half cycle of input COUNT UP clock when all outputs are high (Binary 15), BORROW is negative half cycle of input COUNT DOWN clock when all outputs are low (Binary 0),A logic block of QA stage: DATA A LOAD f{—_______» Loan “> CLEAR count uP ea 0 QB a RIGGER counr DOWN CLEARL Load DATA Logle Schematic of four stages: LoAD crock, DOWN OH paTac aa ap ac — same as binary COUNTER ————» a, The 2° stage is identical to binary count ~ b. The 2} stage, at glock pulse 11 would go to a one in a binary counter, Here, it stays low, Note that at this time the 29 stage is a one - or the 21 stage clocks normally unless 2° is a one, he 2° stage acts as it would in a binary counter: Changing state whenever the 2° and 24 move from binary 1 to binary 0, a, The 2° stage on the 11th clock pulse in a binat to zero, Or, it acts the same unless 2° and 2 counter would not change: In the BCD counter it goes are both "ones", e, Summary of BCD gating required. (1) 20: divide by 2 @) 24; not allowed to clock if 2° is high (2: clocks whenever 2°,2* are high (2: clocks whenever 2,27, 2 are high or when 2° is high. f, Logie eireuit, BCD counter: (@Qav@D) (QA QB)QC) cLock (@an@B) 4Q4)(@D) -QA QB QC + QA QD Wescock SIU on 4 oe Pb Pope Mire an 0 oft to of t]o oo oft t]o ofr ae oo I oa M1 ec 0 00 oft i1 ifoooeo ftir 1 itfooe ca oa OlgaaseTs 901234567890 3.3 The SN 74192 Synchronous four bit up/down decade counter will generate the BCD code as well, a, Logie Block: TOAD CIEAR A BC D cAnEY —pcount-uP DATA INPUT. I> COUNT-DOWN BORROW 1B ay ate 2a) amy b, Logie: Low input to LOAD (11) sets QA = A, QB =B, QC = C, QD =D Clear overrides load High input to CLEAR (14), QA = QB, QC» QD ~ low Clocks on positive transitions. Clocks should not be supplied to COUNT UP (5) and COUNT DOWN (4) simultaneously. CARRY is negative half eyele of input COUNT UP clock when QA and QD are high (BCD 9) : BORROW is negative half eyele of input COUNT DOWN clock when QA, AB, AC and AD are low (BCD zero) Ww-9caRRY our fe, Logie Schematic DaTAB DATAA Thur LoaD DATA @ DATAT BORROW our Loap crock ORD J pos ope CLEAR crock up wir CLEAR 4, When docking up - counting from zero to nine the gating and waveforms are the same as these in paragraph 3.2.1, fe. Counting backwards, i ean be analyzed using equations BoD pec 2 2 2° stage: +2 o o ° 0 ° ® 1 ° ° q stages (GATE 7 and 10) @Ay (QB 1 QC + QD) 1 ° 0 ° Bap ° 1 7 1 6 ° 1 1 ° @vQB) - Tec 5 ° l ° 1 4 o 1 o ° (A) BO, 3 o ° 1 1 2 ° ° 1 ° @®) aD 1 ° ° ° ° ° ° ° ° ° 1 ° ° ’ . 1 o ° ° Ww-10Bep 2 stage, Gate 18 2° 2 a stage, Gates 10 and 19 = QA QB 0 ° ° o (GA GB) (QC + QD) 1 ° ° 1 | 4 © ° 0 = AD @D ° T 1 1 ° 1 1 ° ° 1 ° 1 ° 1 o 0 AW acy ° 0 1 1 ° ° 1 ° ° ° o 1 ° ° ° ° T ° ° 1 {, The Waveforms for a backward count: count own [11 FLU aa off TL Po foe fe fT. GATE 7 1 n nnn n ap 0 0 oft 1]o oft z]o 0 o oft to oft tp 0 0 0 GATE 15, 1 h n n il ac oo offi ilooooo offiti tloo000 off GATE 18 @ oft tloo oo oo o oft tfo0 00000 off ifo GATE 1 4 Counters are frequently used for purposes other than generating binary nambers in logic cireuits, This section will present some typical uses of binary and decade (BCD) counters, using the SN 74192 and SN 74193, 4,1 To drive a tape timer a 240Hz (626) or 250Hz (625) capstan tach signal is used. This must be divided by 8 40 30H for 525 standards and by ten to 25Hz on 625 standards Ina machine with switchable standards the SN 74192 Decade counter can be used directly to provide the 25H2 pulse, but modification is necessary if the same counter is also to divide by elght on 525 standards, ‘The tachometer signal is first retimed to a system clock, a fairly common technique in logie circuits 240/250He 825 CARRY snTa192 Ao Bo_Co Do 500KHz CLOCK 12 RSE eae] ‘Timing for A7-3 a ee te 8.5 usee sore crocs PLL FL LILLE __L_SL_L i ! suo po oh ' cape _ Pata ih m1 ‘ 1 ' 1 1 t $$ ! - 1 A9-6 1 . ‘ i 1 a Ly ars | ‘The gate A7-8 has a 2 usee pulse out for each positive transition of the tach signal. b.Operst sof eouter Ads on 525 ataarda 25 ' ' : woo Tho Pr lolita Lo fle a rr ' ae 9 0 a SP Leo Po ! ' aso 0 0 ol [To Le Ne7 t ast TLe_o Mo o oo fr ase Fone ome 35-2 A35~6 ©. On 625 operation the counter has no special gating, since A90-12 is inhibited, and the carry pulse is a two microsecond pulse every 40Ms (2582) In a tape timer, It is necessary, for tens of seconds and tens of minutes binary coded decimals, to restrict the count to the BCD numbers zero through 5, with the capability of counting forwards or backward. In the AVR-1 tape timer this clrcult required ten diserete integrated circuits ~ without Including those whieh allowed a thumbwheel preset time to be entered. The Tape Timer in the ACR- I-12WSS seein accomplished the same thing with BCD FROM PRESET SWITCHES UNITS OF SECON CARRY aa UNITS i ogseconps ——| ‘BORROW soo 4 KHe, cLock count DOWN (3 Kee TO DISPLAY 2° 2) 2? 23 DEC wy) (yy O] 0 [uo] o to foo} 1 o 1 00 500KH2 11 0 0 500KHz o fo] 2 1}o fo} 3 0 1 10 500KH2 11 40 500KHz O}o fo] 4 1]o for} 5 o}0 [oo] 0 DISPLAY WEIGHT «29 a! a, The Units of Seconds Carry (or Borrow when counting down) occurs every ten seconds to advance counter A28, D, Whenever the Bo, A28-2, Is high 500KHz pulses are gated through A25-6 to advance the counter, ‘The timing chart below covers the period when the Units of Seconds carry is advancing A28 from a display of ten seconds to twenty seconds. 20-5 (0.8, CARRY) af 2 se 25-4 (600 Kila) mn FLL Lec ]s- 0.5 nv00 426-8 (Ay) @) 7 Lo 28-2 (Bo) : 1 A28-6 (Cg) @) = ' 2 28-1 09 @) 0 0 I-13Mass In another application, there is a requirement to divide a 240H1z signal by four to GOHz or a 250Hz signal by five, to SOHz. In the simplified block below, pulse former #1 produces a positive 2 ysee pulse for every negative transition into it, and pulse former #2 produces a 2 weeo negative pulse for every nogative transition into it, PUISE, FORMER, a 2 psec Iw —_} 625 (GND) LoaD Arby C1 Dy PR, SN Ta192 Ao By Cg Do a, Timing, 525 4. IN an ao a Le a tT 1 bp se op ee co pb 3 —elr 2be 2*sy rite 2“si 1lt GATE 1 DE #2 Gate e 16.8 MS (1) Whenever Gate 1 decodes four lows (zero) a pulse is gated through Gate (2) When the next positive transistion clocks the counter to Binary one, the negative transistion out of Gate 1 is formed into a two microsecond pulse which loads the counter back to binary b, Rather than drawing the waveforms, merely setting down the binary combinations should suffice, on 625, da Dene ee | De ° t 1 1 20Ms 1 o o 1 LL w-144.4 ‘The counter can he used to provide an accurate and consistent delay, 2 usce ur 16.6 MS oon) By 1oMHt2 CLOCK ‘A 2usee pulse at a G0lls rate sets RS Latch A28-3/6, whose low output has been Keeping the counter preloaded. "When A28-3 goes high, 10MEL2 (0.1 usec period) is gated through A7-2 to clock the Counters A carry pulse out of A2T-12 resets the latch and stops the counter, putting ft back to ite preset state, What is the width of the positive pulse out of A28~37 "This i a problem which is not practically solved by drawing waveforms. (1) Consider that there are three four stage binary counters in series, ‘The maximam "mumber binary counter ean go to before jf goes back to zero is 21, where nis the number of stages, Or, this counter will count to 219-1, oF decimal 4095. The next elock will drive it to zero, al While itis at 409, the negative haif eyele of the input clock will be gated out as a earry, which {In this cage will stdp the counter by resetting latch A28-2/6, (2) The pretoad of the counter as Ay 2) ooot 8 eb ow ov 08 cy aw" 9000 p, ey "0" 0000 aw ay athe cores oose oes oiae nat o2s6 0000 o 000 pose reas (8) Clock puses required to dive to zro are 409-2540, oF 1850 clocks. snc the clock rte has a period of 0.1 psec, or the waveform out of A28-1 (a high for 155 microseconds ~ approximately 2 1/2 horizontal line (4) The delay can be changed by changing the preloads on the counters, elther by wiring or with logic commands, wos > 199 74193 CARRYP ti aaTTS SEAMB ewe 4.5 Another example of this type of circuit uses the SN 74192 BCD counter. tomes AIS (PERIOD sN74192 1010 oot oto » 5, 8 1 4 4, Since BCD, or decade counters are used then the preload can be considered as decimal 4785. A carry ut of A14-12 Indleates that the counter is at 9099, and will move to zero. The carry pulse however Will preload the counter back to 4785 after about Sons of delay provided by AZ0-11 and A18-8,10, und 12. 1b, The counter then takes 9999-4785, or 5214 pulses. AL4-12 then Is a series of pulses every 521.4 micro~ Seconds as long a8 the ENABLE signal is high. 4.6 ‘The drawing "GENERATION OF COMPOSITE SYNC" is another eircult whieh should be analyzed with a minimum number of waveform drawings. 8, Logle fanetions (1) 5-5 GN 7474) ie an edge triggered D latch used here as a divide by two. (2) A2 GN 74154 is a binary to decimal decoder with enable inputs Gand G2, Mf G1 or G2 or both are high, then all outputs are high when Gl and G2 are both low then the binary coded decimal Sutpat of counter Ad will cause one outout to go low. (2) Multiplexer 415-2 was disgussed in section 11. ‘The output will he the inout selected by the binary umber appearing at Sp (29) and 8, (21), ‘The mulliolexer iaverte the signal at the Z output. 1b, ‘The outputs of the decoder A2 provide the J input, and through multiplexer A1d, the K input of JK flip flop AG, whose Q output ig composite sine, The clocking of the flip-flop Is inverted 80 X'It. (1) Except during the vertical drive interval, the decoder is enabled once during a horizontal Line, ‘when both outputs of counter Ai are low,” A decoded "3S" (A2-4) controls they Input, and a evaded "6" (A2=7) the K pu (2) Looking at the output of A4 during this interval aL fe eb see Ate T Ate AAs Att DECIMAL UU ate need bette 1 0:8 pase As-4 a) « 6-19 @ 3X1. nace >| {@) This pattern will repeat at a horlaontal rate until the start of vertical drive, Vertical drive will start when the BCD counter is at zero, but starting on one field when A8-2 (H) is high and on the fest when it Ys low the half line difference.zuwee"t WONT ‘DNAS SLISOSHOO 30 NOLLYWANGD onas auisoaNoo tT astna IoLgA, ie fs 4 * tt gta ery TOE s-elv au | ——| SHSLNMO9 TYOLLUA OL He lux oae-vw 1 fit x oe-ev aes ot mf aa za 8 FUUUUUUL = wm asimaue NS Sosite°0 eb 7 SWHOSAVA ONDIOOTO Saravana suntan a a AS MOT SSTAd HE agTaWNa SLAdLAO 2¥ oorrtro0go0 ooTLooTToo0OL +} ss" & at ‘aavoaa ore t ast 2 HZ/T FoLOroOLOLoLOLOLOLOLOLOFOLOLOLOLOLOLoOLOLO be sost grax nest ToooD0TTILODOODOTTTI 0000 (Obs-HV OOTLOOOOTIOOTIOOOOTTOOT TOD (aderv (vbie-v ez" 1 weit©, The generation of the equalizing pulses is similar to that of the horizontal syne interval, except for the width, It must start at the same time, since the negative edge of an equalizing pulse must have the same timing as the leading edge of syne, (Q) ‘The equalizing palse timing, Ada of: feyT:feJ:]Jo[7]-]Ji Jo ae [oo | a o {| 1 0 A-6 0 a a Att 1 DECIMAL oliTe2 a+ tsTeli ts To are ULL. A5~5 6-440) 6-34) AG-13Q) 167 .8= 2.4 usec d, Its left for the reader to use similar techniques'to develop the timing during the 3H vertical pulse interval, I-18TRAINING USE ONLY vo023 SECTION 6: THE SHIFT REGISTER REV 2 In general, the state of a binary counter stage after a clock pulse depends on the condition of all previous stages prior to the clock pulse. In a shift register, in general, the condition of a particular stage after the clock pulse depends only on the conditions existing at the output of the previous Stage prior to the ap- plication of the clock pulse. 2.1 2.5 The term "shift register" is frequently shortened to "register" The clock pulses are usually called "shift pulses". The term "ring counter" usually describes a special ap- plication of the shift register. It can be used as a short term memory or storage device Information can be retrieved without destruction. The register can convert "serial" information into "parallel" data. The television tube could be considered a serial to parallel converter. The television signal is trans- mitted serially - any instant of time contains one bit of information; or a horizontal sync pulse is followed by 1/525th of the total information required to display a complete television frame or picture. Because of phosphor persistance, the information pre- sented serially over a period of 33 milliseconds seems to appear instantaneously. Continuous updating with new information produces the illusion of motion. The waveform monitor, particularly when operated at a field rate, displays the same information in its serial format. The register can also convert parallel information into a serial format. The television camera converts the scene in front of the lens into the serial television signal required for transmission.3. 2.6 As a memory device, the shift register may accept in- formation in parallel form, hold (delay) it, and then transmit it in serial form or parallel. It can also accept serial information and store it, then read it out in either serial or parallel form. The RA-4000 TIME CODE GENERATOR puts the information from a clock counter into a register in parallel form, then reads it out on to tape in serial form. a. The RA-4000 TIME CODE READER takes the serial in- formation coming off of tape, puts it into a reg- ister; then the parallel outputs of the register drive a binary to decimal decoder and displays the output on a nixie readout. Review of the J-K Flip-Flop 7 Cp K If both J and K are HIGH, the F/F acts as a divide by two whenever both J and K are high and the Clock Pulse shifts positive to negative. a. In the counter application J and K were tied together. b. If J and K are separately controlled, the Q follows J on the clock pulse transition. c. Sp and Cy override any other inputs VI-2A SEX bela 3.2 TRUTH TABLE, typical J-K Flip-Flop (Q,t1 is time after clock pulse has made plus-minus change) J K Sp Cy Q Qe 2 Qa PRESET, ANY _| STATE || LOW Low || wien | HIGH|| HrcH | HIGH (N.D.) RESET, Any _| stare || H1cH | Low || Low | HcH|| wtcH | HIGH TABOR DATA Any_| stare || Low HIGH || HIGH | HIGH|| Low | Low INPUT BINARY OR BCD HIGH | HIGH || HIGH | HIGH|| HIGH | Low || Low | HIGH COUNTER DIVIDE BY 2 HIGH | wIGH || HrcH | HIGH|| Low | HrcH|| HIGH | Low Low_| Low HIGH | HIGH || Low | Low || _urcH | HIGH INHIBIT (STORE) Low | Low uicH_| urcH||H1cH | HcH|| Low | Low SHIFT HIGH | LOW uicH_| HcH|| Low | HicH|| HIGH | Low REGISTER HIGH | Low HicH_ | rcH|| HIGH | HicH|| Low | Low OPERATION Low | nicH_|| ncn | nrcH||HtcH | Low || tow | nich SERIAL [Low | HrcH || HIcH | HicH|| Low | Low || HicH | HIGH | 3.3 The state of J and K must be established prior to the clock pulse transition from positive to negative. 4, The J-K as a memory or delay device. 4.1 In the AVR-1 Control System, a flip/flop is set by hit ting the PLAY button momentarily. The flip/flop remains set until STOP or SHUTTLE is commanded, remembering that the machine is to be in PLAY. 4.2 Another application, which is in a sense a one stage shift register is the retiming application. It is fre- quently necessary to retime a random event to a precise oscillator, or to external information. a. In the HS-100, the slow motion rate is determined by a free running oscillator operating at approximately the desired frame rate. The oscillator is retimed using vertical sync. VI-3gs 22S $$ b. In the AVR-1 Blanking Switcher, the Headwheel tacho- meter signal is retimed so that each of its transitions occur during horizontal blanking - or each edge of the 240/250 Hz signal is delayed up to 64 microseconds. 240/2S0Hz 1skHz—] c. The above techniques are also referred to as "Time Quantizing". 5. The basic shift register. DATA OUT PARALLEL CLOCK PULSE "DATA" a) DATA OUT SERIAL DATA OUT SERIAL — IN CLEAR CLOCK CLEAR DATA 1 (Q) aloo. 2 (Q) 1 3 (Q) 4 (Q) rjoo ft vI-45.1 Step by Step Operation CLEAR ~#----$----6-- a. State while CLEAR Hone d, After Clock 3 of DATA OUT e. After Clock 4 6. To produce a two phase output with 90° between phases: cLock #1Q #2.Q VI-5a The Shift Register is available as an integrated circuit Ta DL Ds Do DL Ds Do Fairchild FC9328 Dual 8 Bit Shift Register, AMPEX P/N 586-303, ow Di (Ds) (Do) + (Ds) (D1) @) |_ ) cy ar] 34 © 7 CLEAR SERIAL DATA OUT Used in MK IV EDITOR (AVR-1) Includes two eight stage shift registers Serial in, serial out capability only The register shifts on the positive transition of the clock, A negative on the CLEAR holds all stages reset, and Q7 (the eighth stage) is low VI-6WUT rasa] [3 A 4 woo vt OA LI) EI {sb fp wo " sd petal &é 6 6 6 dS 6 +a01stBer 31q g eTBuTs © UTeIuOD XeasTBax ano TeTTeAed/ut TetTIes OSP-98S N/d X4dNV ‘OL8SWT XOIIMPUOrTUES Te“OTIEN OUL ZLClocks on positive transition Negative on CLEAR holds through Q8 low. Q8 output is equivalent to Q7 output on the Fairchild 9328. Used in MK IV EDITOR (AVR-1) VI-8PMS sasseron] Lda LAKHS IHOIY LATHS L 1no a ino a ino 9 ino 9 Ino TaTIvaVg uv’ ino Ln0 V uno v — § NId TeULOIxXE :TLON ‘ZoystBol aFTYS 7FOT-IFTYS WBTA ITq IOI S6yL/S6YS NS S3UoUNAISUT SeXaL ndLNO TATIVEVE a o aa 1 a a 7 9 3 ® Indino ALNdNI Ind Lno ¥ y ap 5 2 s s8. The Texas Instruments SN 5495/7495 Four Bit Right Shift - Left Shift Register is a very flexible unit. 8.4 Serial in, serial or parallel out Date may be shifted in from two directions Clocked parallel input Data transfer occurs when the clock pulse shifts from a high to a low. In RA-4000 operation the format of serial time code information recovered from magnetic tape depends on the direction of tape travel - the most significant bits may be deserialize and standardize the format. The SN7495 may be operated in a shift right-shift left mode to accomplish this. a, If a low is applied to pin 6 "MODE CONTROL" , the number 1 gate are enabled. Clock pulses at pin 9 “CLOCK 1 RIGHT SHIPT" will move data appearing at pin 1 "SERTAL IN" to be shifted to the right, A-B-C-D, If it is connected as shown, with the output of each stage connected to the input of the previous stage, data can be entered serially in the opposite direction. a, With a high on pin 6 "MODE CONTROL" the Number 2 gates are enabled. b. Clock pulses are applied to pin 8 "CLOCK 2 LEFT SHIFT" and serial data to pin 5 "INPUT D". The data is shifted on successive clock pulses from "D" to "C" to "B" to "AN €. Outputs "A", "B", "C", and "D" provide parallel inform- ation The register may also be connected for parallel input operation. Pins 2,3,4, and S$ are parallel the information will be entered when pin 6 is high, and a clock pulse occurs at pin 8 nputs where (ODE CONTROL" LOCK 2" input. a, The data could then be shifted out serially by causing "MODE CONTROL" input to go low, and applying clock pulses to pin 9. Serial data would appear at pin 10, “OUTPUT D". VI-10If the serial data out at Pin 10 (OUTPUT "D") were to be fed back to serial data input pin 1 (SERIAL IN) the register would be in ring type configuration such that the same data could be continuously shifted and read out in parallel and/or serial format. In actual operation all of these modes and their distinct operations could be controlled by proper "time share" gating. VI-11TRAINING USE ONLY SECTION 7: PULSE CIRCUITS Yoo NOTE: Some of us tend to forget the basic electronic circuits we learned. This series by the AMPEX Training Department is intended primarily as a rapid review and summary. For this section, we suggest you review the section on Resistance/ Capacitance time constant concept in your favor- ite basic text. 1.0, A common requirement in pulse circuits of the narrowing of a wide pulse, or defining the lead- ing and trailing edge of a pulse. Frequently, a large amount of pulse delay is required, with- out the use of LC type delay lines. Tele The most frequently seen circuit is some variation of the RC (Resistance/Capacitance) network. A. Some common names for such circuits are "delay"; "boxcar"; "pulse former"; "differentiator". 1.2. The term "differentiator" is derived from the calculus A. It defines the process of measuring the rate of change of a waveform. B. By the proper choice of resistance and capacitance, the mathematical process can be electrically simu- lated. qa) © EIN R € OUT (2) SINE WAVE AT TOP OF SINE WAVE, ZERO CHANGE ew -/$\.-f\__ AT CROSSOVER OF AXIS, MAXIMUM CHANGE MORE PRACTICALLY, THE OUTPUT, IN THE PERFECT CASE, LEADS THE INPUT E ouT By 90) VIT-1(3) PULSES MAXIMO NEGATIVE CHANGE EIN Lt SL | ___ MAXIMUM POSITIVE CHANGE cour _') h 4 j NO CHANGE (4) A "#" to "=" RATE OF CHANGE ; ; RATE OF CHANGE CONSTANT NEGATIVE V2: C. Theoretically differentiation is mathematically perfect if the time constant, equal to R x C, is infinitesimal. Of course under these conditions the output voltage is also infinitesimal. The real value of a practical RC network wili deter- mine the amount of phase shift of a sine wave, or the width of the output pulse when a square wave is applied. D. It may be more famiWaras the grid or base coupling circuit of a resistance coupled amplifier, but with the resistance and capacitance selected so as not to pass low frequencies. It is a high pass filter. "R" and "C" are selected on the basis of the low- est frequency that must be passed. RATE OF CHANGE CONSTANT POSITIVE 1.3 The circuit is sometimes used to deliberately in- troduce a specific amount of phase shift. ' E OUT . i PHASE E OUT = TAN ( 1 | Ry on. =]-E IN 1.4 It is more frequently encountered in circuits requir sharply defined pulses. + VIT-21.5 NPN Circuit. A CASE 2 “LIE EIN Q1_TURN-ON LIMITS PEAK VOLTAGE — ouT U B. The output pulse width equals approximately 0.7 RC C. AMPEX Training Department block diagrams have used the following symbol: D. Case 2 represents delay. VII-31.6. PNP Circuit A B. Symbols used. C. On block diagrams, the period of the final pulse is included only when it is important in under- standing the circuit. 1.7. When the network is used with integrated circuits ("chips") all or part of the "R" in the RC equation may be internal to the chip, and must be taken into account, when computing the time constant to deter- mine the pulse width. The multiplying factor may be included on the manufacturer's spec sheet. VII-4—__ __ Sn 2. 2. 2. 4. coe THE MONO STABLE MULTIVIBRATOR The flip-flop, or bi-stable multivibrator is basically two saturation type amplifiers with 100% feedback. It normally assumes one of two states indefinitely until triggered into a re- verse condition. It is duscussed in Section III. + W “Vv “Vv If one of the feedback paths is changed to an RC differentiator network, the result is: a circuit designated: ONE SHOT (0.$.) Single Shot (SS) Delay multivibrator, or delay mult Nonostable multivibrator, or simply "mono" Collector Driven One Shot2. 5. A. B. c. In the stable state Q3 is conducting, and the output 3 is close to ground. Q1/Q2 are off, and their coilectors are positive A positive trigger on the base of Ql send its collector to ward ground The negative shift is differentiated by RC, and the pulse turns off Q3. The feedback from the collector of Q3 to the base of Q2 keeps it conducting for 0.7 RC Any input pulses during the active time of the one shot are ignored-the one shot in this case is non- retriggerable. Output may be taken from either side If R is made variable, then the period of the one- shot can be adjusted. The "R" may include a transistor as the charging source, with some type of error signal controlling the current and therefore the period of the one shot The trigger may be brought in on the base of Q2 Retriggerable One-Shot Ole rr 40.7 RO OL Input pulse turns on Q3 and charges C, positive, and turning off Q2. C1 starts charging through Rl until sufficiently negative to turn on Q2. If the period (0.7RC) is longer than the period between input pulses, the one shot does not re- vert to its stable state. VII-6D. A missing pulse will allow it to revert to a stable state. E. It is sometimes called a pulse to dc converter. Nand/Nor Integrated Circuit One Shots The FC 914 NOR Gate may be used as a one-shot + AIN A . BIN out ¢ OWA C= (A)(B) LOGIC = B A. If either input goes high, the output will swing low. If both inputs are iow (near ground) the output will be high (near supply voltage One-Shot VII-73.3, The period of the One-Shot, using the FC914 is 0.33RC. This will vary depending on the integrated circuit used, and its internal resistance. In general, it may be used in the same way as a one-shot using discrete components. Diode-Transistor logic circuits may also be used in a similar way. The system subcarrier phase shifter in the Universal Colortec (Model 1012) and the Ref- erence Subcarrier Processor #1, Module 203 in the AVR-1 employ a different version of the dif- ferentiator. Delay lines are used instead of resistance and capacitance The logic units are Motorola MECL 1204L, where a high is between ground and -0.7 volts, and a low is on the order of minus 2 volts. BAND PASS FILTER out 3.58 MHz or 4.43 MHz (REFERENCE DESIGNATION REFER TO AVR-1 PWA 203) Input pulses are at 1/2 television signal color subcarrier rate. The preceeding circuit discussed later varies the timing of the positive transitions of the input pulse. DL2 and DL3 appear as shorted delay lines due to the 1.0ufd capacitor and the input frequency of 1.79 or 2.2 MHZ. VII-8Saeed C, Because of the bias at the end of the delay line Al-6 and Al-8 see only the positive going reflections. P 15NS ro NO OUTPUT 30NS { AT A1-6 “30NS gerusn REFLECTION D. Initial (Stable) State 18 bul 3 e EIN Ein low A2 pin 10 also low = Pin A2-9 high, keeping A2-8 Tow, and maintaining the stable state. E, Unstable (triggered state) VII-94.0. 4 4.2. = Pin 11 goes high for 30 nano seconds = Pin 8 goes high, but it is 100 nano- seconds later before A2-3 goes high - The low out of A2-9 keeps A2-5 high, keeping A2-9 low. = 100 nano seconds later A2-3 goes high A2-5 goes low, and the one shot re- verts to its stable state. Integrated Circuit One-Shot The Fairchild 9601 Retriggerable Monostable Multi- vibrator is a single "chip" that performs the one- shot function. An external resistor and capacitor determine the period. Inputs are d.c. coupled so that triggering is in- dependent of input transition time. 0.32RC [92] +5V Hora woo sox For trouble shooting purposes, T=0.32RC is adequate. When electrolytic capacitors are used, Fairchild recommends a diode or transistor across the cap- acitor to prevent reverse voltage across it. +5V +5V VII-104a. 4. 23, 4. 55 General considerations for the FC9601 If 3 and 4 are not used they are tied to +5V If NOR inputs 1 and 2 are not used they are tied to ground. If the period is longer than the input trigger period, the one-shot will continuously retrigger and the output will be a de level. NOTE: Retriggering will not occur if the retrig- ger pulse comes within 0.32 CX RX (.7RC) after the initial trigger. Non-retriggerable connections. fe 63.5usecey Jo 31.7us pe uy UU UW | + 40usec This circuit is used in the Video Tape Recorder to identify the horizontal component of composite sync. It eliminates the half line information during the 7% (625) or 9 line (525) vertical interval. Voltage Controlled Oscillator Basic circuit-the output of the one-shot is delayed by a period equal to the nominal period of the de- sired frequency, thenretriggers the one-shot CONTROL VOLTAGE T25usec + 10% VARIABLE DELAY OSCILLATOR out NOMINAL 8 kHz VIT-114 6. TPT ERROR VOLTAGE (NOMINAL 0 VOLTS SOURCE Typical Logic Circuit. + CONSTANT CURRENT SOURCE Circuit operation of voltage controlled oscillator. A 5 usec pulse from the one shot turns on transistor. switch Q1, discharging Cl to ground. At the end of the pulse, the capacitor starts charg- ing at a linear rate, the ramp rate determined by the constant current source. -the constant current source may be adjustable (R1) -it would probably be adjusted so that the error voltage (TP1) equalled zero volts under some special control condition. The positive going ramp (in the AVR-1 it is usually +5V) is the minus input to voltage comparator Al The positive input to the comparator is determined by voltage divider R2, R3, and R4 -when the error voltage is zero, then the divider is R2, and R3. -this determines the nominal operating frequency When the ramp voltage exceeds the reference voltage, the output of Al swings negative, triggering one-shot 2. The action repeats. VII-125.0. A less frequently encountered circuit is the "Integrator"-essentially the complement of the differentiator. Again the term is derived from the claculus. 5.1. The process is simulated electrically by a resis- tance Capacitance network. R ra A. Again, the integration approaches mathematical perfection if R and C are infinite in value. Of course E out becomes infinitesimal. 5.2, It can also be considered a low pass filter-and the circuit is probably most familar as an RC Power Supply Filter. EIN E— OUT 5.3. In the case of sine wave, a phase shift results. VII-135.4. 5. 5. The ramp generator is another example EIN | —— IDEAL ae . VWAe™ CURVE (0.63RC) The AVR-1 uses a variation of the integrator circuit to perform the differentiator pulse former function. Review of differentiator pulse former “Vv I I | PULSE WIDTH 0.7RC I I VIT-14B. AVR-1 Pulse Former A1,A2,A3 - MC846P (TYPICAL) LOGIC BLOCK //jonancel af A3 | | | L £ VII-155.6. Circuit Operation -Every negative transition of the input signal produces a pulse at the output. - Pulse width approximately 1 micro second for every 1040pf of Cl in most applications -As long as input to A2 is positive, its output transistor is conducting, keeping C1 at ground -hen the input to AZ swings negative, the output transistor turns off, and Cl starts charging towards +5V through 6000ohms, until positive enough to turn on the input transistor of A3, causing A3 output to go low, to ground. A variation of this circuit uses the "WIRED AND" gate wl ob T usec = Cuf/.001 The output of "WIRED AND" gate low when either Al or A2 output low (ground) The circuit produces a positive pulse out for every negative transition of the input signal. VII-16The pulse former ciruit may be utilized as a frequency doubler. NEGATIVE EDGE OOOO C ©oOo VII-175.8. One method of pulse width discrimination uses the ramp generator. 75 CHARGE SWITCH LSQURCE Q comp SYNC (4 be LAL A, During the time that the compostie sync signa is positive, switch Ql operates and keeps Cl at ground. B. When a sync pulse swings negative, Ql turns off and allows Cl to charge positive. C. During H sync time, it is allowed to charge for about 4.5 usec; during the 5 or 6 equalizing pulses, about 2.5 usec. D. During 'the serrated vertical pulse, C1 has about 27 usec to charge towards +5Volts. -Only during the vertical interval can Cl charge positive enough to exceed the +2.5V bias on the minus input to voltage comparator Al, and allow its output to swing positive. VII-185.9, The integrator is in another way to recognize the vertical sync interval. 100k T loool | | | I | | Lunar Li——_4—--——4-+. le Le A. The RC time constant is 100 usec B. During horizontal sync pulses (about 4.6 usec and equalizing pulses (about 2.5 usec) the cap- acitor gets very little charge and during the following line or half line is completely charged C. During the serrated vertical sync pulse it ha has about 27 usec to charge positive, but only 5 micro seconds to discharge, so that it produces a pulse representing the vertical pulse D. Or, the circuit has acted as a low pass filter, leaving only the fifty or sixty cycle component of the synchronizing signal. 5.10. In one case in the AVR-1 this circuit is used as a frequency discriminator, producing a D.C. voltage out which is proportional to the period of the in- put constant width pulses. 6.0. Phase shifter 6.1. The editor tach phase shifter or PWA 141 of the AVR-1 operates at 240/250HZ VII-19Es = $$ 6.1. Two pulse formers and NOR GATE A34-11 produce a series of narrow pulses at twice tach frequency (480/500Hz) which, through, Q4 discharge C43 to -5 volts. At the end of the pulse C43 starts charging through Q3 towards +6 volts. T. Requires about 1 millisecond, or 90° of tach and is the "+" input to A30-6. The negative input to A30-6 is a voltage from the EDIT TACH PHASE potentiometer on the EDITOR Control Panel. At the input to A-30, it varies continuously from +4.2V to -4.2Vde. At the center of the range it is zero volts. As long as the "+" input to A30-6 is more negative than the "-" input, the output is negative. 1, The output of A30 swings positive when the "+" input (ramp) voltage is more positive than the "-" input (variable de voltage). Q2 inverts the signal and the variable (now negative going because of the inversion) transition clocks J-K Flip-Flop Al4-8, connected as a divide-by-two A pulse from A34-6 to the "SD" input of Al4-8 assures that output phase is correct. 1. A negative level on the "SD" input overrides and other inputs and puts Al4-8 (Q output) High., VII-206.2. Circuit: +6.5 +12 , VV V Is CW 840 usec 40 usec +E J CENTER J 450usec REY R44 1p2 te t 145° To 220° REPHASE JK A14-8 IF NECESSARY VII-216.3. A somewhat different version is used in the ref- erence subcarrier phase shifter in the Universal Colortec and the AVR-1 Module 203. SIMPLIFIED CIRCUIT A, The input signal is Subcarrier (3.58/4.43MHZ) which has been squared up in a limiter. B. A3 is an AC coupled JK Flip-Flop. A positive transition on J causes Q to go high. GG) input LJ 1 @ ih Q OUTPUT 3) AZ OUT (1) (2) Al OUT (1) (Q) — = DC INPUT {-) TO A4/A5 L SECHES) r VII-22SECTION: 8 TRAINING USE ONLY voors DIFFERENTIAL & OPERATIONAL AMPLIFIERS I, Differential Amplifier - Basic Circuit INPUT A O+y OUTPUT B Q1,Q2 MATCHED PAIR INPUT B CURRENT SOURCE Produces output proportional to input signal Signals of equal amplitudes and same polarities applied le to input would cancel at outputs. Example - Output taken at Output A with equal inputs at Input A & B Input A is inverted to - A at Ql collector Input B sees Q2 as emitter follower with no inversion and Q] as common base amplifier with no inversion Signal at Ql collector equals - A + B, signal at Q2 collector equals A - B Differential Amplifier used as phase splitter - driven single ended produces outputs of opposite polarity and amplified a. be Example: Signal at Input A is amplified and inverted by Ql to produce - A, Q2 base tied to fixed bias Signal also sees Ql as Emitter follower and is coupled to Q2 emitter where it is amplified by Q2 operating in common base configuration to produce amplified A at AZ collector. Differential Amplifier used in input circuits to reduce hum caused by different ground potentials between two chassis. (Common Mode Rejection) b. ce Input A driven single ended from center conductor of unbalanced line. Output taken from Q2 collector. Input B connected to shield of unbalanced line Common Mode Signal (hum) would cancel at Q2 collector A-B Main line signal at Input A would be amplified and appear at Q2 collector free from hum. VIII-1INPUT A. B i. RI Q1, Q2 MATCHED PAIR INPUT B 9 Zi] Fixed BIAS CURRENT SOURCE -V Differential amplifier used as reference amplifier. (Power Supplies a. Q2 base tied to stable voltage source (Zener Diode) b. QI base connected to voltage sensing lead from Power Supply Output. c. QI collector goes to drive series regulator transistor d. QI, Q2 bases will try to be at same potential - if any change at Ql base it will be sensed and output from Qi collector will be used to control series regulator transistor. + Q3 acts as constant current source, Current that flows thru Q1, Q2 will be fixed and held constant by Q3 a. With current source total current divides at Q1, Q2 emitters and is equal to Q3 collector current b. Advantage to give better common mode rejection to supply changes c. Gain will not change with common mode signals. Oper- ating point of circuit constant. d. Current determined by fixed bias and value of Q3 Emitter resistor. Input very high impedence. Differential amplifier used as switch a. Reverse bias Q3 base - emitter junction - no current flows - acts as high isolation switch Differential amplifier as limiter a. Sum of Q1, Q2 collector equals the emitter currents b. Input A driven so Q1 takes all current, no current will flow thru Q2, maximum possible change equal to Te R1 c. Emitter currents constant Q1, Q2 never driven into saturation d. Limiting is symmetrical - limiting action equal for input positive and negative input excursions. Differential amplifier as amplitude modulator a. RF applied to Input A. Input B tied to fixed bias b. Modulating voltage applied to Q3 base controlling gain of Ql, Q2 VIII-2Il. Operational Amplifiers A Generally high gain direct coupled amplifier 1. Circuit action generally controlled by external components 2. Works similar to differential amplifier 3. Generally balanced input and single-ended output 4. Features high input impedance and low output impedance Performs various analog functions 1. Inverting and non-inverting amplifiers a. Cpen loop aain verv high and closed loop gain controlled by feedback resistors . Current drivers . Integration and differentiation + Summing . Reference amplifiers-power supplies : Active filters : Oscillators, modulators and synchronous detectors ypical Fairchiid 741 2 2 3 4 5 6 7 T. 6 1. Has two inputs labeled + and -. + is the non-inverting input. - is the inverting input. It amplifies the dif ference between the voltages applied to its two input terminals 2. Various circuit functions that can be performed by oper ational amplifiers a. Source follower amplifier (circuit action similar to transistor emitter follower). Eout = Ein (1- 1/A0) Ao nearly 3 Eout unity Ein ee 1. Gain unity 2. Input impedance very high (50 megohms 3. Non-inverting b. Non-inverting amplifier R2 2 6 3 Eout EinS R 1G = R2+R1 RI VIII-3c. Inverting Amplifier RZ R1 6 Ein 2 Eout 3 a 1. Gain = R2/R1 d, Integrating Amplifier (sawtooth generator) Ein 1 ; Eout = = Ein dt xf e. Differential Amplifier Eout f. Summing Amplifier RI a R2 Ra 2 R3. 3 20 o—___4_______> eo (e, Rais (ep ®/Re)+ (eg *4/R3) VIII-4g. Common application of 741 as a reference amplifier in power supply. Sense + Te Voltage from sense lead applied to reference amplifier. Reference amplifier amplifies difference between its input terminals and controls a series reg- ulator. Two input terminals should be within a few milli- volts of each other. Amplifier operating open loop-voltage gain very high. Small difference at input will result in large Change in output. Voltage more than 15 millivolts between 2 and 3 indicates fault condition. Pin 2 more positive than 3-output towards negative side. Pin 2 more negative than 3-output towards positive side. Note that a short or partial short on the output will restrict the output swing. The amplifier may have a large voltage difference at the input but will be good if output is trying to swing toward correct supply. Band Pass Filter. 1. 2. The 741 has internally controlled roll-off so that the voltage gain rolls off at 6db/octave Frequency response can be controlled further by RC combinations in the feedback networks a. Example--Roll-off in control track reproduce amplifiers. b. Example-10HZ Band Pass Filter in auto-tracking VIII-510 HZ B.P.F. i, Special operational amplifiers serve functions as balanced modulators-demodulators. 1, Example-Encoding and decoding in color television which uses amplitude modulation suppressed carrier. VIII-6eM III. Digital applications of OP Amps ) A. Schmitt Trigger - transistor mode 1. Multivibrator that is used in squaring applications a. Converts waves with slow rise and delay times to waves having steep edges. (Sine waves to square waves). b. Used to regenerate pulses at input of machines 2. Basic Circuit THRESHOLD OR TRIGGERING E OUTPUT ouTPUT a. QI, Q2 alternate their conduction states in response to the input sine wave. b. Ql, Q2 have two states: they can be in full-on, or 1 fuil-off. c. Static state QI biased off, Q2 biased on. 1. Q2 biased on via R1, R3. Q2 collector ground. 2. Current flow through RE helps reverse bias QI emitter (maintain at a positive potential). 3. Positive going sine wave at input ultimately goes positive enough to overcome positive bias on Q1 emitter. 4. Ql collector voltage drops - coupled over to Q2 base via Cl, R3 to turn off Q2, its collector voltage rises 5. Avery rapid switching action ensues with Q1 turning full-on and Q2 turning full-off 6. Circuit stays in this condition until input sine wave falls to a value more negative than the value assoc- iated with the first switching action. 7. When the input voltage reaches this triggering voltage the Schmitt Trigger will reverse states. VIII-7B. 8. Difference between the two triggering voltages is called the voltage hysteresis. 9. Schmitt Trigger has two possible states on the output, a high or a low. Differential Voltage Comparator High gain differential input, single-ended output am- plifier. Compare signal voltage on one input with reference voltage on other input. Produce digital one or zero when one input is higher 1. 2. 3. than Uses a. the other. Schmitt trioaer b. Pulse height discriminator c. Voltage comparator in A/D converter d. Zero crossing detector e. Threshold detector Basic level detector circuit (Fairchild 710) ein 7 £ our + £ OUT 2 2 +E IN VREF VREF "TRANSFER FUNCTION a. When Ein exceeds Vref the output switches positive or negative depending how the inputs are connected. b. Transfer function illustrates this. 1. Ein more positive than Vref, £ out goes to a low level. c. Auto-wipe circuit in VS-600 - example of voltage com- parator in A/D converter. E IN3 ? 2 E OUT VREF VIII-8—_———_.aT—_!W TC Mngt] VREF EIN A BA ifr IP [i Te oor | ale PPEPEL or] 1. Vref is a Vertical rate sawtooth waveform. Ein is a horizontal rate sawtooth. 2. £ out a switching waveform that selects pic- ture A or B. 3. As Vref moves from left to right we take more of a Picture A than B. C. Dual Differential Voltage Comparator 1. Basic Circuit Fairchild 711 2 STROBE 1 OUTPUT 8 STROBE 2 2. Individual comparators the same as Fairchild 710 3. Outputs are ORed together internally inside the chip 4. If output from either comparator goes high - output of chip will be high. 5. Strobe inputs provide a method of disabling individual channels. a. Strobe terminal grounded output of that side will stay low. VIII-9oOEr Ee ier | REV SECTION IX = EMITTER COUPLED LOGIC La 1.1.2 12 1,2,1 1.3 1.3.1 1.3.2 1.3.3 ‘The integrated circuits used in the AVR-1/ACR-25 Time Base Corrector - the Buffer - are almost exclusively the Motorola 1200 series MECL Il. ‘They reduce propagation delay to 7 to 10 nanoseconds by operating in a non saturation mode, The Diode~Transistor Logic (DTL) used in the servo has typical delays of 70 to 100 nanoseconds, Propagation delay is simply the time required for the output of a circuit to respond to a change of the input signal, One way of demonstrating the importance of this is to examine a ten unit ripple counter, WithDTL, the effect of an input clock pulse would not be felt at the output of the last stage for one microsecond; a similar ECL counter would have a delay of 0.1 microsecond, ‘The Emitter Coupled Logic has a high input impedance and very low output impedance, The output is an emitter follower. ‘The fan-out (loading) capability fo DTL is typically 6 to 8 similar units; the ECL can handle up to 25 loads without propagation delay degradation, The ECL circuits are noise susceptable, and require adequate shielding. Shields on buffer boards should be removed only for trouble shooting, and immediately replaced. Replace in the same way it was removed, to avoid breaking of the brass grounding strips which mate with the board cover and internal shields on the printed circuit assembly. Unused inputs are always connected to a supply voltage between -1,2V and -5,2V de. When trouble shooting, keep scope ground leads as short as possible. Scope probes whose tips fit directly in the co-axial test points on the front of buffer boards are available. When moving from 12 volt transistor circuits to the ECL chips, touch the scope leads to round first, to discharge to coupling capacitor to avoid damage. Also be careful of static electricity discharge. Ix-1‘The basic gate in the MECL II is the OR/NOR function, of which the MC 1204 L.is an example, A schematic and logic symbol is shown in Figure 2.1. rve"n"y 1.7V("0" 21 2a 2.1.2 2.13 FIG, 2.1 MC12041L AVR-1 As used in the buffer, Vec is ground, and Vpg is -5.2v de. In the AVR-2 Digital Time Base Corrector Vee is #12, and Vppp is +6.8v. The term Vp will be found on several schematics. This is -1.2v de in the AVR-1. ‘The basic output voltage swing is from ground (a "High" or "1") to -1.7v ("low"' or logic "0").EES iii} 2.1.4 Other gates included in the Ampex Training Department Intograted circuit handbook and used in the buffer are the MC1201, MC1203, MC1210, MC1226, MC1230, and MC1231. a, The MC12801 is an Exclusive OR ~ the output is high when the two inputs are different, and low when they are the same, whether high or low, b, The MC1231L is an Exclusive NOR, whose output is low when the two inpats are different, and high when both inputs are the same. 2.2 ‘The MC1217L converts TTL/DTL saturation type levels (+5v and ground) to ECL levels (ground and -1.7¥). 2.2.1 If any input is at or close to ground, the output is -1,7v performing a negative OR function, When all inputs are positive - usually near +5v ~ the output swings to ~0,7¥, a, On some schematics bubbles are shown indicating inversion, However no inversion, only a level shift has occurred, 2.2.2 Pin 2 has an output of ~1,2 volts, labeled Vpp. 1 = (8)(4)(5)(6) 3 8 IN our 4 1 a L TV GND = (+5V)(+5V) (+5V) (+5V) > 5 xD “1.7 4 6 FIG, 2.2 MC1217L. 2,3 ‘The MC1239L converts ECL levels to DTL/TTL type levels, and as OR function, 2,8,1 With either input at between ground and -0,7v, the output approaches +5v, If both inputs are between ~1.2 and -5,2 volts, the output is close to ground, 2.3.2 Pin 9 has an output designate Vj, which is -1.2v de, our —— ‘pp ah Nov cad = (1, T)(-1. 79) -0.7v 4 40,7V FIG, 2.3 MC12391L3 ‘The wired, or phantom gate, where the outputs of two gates are tied together, follows the samerule as in DTL logic ~ if one output is close to ground, the other output is not allowed to change. However inDTL, a ground is the low condition; in ECL a ground represents a hi DTL “0 4v Qn ECL Tete Dey PD et sigh ax “1. 0" ov B B tot Ww FIG, 3,1 Wired Gates 4, NAND/NOR gates may be used as buffers and inverters in ECL by connecting unused input to a negative bias voltage - usually -5,2v, 4,1 Also widely used is the MC1235 "Triple Differential Amplifier". It is used as both an inverting and non inverting buffer, as a schmitt trigger, and as a limiter. 320 2,04K 410 FIG, 4,1 MC1285 Schematic8 1 4 2 5 L | a 8 B IL 6 ven} u ifn | 4 ven} Lu iL | a 10 18 FIG, 4.2 MC1235 ‘Triple Differential ‘Amplifier » u VBB = -1.2V PIN 14 = GND (vcc) PIN 7=-5.2V (VEE) VBB F— 9 =1.2v 4,2 When it is used as a buffer, one input may be tied to Vpp, a-1.2vde. The Motorola logic symbols, shown in Fig. 4.2 are shown logically with pins 4,6, or 11 tied to Vppe 4,2,1 If pins 3,5, or 10 are tied to Vpp and the signal applied to pins 4,6, or 11, then the level indicators on the symbols above are incorrect. The correct symbol is shown in Fig. 4,3, Some buffer schematics have this logic symbol incorrectly drawn, aay “tev 2 13 Le : SIGNAL sicnaL 11 SIGNAL FIG. 4.3 Ix-55.1 5.2 5.2.1 The J/K flip flop used is a MC1213L (70 MHz) or MC1227L (120 MHz). Its inputs are AC coupled. The Motorola logic symbol, figure 5.1, does not, adequately describe its operation, Figure 5,2, a schematic of the unit, is included only to satisfy the student's curiosity, and will not be discussed in this outline, 8456 8 91011 FIG, 5.1 MC1213L, Logie Symbol ‘The Set (2) and Reset (12) inputs cause the unit to function as an RS flip flop. Including the ambiguous condition where if both "'S" and "R" inputs are high, then both of the outputs "@" and "Q" will be high, In the buffer these are used only in their normal preset/reset functions. The J (NOT J) and K (NOT K) inputs are capacitively coupled, The unit changes state only on a negative-to-positive transition when these inputs are used. In an asynchronous mode (not clocked) only one input (J or K) should change state, from negative to positive, and all their inputs must be at a low ~1.2 to -5.2v. a, This determines a characteristic called "time to dominate", (1) IfaJ and K input move from negative to positive within six nano- seconds of each other, the unit acts as a "divide by two", (2) If the input transitions occur more that six nanoseconds apart, the final state is determined by the last positive transition, If K is the last to move positive, then the Q output will be high. x5.4 In synchronous mode (clocked) operations counters a J_and a K input are tied together to form a CP input, Ina counter, the other J and K inputs are used for control, cp gn KJ J FIG. 5.3 i ° Counter cp l 1Q o fit Lo fi Lo Ji Lo ft Lo 2Q oo fi alo oft 1 |e 4Q 0 0 0 0 1 1 1 1 FIG. 5.4 Counter Timing Q JT Q JQ cp. cp "1" lop "20 ep "a 7 rt K IK S ¢ FIG, 5.5 Counter Funetional Logic Diagram 5.4,1 The Q transition occurs after the clock pulse has gone high, therefore, it does not affect the following stages. Ix-8. ‘There are several different types of one shots used in the buffer which are "fabricated" from standard ECL circuits, 6.1 One type employs the MC12101, two input NOR gate, and is shown in Figure 6.1. 5.2 FIG, 6.1 MC1210L ‘One Shot, 6.1,1 The symbols used in Figure 6,1 could be redrawn to indicate its unstable state, FIG, 6,2 Unstable State IX -96.1.2 A positive transition is differentiated by C1,R1,R2 to put a positive pulse into Al4-3, and send its output low (-1,7V). a. C2 was charged negative during the one shot stable period; the negative transition out of Al4~3 puts the two inputs to A14-6 low, and its output goes high to -0,7V. This high keeps output of Al4-3 low (-1.7V). ‘The negative side of C2 discharges through R3 to the output voltage of Al4-6, until A14~6 sees a high on its input, causing its output to go low. This puts two lows into A14~3 and its output goes high, which keeps A14-6 output low, and charging the negative side of C2 to -1.7V Figure 6.3 is a logic drawing representing this stable state. FIG, 6.3. Stable State 6.2 Another type of one shot uses the MC1213L J/K flip flop. The example shown in Figure 6.4 is extracted from the horizontal sync separator on Board 217(D13). Re =@) 105 (330) a0 Fa.4) 330pf As-13 -L More Than LI Adis SL LS LS Li v/a tnsco f= tH oh IX - 10 FIG. 6.4 One Shot6.2.1 6.3 6.3.1 In the stable state A3~13 (Q output) and A4-13(Q) are both low at about -1,.7V, and C is negative. a. i ‘The negative edge of syne inverted by Al, clock the J input of AS and A4, and the Q outputs go high, toward ground, Cy starts discharging toward ground through "R", ‘The junction of C1/R1 approaches -0.7V and causes A3 to be RESE' During vertical interval the sync transitions occur at a half line rate. The first one triggers both one shots, A3 and Ad, ‘One half line later, the equalizing pulse transition has no effect on A3 since with its period greater than 1/2H, it is still ina SET condition, with Q output high, Since A3-13 is high, A4-13 cannot be triggered. One half line later, A8~13 is low, and a sync transition can trigger both one shots. ‘The MC12131 is also used extensively’as a part of precision one shot which is used widely in the Buffer. Figure 6.5 Initially A1 is in the RE‘ condition with the Qoutput high or at about -0.7V. As a result the differential compa. tor switch Q1/Q2 has Ql conducting and Q2 off. With the base of Q3 positive, it is conducting, and Cx is discharged to ground. A positive transition into the J input of AJ puts the Qoutput low. a. b. © a. This reverses the switch Q1/Q2, and Q3 turns off, Cx starts charging positive through R6 and RS, When the ramp reaches a voltage more positive than the "-"' input to A2, suppled by Rx, the output of A2 swings positive, ‘This is soupied through @4, a logic level converter, and Resets the JK Al. ‘There are several variations of the basic circuit, a. ‘The "Rx" may be replaced with a voltage controlled by some type of variable "error", ‘The optional clamp circuit indicated on the figure will clamp the ramp to a reference voltage, By reversing the inputs to A2, a negative going ramp can be used, The capacitor Cx current source may be using a transistor rather than R6 and R5. Ix = 117 s ( z Ed Fi 3t ge e au #8q Fa ese Ei Bags ‘rs aaa nl ste9 ge a. Begs 2B 4288 B Bye ado NO £0 NO 410 2 ado NO 10 @IaVISNA STAVLS NI gs1nd waDOTEL Ix - 12 ou o0e ae 98 oss ross ql fPOBNOS BOVUTON — gy 40 4 | unoms I eas a] [/@ 400 LaWvIo_ “40 4 AGT = 7 " aDOTIL WIL ' astd sup asINd “sod Le. 10 asTNd “OaN