Buck Converter Modeling, Control,

and Compensator Design

1
 OUTLINE

• Three terminal PWM switch modeling

• Open loop transfer function
• Voltage Mode Control and Peak Current Mode Control
• Closed loop transfer functions
• Closed loop gain
• Compensator Design
• Pspice and Mathcad Simulation
• Experimental verification

2
 Voltage Mode Switching Regulator
VO

VIN +
Converter
Power Stage R

K
PWM
Comparator Loop
d Compensator
-
Fm -
+ A(S)
+ VREF
Feedback Control To Achieve

• Accuracy: Steady-State Error

• Speed: Transient Response
• Stability Gain and Phase Margin
3
Average Small Signal PWM Switch Modeling

4
 Average Model

L RL
Q1

Rc
Vin + ? Ro
D Co

Nonlinear Characteristics for Switching Elements Q1 and Q2

Modeling Method:
1. Space Average Model-----Middlebrook (CIT)
2. Three Terminal Switch --- Vorperian (VPEC)
3. DC Transformer Based
5
 PWM Switch in Basic DC-DC Converters
Buck Boost
L P
L C
A Q1 C
D
VIN Co
Vin + Ro
+ ? R
? Co
Q1
D A
P

Buck-Boost

A Q1 C D P
• A: Active Switch Node
• C: Common Node ?
• P: Passive switch (Diode) Vin + L Co Ro

6
 Non-Linear PWM Switch

A Q1 C

DC Model AC Model

A D C A d C

D’ d’

P P
Where D’ = 1 - D
7
 Average Model for Buck Regulator (Cont.)

A Q1 C iL L RL
iin
Ip
Iv
iin +
Rc
iL
+ Vin
? vPH
-
Co
d

Vin
vQ2
P
I p + Iv
i in = • d = d iL DC Average Model
2 iin A 1:d C iL
Transformer Characteristics
+
i in = i L d
vPH
v PH = v ind
-
Model valid only at CCM
P
8
 What is Small Signal Model?

• Adding a small signal near the operating point

v in = Vin + v̂ in A Q1 C iL L RL

i in = I in + î in iin +
Rc
d = D + d̂
i L = I L + î L
+ Vin
? vPH
-
Co

v PH = VPH + v̂ PH P

9
 Small Signal Average Model of three Terminal PWM Switch

i in = i L d A Q1 C iin A 1:d C iL
v PH = v ind +
Linearization
v in = Vin + v̂ in
? vPH
-
i in = I in + î in P P
d = D + d̂
Small Signal Average Model
i L = I L + î L
î in A C
v PH = VPH + v̂ PH

+
ILd̂ 1:D Vind̂

î in = I L d̂ + D î L
v̂ PH = Vind̂ + D v̂ in
P 10
 Small Signal Average Model Buck Converter

A C
A C

+
L
ILd̂ 1:D Vind̂ R
VIN + Co

P P

A C

+
L
ILd̂ 1:D Vind̂
+ V̂ R
in Co

11
 Open Loop Line to Output Transfer Function (Buck)

A C RL v̂ o

+
1 + ωS L
v̂ o z ILd̂ 1:D Vind̂
Gv = =D + RC R
v̂ in S S2
d̂ =0 1 + Qω + 2
o ωo V̂in C
Vo
Gv = =D
Vin S =0 P
A C RL L v̂ o
1:D
+ RC R
V̂in C

1 1 RL R P
ωo ≈ , ωz = , ωzL = , Q≈
LC Rc C L L
C
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 Open Loop Line to Output Transfer Function (buck)

v̂ o 1 + ωS
z Q factor
Gv = =D Gv
v̂ in S S2 D
d̂ =0 1 + Qω + 2
o ωo
ωo -40db/dec
Vo
Gv = S =0 = D
Vin
ESR Zero
-20db/dec
1 1 RL R
ωo ≈ , ωz = , ωzL = , Q≈
LC Rc C L L
C

13
 Open Loop Control to Output Transfer Function (Buck)

A C RL v̂ o

+
L
ILd̂ 1:D Vind̂
+ RC R
V̂in C

P
S RL L v̂ o
v̂ o 1+

+
ωz
Gd = = VIN Vind̂ C
d̂ S S2 RC R
v̂ in =0 1 + Qω + 2
o ωo
C
P
Vo 1 + ωS
z
Gd ( DC ) = = VIN = VIN
D S S2 1 1 RL R
1 + Qω + 2 ωo ≈ , ωz = , ωzL = , Q≈
o ωo LC Rc C L L
S =0 C
14
 Control to Output Transfer Function (buck)

Q factor
VIN
Gd
v̂ o 1 + ωS
z
Gd = = VIN
d̂ S S2 ωo -40db/dec
v̂ in =0 1 + Qω + 2
o ωo

ESR Zero
-20db/dec
1 1 RL R
ωo ≈ , ωz = , ωzL = , Q≈
LC Rc C L L
C

15
 Open Loop Output Impedance
A C RL v̂ o

+
L
ILd̂ 1:D Vind̂
v̂ o + RC R
Zp = V̂in C
î o
d̂ =v̂ in =0
P

( 1 + ωS ) • ( 1 + ωS ) RL v̂ o
v̂ o z zL
Zp = = RL // R • L
î o S S2
1+ Qωo + 2 RC R ZO
ωo
Z p (S = 0 ) = RL // R C
Z p (s = ∞) = Rc // R

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 Open Loop Output Impedance

S RL v̂ o
v̂ o (1 + ωz) • ( 1 + ωS )
zL
Zp = = RL // R • L
î o S S2
1+ Qωo + ω2 RC R ZO
o
Z p (S = 0 ) = RL // R C
Z p (s = ∞) = Rc // R
Zp
Q factor

ωZL ωo -20db/dec
RL //R
20db/dec Rc //R
1 1 RL R ESR Zero ω
ωo ≈ , ωz = , ωzL = , Q≈ Z
LC Rc C L L
C
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Single Close Loop Controlled Switching Regulator

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 Small Signal Close Loop Controlled Switching Regulator

Small Signal Block Diagram

Converter îo v̂ in Power Stage
v̂ in Power Stage GV
v̂ v̂ o v̂ o
, , , ...
v̂ o îo v̂ o
v̂ in îo d̂ ZP X
d̂ Compensator -A(S) T -A(S)
Gd

d̂
Fm Fm
PWM
Comparator

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 Open-loop Transfer Function

v̂ in
GV

îo v̂ o
Open Loop Voltage Gain ZP X
(Open loop audio Susceptibility)
v̂ o T
Gv = @ î o = 0 and d̂ = 0 Gd -A(S)
v̂ in
d̂ v̂ C
Fm
Open Loop Output Impedance
v̂ o
Zp = @ d̂ = 0 and v̂ = 0
î o

20
 Open-loop Transfer Function (Cont.)
v̂ in
GV
Control to Output Transfer Function îo v̂ o
v̂ o
ZP X
Gd = @ v̂ in = î o = 0
d̂
Gd
T -A(S)
Loop Compensator Gain
d̂ v̂ C
v̂ c Fm
A(s) =
v̂ o

PWM Comparator Gain

d̂
Fm =
v̂ c
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 Small Signal PWM Comparator Gain Fm

PWM Comparator vcomp

vramp
vc
v̂c v̂ c VP
Vc
+
Fm d̂
-

DTs
d̂Ts

dd d̂ 1
Fm = = =
dv c v̂ c VP

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 Closed Loop Audio-Susceptibility (Line Trans. Response)

v̂ o v̂ in
Audio Susceptibility GV
v̂ in
î o = 0 îo v̂ o
v̂ o = Gv v̂ in + Gd d̂ ZP X
d̂ = -Fm A v̂ o
Gd
T -A(S)
v̂ o Gv Gv
= = d̂ v̂ C
v̂ in 1 + Gd Fm A 1 + T Fm
Audio-Susceptibility Physical meaning: Line transient response

Loop Gain: T = Fm Gd A
• High loop gain T will improve the line transient response
23
 Closed Loop Output Impedance (Load Transient Response)

v̂ o
Closed Loop Output Impedance
î o v̂ in = 0

îo v̂ o
v̂ o = Z p î o - Gd Fm A v̂ o ZP X
v̂ in
v̂ o Zp Zp GV T
= = Gd -A
îo 1 + Gd Fm A 1 +T
d̂
Fm
Output Impedance Physical meaning: Load step transient response
• The smaller the output impedance, the faster the transient response
• Higher loop gain is desired
24
 Loop Gain Analysis

Loop Gain Provides:

• System performance analysis: Transient response
• Stability analysis:
• Absolute stability
• Degree of stability
• Design insight
• Measurement verification

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 Function of Loop Gain T: Closed-Loop Audio Susceptibility

v̂ o 1 + ωSz v̂ in
Gv = =D GV
v̂ in S S2
1+ + v̂ o
Qωo 2
ωo îo
ZP X
1+T
fC (bandwidth) Gd
T -A

fo d̂
GV T Fm
ESR Zero
v̂ o Gv
GCL
GCL = =
v̂ in 1 + T
• The smaller GCL, the faster line transient response
• Require higher bandwidth fc
26
 Function of Loop Gain T: Closed-Loop Output Impedance

v̂ o ( 1 + ωSz ) • ( 1 + ωSzL ) v̂ in
Zp = = RL // R • GV
îo S2
1 + QSωo + 2 îo v̂ o
ωo
1+T ZP X
fC (bandwidth) T -A
Gd
fo
T d̂
ZP ESR Zero Fm
v̂ o Z p
RL ESR ZCL = =
ωzL =
L îo 1 + T
ZCL • ZCL used for load transient analysis
• The smaller ZCL, the faster load transient response
• The minimum high frequency Zo is ESR
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 Closed-Loop Output Impedance
L
ZO
Q1 RL

Rc
+ Ro
Q2 Co

1+T
v̂ o Zp
fC (bandwidth) ZCL = =
î o 1 +T
fo
T When f
ZP ESR Zero
• C shorts and L open
RL ESR • Minimum ZO: ESR
ωzL =
L • Smaller ESR, better load transient
ZCL • Higher T, better load transient
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 Ideal Loop Gain Characteristics

• High DC gain (Low frequency) for small DC error

• Wide bandwidth for fast transient response
• -20dB/dec slope near cross-over frequency for higher phase margin
• High attenuation at high frequency for noise reduction

|T|
fC (bandwidth)
0dB
fo Gm: Gain margin
∠T

Phase margin Φm
-180o
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 Examples of Loop Gain T
S=jω
• Single Order System ; T = Gm Definition
ω S Magnitude = 20 log T
T p 1+
ωp Phase = Angle (T )
-20dB/Dec
ω

S-Plane
0o (-1,0) Gm (S=0)
-45o
-90o
Phase Margin: 90o
-180o
T=1/(1 + j) @ S=jωp
• Always stable Magnitude = -20 log 2
• 90o phase margin Phase = -45 degree
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 Examples of Loop Gain T
Gm
• 2nd Order System ; T =
S S2
1+ + 2
ωoQ ωo
T ωo
ω
|T|=1 S-Plane
-40dB/Dec
(-1,0) Gm (S=0)
0o
ϕ
-90o
-180o

• Stable S = jωo
• ϕ phase margin: may be very small QGm
• Gain margin: infinite (theoretical) T =
j
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 Basic Pole and Zero Characteristics
ωp
One Pole T
• 45 degree at the Pole (frequency fp) 20dB/Dec
ω
• Total of 90o phase delay after >10 fp
• -20 db/dec

One Zero 90o

45o
• 45o phase lead at the zero
0o
• Total of 90o phase lead after >10 fz
• +20db/dec S
1+
10 3
G( S ) =
S
1+
10 5
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 DC Loop Gain

îo OUTPUT
ZP +
v̂ in
GV Gd
T Vo
-
d̂ A
Error + VREF
Fm

v̂ in = îo = 0
Vo Vo
DC Error = VREF - Vo = =
AFmGd T ( DC loop gain )
S =0

• The higher DC loop gain, the smaller the DC steady-state error

• 40dB DC loop gain, 1% error
33
Compensator Design Considerations

34
 Objectives of Loop Gain Design

v̂ in
GV
îo v̂ o
Objective: ZP +
• To shape the loop gain T for achieving
Gd T -A(S)

High DC gain at low frequency
d̂

>40 degree phase margin Fm

> 10 dB gain margin

High bandwidth for fast transient response

T = Gd • A( S ) • Fm

35
 Load Transient Step Response vs Phase Margin

• The amount of ringing determines the phase margin

– 45º phase margin is sufficient
• The crossover frequency is equal to the ringing frequency
– Crossover frequency should be 1/5 or 1/10 of the converter
switching frequency
1.659
2

ϕ=15°°
ϕ=30°°
1.5
ϕ=45°°
v( t , 15 ) ϕ=60°°
v( t , 30 )
1
v( t , 45 )

v( t , 60 )
Crossover
0.5
Frequency

−4
1.177 ×10 0
0 5 10 15 20
0.015 ω c⋅ t 20

36
 Compensator Design Considerations (Voltage mode)

Buck Converter
Compensator: Constant Gain
T ωo
T = Gd AFm , A(s) = K c ;
1 + ωS fC (bandwidth)
z
T = FmVIN • Kc
S S2 ESR Zero
1 + Qω + 2
o ωo 0o ωZ
1 1 R
-90o
ωo ≈ , ωz = , Q≈
LC Rc C L
-180o
C

• Low DC gain, need an integrator

• Almost 0o phase margin if ωz > 3 ωo
• Stable if ESR zero ωz < 3 ωo
37
 Compensator Design Considerations (cont.)

Compensator: Integrator -20db/dec

ωo
Kc
T = Gd AFm , A(s) = S ; -60db/dec
T
ωC (bandwidth)
1 + ωS Kc
z
T = FmVIN 2 • S ESR Zero
S
1 + Qω + S2 -90o
o ωo ωZ -40db/dec
-180o
1 1 R
ωo ≈ , ωz = , Q≈ -270o Unstable
LC Rc C L
C

• Integrator: 90o delay; Double pole: 180o delay

• low bandwidth or unstable
• Need to introduce two zeros before cross-over frequency ωC
38
 Type III Compensator Characteristics

TOPEN = Gd Fm Integrator Two Poles

A(S)
TCLOSE = Gd Fm A(s ) Two Zeros x x
• Design based on OPEN LOOP GAIN
GdFm
• An integrator for high DC gain fo
• Place two zeros around fo for
ESR Zero
compensating phase delay due to |T|
the integrator and double poles
• Two high frequency poles
• to cancel ESR zero
fC
• to attenuate high frequency noise
• to ensure the gain decreasing after fc -90o
∠T
• to ensure the phase lag minimum at fc
-180o
39
 Type III Loop compensator Circuit

v̂ c ZF ZF
A( S ) = =- , C3
v̂ o ZI ZI
R2 C1 R3 C2
1 1
ZF = // ( R2 + );
SC3 SC1
vC vo
1 -
Z I = R1 //( R3 + ) R1
SC2 Compensator +
output VREF
S S
KI ( 1+ ) •( 1+ )
A( S ) = -
ω z1 ωz 2 K I = R (C1 +C ) ,
1 1 3
S ( 1+ S )•( 1+ S )
ω p1 ω p2
ωz1 = R 1C , ωz 2 = C (R1 +R )
2 1 2 1 3
• Zeros: • Poles:
1. R2, C1; 1. DC ω p1 = R 1C , ω p 2 = 1
C1C3
3 2
2. R1+R3, C2 2. R2, C3 if C1>>C3 R2
C1 +C3
3. R3, C2
40
 Loop Gain Design (voltage mode)
v̂ in
GV
îo v̂ o
T = Gd AFm ZP +
1 + ωS K c ( 1 + ωS ) • ( 1 + ωS )
z z1 z2
T = FmVIN Gd T -A
S S2 S • (1 + S ) • (1 + S )
1 + Qω + 2 ω p1 ωp2
o ωo d̂
Fm
Gd(S) A(S): Compensator
1 1 R
ωo ≈ , ωz = , Q≈
LC Rc C L
C
• Type III compensator: two zeros (ωz1, ωz2) and three poles (0, ωp1, ωp2)
• Loop gain is proportional to the input voltage.
Need input voltage feed-forward function
41
 Objective of Compensator Design

T = Gd AFm
1 + ωS K c ( 1 + ωS ) • ( 1 + ωS )
z z1 z2
T = FmVIN
S S2 S • (1 + S ) • (1 + S )
1 + Qω + 2 ω p1 ωp2
o ωo

• Objective is to design a compensator, Kc, ωz1, ωz2, ωp1, ωp2, to SHAPE

the loop gain T for stability and optimum performance for given power
stage parameters, ωz, ωo, Q, VIN, and PWM gain Fm.

42
 Loop Gain Design Procedure (Case 1)

VIN ( 1 + ωS ) K c ( 1 + ωS ) • ( 1 + ωS )
Integrator T = Fm
z z1 z2
S S2 S • ( 1 + ωS ) • ( 1 + ωS )
-20db/dec 1 + Qω
o
+ 2 p1 p2
ωo

Gd(S) A(S)
ωz1, ωz2 ωp1
T
ωc ωp2 • Bandwidth fc = (1/5-1/10) fs
• ωz1, ωz2 near ωo
FmGd ωo
• ωp1 cancel ESR zero ωz
-40deb/dec • ωp2 = 10 ωc
ESR Zero ωz
• Determine Kc
• Select compensator R’s and C’s
43
 Type III Compensator Design (Case II)

Integrator Two Poles

A(S)
• An integrator for high DC gain Two Zeros x x
• Place two zeros around fo GdFm
fo Open loop Gain
• Two high frequency poles to
ESR Zero
cancel ESR zero and increase |T|
gain attenuation at high frequency

fC

-90o
∠T

-180o
44
 Type II Compensator

Integrator
A(S) One Zero One Pole
Type II Compensator x
• One zero and two poles GdFm ωo
• if ESR zero is close to double pole ωz
ωz< 3 ωo
|T|
S
K I 1 + ωz 1
A( S ) = •
S 1+ S ωC
ω p1

∠T
-90o

-180o
45
 Loop Gain T function of Input Voltage

VIN ( 1 + ωS ) K c ( 1 + ωS ) • ( 1 + ωS )
z z1 z2
T = Fm
S S2 S • (1 + S
) • (1 + S
)
1 + Qω + 2 ω p1 ωp2
o ωo
VIN • T is function of VIN
• Need feed-forward function to cancel
VIN effect
VIN
fC

-90o

-180o Very little phase margin

46
 Comparator Gain with Feed-Forward Function

Feed-Forward:
PWM ramp is function of the input voltage
PWM Comparator
d 1 v comp
=
Vcomp VP
+
Fm
d
-

dd d̂ 1 vcomp vramp
Fm = = = VP
dv comp v̂ comp VP

1
VP = K VIN Fm =
KVIN d

47
 Loop Gain with Feed-Forward Function

T = Gd AFm
1 + ωSz Kc ( 1 + ωSz1 ) • ( 1 + ωSz 2 )
T = Fm VIN
S2 S • ( 1 + ωSp1 ) • ( 1 + ωSp 2 )
1 + QSωo + 2
ωo

1
Fm =
KVIN

S S S
1 1+ ωz Kc (1 + ωz1 ) • (1 + ωz 2 )
T = V IN
KV IN S S2 S • (1 + S
) • (1 + S
)
1+ Q ωo + 2 ω p1 ωp2
ωo
• Loop Gain is INDEPENDENT of input voltage.
• Fast line step transient response, Only depends on conversion speed
of Vramp= f(VIN)
48
 How to Measure the Loop Gain

Q1
L VO
RESR
VIN + R
Q2 Co c

R1
Vexcite = 10-20mV
Ton Gate
D= driver
- -
Ts + A(S)
+ b
a VC VREF R2
PWM
Comparator Compensator

• Network Analyzer
• AP200
• a and b: 20-50mV perturbation; c: depends on output voltage
49
 Modeling, Simulation and Test Example

TPS40200
• Voltage mode PWM controller
• Input Voltage range: 4.5V to 50V
• Input Voltage Feed Forward function
PWM ramp voltage = VIN/10
• Programmable switching frequency
• Vout: 0.7V to 90% of VIN

VIN=20V, VOUT= 5V, fs = 300kHz, L=47uH, Co=22uF/10mΩ

Ω

50
 Buck Converter with Voltage Mode and Type III Compensator

L: 47uH, 0.25Ω
Ω
Q1
VO
RESR
VIN 5mΩΩ
+ D R
20V Co
22µ
µF
C3: 10p
VIN C2
R2: 23.2k C1:1.5n R1 1n
10 30.9k R3
Ton Gate
D= driver
- -
1.15k
Ts + A(S)
VC + Rx
PWM VREF
+ 0.7V 4.99k
Comparator

51
 Pspice Simulation Schematic

PWM small signal average model

PWM gain

Loop gain test perturbation Type III Compensator

52
 Simulation and Test Results

PSPICE Simulation Results Test Results

0.3 3.5

Output Voltage
0.2 3
Load Current
0.1 2.5
VOUT VOUT
Output Voltage (V)

Load Current (A)

0.0 2

-0.1 1.5

-0.2
IOUT 1 IOUT
-0.3 0.5

-0.4 0

-0.5 -0.5
0 40 80 120 160 200 240 280 320 360 400
Time (us)

Load Step Transient: 0.4A to 0.8A

53
 Simulation and Test Results

PSPICE Simulation Results Test Results

1.0 3.5

0.5 3

0.0
VOUT 2.5
Output Voltage (V)

Load Current (A)

-0.5 2
Output Voltage
-1.0
IOUT Load Current
1.5

-1.5 1

-2.0 0.5

-2.5 0

-3.0 -0.5
0 100 200 300 400 500 600 700 800 900 1000
Time (us)

Load Step Transient: 0.1A to 1.5A

54
 Loop Bandwidth Simulation: Mathcad and Pspice
Mathcad Pspice
60 60
50

Bandwidth 40
Bandwidth
35kHz 20 45kHz
0
gain(Tv( S( fi) ) ) 0

-20
50
-40

− 80 -60
3 4 5 6
100 1 .10 1 .10 1 .10 1 .10
100 f( fi) 6
1.0E+02 1.0E+03 1.0E+04 1.0E+05 1.0E+06
1×10

0
0 0

Phase Margin
50 65 degree -50

phase( Tv( S( fi) ) )

− 180
100 -100
Phase Margin
150 -150
70 degree
-180
− 200 200
3 4 5 6 -200
10 100 1 .10 1 .10 1 .10 1 .10
10 f ( fi) 1×10
6 1.0E+02 1.0E+03 1.0E+04 1.0E+05 1.0E+06
55
 Thanks!

Current Mode Loop Compensator Design will be next time

56