Instructors

ECE 551 Eric Hoffman

Not a professor
Digital Design And Synthesis
Have no PhD, Masters only

17+ years industry experience doing Integrated Circuit &
System design
Fall ‘09 • 9+ years at Intel
• 7+ years at ZMD (Mixed signal, Analog/Digital IC’s)
Lecture 1 • 1+ years as independent consultant

Instructing experience:
• Instructor Introduction • ECE555, ECE551, ECE353
• Course Introduction
• Administrative Stuff Vinod Nalamalapu = TA
• Introduction to Verilog
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Instructor and TA Office Hours Course Goals

Eric Hoffman
Provide knowledge and experience in:
• Office = EH2359, if not there then check B555
• Hours = Held in office 1st part of semester, held in B555 later. • Digital circuit design using a HDL (Verilog)
 Wednesday after class (2:20-3:30) • HDL simulation
 Friday after class (2:20 – 3:30) • How to build self checking test benches
• Email = [email protected]
• Good practices in digital design verification

TA = Vinod Nalamalapu • Synthesis of dataflow and behavioral designs
• Office Hours = Held in B555 • Basic static timing analysis concepts
 Thursday 1:00-2:30
• Optimizing hardware designs (timing, area, power)
• Email = [email protected]
• Design tools commonly used in industry

Discussion Session(s)
Monday (after class) 2:15  3:15
OR Tuesday 2:30  3:30
Teach you to be able to “think hardware”
Room 3418 Room 3349

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What You Should Already Know Course Website

Principles of basic digital logic design (ECE 352)
eCOW2
• Number representations (unsigned, signed, Hex & Binary) • Follow the link on:
http://www.engr.wisc.edu/ece/courses/ece551.html
• Boolean algebra
• Gate-level design

What the Website will have:
• K-Map minimization
• Lecture Notes (I will try to stay 1 week ahead of class)
• Finite State Machines
• Homework Assignments
• Basic datapath structures (adders, shifters, SRAM)
• Tutorials

How to log in to CAE machines and use a shell • Project Information
• Midterm Solution

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Course Materials Evaluation and Grading

Lectures
Approximately:

Textbook • 20% Homework (individually or as project team)
• Samir Palnitkar, Verilog HDL, Prentice Hall, 2003. • 30% Project (groups of 2 or 3) (Establish team soon)

Standards • 25% Midterm
• IEEE Std.1364-2001, IEEE Standard Verilog Hardware • 25% Final
Description Language, IEEE, Inc., 2001.
Homework due at beginning of class
• IEEE Std 1364.1-2002, IEEE Standard for Verilog Register • 15% penalty for each late period of 24 hours
Transfer Level Synthesis, IEEE, Inc., 2002 • Not accepted >72 hours after deadline

Synopsys on-line documentation • Your responsibility to get it to me

Other useful readings Can leave in my mailbox with a timestamp of when it was turned in

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Class Project Course Tools

Work in groups of 2 or 3 students
Industry-standard design tools:

Design, model, simulate, synthesize, and test a • Modelsim HDL Simulation Tools (Mentor)
complex digital system • Design Vision Synthesis Tools (Synopsys)

Several milestones • LSI Logic Gflx 0.11 Micron CMOS Standard Cell
• Forming teams Technology Library
• Project status report
Tutorials will be available for both tools
• Progress demonstrations (maybe) • Modelsim tutorial next week
• Final demonstration & report • Design Vision tutorial a few weeks later
• Tool knowledge will be required to complete homeworks

More details coming later in the course • TA will be a resource for help on tools

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ModelSim Tutorial Readings for Week 1

ModelSim is our Verilog simulator.
Read Chapter 1 (short)
• Tutorial takes about 1 to 1.5 hours • Overview of Digital Design with Verilog HDL

Read Chapter 2 (short)
• 2 tutorial sessions will be held next week in B555 • Hierarchical Modeling Concepts
Wednesday Sept. 9th 4:30 – 6:00
Thursday Sept. 10th 1:00 – 2:30

Read Chapter 3
• Basic Verilog Syntax
• You only need to attend one of these sessions!

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What is an HDL? What is an HDL? (continued)

HDL = Hardware Description Language
module counter(clk,rst_n,cnt); • It looks like a programming language
• Allows for modeling & simulation (with timing) of digital
input clk,rst_n; • It is NOT a programming language
designs
output [3:0] cnt;
• Can be synthesized into hardware (netlist) by synthesis reg [3:0] cnt;
 It is always critical to recall you
are describing hardware
tools (Synopsys, Ambit, FPGA compilers)
always @(posedge clk) begin
 This codes primary purpose is to
• Two major standards in industry & academia if (~rst_n) generate hardware
 Verilog (Flexible, loose, more common in industry) cnt = 4’b0000;
else  The hardware this code describes
 VHDL (Strongly typed, more common in defense and automotive) (a counter) can be simulated on a
cnt = cnt+1;
 Having used both I prefer Verilog. This course will use Verilog end computer. In this secondary use of
 Once you have the concept of an HDL down (can think and code endmodule
the language it does act more like a
hardware), the language makes little difference. programming language.

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Simulating/Validating HDL What is Synthesis?

The sad truth…
Takes a description of what a circuit DOES
• 10% design, 90% validation
Creates the hardware to DO it Output is actually a text
netlist, not a GUI schematic
• If you do it right you will spend 9X more time module counter(clk,rst_n,cnt); form.
testing/validating a design than designing it. input clk,rst_n;
output [3:0] cnt;

Testbenchs are reg [3:0] cnt;

cnt[3:0]

written in verilog
as well. always @(posedge clk) begin
Output if (~rst_n) rst_n 4 4
Testbench verilog Stimulus Design 4
Monitoring cnt = 4’b0000;
is not describing Generation Under Test
Self Checking else
hardware and (verilog) (verilog)
(verilog) cnt = cnt+1;
can be thought end
of as more of a clk
endmodule
program. file file
Verilog test bench shell

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Synthesizing the Hardware Described Why Use an HDL?

All hardware created during
Enables Larger Designs
if (a) f = c & d;
synthesis else if (b) f = d; • More abstracted than schematics, allows larger designs.
• Even if a is true, still else f = d & e;  Register Transfer Level Description
computing d&e  Wide datapaths (16, 32, or 64 bits wide) can be abstracted to a
single vector
Synthesis tool does the bulk of the tedious repetitive work vs

Learn to understand how schematic capture
• Work at transistor/gate level for large designs: cumbersome
descriptions translated to
c
hardware f
Portable Design
d • Behavioral or dataflow Verilog can be synthesized to a new
e process library with little effort (i.e. move from 0.11µ to
45nm process)
b a
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Why Use an HDL? (continued) Why Use an HDL? (continued)

Portable Design (continued)
Better Validated Designs
• Verilog written in ASCII text. The ultimate in portability. • Verilog itself is used to create the testbench
Much more portable than the binary files of a GUI  Flexible method that allows self checking tests
schematic capture tool.  Unified environment
• Synthesis tool are very good from the boolean correctness point of view

Explore larger solution space  If you have a logic error in your final design there is a 99.999% chance
• Synthesis options can help optimize (power, area, speed) that error exists in your behavioral code

• Synthesis options and coding styles can help examine  Errors caused in synthesis fall in the following categories
 Timing
tradeoffs  Bad Library definitions
Speed  Bad coding style…sloppyness
Power
area

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Other Important HDL Features Hardware Implementations

Are highly portable (text)
HDLs can be compiled to semi-custom and

Are self-documenting (when commented well) programmable hardware implementations

Describe multiple levels of abstraction
Full Semi- Programmable

Represent parallelism Custom Custom

Provides many descriptive styles
• Structural
Manual Standard Gate
• Register Transfer Level (RTL) VLSI Cell Array
FPGA PLD
• Behavioral

Serve as input for synthesis tools less work, faster time to market
implementation efficiency

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Hardware Building Blocks Standard Cells

G

Transistors are switches
Library of common gates and structures (cells)

Decompose hardware in terms of these cells
D

Use multiple transistors to make a gate
S

Arrange the cells on the chip

Connect them using metal wiring
A A A A

Use multiple gates to make a circuit …

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FPGAs What is a Netlist?

“Programmable” hardware
A netlist is a ASCII text representation of the interconnect of a
schematic

Use small memories as truth tables of functions

Many Standards Exist:

Decompose circuit into these blocks • Spice Netlist

Connect using programmable routing • EDIF (Electronic Data Interchange Format)

SRAM bits control functionality • Structural Verilog Netlist (this is what we will use)
module comb(Z,A,B,C);
FPGA Tiles P1 input A,B,C;
P2 output Z; A comb
P P3 OUT n1
P4 wire n1, n2; A1
P6
P5
and02d1 A1(n1,A,B);
= B
P7 I1
A2
inv01d1 I1(n2,C); C n2 Z
P8 and02d1 A2(Z,n1,n2);
I1 I2 I3 endmodule
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FSM Review Mealy/Moore FSMs

Combinational and sequential logic Mealy

Often used to generate control signals
Inputs

Reacts to inputs (including clock signal) Next State Output
Outputs

Can perform multi-cycle operations Logic Logic

Examples of FSMs State Register

• Counter
• Vending machine Current State
Next State
• Traffic light controller FF
• Bus Controller
• Control unit of serial protocol (like RS232, I2C or SPI)

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FSMs Remember Bubble Diagrams?

Moore
They can be useful. I sometimes will draw a bubble
• Output depends only on current state diagram first for a complex FSM. Then code it.
• Outputs are synchronous (but not necessarily glitch free) Analog_in
Given the datapath

Mealy clr_dac DAC 10-bit

-

+
gt
For a single slope
A2D converter.
Counter DAC
• Output depends on current state and inputs inc_dac

clk
10 Draw a bubble
diagram
For a FSM that can
• Outputs can be asynchronous control it.

Change with changes on the inputs 0

clr It should run the
result converter for 8 times
• Outputs can be synchronous 1 13 13
and accumulate the 8
results in a 13-bit
Register the outputs {000,cnt}
13
clk
register.

Outputs delayed by one cycle clr_smp Sample Digital

13

Compare smp_eq_8
inc_smp Counter
To 7

accum
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Verilog Module Verilog Module

In Verilog, a circuit is a module. A[1:0]
module name ports names
A[1:0]
2 of module 2

module decoder_2_to_4 (A, D) ; Decoder module decoder_2_to_4 (A, D) ; Decoder

2-to-4 2-to-4
input [1:0] A ; port input [1:0] A ; port
types sizes
output [3:0] D ; 4 output [3:0] D ; 4

assign D = (A == 2'b00) ? 4'b0001 : D[3:0] assign D = (A == 2'b00) ? 4'b0001 : D[3:0]

(A == 2'b01) ? 4'b0010 : (A == 2'b01) ? 4'b0010 :
(A == 2'b10) ? 4'b0100 : (A == 2'b10) ? 4'b0100 :
module
(A == 2'b11) ? 4'b1000 ; (A == 2'b11) ? 4'b1000 ; contents
endmodule endmodule
keywords underlined
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Declaring A Module Declaring Ports

Can’t use keywords as module/port/signal names
A signal is attached to every port
• Choose a descriptive module name
Declare type of port
• input
• output

Indicate the ports (connectivity) • inout (bidirectional)

Declare the signals connected to the ports
Scalar (single bit) - don’t specify a size
• input cin;
• Choose descriptive signal names

Vector (multiple bits) - specify size using range
• Range is MSB to LSB (left to right)

Declare any internal signals • Don’t have to include zero if you don’t want to… (D[2:1])
• output [7:0] OUT;
• input [0:4] IN;

Write the internals of the module (functionality)
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Module Styles Structural

Modules can be specified different ways
A schematic in text form (i.e. A netlist)
• Structural – connect primitives and modules
Build up a circuit from gates/flip-flops
• Dataflow– use continuous assignments • Gates are primitives (part of the language)
• Behavioral – use initial and always blocks • Flip-flops themselves described behaviorally

A single module can use more than one method!
Structural design
• Create module interface

What are the differences? • Instantiate the gates in the circuit
• Declare the internal wires needed to connect gates
• Put the names of the wires in the correct port locations of
the gates
For primitives, outputs always come first
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Structural Example RTL Example
module majority (major, V1, V2, V3) ; module majority (major, V1, V2, V3) ;

output major ; output major ;

input V1, V2, V3 ; V1 N1 input V1, V2, V3 ;
A0
V2 V1
wire N1, N2, N3; assign major = V1 & V2
| V2 & V3 V2 majority major
and A0 (N1, V1, V2), V2 N2 | V1 & V3;
A1 Or0 major V3
A1 (N2, V2, V3), V3 endmodule
A2 (N3, V3, V1);

or Or0 (major, N1, N2, N3); V3 N3

A2
V1
endmodule majority

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Behavioral Example Things to do

module majority (major, V1, V2, V3) ;
Read Chapter 1 (short)
• Overview of Digital Design with Verilog HDL
output reg major ;
input V1, V2, V3 ;
Read Chapter 2 (short)
always @(V1, V2, V3) begin • Hierarchical Modeling Concepts
V1
if (V1 && V2 || V2 && V3
|| V1 && V3) major = 1; V2 majority major
Read Chapter 3
else major = 0; • Basic Verilog Syntax (a little dry/boring but necessary)
end V3

Familiarize self with eCOW webpage
endmodule

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Review Questions

What are some advantages of using HDLs, instead of
schematic capture?

What advantages and disadvantages do standard cell
designs have compared to full-custom designs?

What are some ways in which HDLs differ from
conventional programming languages? How are they
similar?

What are the different styles of Verilog coding?

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