NIKO-SEM P-Channel Logic Level Enhancement P2003EVG

Mode Field Effect Transistor SOP-8

Lead-Free

D
PRODUCT SUMMARY
4 :GATE
V(BR)DSS RDS(ON) ID
5,6,7,8 :DRAIN
G 1,2,3 :SOURCE
-30 20mΩ -9A

S
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C Unless Otherwise Noted)
PARAMETERS/TEST CONDITIONS SYMBOL LIMITS UNITS
Drain-Source Voltage VDS -30 V
Gate-Source Voltage VGS ±20 V
TC = 25 °C -9
Continuous Drain Current ID
TC = 70 °C -8 A
1
Pulsed Drain Current IDM -50
TC = 25 °C 2.5
Power Dissipation PD W
TC = 70 °C 1.3
Operating Junction & Storage Temperature Range Tj, Tstg -55 to 150
°C
THERMAL RESISTANCE RATINGS
THERMAL RESISTANCE SYMBOL TYPICAL MAXIMUM UNITS

Junction-to-Case RθJc 25 °C / W

Junction-to-Ambient RθJA 50 °C / W
1
Pulse width limited by maximum junction temperature.
2
Duty cycle ≤ 1%
ELECTRICAL CHARACTERISTICS (TC = 25 °C, Unless Otherwise Noted)
LIMITS
PARAMETER SYMBOL TEST CONDITIONS UNIT
MIN TYP MAX
STATIC
Drain-Source Breakdown Voltage V(BR)DSS VGS = 0V, ID = -250µA -30
V
Gate Threshold Voltage VGS(th) VDS = VGS, ID = -250µA -1 -1.5 -3
Gate-Body Leakage IGSS VDS = 0V, VGS = ±20V ±100 nA
VDS = -24V, VGS = 0V -1
Zero Gate Voltage Drain Current IDSS µA
VDS = -20V, VGS = 0V, TJ = 125 °C -10

On-State Drain Current1 ID(ON) VDS = -5V, VGS = -10V -50 A

Drain-Source On-State VGS = -4.5V, ID = -7A 25 35

RDS(ON) mΩ
Resistance1 VGS = -10V, ID = -9A 15 20
Forward Transconductance1 gfs VDS = -10V, ID = -9A 24 S

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NIKO-SEM P-Channel Logic Level Enhancement P2003EVG
Mode Field Effect Transistor SOP-8
Lead-Free

DYNAMIC
Input Capacitance Ciss 1610
Output Capacitance Coss VGS = 0V, VDS = -15V, f = 1MHz 410 pF
Reverse Transfer Capacitance Crss 200
2
Total Gate Charge Qg 17 24
Gate-Source Charge2 Qgs VDS = 0.5V(BR)DSS, VGS = -10V, 5 nC
Gate-Drain Charge 2
Qgd ID = -9A 6
Turn-On Delay Time2 td(on) 5.7
2
Rise Time tr VDS = -15V, RL = 1Ω 10
nS
2
Turn-Off Delay Time td(off) ID ≅ -1A, VGS = -10V, RGS = 6Ω 18

Fall Time2 tf 5
SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TC = 25 °C)
Continuous Current IS -2.1
3
A
Pulsed Current ISM -4
Forward Voltage1 VSD IF = -1A, VGS = 0V -1.2 V
1
Pulse test : Pulse Width ≤ 300 µsec, Duty Cycle ≤ 2％.
2
Independent of operating temperature.
3
Pulse width limited by maximum junction temperature.

REMARK: THE PRODUCT MARKED WITH “P2003EVG”, DATE CODE or LOT #

Orders for parts with Lead-Free plating can be placed using the PXXXXXXG parts name.

OCT-20-2004
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NIKO-SEM P-Channel Logic Level Enhancement P2003EVG
Mode Field Effect Transistor SOP-8
Lead-Free

Body Diode Forward Voltage Variation with Source Current and Temperature
100
V GS = 0V
10
-Is - Reverse Drain Current(A)

1 T A = 125° C

25° C
0.1

-55° C
0.01

0.001

0.0001
0 0.2 0.4 0.6 0.8 1.0 1.2
-VSD - Body Diode Forward Voltage(V)

OCT-20-2004
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NIKO-SEM P-Channel Logic Level Enhancement P2003EVG
Mode Field Effect Transistor SOP-8
Lead-Free

OCT-20-2004
4
NIKO-SEM P-Channel Logic Level Enhancement P2003EVG
Mode Field Effect Transistor SOP-8
Lead-Free

SOIC-8(D) MECHANICAL DATA

mm mm
Dimension Dimension
Min. Typ. Max. Min. Typ. Max.

A 4.8 4.9 5.0 H 0.5 0.715 0.83

B 3.8 3.9 4.0 I 0.18 0.254 0.25

C 5.8 6.0 6.2 J 0.22

D 0.38 0.445 0.51 K 0° 4° 8°

E 1.27 L

F 1.35 1.55 1.75 M

G 0.1 0.175 0.25 N

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