A SEMINAR REPORT ON

ENERGY EFFICIENT DESIGN OF BATTERY POWERED

EMBEDDED SYSTEMS

By
G.SHRICHARAN
(09B91D3812)
M.Tech (DECS)
I-year I-Semester

Department of Electronics and Communication Engineering

GURUNANAK ENGINEERING COLLEGE
ACCREDITED BY NBA, AICTE & Affiliated to JNTUH)
Ibrahimpatan (M), R.R. District.
 TABLE OF CONTENTS
CHAPTER PAGE NO
GURUNANAK ENGINEERING COLLEGE............................................................................................1
TABLE OF CONTENTS........................................................................................................................................2
LIST OF FIGURES........................................................................................................................................3
1. SUMMARY.................................................................................................................................................4
2. INTRODUCTION......................................................................................................................................5
3. RECENT WORK........................................................................................................................................6
4. METHODOLOGY.....................................................................................................................................7
4.1.VALIDATION OF THE SIMULATION METHODOLOGY..............................................................9
4.2.EMBEDDED MPEG DECODER DESIGN EXPLORATION.............................................................9
4.3. PROFILING OF SOFTWARE ENERGY CONSUMPTION............................................................10
5.RESULTS...................................................................................................................................................11
6.CONCLUSION..........................................................................................................................................15
7.REFERENCES..........................................................................................................................................16
 LIST of FIGURES

LIST of TABLES
1. SUMMARY

Energy-efficient design of battery-powered systems demands optimizations in both

hardware and software. A modular approach is presented for enhancing instruction level
simulators with cycle-accurate simulation of energy dissipation in embedded systems.
The methodology has tightly coupled component models thus making the approach more
accurate. Performance and energy computed by our simulator are within a 5% tolerance
of hardware measurements on the Smart Badge. The suggested simulation methodology
can be used for hardware design exploration aimed at enhancing the Smart Badge with
real-time MPEG video feature. In addition, a profiler is presented that relates energy
consumption to the source code. Using the profiler a designer can quickly and easily
redesign the MP3 audio decoder software to run in real time on the Smart Badge with low
energy consumption. Performance increase of 92% and energy consumption decrease of
77% over the original executable specification has been achieved.
2. INTRODUCTION
ENERGY consumption is a critical factor in system-level design of embedded
portable appliances. In addition, low costs with fast time to market are crucial. As a
result, typical portable appliances are built of commodity components and have a
microprocessor-based architecture. Full system evaluation is often done on prototype
boards resulting in long design times. Field programmable gate array (FPGA) hardware
emulators are sometimes used for functional debugging but cannot give accurate
estimates of energy consumption or performance. Performance can be evaluated using
instruction-set simulators , but there is limited or no support for energy consumption
evaluation.

A designer would like to explore a limited number of architectural alternatives and

test functionality , Energy consumption and performance. Designer then optimizes S/W
& H/W during development of Embedded System. Finally the prototype is built in order
to get the best performance and energy consumption from the system.

The distinctive features of our approach are the following: i) complete system-level
and component energy consumption estimates as well as battery lifetime estimates; ii)
ability to explore multiple architectural alternatives; and iii) easy estimation of the impact
of software changes both during and after the architectural exploration.
 System model and the methodology for cycle-accurate simulation of energy
dissipation are presented. The simulation results of timing and energy dissipation using
the methodology presented are within 5% of the hardware measurements for the
Dhrystone test case. Hardware architecture trade-offs for Smart Badge’s real-time MPEG
video decode design are explored using cycle-accurate energy simulation. The profiling
support that developed is also discussed. A full software design example of MP3 audio
decoder for the Smart Badge that uses profiler is shown in the methodology (4).

3. RECENT WORK

As portable embedded systems have grown in importance in recent years, so has the
need for tools that enable energy consumption estimation for such systems.

Processor energy consumption is generally estimated by instruction-level power

analysis. A few research prototype tools that estimate the energy consumption of
processor core, caches, and main memory in SOC design have been proposed [7], [10].
The final system energy is obtained by summing over the contribution of each
component. The main limitation of the approaches presented in [7] and [10] is that the
interaction between memory system (or I/O peripherals) and processor is not modeled.

Cycle-accurate register-transfer level energy estimation is presented in [8]. An alternative

approach for energy estimation using measurements as a basis for estimation is presented
in PowerScope tool [9]. Finally, previous approaches do not focus on battery life
optimization,the ultimate goal of energy optimization for portable systems. In fact, when
the battery subsystem is not considered in energy estimation significant errors can result
[21]. Some analytical estimates of the tradeoff between battery capacity and delay in
digital CMOS systems are presented in [18].
 In contrast to previous approaches, in this work memory models and processor
instruction-level simulator are tightly integrated together with an accurate battery model
into cycleaccurate simulation engine. The largest energy savings were observed at the
interprocedural level that compilers have not been able to exploit.

This approach enables complete system-level and component energy consumption

estimates as well as battery lifetime estimates. In addition, it provides an ability to
quickly explore multiple architectural alternatives. Finally, it enables software
optimization both during and after architectural exploration using the presented energy
profiling tool.
4. METHODOLOGY

We use SmartBadge [2] throughout this paper as a vehicle to illustrate our

methodology and to obtain hardware measurements. The SmartBadge, shown in Fig. 1, is
an embedded system consisting of the StrongARM-1100 processor, FLASH, SRAM,
sensors, and modem/audio analog front-end on a PCB board powered by the batteries
through a DC–DC converter. The SmartBadge could be used as a corporate ID card,
attached (or built in) to devices such as PDAs and mobile telephones, or incorporated in
computing systems. The design goal for the SmartBadge has since been extended to
combine location awareness and authentication with audio and video support.

Fig. 1. SmartBadge.

The system we use in this work to illustrate our methodology, the SmartBadge,
has an ARM processor. As a result, we implemented the energy models as extensions to
the cycle-accurate instruction-level simulator for the ARM processor family, called the
ARMmulator [1]. The ARMulator is normally used for functional and performance
validation. Fig. 2 shows the simulator architecture. The typical sequence of steps needed
to set up system simulation can be summarized as follows: 1) The designer provides a
simple functional model for each system component other than the processor; 2) The
functional modelis annotated with a cycle-accurate performance model; 3) Application
software (written in C) is cross-compiled and loaded in specified locations of the system
memory model; and 4) The simulator runs the code and the designer can analyze
execution using a cross-debugger or collecting statistics. A designer interested in using
our methodology would only need to additionallyprovide cycle-accurate energy models
for each component during step 2) of the simulation setup. Thus, the designer can
obtain power estimates with little incremental effort.

Two main classes of processor cycle types are processor active, where active
power is consumed, and processor idle, where idle power is consumed. The processor
idle state represents an off-chip memory request. The number of cycles that the processor
remains idle depends on L2 cache and memory model access times. L2 cache, when
present, is always accessed before the main memory and so is active on every memory
access request. On L2 cache miss, main memory is accessed. Memory model accounts for
energy spent during the memory access. The interconnect energy model calculates energy
consumed by the interconnect and pins based on the number of lines switched during the
cycle on the data and address busses.

The total energy consumed by the system per cycle is the sum of energies

consumed by the processor and L1 cache ( ), interconnect and pins ( ), memory

( ), L2 cache ( ), the DC–DC converter ( ) and the efficiency losses in the

battery ( ).
 The total energy consumed during the execution of the software on a given
hardware architecture is the sum of the energies consumed during the each cycle. Models
for energy consumption and performance estimation of each system component are
described in the following sections.

4.1.VALIDATION OF THE SIMULATION METHODOLOGY

We validated the cycle-accurate power simulator by comparing the computed energy

consumption with measurements on the SmartBadge prototype implementation. All the
components except the CPU core are powered through the 3.3 V supply line. CPU core
runs on 1.5 V supply. DC–DC converter is powered by the 3.5 V supply. Average current
consumed by the processor’s power supply and the total current drawn from the battery
are measured with digital multimeters. Execution time is measured using the processor
timer.

4.2.EMBEDDED MPEG DECODER DESIGN EXPLORATION

The primary motivation for the development of cycle-accurate energy consumption

simulation methodology is to provide an easy way for embedded system designers to
evaluate multiple hardware and software architectures with respect to performance and
energy consumption constraints. The MPEG decoder design consists of the processor, the
off-chip memory, the DC–DC converter, output to the LCD display, and the interface to
the source of the MPEG stream. The input and output portions of the MPEG decoder
design will not be considered at this point. We focus on selection of memory hierarchy
that is most energy efficient. Using faster and more power-hungry memory can be energy
efficient.

The analysis of peak energy consumption and the fine tuning of the architectures
can be done by studying the energy consumption and the memory access patterns over a
period of time. Peak energy consumption can reach twice the average consumption, so
the thermal characteristics of the hardware design, the DC–DC converter, and the battery
have to be specified accordingly.

For best battery utilization, it is important to match the current consumption of the
embedded system to the discharge characteristic of the battery. On the other hand, the
more capacity battery has, the heavier and more expensive it will be.

The design exploration example presented in this section illustrates how the
methodology for cycle-accurate energy consumption simulation can be used to select and
fine-tune hardware configuration that gives the best tradeoff between performance and
energy consumption.The main limitation of the cycle-accurate energy simulator is that
the impact of code optimizations is not easily evaluated.

4.3. PROFILING OF SOFTWARE ENERGY CONSUMPTION

Profiling for energy and performance enables designers to identify those portions
of their source code that need to be further optimized in order to either decrease energy
consumption, increase performance, or both.

The profiler operates as follows. Source code is compiled using a compiler for a
target processor (e.g., application or operating system code). The output of the compiler
is the executable that the cycle-accurate simulator executes (represented in this figure as
assembly code that is input into the simulator) and a map of locations of each procedure
in the executable that a profiler uses to gather statistics (the map is correspondence of
assembly code blocks to procedures in “C” source code).

During each cycle of operation, the cycle-accurate energy consumption simulator

calculates the current total execution time and energy consumption of all system
components as shown in. The profiler works concurrently with the cycle-accurate
simulator.It periodically samples the simulation Results and maps the energy and
performance to the function executed using information gathered at the compile time.
The main advantage of the profiler is that it allows designers to obtain energy
consumption breakdown by procedures in their source code after running only one
simulation.

Fig 2: Profiler Architecture

5.RESULTS

. A good example of profiler usage is shown in Table IV. The table shows a
portion of energy profile for MP3 audio decode. The first column gives the name of the
top procedure, followed by its children. The next column gives the total energy spent for
that procedure. For example, the total energy spent running the program (main) is 0.32
mWhr. The final column gives the amount of energy spent only in that particular
procedure. For example, under main it is clear that III hybrid and its descendants spend
the most energy, 0.0671 mWhr. Looking at the entry for III hybrid , it is easy to see that
the largest portion of energy is consumed by its child, inv_mdctl . Therefore, the
procedures to focus optimization on are inv_mdctl and SubBandSynthesis. Although in
this example we showed source code profile of total battery energy consumption, the
profiler can report energy consumption for any system component, such as SRAM or the
interconnect.

The profiler allows for fast and accurate evaluation of software and hardware
architectures. Most importantly, it gives good guidance to the designer during the design
process without requiring manual intervention. In addition, the profiler accounts for all
embedded system components, not just the processor and the L1 cache as most general-
purpose profilers do. In the next section we present a real design example that uses the
profiler to guide the implementation of the source code optimizations described earlier
for the MP3 audio decoder running on the SmartBadge.
TABLE 1
Sample Energy Profiling
 TABLE 2
PROFILING FOR MP3 IMPLEMENTATIONS
 Profiling results in Table 2 show that the algorithmic optimizations considerably
reduced the energy consumption of Sub- BandSynthesis function—it does not appear in
the top three functions, and in fact it is only 3.2% of the total energy consumption. The
final step is to combine the algorithmic changes with the data and instruction-level
changes, resulting in decrease of Sub- BandSynthesis fraction of energy consumption
to6% of total.

TABLE 3
ENERGY FOR MP3 IMPLEMENTATIONS

System and component energy consumptions are shown inTable 3 for different
revisions of source code optimization. Positive percentages show energy decrease with
respect to the original code.

TABLE 4
PERFORMANCE FOR MP3 IMPLEMENTATIONS
 Table VII shows the same results but for performance measurements. Positive
percentages show performance increase. Although the energy savings of algorithmic
versus data and instruction-level optimizations as compared to original code are
comparable, the performance improvement of data and instruction-level optimizations is
significant. Note that the increase in energy consumption and the decrease in
performance of Flash is due to the increase in code size with the algorithmic change in
SubBandSynthesis procedure. The total improvement in system performance and energy
consumption more than makes up for the degradation of Flash performance and energy
consumption. Combined optimizations give real-time performance for MP3 audio decode
which is a primary constraint for this project. In addition, lower energy consumption
enables longer battery life. Note that faster implementation that is also more energy
efficient might imply higher power consumption, which can be an issue for thermal
design of the device. In the case presented in this paper, it was critical to get real-time
performance with longer battery lifetime. The average and peak power consumption
constraints are met with our final design.

6.CONCLUSION
We developed a methodology for cycle-accurate simulation of performance and energy
consumption in embedded systems. Accuracy, modularity, and ease of integration with
the instruction- level simulators widely used in industry make this methodology very
applicable to the embedded system hardware and software design exploration. Simulation
is found to be within 5% of the hardware measurements for Dhrystone benchmark. We
presentedMPEGvideo decoder embedded system design exploration as an example of
howour methodology can be used in practice to aid in the selection of the best hardware
configuration. We have also developed a tool for profiling energy consumption of
software in embedded systems. Profiling results enabled us to quickly and easily target
the redesign the MP3 audio decoder software. Our final MP3 audio decoder is fully
compliant with the MPEG standard and runs in real time with low energy consumption.
Using our design tools we have been able to increase performance by 92% while
decreasing energy consumption by 77%.

7.REFERENCES

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Toolkit Version 2.11, 1996.
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[9] J. Flinn and M. Satyanarayanan, “PowerScope:A tool for profiling the
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[10] B. Kapoor, “Low power memory architecutres for video applications,”
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