MOS VIDEO SOLUTION

GATE PREVIOUS YEAR

MOS - DC ANALYSIS
[GATE-EC-2004-IITD]
(1) The drain of an n-channel MOSFET is shorted to the gate so that VGS = VDS. The threshold voltage (VT)
of – MOSFET is 1 V. If the drain current ID is 1 mA for VGS = 2 V ,then for VGS = 3 V, ID is
(A) 2 mA (B) 3 mA
(C) 9 mA (D) 4 mA
Answer : D
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[GATE-EC-2005-IITB]
(2) For an n-channel MOSFET and its transfer curve shown in the figure, the threshold voltage is:

(A) 1 V and the device is in active region

(B) 1 V and the device is in saturation region
(C) 1 V and the device is in saturation region
(D) 1 V and the device is in active region.
Answer : C
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[GATE-EC-2014-IITKGP]
(3) For the n-channel MOS transistor shown in the figure the threshold voltage VTh is 0.8 V. Neglect
channel length modulation effects. When the drain voltage VD = 1.6 V, the drain current ID was found
to be 0.5 mA. If VD is adjusted to be 2 v by changing the values of R and VDD, the new value of ID (in
mA) is :
 (A) 0.625 (B) 0.75
(C) 1.125 (D) 1.5
Answer : C
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[GATE-EC-2015-IITK]
(4) For the NMOSFET in the circuit shown, the threshold voltage is Vth , where Vth  0 .
The source voltage
VSS is varied from 0 to VDD . Neglecting the channel length modulation, the drain current ID as a
function of VSS is represented by

(A) (B)

(C) (D)

Answer : A
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[GATE-EC-2014-IITKGP]
(5) A depletion type N-channel MOSFET is biased in its linear region for use as a voltage controlled
resister. Assume threshold voltage VTH = -0.5 V, VGS = 2.0 V, VDS = 5V, W/L = 100, COx = 10-8 F/cm2
and μn = 800 cm2/V-S. The value of the resistance of the voltage controlled resistor (in  ) is _______.

Answer : 499-501
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[GATE-EC-2016-IISc]
(6) Consider an n-channel metal oxidesemiconductor field effect transistor (MOSFET) with a gate-to-
W
 4 ,  N Cox  70  10 AV , the threshold voltage is 0.3V,
6 2
source voltage of 1.8 V. Assume that
L
and the channel length modulation parameter is 0.09 V 1 . In the saturation region, the drain
conductance (in micro seimens) is _______.
Answer : 28-29
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[GATE-EC-2017-IITR]
(7) Two n-channel MOSFETs, T1 and T2, are identical in all respects except that the width of T2 is double
that of T1. Both the transistors are biased in the saturation region of operation, but the gate overdrive
voltage ( VGS  VTH ) of T2 is double that of T1, where VGS and VTH are the gate-to-source voltage and
threshold voltage of the transistors, respectively. If the drain current and transconductance of T1 are I D1
and gm1 respectively, the corresponding values of these two parameters for T2 are
(A) 8I D1 and 2 g m1
(B) 8I D1 and 4 g m1
(C) 4 I D1 and 4 g m1
(D) 4 I D1 and 2 g m1

Answer : B
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[GATE-EC-2017-IITR]
(8) Assuming that transistors M 1 and M 2 are identical and have a threshold voltage of 1 V, the state of
transistors M 1 and M 2 are respectively

(A) Saturation, Saturation

(B) Linear, Linear
(C) Linear, Saturation
(D) Saturation, Linear
Answer : C
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[GATE-IN-2015-IITK]
(9) In the circuit shown in the figure, both the NMOS transistors are identical with their threshold voltages
being 5 V. Ignoring channel length modulation, the output voltage Vout in volt is _____ V.
Answer : 20
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[GATE-EC-2011-IITM]
(10) In the circuit shown below, for the MOS transistors,  n Cox  100 A/V 2
and the threshold voltage
VT  1V . The voltage Vx at the source of the upper transistor is

(A) 1 V
(B) 2 V
(C) 3 V
(D) 3.67 V
Answer : C
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[GATE-EC-2005-IITB]
(11) Both transistors T1 and T2 show in the figure have threshold voltage of 1 volts. The device parameters
K1 and K 2 of T1 and T2 are respectively, 36 μA / V 2 and 9 μA / V 2 . The output voltage V0 is:

(A) 1 V (B) 2 V
(C) 3 V (D) 4 V
Answer : C
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 [GATE-EC-2019-IITM]
(12) In the circuit shown, the threshold voltages of the pMOS (|Vtp |) and nMOS (Vtn ) transistors are both
equal to 1V. All the transistors have the same output resistance rds of 6 M . The other parameters are
listed below :
W
 n Cox  60A/V 2 ;   5
 L  nMOS

W
p Cox  30A/V 2 ;    10
 L pMOS

 n and μ p are the carrier mobilities, and Cox is the oxide capacitance per unit area. Ignoring the effect of
channel length modulation and body bias, the gain of the circuit is _____
(rounded off to 1 decimal place).

Answer : -900
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[GATE-EC-2014-IITKGP]
(13) The slope of the ID vs. VGS curve of an n-channel MOSFET in linear regime is 103 1 at V DS = 0.1 V.
For the same device, neglecting channel length modulation, the slope of the I DVs V GS curve

 in 
A / V under saturation regime is approximately --------.

Answer : 0.06to0.08
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[GATE-EC-2018-IITG]
(14) In the circuit shown below, the (W / L) value for M 2 is twice that for M 1 . The two nMOS transistors
are otherwise identical. The threshold voltage VT for both transistors is 1.0V.Note that VGS for M 2
must be>1.0 V.
Current through the nMOS transistors can be modeled as
 W  1 2 
I DS  Cox   (VGS  VT )VDS  VDS  for VDS  VGS  VT
 L  2 
W 
I DS  Cox   (VGS  VT ) / 2
2
for VDS  VGS  VT
L 
 The voltage (in volts, accurate to two decimal places) at Vx is _______.

Answer : 435
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MOS BASED CURRENT MILLER CIRCUIT

[GATE-EC-2008-IISc]
(15) For the circuit shown in the following figure, transistors M1 and M2 are identical NMOS transistors.
Assume that M2 is in saturation and the output is unloaded.

The current I x is related to I bias as

(A) I x  I bias  I s
(B) I x  I bias
(C) I x  I bias  I s
 Vout 
(D) I x  I bias   VDD  
 RE 

Answer : B
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[GATE-EC-2019-IITM]
(16) In the circuit shown, V1 = 0 and V2 = Vdd. The other relevant parameters are mentioned in the figure.
Ignoring the effect of channel length modulation and the body effect, the value of I out is _____mA
(rounded off to 1 decimal place).
Answer : 12
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[GATE-IN-2019-IITM]
(17) In the circuit shown below, all transistors are n-channel enhancement mode MOSFETs. They are
identical and are biased to operate in saturation mode. Ignoring channel length modulation, the output
voltage Vout is ______ V.

Answer : 4
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*************

MOS - AC ANALYSIS
[GATE-EC-2018-IITG]
(18) Two identical nMOS transistors M 1 and M 2 are connected as shown below. The circuit is used as an
amplifier with the input connected between G and S terminals and the output taken between D and S
terminals. Vbias and VD are so adjusted that both transistors are in saturation. The transconductance of
iD v
this combination is defined as g m  while the output resistance is r0  DS , where iD is the
vGS iD
current flowing into the drain of M 2 . Let g m1 , gm2 be the transconductances and r01 , r02 be the output
resistances of transistors M 1 and M 2 , respectively.

Which of the following statements about estimates for gm and r0 is correct?

(A) gm  gm1  gm2  r02 and r0  r01  r02 .
(B) gm  gm1  gm 2 and r0  r01  r02 .
(C) g m  g m1 and r0  r01  gm 2  r02 .
 (D) g m  g m1 and r0  r02 .
Answer : C
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A
(19) Given figure shows a two-stage CMOS amplifier. Determine its overall gain, ( v0 / vin ). Assume all
transistors in saturation.

(A) gm1 gm 4 (rd1 || rd 2 )(rd 3 || rd 4 )

(B)  gm4 (rd1 || rd 2 )(rd 3 || rd 4 )
(C)  gm1 (rd 1 || rd 2 )(rd 3 || rd 4 )

(D)  gm1 gm 4 (rd1  rd 2 )(rd 3  rd 4 )

Answer : A
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[GATE-EC-2008-IISc]
(20) Two identical NMOS transistors M1 and M2 are connected as shown below. V bias is chosen so that both
dI
transistors are in saturation. The equivalent g m of the pair is defined to be out at constant Vout .
dVi

The equivalent g m of the pair is

(A) The sum of individual g m ' s of the transistors

(B) The product of individual g m ' s of the transistors
(C) Nearly equal to the g m of M1
(D) Nearly equal to g m / g o of M2.

Answer : C
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[GATE-IN-2019-IITM]
(21) A voltage amplifier is constructed using enhancement mode MOSFETs labeled M1, M2, M3 and M4 in
the figure below. M1, M2 and M4 are n-channel MOSFETs and M3 is a p-channel MOSFET. All
MOSFETs operate in saturation mode and channel length modulation can be ignored. The low
frequency, small signal input and output voltages are vin and vout respectively and the dc power supply
voltage is VDD . All n-channel MOSFETs have indentical transconductance g mn while the p-channel
MOSFET has transconductance g mp .

The expressions for the low frequency small signal voltage gain vout / vin is

(A)  g mn / g mp

(B)  gmm ( gmn  gmp )1

(C)  g mm / g mp

(D) gmn ( gmn  gmp )1

Answer : C
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(22) Determine (v0 / vin ) for the CMOS inverter circuit of given figure. Assuming both transistors in
saturation.

(A)   gm1 (rd1 || rd 2 )

(B)   gm 2 (rd 1 || rd 2 )
(C)  ( gm1  gm 2 ) rd 1

(D)  ( gm1  gm2 )(rd1 || rd 2 )

Answer : D
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 [GATE-EC-2020-IITD]
(23) Using the incremental low frequency small-signal model of the MOS device, the Norton equivalent
resistance of the following circuit is

1
(A) rds  R (B) rds  R  gm rds R
gm

rds  R
(C) (D) rds  R
1  g m rds

Answer : C
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Common Data Question for next two questions

Assume that the threshold voltage of the N-channel MOSFET shown in figure is +0.75 V. The output
characteristics of the MOSFET are also shown.

[GATE-EC-2005-IITB]
(24) The transconductance of the MOSFET is :
(A) 0.75 mS (B) 1 mS
(C) 2 mS (D) 10 mS
 [GATE-EC-2005-IITB]
The voltage gain of the amplifier is :
(A) +5 (B) -7.5
(C) +10 (D) -10
Answer : B & B
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