Microprocessor Systems I: Dara Rahmati
Microprocessor Systems I: Dara Rahmati
Microprocessor Systems I
Dara Rahmati
I/O I/O
CPU Memory
Microprocessor
ports devices
Data bus
Control bus
Princeton architecture
1.Five components partitioning
• Input/Output I/O Ports
• Memory Memory
• ALU
• Registers CPU
• Control unit
2. Three key concepts:
– Both instructions and data are stored in a single
read-write memory
– The contents of memory are addressable by location,
without regard to the type of data Harvard architecture
– Execution occurs in a sequential fashion
Microprocessor
CU
(μP)
Microcomputer
Memory Registers
( μC )
I/O Device 1
Microcomputer I/O ports
system I/O Device 2
(μCS) I/O devices …
I/O Device n
System software
Application software
Microprocessor
ADDRESS
BUS
mamulan
baraye rah
har no
oftadane
mobadele
system ast
yek format
Keyboard
Microprocessor BOOT az energy b
digari Screen
ROM Instruction Data
Contains: UART
ALU (program) Transducers
RAM Parallel
CU Used at ROM/RAM mese
Registers microphon interface
startup e
(mekaniki
etc.
b electriki)
DATA BUS
ADDRESS
BOOT
ROM Instruction Data UART
Microprocessor (program) RAM Parallel
Used at ROM interface
contains
CU startup Transducers Etc
ALU
Registers
DATA
Primary Secondary
CPU
Internal
Cache memory memory
Regs.
• Memory hierarchy
– Cache(s)
– Primary memory: ROM, RAM
– Secondary memory: magnetic disk, optical memory, tape, …
Primary Secondary
CPU
Internal
Cache memory memory
Regs.
• Memory hierarchy
– Cache(s)
– Primary memory: ROM, RAM
– Secondary memory: magnetic disk, optical memory, tape, …
IO device
CPU RAM ROM I/O ports
IO device
Data Bus
Control Bus
Memory
IO device IO device IO device
• A dedicated bus between CPU and memory, and a dedicated bus between CPU
and I/O devices
• pro:efficient in terms of data transfer
• con:information between memory and I/O devices has to go through CPU.
Therefore, poor CPU performance
Address
Address Memory
MA address
Address Memory address Memory
chosen
CPU CPU
• Isolated I/O
– Two separate address spaces for memory and I/O
modules
– Using different sets of accessing instructions
Microprocessors and Assembly 48
End