Design and Implementation of Efficient 4x4

Vedic Multiplier for DSP Applications

 having multiplier, adder and accumulator register as basic

Abstract—The ne ed of high speed, low power and area building blocks. The multiplier unit is going to generate the
e fficient Digital Signal Processors (DSPs) is increasing day
by day. However, in order to design a proficie nt Digital
partial product, performing the reduction of generated
Signal Processor or other applications related to signal partial product, further performing the propagation of the
processing, Multiply-Accumulate (MAC) unit is one of the carry and finally adding the propagated carry here.
most vital blocks of processor. The multipliers are the basic
Additionally, the accumulator unit is a standard PIPO
building blocks of these MAC units. Also, the computation
pe rformed using Vedic Mathematics is found to be more (Parallel Input Parallel Output) shift register in order to
e fficient than the basic Mathematics. This paper has store the accumulation results. The existing result is further
pre sented the implementation of various types of Vedic going to be added with the stored results of the available
multiplier circuits based on different Vedic sutras such as
Urdhva Tiryakbhyam sutra and Nikhilam sutra and different accumulator unit. In this research work, we first implement
type s of adder architectures such as Ripple Carry Adder, the basic Vedic multiplication theorems namely Nikhilam
Kogge Stone Adder and Multiplexer based Adder etc. From Sutra and Urdhva Sutra for both designing 2-bit multiplier.
comparative analysis, 4x4 Vedic multiplier using Urdhva
Tiryakbhyam sutra and multiplexer based full adder was This is further proceeded to design 4-bit multiplier using
found to be proficient in terms of delay, speed and area. different types of adders in order to obtain the efficient
multiplier. The final design of 4-bit multiplier will be a basic
Index Terms—Carry Propagation, Delay, Multiplexer unit in order to design higher order multiplier and further
Based Adder, Power Consumption , Vedic Multiplier.
designing of MAC unit which is area of research of author.
Here, the comparison of various performance parameters
Paper Classification
DOI: 10.7251/ELSxxxxxxxx such as power, delay, and area has been performed to make
inroads for further research. The rest of the paper is
I. INT RODUCT ION organized as follows: Section II covers the literature survey
in the related domain. Section III explains the proposed
Digital signal processing (DSP) is one of the most widely
research work with detailed description. In section IV
used and exceptionally pulsating field in the current
experimental results and comparison of various designs
scenarios of Electronics industry. There is a wide range of
have been presented. Section V presents the conclusion of
research area such as digital image processing, digital
the research work.
signal processing, audio-video processing etc [1-3]. In
II. LITERATURE SURVEY
order to carry out all these research works especially for
digital signal processing, computing machines with
The design and implementation of an 8-bit Vedic multiplier
superior computational accuracy, leveraged complexity and
was done in [7] with the extensive use of a special 8-bit
enhanced speed. All the basic algorithms and operations
barrel shifter. This barrel shifter needs only single clock
such as Fast Fourier Transform (FFT), digital filtering,
cycle in order to perform n number of shifts. This design
convolution and correlation etc need to perform basic
was found to be superior with respect to propagation delay
arithmetic operations. To perform these numerous
in comparison of other traditional multipliers such as tree
arithmetic operations, design of an efficient Multiply
multiplier, Braun multiplier, Modified Booth multiplier, and
Accumulate (MAC) unit becomes one of the vital and
Array multiplier. Another novel design of multiplier was
challenging tasks. Furthermore, performance of these MAC
proposed in [8] which results in the reduction of
units determines the performance parameters such as
generation of partial products. Various types of adders
delay, area, and power consumption etc. of the digital
were used here with comparison of various performance
processors. The standard architecture of MAC unit is
parameters. However, Kogge Stone adder was selected
among all since it was found to have optimized values for
power consumption and propagation delay.
 Step 2: The second value i.e. the coefficient of x is
A comprehensive study of various multipliers based on achieved by performing the crosswise multiplication of a 1
Constant coefficient multiplication (KCM) scheme, Array and b 2 and of b 1 and a2 and further the addition of the two
Multiplier, and Vedic Mathematics based multiplication obtained partial products.
was present in [9]. All the designed multipliers were Step 3: The third value i.e. constant coefficient is achieved
compared for area (based on the number of slices and look by performing the vertical multiplication of constants b 1
up tables) and combinational path delays. Moreover, the and b 2.
multiplier designed based on Vedic Urdhva multiplication
The Urdhva Tiryagbhyam Sutra based algorithm is
sutra was found to be the fastest. In [10] author worked on
basically based on the scheme of generation of all partial
Karatsuba-Ofman algorithm in order to design and
products along with their additions happening
implement an efficient Vedic multiplier in terms of area, simultaneously in concomitant fashion. Hence, the
speed, delay and design complexities. This work was multiplier is solely independent of processor clock
further extended to design Vedic MAC unit. frequency for synchronous circuits, which results in quick
calculation of final product and superiority at higher order
Vedic Nikhilam sutra based on recursive application was frequency clock circuits. Furthermore, the above discussed
generalized in order to implement multiplication for radix-2 steps can further be extended and generalized for higher
number system based digital applications in [11]. order multiplications.
Furthermore, the statistical study was performed which
1.2.NIKHILAM SUTRA
was derived from the numerous recursion profile
depending on the minor multiplicand. The designed
The Nikhilam Sutra is also derived from Sanskrit literature
technique was claimed to be proficient for minor which means All from 9 and last from 10". However, this
multiplicands in addition, nothing like the majority of the scheme can be widely used for all sorts of multiplications,
asymptotically quick methodologies. This work was limited but becomes more proficient when the given operand
to the calculation for two variable bit operands only. numbers of multiplication are having values closer to the
Additionally, the proposed scheme was found to be base. In this algorithm the complement of thel arger
exclusively dependent upon the ratio of the number of 0's number is calculated from the nearest base in order to carry
and 1's used in order to represent the binary number more out the multiplication operation. Hence, we can say closed
willingly than upon the order and magnitude of the the number to the base, the lesser will be the complexity
operands. involved during the multiplication. In general, this sutra is
III. PROPOSED WORK also incorporated in order to translate the higher order
1.Vedic sutras digit multiplications to the lower order digit multiplications
In this paper, we have worked on two Vedic Sutras namely after performing basic arithmetic steps such as add,
Urdhva Tiryagbhyam Sutra‘ and ‗Nikhilam Sutra‘. Based subtract and shift. Following are the steps involved during
on the performance parameters such as area, power multiplication of two binary numbers P‘ and Q‘
consumption, speed, design complexity etc. we will choose Case-1 When both P and Q are greater than the nearest
between these two. base
Step 1: Calculate P1 = P – Nearest Base
1.1. URDHVA TIRYAGBHYAM SUTRA Step 2: Calculate Q1 = Q – Nearest Base
The Urdhva Tiryagbhyam Sutra as the name suggests is Step 3: Calculate R = P1 X Q1
based on the vertical and further crosswise multiplication Step 4: Calculate S = P + Q1 = Q + P1
technique since derived from Sanskrit literature where the Step 5: Calculate Result = (Nearest Base x S) + R
word Urdhva‘ means ‗Vertical‘ and the word Tiryagbhyam‘ Case-II When both P and Q are lesser than the nearest
means ‗crosswise‘. Lets‘ we need to perform multiplication base
on two numbers (both are two digit numbers) as (a1x+b 1) Step 1: Calculate P1 = Nearest Base - P
and (a2x+b 2). The simple product is given by a1a2x² + (a1b 2+ Step 2: Calculate Q1 = Nearest Base - Q
b 1a2) x + b 1b 2. Step 3: Calculate R = P1 X Q1
Following are the steps involved during multiplication for a Step 4: Calculate S = P - Q1 = Q - P1
2-digit multiplier. Step 5: Calculate Result = (Nearest Base x S) + R
Case-III When P is greater than and Q is lesser than the
Step 1: The first value i.e. the coefficient of x² is achieved nearest base
by performing the vertical multiplication of a 1 and a2. Step1: Calculate P1 = P – Nearest Base
Step2: Calculate Q1 = Nearest Base - Q B. Carry generation stage
Step3: Calculate R = P1 X Q1
Carry generation stage is the second stage of Kogge Stone
Step 4: Calculate S = P - Q1
adder. In this stage, all the carries for corresponding bits
Step 5: Calculate Result = (Nearest Base x S) - R
are exclusively generated similar to carry look ahead adder.
Furthermore, these generated carries are distributed into
2.ADDER ARCHITECTURES
smaller segments (Black cell and Grey cell) in order to carry
2.1. RIPPLE CARRY ADDER
out the entire process in parallel for all available bits of
Ripple carry adder is a conventional and basic adder circuit
input data. Moreover, carry generate and carry propagate
which designed using numerous basic single bit full adders
bits are generally used as transitional and intermediary
in order to perform addition of n-bit numbers. However,
data signals. The Boolean expressions for them are given
each individual unit of full adder accepts Cin as one of the
by the equation (3) (4) & (5).
inputs which is traditionally Cout of preceding adder unit.
Since, the carry bit from preceding adder unit is getting C.Black Cell
rippled to the next adder unit hence circuit is named as
ripple carry adder. This circuit is easy to design but the The black cell is going to take input as two distinct pair of
major drawback is propagation delay. This slowness is both propagate and generate signals obtained in
mainly due to waiting time during preceding carry to get preprocessing stage ( , ) and ( , ). This Black cell
rippled into next adder unit. A simple 4-bit ripple carry generates output as another pair of propagate and
adder is consisting of four single bit full adders. This is generate signals ( , ) which is given by equation (3) &
generally constructed using AOI (AND OR INVERT) logic. (4).
(3)
(4)
a)
D.Grey Cell:
b)
c) The grey cell is going to take input as two distinct pair of
d) both propagate and generate signals obtained in
e) preprocessing stage ( , P i ) and ( , ). This Grey cell
Fig.1 Ripple Carry Adder (RCA) generates output as generate signals (G) which is given by
equation (5).
2.2. Kogge Stone Adder (KSA) (5)
Kogge Stone adder is a type of parallel prefix version of E. Post Processing Stage
carry look ahead type of adder. This adder circuit is
broadly considered as one of the super fastest type of Post processing stage is the third and the last stage of Kogge Stone
adder. T his stage is generally regular for all types of adders
adder and is extensively utilized in real time application in
designed. T his calculation is given by equations (6) & (7).
order to design arithmetic circuits with enhanced
performance. However, the overall functionality of Kogge (6)
Stone adder can be straightforwardly realized with analysis
(7)
of its three individual building units namely pre-
processing, prefixand final computation.
A. Preprocessing Stage

Preprocessing stage is the very first stage of Kogge

Stone adder. This stage is going to provide both generate
and propagate signals for all the set of bit of the
corresponding input numbers A and B exclusively. The
Boolean expressions for both generate and propagate
signals are given by the equation (1) & (2).
(1)
(2)
 addition for two 4-bit operands which is achieved after
concatenation of 4- bit (Carry output of first adder unit and other two
as the most significant output sum result bits of second
adder) and another 4-bit operand is achieved as the result
of left hand most of first 4-bit adder one 4-bit operand we
get as the output sum of left hand most of 2x2 Vedic
multiplier unit. Depending on the types of adder used in
circuit; delay, power, area etc. types of performance
parameters can be optimized further.

Fig.2 Kogge Stone Adder (KSA)

3. Mux Based Full Adder (Mux-FA)

The traditional full adder in order to design an array
multiplier is substituted with a different type of full adder
which is designed using multiplexer (MUX) XOR gates.
Here, two XOR gates and one 2:1 MUX is used. This
design results in decrease of area and delays further. The
architecture of mux based full adder is shown in fig.3
Fig.4 4 x 4 Vedic Multiplier

IV. Implementation & results

In the proposed work, first 2x2 bit Vedic multiplier is
designed using both Urdhva Tiryakbhyam sutra and
Nikhilam sutra in Verilog-HDL coding language.
Furthermore, RTL level synthesis and simulation is
performed with extensive use of Xilinx EDA tool with
ISim simulator for Xilinx family of FPGA namely Virtex-4
Fig.3 Mux based Full Adder (Mux-FA)

4.4x4 Urdhva Vedic Multiplier TABLE I. COMPARISON OF VEDIC SUTRAS FOR

2X2 MULTIPLIER
Design 4x4 Vedic multiplier is done using 2x2 Vedic multiplier
units and 4-bit adders. Here, first the partial products are Vedic Sutra for No. of No. Delay Dynami Logic
generated using 2x2 multipliers and then subsequently 2x2 Slices of (nS) c Count
added further to obtain the final results. The general
architecture of 4x4 Vedic multiplier is shown in Fig.4. Here, Multiplier LUTs Power (Area)
total four 2x2 Vedic multipliers along with three 4-bit adder
(W)
units are used. The very first 4-bit Adder is used in order
to perform addition for two 4-bit operands which are Nikhilam 2 4 6.134 0.678 15
achieved after performing the cross multiplication for the
two middle 2x2 Vedic multiplier units. The second 4-bit Sutra
adder is used in order to perform additionfor two 4-bit
Urdhva 2 4 4.987 0.001 4
operands which is achieved after concatenation of 4-bit and the
other two as the most significant bits of right hand most of 2x2 Tiryagbhya
Vedic multiplier unit) and another 4-bit operand is achieved
as the result of first 4-bit adder. The output carry from this m Sutra
adder is further given as input to the third 4-bit adder unit.
Next, the third 4-bit adder unit is used in order to perform Table-I presents the comparative analysis for 2x2
 Vedic multiplier design using both sutras. From V.CONCLUSION
comparison results it is quite obvious that Urdhva sutra
based multiplier outperforms Nikhilam sutra based This paper has presented the implementation and design
multiplier. Hence in order to design higher order efficient of various arithmetic circuits based on Vedic
multipliers, Urdhva sutra based Vedic multiplier Mathematics. First, a 2x2 Vedic multiplier is designed
techniques are incorporated. using both Urdhva Tiryakbhyam sutra and Nikhilam
sutra. From comparative analysis, multiplier based on
Urdhva Tiryakbhyam sutra was found to be efficient in
terms of power and area. Furthermore, this 2x2 Vedic
multiplier based Urdhva Tiryakbhyam sutra is extended
to design 4x4 Vedic multiplier. However, three different
types of adders are used in design of 4x4 Vedic
multiplier namely Ripple Carry Adder, Kogge Stone
Adder and Multiplexer based Adder. From comparative
analysis, multiplier using multiplexer based full adder
was found to be proficient in terms of delay, speed and
Fig.5 Simulation results for 4x4 Vedic Multiplier using area. This reduction in delay and area leverages the
Multiplexer based Full Adder
researcher in order to design high speed and compact
SoC applications such as MAC units for DSP related
TABLE II. COMPARISON OF VARIOUS 4x4 VEDIC applications for further research work.
MULTIPLIERS
Type of No. of No. of Delay Dynami Total REFERENCES
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