Experiment

1 – LEDs and 7-Segment Display (Part 1)

A. Learning Outcomes
The table below shows the expected learning outcomes for this activity:

CILO Description
SO1.1 Identify applicable methods and techniques in designing sequential circuits and fundamental
principles of a microcomputer systems.
SO1.5 Formulate methods and solutions using appropriate knowledge in electronics engineering to
design sequential circuits
SO6.2 Analyze and interpret experimental data and results to develop generalizations or
conclusions
SO6.4 Design appropriate experimental procedures or tests, algorithms, methods, and/or process
flow to acquire necessary data for the microprocessor system design.

B. Sample Code
// This code lets the green LEDs blink for every 0.5 seconds where the LEDs are on for a
// half second and off for the next half second.

1 module activity (clk, rst, ledg);

2
3 input clk, rst;
4 output [7:0] ledg;
5
6 reg [7:0] state;
7 reg [24:0] counter;
8
9 assign ledg = state;
10
11 always @ (posedge clk)
12 if (rst == 0)
13 counter <= 0;
14 else if (counter == 25_000_000)
15 counter <= 0;
16 else
17 counter <= counter+1;
18
19 always @ (posedge clk)
20 if (rst == 0)
21 state <= 8’b00000000;
22 else if (counter == 25_000_000)
23 state <= ~state;
24 endmodule

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Verilog Code Descriptions

Line No. Descriptions

1 Words in blue are reserved words. Any Verilog program starts with the
reserved word module <module_name>. In this example, the module is
named activity. After declaring the module name, the port declaration
follows and are enclosed in parenthesis. For this module, it has the following
ports: clk, rst, ledg.
3 Declaration of scalar input ports (clk, rst)
4 Declaration of an 8-bit output port (ledg)
6-7 Declaration of an 8-bit register state and 25-bit register named counter
9 The value of register state is continuously assigned to the output port
ledg. Take note that in using assign statement, the left-hand side should
always be a port.
11-17 This block is executed for every positive edge of the clock. First, it checks
whether rst is 0 or KEY0 is pushed down. If yes, counter is set to 0, if not, the
value of counter is checked. If the condition is satisfied that is, if counter is
equal to 25,000,000, then, counter is set to 0. If not, counter is
incremented. Thus, this block basically increments/counts a value from 1 to
25,000,000 stored at counter register.
Note:
For simulation purposes, we will scale down the counter to 5 or 10.
19-23 This block is also executed for every positive edge of the clock. First, it checks
whether rst is 0 or KEY0 is pushed down. If yes, all the bits of state have the
value of 0, as a result, all the 8 LEDs are turned off. If not, the value of counter
is checked. If the condition is satisfied that is, if counter is equal to 25,000,000,
state[0] or the least significant bit (LSB) of state is set to the complement of
the previous value of state[0]. As a result, the value of state changes every 0.5
second and the green LEDs light up for 0.5 seconds and then, it is turned off
for 0.5 second.
Note: Why 25,000,000? The frequency of the oscillator is 50MHz which
represents 50,000,000 cycles per second. If each transition should only take
0.5 second, then, the counter should be set at 50,000,000/2 or 25,000,000
before the next transition.
24 It is a reserved word that signifies the end of the Verilog module.

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C. Pin Assignment
In the sample code, the pin assignment is given below (TCL Script).
Note that for simulation purposes, there is no need to create a TCL Script.

1 set_location_assignment PIN_L1 –to clk

2 set_location_assignment PIN_R22 –to rst
3 set_location_assignment PIN_U22 –to ledg[0]
4 set_location_assignment PIN_U21 –to ledg[1]
5 set_location_assignment PIN_V22 –to ledg[2]
6 set_location_assignment PIN_V21 –to ledg[3]
7 set_location_assignment PIN_W22 –to ledg[4]
8 set_location_assignment PIN_W21 –to ledg[5]
9 set_location_assignment PIN_Y22 –to ledg[6]
10 set_location_assignment PIN_Y21 –to ledg[7]

D. Simulation using ModelSim

1. Modify the “counter” value in the given Verilog code. Set your “counter” value to 5.

2. Add a new University Program VWF

3. Import all the input and output ports (clk, ledg, rst).
4. Use the following settings:
a. End time: 1 microsecond
b. Grid size: 10 nanoseconds
c. Port ‘clk’ value: “OverwriteClock” with period of 20ns, o0 offset, 50% duty cycle
d. Port ‘rst’ value: “Forcing High (1)”

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 5. Run the simulation and check the results.

5 clock cycles

OFF ON OFF ON

E. Instructions

1. Create a new project in Quartus IDE and save it to the working directory.
2. Create a new Verilog HDL file and save it as experiment1A.v.
3. Design a Verilog code such that the delay in change of LED pattern is controlled by switch
SW1. When SW1 set to low logic level, the pattern interval is every 2 clock cycles. When
SW1 set to high logic level, the pattern interval is every 5 clock cycles. The LED pattern is
shown below:

SW2 Pattern Interval

0 Every 2 clock cycles
1 Every 5 clock cycles

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 4. Create a simulation waveform (vwf file) with the given setting below. Set the end time to
1us and grid size to 20ns. Adjust the output display to Hexadecimal if the binary display is
truncated.
a. Waveform 1:
• Clock period is set at 20ns, 50% duty cycle
• SW1 is at low logic level
• Reset is at high logic level
b. Waveform 2:
• Clock period is set at 20ns, 50% duty cycle
• SW1 is at high logic level
• Reset is at high logic level
c. Waveform 3:
• Clock period is set at 20ns, 50% duty cycle
• SW1: Overwrite Clock with 400ns period, 50% duty cycle
• Reset: Random, every fixed intervals (200ns)
d. Waveform 4:
• Clock period is set at 20ns, 50% duty cycle
• SW1: Overwrite Clock with 500ns period, 50% duty cycle
• Reset is at high logic level

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 Experiment 1 – LEDs and 7-Segment Display (Part 2)

A. Learning Outcomes
The table below shows the expected learning outcomes for this activity:

CILO Description
SO1.1 Identify applicable methods and techniques in designing sequential circuits and fundamental
principles of a microcomputer systems.
SO1.5 Formulate methods and solutions using appropriate knowledge in electronics engineering to
design sequential circuits
SO6.2 Analyze and interpret experimental data and results to develop generalizations or
conclusions
SO6.4 Design appropriate experimental procedures or tests, algorithms, methods, and/or process
flow to acquire necessary data for the microprocessor system design.

B. Sample Code
// This code outputs the counting of numbers from 0 to 9 at half second interval in
// the digital display of the Altera D1SK.

1 module activity (clk, rst, hex0, hex1, hex2, hex3);

2
3 input clk, rst;
4 output [6:0] hex0, hex1, hex2, hex3;
5
6 reg [24:0] counter;
7 reg [6:0] display0;
8
9 assign hex0 = display0;
10 assign hex1 = 7’b1111111;
11 assign hex2 = 7’b1111111;
12 assign hex3 = 7’b1111111;
13
14 parameter num1 = 7'b1001111;
15 parameter num2 = 7'b0010010;
16 parameter num3 = 7'b0000110;
17 parameter num4 = 7'b1001100;
18 parameter num5 = 7'b0100100;
19 parameter num6 = 7'b0100000;
20 parameter num7 = 7'b0001111;
21 parameter num8 = 7'b0000000;
22 parameter num9 = 7'b0000100;
23 parameter num0 = 7'b0000001;
24
25 always @ (posedge clk)
26 if (rst == 0)

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 27 counter <= 0;
28 else if (counter == 25_000_000) //change to 5
29 counter <= 0;
30 else
31 counter <= counter+1;
32
33 always @ (posedge clk)
34 if (rst == 0)
35 display0 <= num0;
36 else if (counter == 25_000_000) //change to 5
37 case (display0)
38 num0: display0 <= num1;
39 num1: display0 <= num2;
40 num2: display0 <= num3;
41 num3: display0 <= num4;
42 num4: display0 <= num5;
43 num5: display0 <= num6;
44 num6: display0 <= num7;
45 num7: display0 <= num8;
46 num8: display0 <= num9;
47 num9: display0 <= num0;
48 default: display0 <= num0;
49 endcase
50 endmodule

Verilog Code Descriptions

Line No. Descriptions

1 Words in blue are reserved words. Any Verilog program starts with the
reserved word module <module_name>. In this example, the module
is named activity. After declaring the module name, the port
declaration follows and are enclosed in parenthesis. For this module, the
ports to be used are named as clk, rst, hex0, hex1, hex2, and hex3.
3 Declaration of input ports (clk, rst)
4 Declaration of a 7-bit output port (hex0, hex1, hex2, and hex3)
6-7 Declaration of 25-bit register named counter (for pattern/display
interval) and 7-bit registers named display0, display1, display2,
display3
9 Assigns the values of the register display0 to hex0

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 10-12 Assigns a 1 value to hex1-hex3; assigning a high logic level to hex1-
hex3 means that all segment LEDs will be turned off. Note that the
segment LEDs in the D1SK are low-enabled.
14-23 Set constant values to parameter num0 to num9 to easily assign numbers
0 to 9 on the 7-segment displays on the latter part of the Verilog code.

25-31 This block is executed for every positive edge of the clock. First, it checks
whether rst is 0 or key0 is pushed down. If yes, counter is set to low.
If not, the value of the counter is incremented until it reached the
count of 25,000,000.
33-49 This block is also executed for every positive edge of the clock. First, it
checks whether rst is at low state or key0 is pushed down. If yes, the
number “0” is displayed on the 7-segment display. If not, the value of
counter is checked. If the condition is satisfied, that is, if counter is
equal to 25,000,000, a case statement follows wherein the value of
number is checked and a new value of number is assigned, which is
displayed in the active 7-segment LED.
50 It is a reserved word that signifies the end of the Verilog module.

C. Pin Assignment
The assignment of the segments a, b, c, d, e, f, and g will depend on your declaration of
your pin assignments in the TCL script. You can assign the most significant bit (MSB) to
segment ‘a’ and the least significant bit (LSB) to segment ‘g’ or vice versa. In the sample code,
the pin assignment is given below. Note that for simulation purposes, there is no need to
create a TCL Script.

1 set_location_assignment PIN_L1 –to clk

2 set_location_assignment PIN_R22 –to rst
3
4 set_location_assignment PIN_E2 –to hex0[0]
5 set_location_assignment PIN_F1 –to hex0[1]
6 set_location_assignment PIN_F2 –to hex0[2]
7 set_location_assignment PIN_H1 –to hex0[3]
8 set_location_assignment PIN_H2 –to hex0[4]
9 set_location_assignment PIN_J1 –to hex0[5]
10 set_location_assignment PIN_J2 –to hex0[6]

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 11 set_location_assignment PIN_D1 –to hex1[0]
12 set_location_assignment PIN_D2 –to hex1[1]
13 set_location_assignment PIN_G3 –to hex1[2]
14 set_location_assignment PIN_H4 –to hex1[3]
15 set_location_assignment PIN_H5 –to hex1[4]
16 set_location_assignment PIN_H6 –to hex1[5]
17 set_location_assignment PIN_E1 –to hex1[6]

**Repeat the same procedure for declaring pin assignments for 7-segment displays hex2 and
hex3.

D. Simulation using ModelSim

1. Modify the “counter” value in the given Verilog code. Set your “counter” value to 5.
2. Add a new University Program VWF.
3. Import all the input and output ports (clk, rst, hex0, hex1, hex2, hex3).
4. Use the following settings:
a. End time: 1000 ns or 1 us
b. Grid size: 10ns
c. Port ‘clk’ value: to “OverwriteClock with period of 10ns, duty cycle 50%”
d. Port ‘rst’ to “Forcing High”
e. Change the radix to Hexadecimal if the binary display is truncated.
5. Run the simulation and check the results.

counting sequence from 0 to 9

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E. Instructions

1. Create a new project in Quartus IDE and save it to the working directory.
2. Create a new Verilog HDL file and save it as experiment1B.v.
3. Design a Verilog code such that it will display the number pattern in HEX0 and HEX1.
Pattern display interval is every 3 clock cycles and returns in a loop:

05 à 10 à 15 à 20

4. Create a simulation waveform (vwf file) with the given setting below. Set the end time to
1us and grid size to 20us. Display the output ports Hex0, Hex1.
a. Waveform 1:
• Clock period is set at 10us, 50% duty cycle
• Reset is at high logic level
b. Waveform 2:
• Clock period is set at 10us, 50% duty cycle
• Reset: Random, every fixed intervals at 200ns

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