High Speed Super Low Power SRAM

512k Word By 16 bit CS16LV81923

Revision History

Rev. No. History Issue Date

2.0 Initial issue with new naming rule Feb.15, 2005
2.1 Add 48CSP-6x8mm package outline Mar. 08, 2005
2.2 Revise 48CSP-8x10mm pkg code from W to K Oct. 25, 2005
2.3 Revised DC characteristics Nov. 23, 2006
2.4 Revised DC characteristics Jun. 20,2007
2.5 Change wafer process from 0.18um to 0.15um May. 19, 2008
2.6 Add CE2 description of 48BGA package Nov. 20, 2009
2.7 Modify Data Retention waveform May. 27.2010

1 Rev. 2.7
Chiplus reserves the right to change product or specification without notice.
 High Speed Super Low Power SRAM
512k Word By 16 bit CS16LV81923

PRODUCT DESCRIPTION
The CS16LV81923 is a high performance, high speed, low power CMOS Static Random
Access Memory organized as 524,288 words by 16 bits and operates from a wide range of 2.7 to
3.6V supply voltage. Advanced 0.15um CMOS technology and circuit techniques provide both high
speed and low power features with a Typical CMOS standby current of 0.3uA and maximum access
time of 55/70ns in 3.0V operation. Easy memory expansion is provided by an active LOW chip
enable1 (/CE), active HIGH chip enable2 (CE2) for BGA product and active LOW output enable
(/OE) and three-state output drivers.
The CS16LV81923 has an automatic power down feature, reducing the power consumption
significantly when chip is deselected. The CS16LV81923 is available in JEDEC standard 44L TSOP
2 and 48Ball Mini_BGA 8x10mm packages.

FEATURES

Low operation voltage: 2.7 ~ 3.6V

Ultra low power consumption:
Vcc = 3.0V: 25mA (Typ.) operating current, 0.3uA (Typ.) CMOS standby current

High speed access time: 55/70ns (Max.) at Vcc = 3.0V.

Automatic power down when chip is deselected.

Three state outputs and TTL compatible.

Data retention supply voltage as low as 1.5V.

Easy expansion with /CE&CE2 and /OE options.

PRODUCT FAMILY
Standby
Operating
Product Family Vcc. Range Speed (ns) Current Package Type
Temp
(Typ.)

0.3 uA
0 ~ 70oC
(VCC = 3.0V)
44 TSOP 2-400mil
CS16LV81923 2.7 ~ 3.6 55/70
48 Mini_BGA 8x10mm
0.3 uA
-40 ~ 85oC
(VCC= 3.0V)

2 Rev. 2.7
Chiplus reserves the right to change product or specification without notice.
 High Speed Super Low Power SRAM
512k Word By 16 bit CS16LV81923

PIN CONFIGURATIONS

■ FUNCTIONAL BLOCK DIAGRAM

For single CE product of 44 TSOP 2-400mil

3 Rev. 2.7
Chiplus reserves the right to change product or specification without notice.
 High Speed Super Low Power SRAM
512k Word By 16 bit CS16LV81923

For dual CE product of 48 Mini_BGA 8x10mm

PIN DESCRIPTIONS
Name Type Function
A0 ~ A18 Input 19 address inputs for selecting one of the 524,288 x 16 bit words in the RAM
/CE1 is active LOW and CE2 is active high. Chip enable must be active when
/CE data read from or write to the device. If chip enable is not active, the device is
Input
/CE1 & CE2 deselected and in a standby power mode. The DQ pins will be in high
impedance state when the device is deselected.
The Write enable input is active LOW. It controls read and write operations.
With the chip selected, when /WE is HIGH and /OE is LOW, output data will be
/WE Input
present on the DQ pins, when /WE is LOW, the data present on the DQ pins
will be written into the selected memory location.
The output enable input is active LOW. If the output enable is active while the
chip is selected and the write enable is inactive, data will be present on the DQ
/OE Input
pins and they will be enabled. The DQ pins will be in the high impedance state
when /OE is inactive.
/LB and /UB Input Lower byte and upper byte data input/output control pins.
These 16 bi-directional ports are used to read data from or write data into the
DQ0~DQ15 I/O
RAM.
Vcc Power Power Supply
Vss Power Ground

4 Rev. 2.7
Chiplus reserves the right to change product or specification without notice.
 High Speed Super Low Power SRAM
512k Word By 16 bit CS16LV81923

TRUTH TABLE
(1) (2) (2)
MODE /CE /CE1 CE2 /WE /OE /LB /UB DQ0~7 DQ8~15 Vcc Current

Fully H H X X X X X High Z High Z ICCSB, ICCSB1

Standby X X L X X X X High Z High Z ICCSB, ICCSB1

Output
L L H H H X X High Z High Z ICC
Disabled

L L DOUT DOUT ICC

Read L L H H L H L High Z DOUT ICC

L H DOUT High Z ICC

L L DIN DIN ICC

Write L L H L X H L High Z DIN ICC

L H DIN High-Z ICC

Note: (1) /CE is used for 44 TSOP 2-400mil of single CE product only.

(2) /CE1 and CE2 are used for 48 Mini_BGA 8x10mm dual CE product only.

(1)

ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Rating Unit

VTERM Terminal Voltage with Respect to GND -0.2 to Vcc+0.5 V

O
TBIAS Temperature Under Bias -40 to +125 C
O
TSTG Storage Temperature -60 to +150 C

PT Power Dissipation 1.0 W

IOUT DC Output Current 35 mA

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage

to the device. This is a stress rating only and functional operation of the device at these or any other

conditions above those indicated in the operational sections of this specification is not implied. Exposure

to absolute maximum rating conditions for extended periods may affect reliability.

5 Rev. 2.7
Chiplus reserves the right to change product or specification without notice.
 High Speed Super Low Power SRAM
512k Word By 16 bit CS16LV81923
o
 DC ELECTRICAL CHARACTERISTICS (TA = 0~+70 C / -400C~+850C ,VCC = 3.0V)
Parameter (1)
Parameter Test Conduction MIN TYP MAX Unit
Name

Guaranteed Input Low (2)

VIL (2) -0.2 0.6 V
Voltage
Guaranteed Input High (2)
VIH (2) 2.2 Vcc+0.2 V
Voltage
IIL Input Leakage Current VCC=MAX, VIN=0 to VCC -1 1 uA
VCC=MAX, /CE=VIH, or
IOL Output Leakage Current -1 1 uA
/OE=VIH , VIO=0V to VCC
VOL Output Low Voltage VCC=MAX, IOL = 2 mA 0.4 V
VOH Output High Voltage VCC=MIN, IOH = -1mA 2.4 V
Operating Power Supply /CE=VIL, IDQ=0mA,
ICC (3) 25 35 mA
Current F=FMAX
ICCSB Standby Supply -TTL /CE=VIH, IDQ=0mA, 0.5 mA
/CE≧VCC-0.2V,
ICCSB1 Standby Current-CMOS VIN≧ VCC-0.2V or 0.3 6 uA
VIN≦0.2V
o
1. Typical characteristics are at TA = 25 C.
2. Overshoot: Vcc+2.0V in case of pulse width≦20ns. Undershoot: -2.0V in case of pulse width≦20ns.
Overshoot and undershoot are sampled, not 100% tested.
3. Fmax = 1/tRC.

OPERATING RANGE
Range Ambient Temperature VCC
o
Commercial 0~70 C 2.7V ~ 3.6V
o
Industrial -40~85 C 2.7V ~ 3.6V

CAPACITANCE (1) (TA = 25oC, f =1.0 MHz)

Symbol Parameter Conditions MAX. Unit
CIN Input Capacitance VIN=0V 8 pF
CDQ Input/Output Capacitance VI/O=0V 10 pF
1. This parameter is guaranteed and not 100% tested.

6 Rev. 2.7
Chiplus reserves the right to change product or specification without notice.
 High Speed Super Low Power SRAM
512k Word By 16 bit CS16LV81923
o

DATA RETENTION CHARACTERISTICS ( TA = 0~+70 C / -400C~+850C )
Parameter
(1)
Parameter Test Conduction MIN TYP MAX Unit
Name

/CE≧VCC-0.2V, VIN≧VCC-0.2V
VDR VCC for Data Retention 1.5 V
or VIN≦0.2V

/CE≧VCC-0.2V, VCC=1.5V
ICCDR Data Retention Current 0.1 3 uA
VIN≧ VCC-0.2V or VIN≦0.2V

Chip Deselect to Data

tSDR 0 ns
Retention Time
See Retention Waveform
Operation Recovery
(2)
tRDR tRC ns
Time
o
1. VCC= 3.0V, TA = +25 C
(2)
2. tRC = Read Cycle Time.

LOW VCC DATA RETENTION WAVEFORM (1) ( /CE1 or /CE Controlled )

7 Rev. 2.7
Chiplus reserves the right to change product or specification without notice.
 High Speed Super Low Power SRAM
512k Word By 16 bit CS16LV81923

LOW VCC DATA RETENTION WAVEFORM (2) ( CE2 Controlled-BGA only )

KEY TO SWITCHING WAVEFORMS

WAVEFORMS INPUTS OUTPUTS

MUST BE STEADY MUST BE STEADY

MAY CHANGE FROM H TO L WILL BE CHANGE FROM H TO L

MAY CHANGE FROM L TO H WILL BE CHANGE FROM L TO H

DON’T CARE ANY CHANGE CHANGE STATE UNKNOWN

PERMITTED

DOES NOT APPLY CENTER LINE IS HIGH IMPEDANCE OFF STATE

AC TEST LOADS

8 Rev. 2.7
Chiplus reserves the right to change product or specification without notice.
 High Speed Super Low Power SRAM
512k Word By 16 bit CS16LV81923
o

AC ELECTRICAL CHARACTERISTICS( TA = 0~+70 C / -400C~+850C , Vcc = 3.0V )
< READ CYCLE >

JEDEC Parameter 55 70
Description Unit
Name Name MIN MAX MIN MAX

tAVAX tRC Read Cycle Time 55 70 ns

tAVQV tAA Address Access Time 55 70 ns

tELQV tCO Chip Select Access Time (/CE) 55 70 ns

tBA tBA Data Byte Control Access Time (/LB, /UB) 55 70 ns

tGLQV tOE Output Enable to Output Valid 30 35 ns

tELQX tLZ Chip Select to Output Low Z (/CE) 5 5 ns

tBE tBLZ Data Byte Control to Output Low Z (/LB, /UB) 10 10 ns

tGLQX tOLZ Output Enable to Output in Low Z 5 5 ns

tEHQZ tHZ Chip Deselect to Output in High Z (/CE) 0 20 0 20 ns

tBDO tBHZ Data Byte Control to Output High Z (/LB, /UB) 0 20 0 20 ns

tGHQZ tOHZ Output Disable to Output in High Z 0 20 0 20 ns

tAXOX tOH Out Disable to Address Change 10 10 ns

SWITCHING WAVEFORMS (READ CYCLE)

For single CE product of 44 TSOP 2- 400mil

9 Rev. 2.7
Chiplus reserves the right to change product or specification without notice.
 High Speed Super Low Power SRAM
512k Word By 16 bit CS16LV81923

NOTES:
1. tHZ and tOHZ are defined as the outputs achieve the open circuit conditions and are not referenced to
output voltage levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device
and from device to device interconnection.

For dual CE product of 48 Mini_BGA 8x10mm

10 Rev. 2.7
Chiplus reserves the right to change product or specification without notice.
 High Speed Super Low Power SRAM
512k Word By 16 bit CS16LV81923

NOTES:
1. tHZ and tOHZ are defined as the outputs achieve the open circuit conditions and are not referenced to output
voltage levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and
from device to device interconnection.

11 Rev. 2.7
Chiplus reserves the right to change product or specification without notice.
 High Speed Super Low Power SRAM
512k Word By 16 bit CS16LV81923
o

AC ELECTRICAL CHARACTERISTICS ( TA = 0~+70 C / -400C~+850C , Vcc = 3.0V )
< WRITE CYCLE >

JEDEC Parameter Description 55 70 Unit

Name Name MIN MAX MIN MAX

tAVAX tWC Write Cycle Time 55 70 ns

tE1LWH tCW Chip Select to End of Write 45 60 ns

tAVWL tAS Address Setup Time 0 0 ns

tAVWH tAW Address Valid to End of Write 45 60 ns

tWLWH tWP Write Pulse Width 45 55 ns

tWHAX tWR Write Recovery Time (/CE, /WE) 0 0 ns

tBW tBW Data Byte Control to End of Write(/LB, /UB) 55 70 ns

tWLQZ tWHZ Write to Output in High Z 0 20 0 20 ns

tDVWH tDW Data to Write Time Overlap 30 30 ns

tWHDX tDH Data Hold from Write Time 0 0 ns

tWHOX tOW End of Write to Output Active 5 5 ns

12 Rev. 2.7
Chiplus reserves the right to change product or specification without notice.
 High Speed Super Low Power SRAM
512k Word By 16 bit CS16LV81923
 SWITCHING WAVEFORMS (WRITE CYCLE)
For single CE product of 44 TSOP 2- 400mil

13 Rev. 2.7
Chiplus reserves the right to change product or specification without notice.
 High Speed Super Low Power SRAM
512k Word By 16 bit CS16LV81923

NOTES:
1. A write occurs during the overlap(tWP) of low /CE and low /WE. A write begins when /CE goes low and
/WE goes low with asserting /UB and /LB for double byte operation. A write ends at the earliest transition
when /CE goes high and /WE goes high. The tWP is measured from the beginning of the write to the end
of write.
2. tCW is measured from the /CE going low to end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end or write to the address change. TWR applied in case a write ends as /CE or
/WE going high.

14 Rev. 2.7
Chiplus reserves the right to change product or specification without notice.
 High Speed Super Low Power SRAM
512k Word By 16 bit CS16LV81923
For dual CE product of 48 Mini_BGA 8x10mm

15 Rev. 2.7
Chiplus reserves the right to change product or specification without notice.
 High Speed Super Low Power SRAM
512k Word By 16 bit CS16LV81923

NOTES:
1. A write occurs during the overlap(tWP) of low /CE1, high CE2and low /WE. A write begins when /CE1 goes
low, CE2 goes high and /WE goes low with asserting /UB and /LB for double byte operation. A write ends at
the earliest transition when /CE1 goes high, CE2 goes low and /WE goes high. The tWP is measured from
the beginning of the write to the end of write.
2. tCW is measured from the /CE1 going low or CE2 going high to end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end or write to the address change. TWR applied in case a write ends as /CE1
going high, CE2 going low or /WE going high.

16 Rev. 2.7
Chiplus reserves the right to change product or specification without notice.
 High Speed Super Low Power SRAM
512k Word By 16 bit CS16LV81923

ORDER INFORMATION

Note: Package material code “P” & “R” comply with RoHS.

17 Rev. 2.7
Chiplus reserves the right to change product or specification without notice.