EECS 16B Designing Information Devices and Systems II

Fall 2018 Elad Alon and Miki Lustig Homework 2

This homework is due on Wednesday, September 12, 2018, at 11:59 PM.
Self-grades are due on Monday, September 17, 2018, at 11:59 PM.

1. Complex Numbers (Mechanical)

A common way to visualize complex numbers is to use the complex plane. Recall that a complex number z
is often represented in Cartesian form.

z = x + jy with Re{z} = x and Im{z} = y

See the Figure 1 for how z looks like in the complex plane.

Im{z}

y z
r

θ x
Re{z}

Figure 1: Complex Plane

In this question, we will derive the polar form of a complex number and use this form to make some
interesting conclusions.

(a) Calculate the length of z in terms of x and y as shown in Figure 1. This is the magnitude of a complex
number and is denoted |z| or r. Hint. Use the Pythagoras theorem.

EECS 16B, Fall 2018, Homework 2 1

 Solution:
p
r= x2 + y2 = |z|

(b) Represent the real and imaginary parts of z in terms of r and θ .

Solution:

x = r cos(θ ) and y = r sin(θ )

(c) Euler’s formula relates an imaginary exponential function to a combination of sines and cosines:

e jθ = cos(θ ) + j sin(θ )

In future lectures, we’ll see the importance of this relationship and why it’s useful.
Use Euler’s formula and your answer to part (b) to show that:

z = re jθ

Solution:

z = r cos(θ ) + jr sin(θ )
= r(cos(θ ) + j sin(θ ))
= re jθ

(d) If z = re jθ , prove that z∗ = re− jθ . Recall that the complex conjugate of a complex number z = x + jy
is z∗ = x − jy.
Solution:

z∗ = (r(cos(θ ) + j sin(θ )))∗

= r(cos(θ ) − j sin(θ ))
= r(cos(−θ ) + j sin(−θ ))
= re− jθ

(e) If we have a complex number

z = x + jy = re jθ
then we define the complex conjugate of z as

z∗ = x − jy = re− jθ

Show that
r2 = zz∗

Solution:

zz∗ = re jθ re− jθ = r2 e jθ − jθ = r2 e0 = r2

EECS 16B, Fall 2018, Homework 2 2

2. RLC Circuit (Mechanical)
Consider the circuit shown below. For t ≤ 0, switch S1 is off (disconnected) while switch S2 is on (con-
nected). At t = 0, S1 turns on while S2 turns off.

t =0 Rs
S1
is +

Vs + S2 t =0 C Vout L
−
iC − iL

(a) Immediately before the switches flip states at t = 0, find the initial conditions for the inductor and
capacitor: iL (0) and Vc (0). Assume the circuit has reached DC steady state (voltages and currents are
constant) before the switches flip states.
Solution:
Before the switches flip states, the circuit looks like:

Rs u1

C Vout L

iC − iL

Since the capacitor and inductor are in parallel,

Vc (t) = VL (t)

We know that for an inductor,

diL (t)
VL (t) = L
dt
Because the circuit is in steady state, all the currents and voltages are constant, which means
diL (0)
=0
dt
Thus:
Vc (0) = VL (0) = 0
To find iL (0), we apply KCL at u1 :

u1 (0) dVc (0)

+C + iL (0) = 0
Rs dt
u1 (0) = Vc (0) = 0

EECS 16B, Fall 2018, Homework 2 3

 Since the circuit is in steady state, all voltage and current derivatives are 0, so
dVc (0)
0 =0
dt
Plugging these back into our KCL equation, we get

0 + 0 + iL (0) = 0

iL (0) = 0
This gives us the initial conditions:
Vc (0) = 0
iL (0) = 0

(b) Define your state variables as Vout (t) and iL (t), and use nodal analysis to derive the homogenous vector
differential equation ( d~
x
dt = A~
x + b) that captures the behaviour of the ciruit at t = 0 (after the switch
flips).
Solution: After the switches flip states, the circuit looks like:

Rs u1

is +

Vs + C Vout L
−
iC − iL

Doing KCL at u1 :
is = iC + iL
Using iC = C dVdtout and Ohm’s law:

Vs −Vout dVout
=C + iL
Rs dt
dVout Vs Vout iL
= − −
dt RsC RsC C
We also know that Vout = L didtL . These two equations give us a nonhomogeneous differential equation.
We can actually turn iL into an auxilary variable using iL = i0 + VRs , which turns the first equation into

Vout i0 dVout
− − =
RsC C dt
We can then turn this into a vector differential equation
" # " #" #
dVout 1 1
dt
− Rs C − C Vout
di0 = 1 0
dt L 0 i

EECS 16B, Fall 2018, Homework 2 4

 (c) Solve the vector differential equation to find Vout (t). Use Vs = 6V, Rs = 1kΩ, C = 1fF, and L = 6.25nH.
Solution: Plugging in values for Vs , R,C, L give us the vector differential equation
" # " #" #
dVout 1 1
dt − 103 ∗10−15
− 10−15 Vout
di0 = 1 0
dt 6.25∗10 −12 0 i

We can find the eigenvalues of the A matrix.

" #
−10 12 −10 15
det   = 0 = λ 2 + 101 2λ + 1.6 ∗ 102 3
1.6 ∗ 108 0

λ = −2 ∗ 1011 , −8 ∗ 1011

We have 2 distinct λ values, so the general form of the solution is:

Vout (t) = c1 eλ1t + c2 eλ2t

dVout (0)
In order to solve for c1 and c2 , we need initial conditions for Vout (0) and dt . In part (a), we saw:

Vout (0) = 0

before the switches flipped states. We also know that it must be the initial condition immediately after
the switches flip states because of the relationship:
dVc (t)
ic (t) = C
dt
if Vout changed instantaneously at t = 0, then there would be an infinite current through the capacitor,
which is not possible. This means we can say that immediately after the switch flips states,

Vout (0) = 0

This gives us the first relationship between c1 and c2 :

0 = c1 + c2 (1)
dVout
We can get an initial condition for dt by looking at the current through the capacitor since:

dVc (0)
ic (0) = C
dt
Doing KCL at u1 , we get:
ic (0) + iL (0) = is (0)
For the same reason why Vc (0) = 0, we know iL (0) = 0, since the voltage across the inductor depends
L (t)
on didt , so iL (t) cannot change instantaneously. This means:

Vs −Vout (0) Vs
ic (0) = is (0) = =
Rs Rs
dVout
Relating ic back to dt :
dVout (0) Vs
C =
dt Rs

EECS 16B, Fall 2018, Homework 2 5

 dVout (0) Vs
=
dt CRs
Vs
By taking the derivative of c1 eλ1t + c2 eλ2t , plugging in t − 0, and setting equal to CRs , we get the 2nd
equation relating c1 and c2 :
Vs
λ1 c1 + λ2 c2 = (2)
CRs
Equations (1) and (2) gives us a system of equations with two unknowns. Solving the system of
equations gives us:
Vs
c1 = −
RSC(λ2 − λ1 )
Vs
c2 =
RSC(λ2 − λ1 )
Plugging in component values:
6
c1 = − = −10
103 × 10−15 × (−2 + 8)1011

6
c2 = = 10
103 × 10−15 × (−2 + 8)1011
This gives us:
11 t 11 t
Vout (t) = −10e−8×10 + 10e−2×10

EECS 16B, Fall 2018, Homework 2 6

3. DRAM: How Big Can We Make Them?
Nearly all devices that include some form of computational capability (phones, tablets, gaming consoles,
laptops, ...) use a type of memory known as Dynamic Random Access Memory (DRAM). DRAM is where
the “working set” of instructions and data for a processor is typically stored, and the ability to pack an
ever increasing number of bits on to a DRAM chip at low cost has been critical to the continued growth in
computational capability of our systems. For example, a single DRAM chip today can store > 8 billion bits
and is sold for ≈ $3-$5.
At the most basic level, every bit of information that a DRAM can store is associated with a capacitor.
The amount of charge stored on that capacitor (and correspondingly, the voltage across the capacitor) sets
whether a “1” or a “0” is stored in that location. In order to pack as many bits together as possible on
to a single chip, rather than running a massive number of wires to access every single bit of the DRAM
individually, the bits are arranged into a set of columns, where each column uses a single wire to access
information from one of the bits. By turning ON the access switch within the particular bit cell via the
single column wire, the corresponding bit is accessed (while leaving all of the switches in the rest of the
cells off).
In this problem we’ll take a look at how long we can make the DRAM columns and still get the device to
work at a reasonable speed. For the purpose of this problem we’ll mostly ignore details of how the DRAM
actually works (and that making the column too long might actually stop the device from functioning at all)
and just focus on the delay introduced by the column wire due to its resistance and its capacitance.
The column wire and its adjacent ground wire are arranged as follows.

Each DRAM cell that gets added adds a length of 0.5µm (i.e., 0.5 · 10−6 m) to the column and ground
wires, the spacing between the column and ground wires is S = 0.1µm, and the wires have dimensions
Hwire = Wwire = 0.5µm. Note that you can assume that the two wires are separated by air; in a real chip
they would be separated by silicon dioxide, but we’ll ignore that for this exercise. You should also assume
that all of the capacitance is purely parallel plate. Furthermore, you can assume that the wire is made out of
copper, with a resistivity ρ = 1.68 × 10−8 Ω·m.

(a) As a function of the number of cells on the column Ncells , what is the total capacitance of the column
wire?

EECS 16B, Fall 2018, Homework 2 7

 Solution: From EE16A, we know that the equation for capacitance of parallel plate is
ε0 A
C=
d
Here, ε0 is the permittivity of free space (about 8.854 × 10−12 m F
), A is the area of the parallel plate
capacitor, and d is the separation distance between the two plates. Using the variables as defined in the
problem (Lcell = 0.5µm, which is the length of wire per cell),

ε0 Hwire Lcell
C=
S
By increasing the number of cells, we are just increasing the area of the parallel plate capacitor by the
specified amount, which is equivalent to having the capacitors connected in parallel.
ε0 Hwire Lcell
Ctot = Ncells = 2.21 × 10−17 F × Ncells
S

(b) As a function of the number of cells on the column Ncells , what is the total resistance of the column
wire?
Solution: From EE16A, we know the equation for resistance of a wire:
ρL
R=
A
In this equation, ρ is the resistivity of the material, L is the length of the wire, and A is the cross
sectional area of the wire. Using the variables defined in the problem:
ρLcell
R=
HwireWwire

The resistors that form each cell are in series here (this can be seen by the fact that they are clearly
connected end to end within each ground and column wire). Thus we get
ρLcell
R = Ncells = Ncells × (3.36 × 10−2 )Ω
HwireWwire

(c) Assuming that we can model the column wire and the top DRAM cell as below (note that this is not
a truly accurate model, but it gives the right form for the answer), what will be the delay between
information from the top of the DRAM column arriving to the bottom of the DRAM column (i.e., the
delay between Vcell and Vbottom ) as a function of Ncells ? We define the delay to be the length of time it
takes for the output value to reach 1/2 of it’s final value. Note that Vbottom (0) = 0V

Rcol,tot
+

Vcell + Ccol,tot Vbottom

−
−

EECS 16B, Fall 2018, Homework 2 8

 Solution: In this case, it is defined as the time it takes for Vbottom = 12 Vcell .
We recognize that this is exactly the same circuit as the pull-up network from class. Therefore we have
the following relation
t
Vbottom = Vcell (1 − e τ )
τ = −Rcol Ccol
Substituting in and solving for the delay, we get the following

t
Vbottom (t) = Vcell (1 − e τ )
Vbottom (t) t
= 1−eτ
Vcell
1 td
= 1−e τ
2
td 1
eτ =
2
td 1
= ln( )
τ 2
td = −ln(2)τ
td = ln(2)Rcol Ccol
ρLcell ε0 Hwire Lcell
td = ln(2)(Ncells )(Ncells )
HwireWwire S
2
ρε0 Lcell
2
td = ln(2)Ncells
Wwire S
td = Ncells × (5.15 × 10−19 )s
2

What is interesting to note here is that the time delay doesn’t scale linearly with an increase in column,
but quadratically. This dramatically decreases the number of cells we can put into a column.
(d) Given your answer to part (c), how many cells could you put on a single column (i.e., solve for Ncells )
such that DRAM can operate at 400MHz (i.e. a 2.5ns clock period).
Solution: From above, we have the following relation:

2.5 × 10−9 = Ncells

2
× (5.15 × 10−19 )
Ncells = 69640

(e) For the sake of comparison, how long would it take for light to travel from the top of the column to the
bottom of the column for the dimension of column wire associated with your answer to part (d)? Note
that the speed of light is c = 3 × 108 ms
Solution:

Lcell = 0.5µm
Lcell Ncell
tlight = = 0.116ns
c

EECS 16B, Fall 2018, Homework 2 9

4. Speakers revisited
In EE16A you were given several homework problems where we had to build circuits to drive a speaker, and
you were told to model the speaker as being an 8Ω resistor. In this problem we will develop a somewhat
more accurate model for the speaker and use this model to understand a few interesting characteristics and
limitations of these devices.
As we will learn about in more detail later on in this class, it turns out that besides just a resistance, speak-
ers usually have another "parasitic" (i.e., potentially undesired) circuit element associated with them - this
element is known as an inductor. The symbol for an inductor is shown below; the physics behind this rela-
tionship will be covered later, but for now all you need to know is that the inductor enforces the following
relationship between its voltage and its current:

dIL
VL = L ×
dt

IL
+ VL −

where L is the "inductance" (which has units of Henries, with typical values in the range of pH to mH).
For the rest of the problem we will assume that the speaker is driven by an ideal voltage source, and that we
can now model the speaker as follows:

Ls = 200µH
+

Vin + Rs = 8Ω Vspeaker
−
−

Note that the audio coming out of the speaker is directly set by Vspeaker - i.e., in the model above, the voltage
across the resistor is what we care about in terms of what we hear.

(a) If Vin is statically set to 1V (i.e., Vin is and always has been 1V), what will Vspeaker be?
Solution: If Vin is statically set, we can solve for the voltage across the inductor fairly easily.
Because the voltage is static, that means the current through the circuit is also static (ie, the current is
not changing). This means dIdtL = 0, implying VL = 0. Thus, all the voltage drop is across the resistor,
and Vspeaker = Vin = 1V .
(b) Now let’s start examining what may happen when Vin changes. Write the differential equation relating
Vspeaker to Vin , Rs , and Ls .
Solution: Let the current I be flowing left to right across the inductor, which also means it flows down
V dI
through the resistor. We know I = speaker
Rs . We also know that (Vin − Vspeaker ) = Ls dt . Differentiating

EECS 16B, Fall 2018, Homework 2 10

 the first equation and placing it within the second gives us

dI 1 dVspeaker
=
dt RS dt
 
1 dVspeaker
Vin −Vspeaker = Ls
Rs dt
L dVspeaker
Vin = +Vspeaker
Rs dt

Interestingly, this is a very similar form to the RC circuit we saw in class! In fact, we already know the
solutions to this equation.
(c) If Vin starts at 1V and then instantaneously transitions to 0V, solve the differential equation from part
(b) and sketch the resulting waveform Vspeaker (t).
Solution:
L dVspeaker
Vin = +Vspeaker
Rs dt
L dVspeaker
Vin −Vspeaker =
Rs dt
L dVspeaker
−Vspeaker =
Rs dt

The last step we did because Vin is zero for all time t > 0. We will need it later to set the boundary
conditions.
We know that eigenfunctions of the derivative function of exponentials, so we substitute an arbitrary
t
exponential (V0 e τ ) into the equation to solve.

L dVspeaker
−Vspeaker =
Rs dt
t L 1 t
−V0 e τ = V0 e τ
Rs τ
L
τ =−
Rs

Now we need to solve for V0 , which is the initial value of the exponential. We know that at times
t < 0 that the inductor had zero volts across it, and therefore Vspeaker = Vin . The inductor resists sudden
change to voltage, as can be seen by the relation V = L dI
R dt . Taking the integral of both sides, we see that
V dt = LI. If a sudden change of voltage were to occur, it would not change the output current. From
this we can say that the boundary between the two states should be continuous and V0 = 1V . Thus, our
final answer is:
Rs t
Vspeaker = 1V × e− L

This is a decaying exponential starting from time t = 0. The plot would look like the following:
(d) Given your solution to (c), how long will it take for Vspeaker to reach 0.25V?

EECS 16B, Fall 2018, Homework 2 11

 Solution:
Rs t
Vspeaker = 1V × e− L
1 Rs t
= e− L
4
Rst
−2ln(2) = −
L
L
t = 2ln(2)
Rs
t = 3.47 × 10−5 s

5. CMOS Scaling
Jerry wants to create a new machine learning accelerator chip utilizing CMOS technology. When designing
his chip, he considers the most important parameters of his design to be the amount of energy dissipated
when the gate transisions, and the delay time it takes for the output of a gate to hit VDD
2 from either ground
or VDD (i.e. the delay of the gate).
Jerry has access to two different fabrication processes: process A and process B.

Process A uses a supply voltage of VDD = 1V. The transistors have a parasitic resistance of R p = 10kΩ,
and the output driven by a representative inverter has a parasitic capacitance of Cp = 5fF.

Process B uses a supply voltage of VDD = 3V. The transistors have a parasitic resistance of R p = 30kΩ,
and the output driven by a representative inverter has a parasitic capacitance of Cp = 1fF.

EECS 16B, Fall 2018, Homework 2 12

In order to determine which process is better for the design, Jerry decides to analyze the circuit where the
input of an inverter transitions from VDD to 0. This can be modeled as the following circuit:

VDD
+

Rp VR (t)

iR −
Vout
ic +
Cp Vc (t)
−

Since the input of the inverter is transitioning from VDD to 0, the initial condition for Vc (t) is:

Vc (0) = 0

(a) Using the values of VDD , R p , and Cp from process A, calculate the total energy delivered by the voltage
source, VDD , while the capacitor is being charged to VDD . Also calculate the time it takes for Vout to
reach VDD
2 .
Solution:
In order to determine the energy dissipation and delay time, first we need to find an expression for
Vout (t)

Vc (t) = Vout (t)

KCL at Vout :
iR = ic
VDD −Vout dVout
= Cp
Rp dt
dVout 1 VDD
+ Vout =
dt R pCp R pCp
Using substitution of variables:
x = Vout −VDD
Vout = x +VDD
dVout dx
=
dt dt
dx 1
+ x=0
dt R pCp

EECS 16B, Fall 2018, Homework 2 13

 − R ptC p
x(t) = Ae
− R ptC p
Vout (t) = VDD + Ae
Using our initial condition:
Vout (0) = 0 = VDD + A
A = −VDD
− t
 
Vout (t) = VDD 1 − e R pCp

We can now find the delay time by setting Vout (t) = VDD
2 :

VDD 
− t

= VDD 1 − e R pCp
2
1 − t
= e R pC p
2
 
1 t
ln =−
2 R pCp
 
1
t = − ln R pCp
2
VDD
From this, we can say that the delay time to reach 2 for any R p and Cp is:
td = 0.69R pCp

Next, we need to find an equation for the energy delivered. The total energy delivered by the source:
Z ∞
Us = VDD iR (t)dt
0

dVout
iR (t) = Cp
dt
1 − R ptCp VDD − R ptCp
iR (t) = CpVDD e = e
R pCp Rp
!
VDD − R ptCp
Z ∞
Us = (VDD ) e dt
0 Rp
Z ∞ 2
VDD − R ptCp
UR = e dt
0 Rp
! ∞
2
VDD − R ptC p 


Us = −R pC e 
Rp 
0
The total energy supplied by the supply when charging up the capacitor is:
2
Us = CVDD

Plugging in component values of process A for the energy dissipation and time delay:
Us = (5 × 10−15 )12 = 5 × 10−15 J
td = 0.69(10 × 103 × 5 × 10−15 ) = 3.45 × 10−11 s

EECS 16B, Fall 2018, Homework 2 14

 (b) Repeat part (a), but with the values from process B.
Solution:
Using the equations from part (a):

Us = (1 × 10−15 )32 = 9 × 10−15 J

td = 0.69(30 × 103 × 1 × 10−15 ) = 2.07 × 10−11 s

(c) Compare the energy and delay of process A and B

Solution:
Compared to process B, process A dissipates less energy per transition, but has a longer delay time.
(d) Jerry’s friend Pat tells Jerry that with process B, one can reduce VDD to 2V. However, the reduction in
supply voltage increases the parasitic resistance R p to 50kΩ. Calculate the new delay and energy.
Solution:

Us = (1 × 10−15 )22 = 4 × 10−15 J

td = 0.69(50 × 103 × 1 × 10−15 ) = 3.45 × 10−11 s

(e) Based on your previous answers, which process should Jerry choose to use?
Solution:
With the new VDD and R p of process B, it ends up that process B and process A have the same delay
time. However, process B dissipates less energy per transition, which means Jerry should choose
process B.

6. Write Your Own Question And Provide a Thorough Solution.

Writing your own problems is a very important way to really learn material. The famous “Bloom’s Tax-
onomy” that lists the levels of learning is: Remember, Understand, Apply, Analyze, Evaluate, and Create.
Using what you know to create is the top level. We rarely ask you any homework questions about the lowest
level of straight-up remembering, expecting you to be able to do that yourself (e.g. making flashcards). But
we don’t want the same to be true about the highest level. As a practical matter, having some practice at
trying to create problems helps you study for exams much better than simply counting on solving existing
practice problems. This is because thinking about how to create an interesting problem forces you to really
look at the material from the perspective of those who are going to create the exams. Besides, this is fun. If
you want to make a boring problem, go ahead. That is your prerogative. But it is more fun to really engage
with the material, discover something interesting, and then come up with a problem that walks others down
a journey that lets them share your discovery. You don’t have to achieve this every week. But unless you try
every week, it probably won’t ever happen.

Contributors:

• Siddharth Iyer.
• Jaymo Kang.
• Kyle Tanghe.

EECS 16B, Fall 2018, Homework 2 15