System Verilog

RANDOMIZATION

ROHIT KHANNA
 Why Randomize?

 As designs grow it becomes more difficult to verify their

functionally through directed test cases.

 Directed test cases checks specific features of a design and can

only detect anticipated bugs.

 Verifying your design using this approach is a time consuming

process.

 Randomization helps us detecting bugs that we do not expect in

our design.

System Verilog Randomization

 Comparison

Directed Random Constrained Random

o Verifies specific o Broader Coverage. o Broad and Deep
scenarios. o TB’s are easy to write. o Tests are more
o Time Consuming. o Tests are redundant. productive
o Linear progress. o Takes longer time to o Finds corner cases
achieve functionality. o Constrained to
achieve functionality

System Verilog Randomization

 What to Randomize?

 Device configuration
 Environment configuration
 Primary input data
 Encapsulated input data
 Protocol exceptions
 Errors and violations
 Delays
 Test order
 Seed for the random test

System Verilog Randomization

Verilog Constrained Randomization
 Random in range

module test;
integer a, b, c;

initial
repeat(20) begin
a=$random % 10; //-9 to 9 (Random range)
b={$random} % 20; //0 to 19 (Random range)
c=$unsigned($random)%15; //0 to 14 (Random range)
#2; end
endmodule

System Verilog Randomization

 Random in range

module test;
integer a, b, c;

initial
repeat(20) begin
a=10 + {$random} % 6; //10 to 15 (positive range)
b=-5 - {$random} % 6; //-5 to -10 (negative range)
c =-5 + {$random} % 16; //-5 to 10 (mix range)
#2; end
endmodule

System Verilog Randomization

 Algorithms

Positive Range:
result= min + {$random} % (max – min + 1);

Negative Range:
result= -min - {$random} % (max – min + 1);

Mix Range:
result= -min + {$random} % (max + min + 1);
//min is the magnitude of minimum number
//max is the magnitude of maximum number

System Verilog Randomization

 Random between ranges

module test;
integer a;

initial
repeat(20)
if ({$random} % 2)
#2 a=10 + {$random} % 6; //10 to 15
else
#2 a= 3 + {$random} % 5; // 3 to 7
endmodule

System Verilog Randomization

 Weighted Random numbers

module test;
integer a, count=0;

always if(count< 10) #2 count=count+1; else #2 count=0;

initial repeat(20)
if (count<3)
#2 a=1 + {$random} % 9; //1 to 9
else
#2 a=11 + {$random} % 8; // 11 to 18 Higher weight
endmodule

System Verilog Randomization

 Real random numbers

module test;
reg sign; reg [7:0] exp;
reg [22:0] mantisa; real a;

initial repeat(20) begin

sign=$random;
exp=$random;
mantisa=$random;
a=$bitstoshortreal({sign, exp, mantisa});
#2; end
endmodule
System Verilog Randomization
 Unique random numbers

while(index!=10) begin
Generate 10 unique random
numbers temp=$random;
begin: loop
integer rec [0:9]; for(i=0; i<index; i=i+1)
integer i, temp, num, index=0; if(rec[index]==temp)
disable loop;
initial begin rec[index]=temp;
$monitor(“num=%0d”, num); index=index + 1; num=temp;
#2; end
end end
System Verilog Randomization
 Result

# num=303379748
# num=-1064739199
# num=-2071669239
# num=-1309649309
# num=112818957
# num=1189058957
# num=-1295874971
# num=-1992863214
# num=15983361
# num=114806029

System Verilog Randomization

 Unique random numbers

while(index!=10) begin
Generate 10 unique random
numbers between 0 to 99 temp={$random} % 100;
begin: loop
integer rec [0:9]; for(i=0; i<index; i=i+1)
integer i, temp, rand, index=0; if(rec[index]==temp)
disable loop;
rec[index]=temp;
index=index + 1; rand=temp;
#2; end
end
System Verilog Randomization
 Result

# num=48
# num=97
# num=57
# num=87
# num=57
# num=25
# num=82
# num=61
# num=29

System Verilog Randomization

 Other types

 Verilog also offers few more randomization system functions apart

from $random. They can be categorized as following:

o$dist_uniform (seed, start, end)

o$dist_normal (seed, mean, standard_deviation)
o$dist_exponential (seed, mean)
o$dist_poisson (seed, mean)
o$dist_chi_square (seed, degree_of_freedom)
o$dist_t (seed, degree_of_freedom)
o$dist_erlang (seed, k_stage, mean)

System Verilog Randomization

 $dist_uniform

module test;
integer num1, num2, seed;

initial
repeat(20) begin
num1=$dist_uniform (seed, 5, 15); //5 to 15
num2=$dist_uniform (seed, -5, 10); //-5 to 10
#2; end
endmodule

System Verilog Randomization

SV Constrained Randomization
 $urandom

module test;
integer num1, num2, seed;

initial
repeat(20) begin
#2 num1=$urandom (seed); //Unsigned 32-bit
//Random Number
num2=$urandom;
end
endmodule

System Verilog Randomization

 $urandom_range

module test;
integer num1, num2 , num3;

initial
repeat(20) begin
#2 num1=$urandom_range(35, 20); //35:max to 20:min
num2=$urandom_range(9); //9:max to 0:min
num3=$urandom_range(10,15); //10:min to 15:max
end
endmodule

System Verilog Randomization

 Result

# num1=27 num2=8 num3=10

# num1=32 num2=0 num3=11
# num1=26 num2=0 num3=14
# num1=29 num2=0 num3=13
# num1=21 num2=6 num3=12
# num1=25 num2=4 num3=10
# num1=20 num2=7 num3=12
# num1=23 num2=2 num3=12
# num1=33 num2=2 num3=13
# num1=22 num2=1 num3=11
# num1=34 num2=8 num3=14
# num1=24 num2=2 num3=15

System Verilog Randomization

 Randomize function

 SV provides scope randomize function which is used to randomize

variables present in current scope.

 randomize() function can accept any number of variables which

have to be randomized as an arguments.

 This function returns true if randomization was successful else false.

 User can also provide inline constraints to control range of random

values.

System Verilog Randomization

 Randomize function

module test;
integer num1, num2;

initial
repeat(20) begin
if(randomize(num1, num2)) //Randomize num1 and num2
$display(“Randomization Successful”);
else $display(“Randomization Failed”);
#2 ; end
endmodule

System Verilog Randomization

 Randomize function with constraint

module test;
integer num;

initial
repeat(20) begin
if(randomize(num) with {num>10; num<20;} )
$display(“Randomization Successful”);
//num should be between 10 and 20 Inline Constraint
#2 ; end
endmodule

System Verilog Randomization

 Result

# num=19
# num=15
# num=11
# num=13
# num=15
# num=14
# num=16
# num=15
# num=17
# num=15
# num=11
# num=15

System Verilog Randomization

 Randomize Object Properties

 In SV properties (variables) inside a class can also be

randomized.

 Variables declared with rand and randc are only considered for
randomization.

 A class built-in randomize function is used to randomized rand and

randc variables.

 User can also specify constraint blocks to constrain random value

generation.
System Verilog Randomization
 rand vs randc

 Variables defined with rand keyword, distribute values uniformly.

rand bit [1:0] num1;

num1: 3, 2 , 0, 3, 0, 1, 2, 1, 3

 Variables defined with randc keyword, distribute values in a cyclic

fashion without any repetition within an iteration.
randc bit [1:0] num2;
num2: 3, 2, 0, 1
0, 2, 1, 3
1, 3, 0, 2
System Verilog Randomization
 Example1

program test; class sample;

sample sm; rand int num1;
initial begin int num2;
sm=new; endclass
repeat(20)
assert(sm.randomize()) //assert checks randomization status
$display(“num1=%0d num2=%0d”, sm.num1, sm.num2);
end
endprogram num1 is randomized num2 remains untouched

System Verilog Randomization

 Result

# num1=-1884196597 num2=0
# num1=-326718039 num2=0
# num1=1452745934 num2=0
# num1=-2130312236 num2=0
# num1=1572468983 num2=0
# num1=131041957 num2=0
# num1=1115460554 num2=0
# num1=-818992270 num2=0
# num1=2000525113 num2=0
# num1=1547354947 num2=0
# num1=1196942489 num2=0
# num1=736230661 num2=0

System Verilog Randomization

 Example2

class sample; program test;

rand bit[1:0] num; main m;
endclass initial begin
m=new;
class main;
repeat(20)
rand sample sm; //rand is must to
assert(m.randomize())
//randomize num
$display(m.sm.num);
function new;
end
sm=new;
endprogram
endfunction
endclass
System Verilog Randomization
 Example3

program test;
class sample; sample sm;
typedef struct { randc int a; initial begin
bit [3:0] b; sm=new;
} st_t; repeat(20)
rand st_t st; assert(sm.randomize())
//rand is must to randomize $display(sm.st.a);
//int present inside structure end
endclass endprogram

System Verilog Randomization

 Example4

class sample; program test;

rand bit[3:0] num; main m;
endclass initial begin
class main; m=new;
rand sample sm1; repeat(20) begin
sample sm2; assert(m.randomize()) ;
function new; $display(m.sm1.num);
sm1=new; sm2=new; $display(m.sm2.num);
endfunction end
endclass end
endprogram
System Verilog Randomization
 Result

# 14 # 0
# 4 # 0
# 9 # 0
# 6 # 0
# 5 # 0
# 15 # 0
# 4 # 0
# 13 # 0
# 1 # 0
# 8 # 0
# 9 # 0
# 14 # 0
System Verilog Randomization
 Specifying Constraints

class sample1;
rand int num;
class sample3;
constraint c { num>10;
randc int num;
num<100; }
int Max, Min;
endclass
constraint c1 { num>Min; }
class sample2; constraint c2 { num<Max; }
randc bit [7:0] num; endclass
constraint c1 { num>10; }
constraint c2 { num<100; }
endclass
System Verilog Randomization
 Example1

class packet; repeat(10)

rand bit [7:0] data; assert(pkt.randomize())
int Max=50, Min=10; $display(pkt.data);
constraint c1 { data>Min; pkt.Min=30;
data<Max; } pkt.Max=100;
endclass repeat(10)
assert(pkt.randomize())
program test;
$display(pkt.data);
packet pkt;
end
initial begin
endprogram
pkt=new;
System Verilog Randomization
 Result

# 22 # 72
# 22 # 53
# 29 # 66
# 27 # 79
# 46 # 68
# 43 # 69
# 33 # 78
# 43 # 95
# 46 # 65
# 36 # 34

System Verilog Randomization

 Example2

class packet; program test;

rand bit [7:0] data; packet pkt;
constraint c2 { data>50; initial begin
data<10; } pkt=new;
endclass repeat(10)
if(pkt.randomize())
$display(“Randomization Success”);
else
$display(“Randomization Fails”); end
endprogram

System Verilog Randomization

 Result

# Randomization Fails
# Randomization Fails
# Randomization Fails
# Randomization Fails
# Randomization Fails
# Randomization Fails
# Randomization Fails
# Randomization Fails
# Randomization Fails
# Randomization Fails

System Verilog Randomization

 pre_randomize and post_randomize

 Every class contains pre_randomize and post_randomize functions

which are evoked every time randomize function is called.

 When randomize function is called, it first evokes pre_randomize

and then randomization is done.

 post_randomize function is only called if randomization was

successful.

 pre_randomize and post_randomize functions can be written in a

class to offer user defined functionality before and after
randomization.
System Verilog Randomization
 Example1

class packet; program test;

rand bit [7:0] data; packet pkt;

function void pre_randomize; initial begin

$display(“Pre-Randomize”); pkt=new;
endfunction repeat(5) begin
void'(pkt.randomize);
function void post_randomize;
$display(pkt.data);
$display(“Post-Randomize”);
end
endfunction
end
endclass endprogram
System Verilog Randomization
 Result

# Pre-Randomize
# Post-Randomize # 33
# Pre-Randomize
# Post-Randomize # 25
# Pre-Randomize
# Post-Randomize # 202
# Pre-Randomize
# Post-Randomize # 138
# Pre-Randomize
# Post-Randomize # 15

System Verilog Randomization

 Example2

class A; class B extends A;

function void pre_randomize; function void pre_randomize;
$display(“A: Pre-Randomize”); $display(“B: Pre-Randomize”);
endfunction endfunction
function void post_randomize; function void post_randomize;
$display(“A: Post-Randomize”); $display(“B: Post-Randomize”);
endfunction endfunction
endclass endclass

System Verilog Randomization

 Example3

program test;
Result
B b1; # B: Pre-Randomize
# B: Post-Randomize
initial begin # B: Pre-Randomize
b1=new; # B: Post-Randomize
repeat(2)
void'(b1.randomize);
Pre-Randomize and Post-Randomize
end
of parent class are overridden
endprogram

System Verilog Randomization

 Controlling Randomization

 Randomization nature of rand and randc variables can be turned

on/off dynamically.

 rand_mode method is used to change randomization status of

rand and randc variable.

 When used as a task, the argument determines the state of rand

and randc variables.

 When argument is 0 then randomization is disabled(turned-off),

when argument is 1 then randomization is enabled(turned-on).

System Verilog Randomization

 Controlling Randomization

 When used as a function, rand_mode returns the current status of

rand and randc variables.

 It returns 1 if randomization is on else it returns 0.

 Hierarchal reference of variables in an object can also be given

to disable/enable specific rand and randc variables.

 Randomization is enabled by default.

System Verilog Randomization

 Example1

class packet; repeat(4) begin

rand bit [7:0] data; void'(pkt.randomize);
$display(pkt.data); end
endclass
pkt.rand_mode(0);
//Disabling Randomization
program test; repeat(3) begin
packet pkt; void'(pkt.randomize)
$display(pkt.data);
initial begin
end end
pkt=new;
endprogram

System Verilog Randomization

 Result

# 33
# 25
# 202
# 138
# 138
# 138
# 138

System Verilog Randomization

 Example2

class packet; if(rand_mode()) //Check current Status

rand bit [7:0] data1; $display(“Randomization on”);
rand int data2; else $display(“Randomization off”);
endclass end
program test; pkt.rand_mode(0);
packet pkt; void'(pkt.randomize);
initial begin if(rand_mode())
pkt=new; $display(“Randomization on”);
repeat(10) begin else $display(“Randomization off”); end
void'(pkt.randomize); endprogram

System Verilog Randomization

 Example3

class packet; repeat(10) if(pkt.randomize)

rand bit [7:0] data1; $display(pkt.data1, pkt.data2);
rand byte data2; pkt.data2.rand_mode(0);
//turn off for data2
endclass
repeat(10) if(pkt.randomize)
program test; $display(pkt.data1, pkt.data2);
packet pkt; pkt.data2.rand_mode(1);
initial begin repeat(10) if(pkt.randomize)
pkt=new; $display(pkt.data1, pkt.data2); end
endprogram

System Verilog Randomization

 Result

# 238 94
# 85 48
# 202 -92
# 29 38
# 155 48
# 225 -91
# 81 -66
# 232 -82
# 85 -112
# 141 -34
# 244 -34
# 32 -34
# 9 -34
System Verilog Randomization
 Example4

class packet; repeat(10)

rand bit [7:0] data1; if(pkt.randomize)
byte data2; $display(pkt.data1, pkt.data2);
repeat(10)
endclass
if(pkt.randomize(data2))
program test; //will also randomize data2
packet pkt; $display(pkt.data1, pkt.data2);
initial begin end
pkt=new; endprogram

System Verilog Randomization

 Result

# 238 0
# 85 0
# 202 0
# 29 0
# 155 0
# 225 0
# 141 75
# 141 115
# 141 -24
# 141 111
# 141 -119

System Verilog Randomization

 Example5

class packet;
rand int data;
int Max, Min;
constraint c1{ data> Min; data<Max; }
constraint c2 { Max> Min; }
task set(int Min, Max);
this.Min=Min;
this.Max=Max;
endtask
endclass

System Verilog Randomization

 Example5

initial begin
packet p1=new;
p1.set(5, 25);
repeat(5) if(p1.randomize)
$display(“Random value=%0d”, p1.data);
p1.set(35, 20);
repeat(5) if(p1.randomize)
$display(“Random value=%0d”, p1.data);
else $display(“Randomization Failed”);
end

System Verilog Randomization

 Result

# Random value=14
# Random value=18
# Random value=15
# Random value=16
# Random value=16
# Randomization Failed
# Randomization Failed
# Randomization Failed
# Randomization Failed
# Randomization Failed

System Verilog Randomization

 Random Stability

module test; repeat(5)

class A; if(a1.randomize)
rand bit [3:0] data; $display("a1.data=%0d",a1.data);
endclass repeat(5)
A a1, a2; if(a2.randomize)
$display("a2.data=%0d",a2.data);
initial begin end
a1=new; endmodule
//Random seed initialized
a2=new;
//Random seed initialized with next seed value
System Verilog Randomization
 Result

# a1.data=12
# a1.data=7
# a1.data=15
# a1.data=6
# a1.data=9
# a2.data=13
# a2.data=13
# a2.data=6
# a2.data=2
# a2.data=15

System Verilog Randomization

 Random Stability

module test; repeat(5)

class A; if(a2.randomize)
rand bit [3:0] data; $display("a2.data=%0d",a2.data);
endclass repeat(5)
A a1, a2; if(a1.randomize)
$display("a1.data=%0d",a1.data);
initial begin end
a1=new; endmodule
//Random seed initialized
a2=new;
//Random seed initialized with next seed value
System Verilog Randomization
 Result

# a2.data=13
# a2.data=13
# a2.data=6
# a2.data=2
# a2.data=15
# a1.data=12
# a1.data=7
# a1.data=15
# a1.data=6
# a1.data=9

System Verilog Randomization

 Random Stability

module test; initial begin

a1=new(3); a2=new(3);
class A;
repeat(5)
rand bit [3:0] data;
function new(int seed); if(a1.randomize)
$display("a1.data=%0d",a1.data);
srandom(seed);
repeat(5)
//set a particular seed
endfunction if(a2.randomize)
$display("a2.data=%0d",a2.data);
endclass
end
A a1, a2; endmodule

System Verilog Randomization

 Result

# a1.data=5
# a1.data=7
# a1.data=12
# a1.data=13
# a1.data=5
# a2.data=5
# a2.data=7
# a2.data=12
# a2.data=13
# a2.data=5

System Verilog Randomization

 Relation in Constraints

 Each constraint expression should only contain 1 relation operator.

< <= == > >= -> <-> || ! &&

class bad_cons; low=20, med=224, hi=164

rand bit [7:0] low, med, hi; low=114, med=39, hi=189
constraint bad {low < med < hi;} low=186, med=148, hi=161
endclass low=214, med=223, hi=201

 lo < med is evaluated. Results in 0 or 1

 hi > (0 or 1) is evaluated.

System Verilog Randomization

 Relation in Constraints

constraint good{ low < med; low=20, med=40, hi=100

med < hi; } low=10, med=25, hi=90

 User can use == to constraint random value to a particular

expression. Using = will give compilation error.

class packet;
rand int length, data, address;
constraint len { length==address * 5};
endclass

System Verilog Randomization

 Set Membership

 User can use inside operator to set membership in a constraint

block.

 Example: To limit address in range from 1 to 5, 7 to 11 and to a

set of values 15, 18, 25.

class packet;
rand int address;
constraint limit {address inside { [1:5], [7:11], 15, 18, 25 };}
endclass

System Verilog Randomization

 Set Membership

 A ! Operator can be used to exclude set of values

class packet;
rand int address;
constraint limit { !(address inside { 6, [12:14]} ) ;}
endclass

 Using arrays to set membership.

class packet;
int arr [ ]= `{ 5, 7, 11, 13, 19};
rand int address;
constraint limit { address inside { arr }; }
endclass
System Verilog Randomization
 Set Membership

class packet;
rand int data;
constraint limit { ( (data==5) || (data==7) || (data==9) );}
endclass
There is a better way of providing such constraints:

class packet;
rand int data;
constraint limit { data inside { 5, 7, 9}; }
endclass

System Verilog Randomization

 Weighted Distribution

 User can provide weights for random numbers to obtain non-

uniform distribution.

 := operator is used to assign same weight to all the values.

 :/ operator is used to distribute weight among all the values.

 dist operator is used to specify distribution.

 Weighted distribution does not work on randc variables.

 Example: constraint con { src dist { 0:=40, [1:3] :=60 };

dst dist { 0:/40 , [1:3] :/60 }; }

System Verilog Randomization

 Example1

class packet;
rand int data;
constraint con { data dist { 0:=40, [1:4] :=60, [6:7]:=20 };
endclass
//Total weight= 40 + 60 + 60 + 60 + 60 + 20 + 20=320

data=3 weight=60/320=18.75%
data=0 weight=40/320=12.5%
data=4 weight=60/320=18.75%
data=1 weight=60/320=18.75%
data=6 weight=20/320=6.25%
data=2 weight=60/320=18.75%
data=7 weight=20/320=6.25%

System Verilog Randomization

 Example2

class packet;
rand int data;
constraint con { data dist { 0:/20, [1:3] :/60, [6:7]:/20 };
endclass
//Total weight= 20 + 60 + 20=100

data=0 weight=20/100=20% data=3 weight=20/100=20%

data=1 weight=20/100=20% data=6 weight=10/100=10%
data=2 weight=20/100=20% data=7 weight=10/100=10%

System Verilog Randomization

 Example3

typedef enum {Red, Green, Blue} color;

class temp;
rand color col;
int redw=5, greenw=3, bluew=4;
constraint weight { col dist { Red:=redw,
Green:=greenw,
Blue:=bluew}; }
endclass

System Verilog Randomization

 Bidirectional Constraints

 Constraints are not procedural but declarative.

 All constraints should be active at same time.

rand bit [15:0] a, b, c; Solution a b c

constraint cp { a < c; S1 6 6 7
b == a; S2 6 6 8
c < 10; S3 6 6 9
b > 5; S4 7 7 8
} S5 7 7 9
S6 8 8 9
 Even though there is no direct constraint on lower value of c,
constraint on b restricts choices.
System Verilog Randomization
 Implication Constraints

constraint mode_c { if (mode == small)

len < 10;
else if (mode == large)
len > 100; }
Is equivalent to
constraint mode_c { (mode == small) -> len < 10;
(mode == large) -> len > 100; }
 If mode is small that implies length should be less than 10.
 If mode is large that implies length should be more than 100.
 Implication helps in creating case like blocks.

System Verilog Randomization

 Efficient Constraints

rand bit [31:0] addr;

constraint slow { addr % 4096 inside { [0:20], [4075:4095] };
}

rand bit [31:0] addr;

constraint fast { addr [11:0] inside { [0:20], [4075:4095] };
}

 In slow, first addr is evaluated and then % is performed and then

constraints are applied. In fast, constraints are directly applied
on selected bits hence faster and achieves the same result.

System Verilog Randomization

 Solution Probabilities

Solution x y Probability
S1 0 0 1/8
class Unconstrained;
S2 0 1 1/8
rand bit x;
// 0 or 1 S3 0 2 1/8
rand bit [1:0] y; S4 0 3 1/8
// 0, 1, 2, or 3 S5 1 0 1/8
endclass S6 1 1 1/8
S7 1 2 1/8
S8 1 3 1/8

System Verilog Randomization

 Solution Probabilities

Solution x y Probability
class Implication1; S1 0 0 1/2
rand bit x; S2 0 1 0
// 0 or 1
S3 0 2 0
rand bit [1:0] y;
S4 0 3 0
// 0, 1, 2, or 3
constraint c { S5 1 0 1/8
(x==0) -> (y==0); } S6 1 1 1/8
endclass S7 1 2 1/8
S8 1 3 1/8

System Verilog Randomization

 Solution Probabilities

Solution x y Probability
class Implication2; S1 0 0 0
rand bit x; S2 0 1 0
// 0 or 1
S3 0 2 0
rand bit [1:0] y;
S4 0 3 0
// 0, 1, 2, or 3
constraint c { S5 1 0 0
y>0; S6 1 1 1/3
(x==0) -> (y==0); } S7 1 2 1/3
endclass S8 1 3 1/3

System Verilog Randomization

 Solve before

 A solve before keyword can be used to specify order in which

random variables would be solved.
class solvebefore; Solution x y Probability
rand bit x; S1 0 0 1/2
// 0 or 1 S2 0 1 0
rand bit [1:0] y; S3 0 2 0
// 0, 1, 2, or 3
S4 0 3 0
constraint c {
S5 1 0 1/8
(x==0) -> (y==0);
S6 1 1 1/8
solve x before y; }
endclass S7 1 2 1/8
S8 1 3 1/8

System Verilog Randomization

 Solve before

class solvebefore; Solution x y Probability

rand bit x; S1 0 0 1/8
// 0 or 1 S2 0 1 0
rand bit [1:0] y; S3 0 2 0
// 0, 1, 2, or 3
S4 0 3 0
constraint c {
S5 1 0 1/8
(x==0) -> (y==0);
S6 1 1 1/4
solve y before x; }
endclass S7 1 2 1/4
S8 1 3 1/4

System Verilog Randomization

 Controlling Constraints

 Constraints can be turned on/off during runtime.

 constraint_mode() is used to achieve this capability.

 When used with handle.constraint, this method controls a single

constraint.

 When used with just handle, it controls all constraints for an object.

 To turn off constraint, 0 is passed as an argument to

constraint_mode and to turn on, 1 is passed as an argument.

System Verilog Randomization

 Example

class Packet;
rand int length;
constraint c_short { length inside { [1:32] }; }
constraint c_long { length inside { [1000:1023]}; }
endclass

System Verilog Randomization

 Example

Packet p;
initial begin
p = new;
// Create a long packet by disabling short constraint
p.c_short.constraint_mode(0);
assert (p.randomize());
// Create a short packet by disabling all constraints
// then enabling only the short constraint
p.constraint_mode(0);
p.c_short.constraint_mode(1);
assert (p.randomize());
end

System Verilog Randomization

 Inline Constraints

 New constraints can be added to existing constraints while calling

randomize function using randomize with.

 constraint_mode can be used disable any conflicting constraints.

class Transaction;
rand bit [31:0] addr, data;
constraint c1 { addr inside { [0:100], [1000:2000] }; }
endclass

System Verilog Randomization

 Inline Constraints

Transaction t;
initial begin
t = new(); // addr is 50-100, 1000-1500, data < 10
repeat(5)
assert(t.randomize() with { addr >= 50;
addr <= 1500;
data < 10;} );

repeat(5) // force addr to a specific value, data > 10

assert(t.randomize() with { addr == 2000;
data > 10; } );
end
System Verilog Randomization
 Constraint in Inheritance

 Additional constraints can be provided in a subclass class(child

class). Child class object has to fulfill both the constraints (parent
and child).
class base; class child extends base;
rand int data; constraint limit2 { data > 50; }
constraint limit1 { data> 0; endclass
data< 100; }
endclass
Parent: 0 < data < 100 Child: 50 < data < 100

System Verilog Randomization

 Example2

class base; class child extends base;

rand int data; constraint limit2 { data == 50;
constraint limit1 { data> 0; }
data< 100; endclass
}
endclass

Parent: 0 < data < 100 Child: data=50

System Verilog Randomization

 Example3

class base; class child extends base;

rand int data; constraint limit2 { data > 10;
constraint limit1 { data> 40; data< 30;
data< 50; }
} endclass
endclass

Parent: 40 < data < 50 Child: 10 < data < 30

Randomization Fails because both constraints are not satisfied

System Verilog Randomization

 Example 4

class base; class child extends base;

rand int data; rand int data;
constraint limit1 { data> 40; constraint limit2 { data > 10;
data< 50; data< 30;
} }
endclass endclass

Parent: 40 < data < 50 Child: 10 < data < 30

Parent data is different as compared to child data. Data Overridden

System Verilog Randomization

 Constraint in Inheritance

 Constraints are overridden in child class if they are defined with

same name as that present in parent class.
class base; class child extends base;
rand int data; constraint limit { data > 50;
constraint limit { data> 20; data < 90; }
data< 40; } endclass
endclass

Parent: 20 < data < 40 Child: 50 < data < 90

Constraints are overridden

System Verilog Randomization

 randcase

 A randcase keyword can be used to make a weighted choice

between several actions.
initial begin
int len;
repeat(20) begin
randcase
1: len = $urandom_range(0, 2); // 10%: 0 to 2
8: len = $urandom_range(3, 5); // 80%: 3 to 5
1: len = $urandom_range(6, 7); // 10%: 6 to 7
endcase
$display("len=%0d", len); end
end
System Verilog Randomization
 randsequence

 The random sequence generator is useful for randomly generating

structured sequences of stimulus.

 randsequence is composed of one or more productions.

 Each production contains a name and one or more production list.

 Production list contains one or more production_item.

System Verilog Randomization

 Example1

module rand_sequence1();
initial begin
repeat(5) begin
randsequence( main ) //main is production
main : one two three ; //main contains one production list
one : {$write("one");}; //one two three are production items
two : {$write("two");};
three: {$display("three");};
endsequence
end
end
endmodule : rand_sequence1

System Verilog Randomization

 Result

# one two three

# one two three
# one two three
# one two three
# one two three

System Verilog Randomization

 Example2

module rand_sequence2();
initial begin
repeat(7) begin
randsequence( main ) //main contains three production list
main : one| two | three ; //one two three are production list
one : {$display("one"); }; //one list will be chosen randomly
two : {$display("two"); };
three: {$display("three"); };
endsequence
end
end
endmodule : rand_sequence2

System Verilog Randomization

 Result

# one
# one
# one
# one
# three
# one
# two

System Verilog Randomization

 Example3

module rand_sequence3();
initial begin
repeat(50) begin
randsequence( main )
main : one:=5 | two:=2 | three:=3 ; //production list with weights
one : {$display("one");};
two : {$display("two");};
three: {$display("three");};
endsequence
end
end
endmodule : rand_sequence3

System Verilog Randomization

 Example4

module rand_sequence4();
int one_1, two_2, three_3; bit on;
initial begin
repeat(100) begin
randsequence( main )
main : one three;
one : if(on) incr_one else incr_two;
incr_one : {one_1 ++; on=~on;};
incr_two : {two_2 ++; };
three: {three_3++;};
endsequence end end
endmodule : rand_sequence4

System Verilog Randomization

 Example5

module rand_sequence5();
initial for (int i = 0 ; i < 10 ; i++)
randsequence( main )
main : case(i %3)
0 : zero;
1, 2 : non_zero;
default : def;
endcase
zero : {$display("zero");};
non_zero : {$display("non_zero");};
def : {$display("default");};
endsequence
endmodule : rand_sequence5
System Verilog Randomization