DATA TRANSFER INSTRUCTIONS

Explanation of
 Opcode  Operand  Description
Instruction
 This instruction copies the contents of the source
 Rd, Rs register into the destination register; the contents of the
Copy from source register are not altered. If one of the operands is
 MOV M, Rs source(Rs) to a memory location, its location is specified by the
destination(Rd) contents of the HL registers.
Rd, M
Example: MOV B, C or MOV B, M
The 8-bit data is stored in the destination register or
 Rd, data memory. If the operand is a memory location, its
Move immediate 8-
 MVI location is specified by the contents of the HL registers.
bit
M, data
Example: MVI B, 57H or MVI M, 57H
The contents of a memory location, specified by a 16-
bit address in the operand, are copied to the
 16-bit
 LDA Load accumulator accumulator. The contents of the source are not altered.
address
Example: LDA 2034H
The contents of the designated register pair point to a
memory location. This instruction copies the contents
of that memory location into the accumulator. The
 B/D Reg. Load accumulator
 LDAX contents of either the register pair or the memory
pair indirect
location are not altered.

Example: LDAX B
The instruction loads 16-bit data in the register pair
 Reg. pair, Load register pair designated in the operand.
 LXI
16-bit data immediate
Example: LXI H, 2034H or LXI H, XYZ
 The instruction copies the contents of the memory
location pointed out by the 16-bit address into register
L and copies the contents of the next memory location
 16-bit Load H and L
 LHLD into register H. The contents of source memory
address registers direct
locations are not altered.

Example: LHLD 2040H

 STA  16-bit 16-bit address The contents of the accumulator are copied into the
address memory location specified by the operand. This is a 3-
byte instruction, the second byte specifies the low-order
address and the third byte specifies the high-order
 address.

Example: STA 4350H

The contents of the accumulator are copied into the
memory location specified by the contents of the
Store accumulator operand (register pair). The contents of the accumulator
 STAX  Reg. pair
indirect are not altered.

Example: STAX B
The contents of register L are stored into the memory
location specified by the 16-bit address in the operand
and the contents of H register are stored into the next
memory location by incrementing the operand. The
 16-bit Store H and L contents of registers HL are not altered. This is a 3-byte
 SHLD
address registers direct instruction, the second byte specifies the low-order
address and the third byte specifies the high-order
address.

Example: SHLD 2470H

The contents of register H are exchanged with the
contents of register D, and the contents of register L are
Exchange H and L
XCHG  none exchanged with the contents of register E.
with D and E
Example: XCHG
The instruction loads the contents of the H and L
registers into
the stack pointer register, the contents of the H register
Copy H and L provide the high-order address and the contents of the L
 SPHL none registers to the stack register provide the low-order address. The contents of
pointer the H
and L registers are not altered.

Example: SPHL
The contents of the L register are exchanged with the
stack location pointed out by the contents of the stack
pointer register. The contents of the H register are
Exchange H and L exchanged with the next stack location (SP+1);
 XTHL  none
with top of stack however, the contents of the stack pointer register are
not altered.

Example: XTHL
 PUSH  Reg. pair Push register pair The contents of the register pair designated in the
onto stack operand are copied onto the stack in the following
sequence. The stack pointer register is decremented and
the contents of the highorder register (B, D, H, A) are
 copied into that location. The stack pointer register is
decremented again and the contents of the low-order
register (C, E, L, flags) are copied to that location.

Example: PUSH B or PUSH A

The contents of the memory location pointed out by the
stack pointer register are copied to the low-order
register (C, E, L, status flags) of the operand. The stack
pointer is incremented by 1 and the contents of that
Pop off stack to
 POP  Reg. pair memory location are copied to the high-order register
register pair
(B, D, H, A) of the operand. The stack pointer register
is again incremented by 1.

Example: POP H or POP A

 The contents of the accumulator are copied into the I/O
Output data from
 8-bit port port specified by the operand.
OUT accumulator to a port
address
with 8-bit address
Example: OUT F8H
Input data to The contents of the input port designated in the operand
 8-bit port accumulator from a are read and loaded into the accumulator.
 IN
address port with 8-bit
address Example: IN 8CH
 LOGICAL INSTRUCTIONS
Explanation of
 Opcode  Operand  Description
Instruction
The contents of the operand (register or memory) are M
compared with the contents of the accumulator. Both
contents are preserved . The result of the comparison is
shown by setting the flags of the PSW as follows:
R Compare register
 CMP or memory with
if (A) < (reg/mem): carry flag is set
M accumulator
if (A) = (reg/mem): zero flag is set
if (A) > (reg/mem): carry and zero flags are reset

Example: CMP B or CMP M

The second byte (8-bit data) is compared with the contents
of the accumulator. The values being compared remain
unchanged. The result of the comparison is shown by
setting the flags of the PSW as follows:
Compare
CPI 8-bit data immediate with
if (A) < data: carry flag is set
accumulator
if (A) = data: zero flag is set
if (A) > data: carry and zero flags are reset

Example: CPI 89H

The contents of the accumulator are logically ANDed with
M the contents of the operand (register or memory), and the
Logical AND result is placed in the accumulator. If the operand is a
R
register or memory location, its address is specified by the contents of
 ANA
memory with HL registers. S, Z, P are modified to reflect the result of the
M
accumulator operation. CY is reset. AC is set.

Example: ANA B or ANA M

The contents of the accumulator are logically ANDed with
the
Logical AND 8-bit data (operand) and the result is placed in the
 8-bit
 ANI immediate with accumulator. S, Z, P are modified to reflect the result of the
data
accumulator operation. CY is reset. AC is set.

Example: ANI 86H

 XRA R Exclusive OR The contents of the accumulator are Exclusive ORed with
register or M the contents of the operand (register or memory), and the
M memory with result is placed in the accumulator. If the operand is a
accumulator memory location, its address is specified by the contents of
 HL registers. S, Z, P are modified to reflect the result of the
operation. CY and AC are reset.

Example: XRA B or XRA M

The contents of the accumulator are Exclusive ORed with
the 8-bit data (operand) and the result is placed in the
Exclusive OR
 8-bit accumulator. S, Z, P are modified to reflect the result of the
 XRI immediate with
data operation. CY and AC are reset.
accumulator
Example: XRI 86H
The contents of the accumulator are logically ORed with M
the contents of the operand (register or memory), and the
Logical OR result is placed in the accumulator. If the operand is a
R
register or memory location, its address is specified by the contents of
ORA
memory with HL registers. S, Z, P are modified to reflect the result of the
M
accumulator operation. CY and AC are reset.

Example: ORA B or ORA M

The contents of the accumulator are logically ORed with the
8-bit data (operand) and the result is placed in the
Logical OR
 8-bit accumulator. S, Z, P are modified to reflect the result of the
ORI immediate with
data operation. CY and AC are reset.
accumulator
Example: ORI 86H
Each binary bit of the accumulator is rotated left by one
position. Bit D7 is placed in the position of D0 as well as in
Rotate the Carry flag. CY is modified according to bit D7. S, Z, P,
RLC  none
accumulator left AC are not affected.

Example: RLC
Each binary bit of the accumulator is rotated right by one
position. Bit D0 is placed in the position of D7 as well as in
Rotate the Carry flag. CY is modified according to bit D0. S, Z, P,
RRC none
accumulator right AC are not affected.

Example: RRC
Each binary bit of the accumulator is rotated left by one
position through the Carry flag. Bit D7 is placed in the
Rotate Carry flag, and the Carry flag is placed in the least
 RAL  none accumulator left significant position D0. CY is modified according to bit D7.
through carry S, Z, P, AC are not affected.

Example: RAL
 RAR   none Rotate Each binary bit of the accumulator is rotated right by one
 position through the Carry flag. Bit D0 is placed in the
Carry flag, and the Carry flag is placed in the most
accumulator right significant position D7. CY is modified according to bit D0.
through carry S, Z, P, AC are not affected.

Example: RAR
The contents of the accumulator are complemented. No
Complement flags are affected.
 CMA  none
accumulator
Example: CMA
The Carry flag is complemented. No other flags are
affected.
CMC  none Complement carry
Example: CMC
Set Carry
 STC  none Set Carry
Example: STC

 
 ARITHMETIC INSTRUCTIONS
Explanation of
Opcode  Operand  Description
Instruction
The contents of the operand (register or memory) are
added to the contents of the accumulator and the result is
stored in the accumulator. If the operand is a memory
 R Add register or
location, its location is specified by the contents of the HL
 ADD memory, to
registers. All flags are modified to reflect the result of the
M accumulator
addition.

Example: ADD B or ADD M

The contents of the operand (register or memory) and M
the Carry flag are added to the contents of the accumulator
and the result is stored in the accumulator. If the operand is
 R Add register to
a memory location, its location is specified by the contents
 ADC accumulator with
of the HL registers. All flags are modified to reflect the
M carry
result of the addition.

Example: ADC B or ADC M

The 8-bit data (operand) is added to the contents of the
accumulator and the result is stored in the accumulator. All
Add immediate to
 ADI  8-bit data flags are modified to reflect the result of the addition.
accumulator
Example: ADI 45H
The 8-bit data (operand) and the Carry flag are added to
the contents of the accumulator and the result is stored in
Add immediate to
the accumulator. All flags are modified to reflect the result
 ACI 8-bit data accumulator with
of the addition.
carry
Example: ACI 45H
The instruction loads 16-bit data in the register pair
 Reg. pair, Load register pair designated in the operand.
 LXI
16-bit data immediate
Example: LXI H, 2034H or LXI H, XYZ
The 16-bit contents of the specified register pair are added
to the contents of the HL register and the sum is stored in
Add register pair the HL register. The contents of the source register pair are
 DAD  Reg. pair to H and L not altered. If the result is larger than 16 bits, the CY flag
registers is set. No other flags are affected.

Example: DAD H
SUB  R Subtract register The contents of the operand (register or memory ) are
 subtracted from the contents of the accumulator, and the
result is stored in the accumulator. If the operand is a
memory location, its location is specified by the contents
or memory from
of the HL registers. All flags are modified to reflect the
accumulator
M result of the subtraction.

Example: SUB B or SUB M

The contents of the operand (register or memory ) and M
the Borrow flag are subtracted from the contents of the
accumulator and the result is placed in the accumulator. If
 R Subtract source
the operand is a memory location, its location is specified
 SBB and borrow from
by the contents of the HL registers. All flags are modified
M accumulator
to reflect the result of the subtraction.

Example: SBB B or SBB M

The 8-bit data (operand) is subtracted from the contents of
the accumulator and the result is stored in the accumulator.
Subtract
All flags are modified to reflect the result of the
 SUI  8-bit data immediate from
subtraction.
accumulator
Example: SUI 45H
The contents of register H are exchanged with the contents
Subtract
of register D, and the contents of register L are exchanged
immediate from
SBI  8-bit data with the contents of register E.
accumulator with
borrow
Example: XCHG
The contents of the designated register or memory) are
incremented by 1 and the result is stored in the same place.
 R
Increment register If the operand is a memory location, its location is
 INR
or memory by 1 specified by the contents of the HL registers.
M
Example: INR B or INR M
The contents of the designated register pair are
Increment register incremented by 1 and the result is stored in the same place.
INX  R
pair by 1
Example: INX H
The contents of the designated register or memory are M
decremented by 1 and the result is stored in the same place.
 R Decrement
If the operand is a memory location, its location is
 DCR register or
specified by the contents of the HL registers.
M memory by 1
Example: DCR B or DCR M
DCX  R Decrement The contents of the designated register pair are
register pair by 1
 decremented by 1 and the result is stored in the same place.

Example: DCX H
The contents of the accumulator are changed from a binary
value to two 4-bit binary coded decimal (BCD) digits. This
is the only instruction that uses the auxiliary flag to
perform the binary to BCD conversion, and the conversion
procedure is described below. S, Z, AC, P, CY flags are
altered to reflect the results of the operation.

Decimal adjust If the value of the low-order 4-bits in the accumulator is

DAA  none
accumulator greater than 9 or if AC flag is set, the instruction adds 6 to
the low-order four bits.

If the value of the high-order 4-bits in the accumulator is

greater than 9 or if the Carry flag is set, the instruction
adds 6 to the high-order four bits.

Example: DAA
 BRANCHING INSTRUCTIONS
Explanation of
 Opcode  Operand  Description
Instruction
The program sequence is transferred
to the memory location specified by
the 16-bit address given in the
16-bit Jump
 JMP operand.
address unconditionally
Example: JMP 2034H or JMP
XYZ
Flag
Opcode Description
Status
JC Jump on Carry CY = 1
Jump on no
JNC CY = 0 The program sequence is transferred
Carry to the memory location specified by
JP Jump on positive S = 0 the 16-bit address given in the
 16-bit Jump
JM Jump on minus S = 1 operand based on the specified flag
address conditionally
JZ Jump on zero Z=1 of the PSW as described below.
JNZ Jump on no zero Z = 0
Example: JZ 2034H or JZ XYZ
Jump on parity
JPE P=1
even
Jump on parity
JPO P=0
odd
Flag
Opcode Description
Status
CC Call on Carry CY = 1 The program sequence is transferred
Call on no to the memory location specified by
CNC CY = 0
Carry the 16-bit address given in the
CP Call on positive S=0 operand. Before the transfer, the
 16-bit Unconditional address of the next instruction after
CM Call on minus S=1
address subroutine call CALL (the contents of the program
CZ Call on zero Z=1 counter) is pushed onto the stack.
CNZ Call on no zero Z=0
Call on parity Example: CALL 2034H or CALL
CPE P=1 XYZ
even
Call on parity
CPO P=0
odd
 RET none Return from The program sequence is transferred
subroutine from the subroutine to the calling
 program. The two bytes from the
top of the stack are copied into the
program counter,and program
unconditionally
execution begins at the new address.

Example: RET
Flag
Opcode Description
Status
RC Return on Carry CY = 1
Return on no The program sequence is transferred
RNC CY = 0
Carry from the subroutine to the calling
Return on program based on the specified flag
RP S=0 of the PSW as described below. The
positive Return from
two bytes from the top of the stack
RM Return on minus S = 1 none subroutine
are copied into the program counter,
RZ Return on zero Z = 1 conditionally
and program execution begins at the
Return on no new address.
RNZ Z=0
zero
Return on parity Example: RZ
RPE P=1
even
Return on parity
RPO P=0
odd
 The contents of registers H and L
are copied into the program counter.
Load program The contents of H are placed as the
 PCHL  none counter with HL high-order byte and the contents of
contents L as the low-order byte.

Example: PCHL
The RST instruction is equivalent to
a 1-byte call instruction to one of
eight memory locations depending
upon the number. The instructions
are generally used in conjunction
with interrupts and inserted using
 RST external hardware. However these
0-7 Restart can be used as software instructions
in a program to transfer program
execution to one of the eight
locations. The addresses are:

Restart
Instructio
Addres
n
s
 RST 0 0000H
RST1 0008H
RST 2 0010H
RST 3 0018H
RST 4 0020H
RST 5 0028H
RST 6 0030H
RST 7 0038H
The 8085 has four additional
interrupts and these interrupts
generate RST instructions internally
and thus do not require any external
hardware. These instructions and
their Restart addresses are:

Restart
Interrupt
Address
TRAP 0024H
RST 5.5 002CH
RST 6.5 0034H
RST 7.5 003CH

 
 CONTROL INSTRUCTIONS
Explanation
 Opcode  Operand of  Description
Instruction
No operation is performed. The instruction is fetched and decoded.
However no operation is executed.
 NOP none No operation
Example: NOP
The CPU finishes executing the current instruction and halts any further
Halt and
execution. An interrupt or reset is necessary to exit from the halt state.
HLT none enter wait
state
Example: HLT
The interrupt enable flip-flop is reset and all the interrupts except the
Disable TRAP are disabled. No flags are affected.
 DI none
interrupts
Example: DI
The interrupt enable flip-flop is set and all interrupts are enabled. No
flags are affected. After a system reset or the acknowledgement of an
interrupt, the interrupt enable flipflop is reset, thus disabling the
Enable
 EI none interrupts. This instruction is
interrupts
necessary to reenable the interrupts (except TRAP).

Example: EI
This is a multipurpose instruction used to read the status of interrupts
7.5, 6.5, 5.5 and read serial data input bit. The instruction loads eight bits
in the accumulator with the following interpretations.

Example: RIM

Read
 RIM none interrupt
mas

SIM none Set interrupt This is a multipurpose instruction and used to implement the 8085
mask interrupts 7.5, 6.5, 5.5, and serial data output. The instruction interprets
the accumulator contents as follows.
 Example: SIM