Multiplex of Data and Address Lines in

8088
• Address lines A0-A7 and
GND 1 40 VCC
Data lines D0-D7 are A14
A13
2
3
39
38
A15
A16/S3
A12 4 37 A17/S4
multiplexed in 8088. A11
A10
5
6
36
35
A18/S5
A19/S6

These lines are labelled as A9

A8
AD7
7
8
9 8088
34
33
32
SS0
MN/MX
RD

AD0-AD7. AD6
AD5
AD4
10
11
12
31
30
29
HOLD
HLDA
WR
AD3 13 28 IO/M
– By multiplexed we mean AD2
AD1
14
15
27
26
DT/R
DEN

that the same pysical pin AD0

NMI
16
17
25
24
ALE
INTA
INTR 18 23 TEST
carries an address bit at CLK
GND
19
20
22
21
READY
RESET

one time and the data bit

another time
Multiplex of Data and Address Lines in
8086
• Address lines A0-A15 and Data lines D0-D15 are
multiplexed in 8086. These lines are labelled as
AD0-AD15.
GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 A16/S3
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD10 6 35 A19/S6
AD9 7 34 BHE/S7
AD8 8 33 MN/MX
AD7
AD6
9
10
8086 32
31
RD
HOLD
AD5 11 30 HLDA
AD4 12 29 WR
AD3 13 28 M/IO
AD2 14 27 DT/R
AD1 15 26 DEN
AD0 16 25 ALE
NMI 17 24 INTA
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET
Minimum-mode and Maximum-mode
Systems
• 8088 and 8086 microprocessors can be
configured to work in either of the two
modes: the minimum mode and the GND 1 40 VCC

maximum mode AD14

AD13
2
3
39
38
AD15
A16/S3
AD12 4 37 A17/S4
 Minimum mode: AD11
AD10
5
6
36
35
A18/S5
A19/S6

 Pull MN/MX to logic 1 AD9

AD8
7
8
34
33
BHE/S7
MN/MX

 Typically smaller systems and contains a AD7

AD6
9
10
8086 32
31
RD
HOLD

single microprocessor AD5

AD4
11
12
30
29
HLDA
WR

 Cheaper since all control signals for memory AD3

AD2
13
14
28
27
M/IO
DT/R

and I/O are generated by the microprocessor. AD1

AD0
15
16
26
25
DEN
ALE

 Maximum mode
NMI 17 24 INTA
INTR 18 23 TEST
CLK 19 22 READY
 Pull MN/MX logic 0 GND 20 21 RESET

 Larger systems with more than one

processor (designed to be used when a
coprocessor (8087) exists in the system) Lost Signals in
Max Mode
Minimum-mode and Maximum-mode
Signals

GND 1 40 VCC
GND 1 40 VCC
AD14 2 39 AD15
AD14 2 39 AD15
AD13 3 38 A16/S3
AD13 3 38 A16/S3
AD12 4 37 A17/S4
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD11 5 36 A18/S5
AD10 6 35 A19/S6
AD10 6 35 A19/S6
AD9 7 34 BHE/S7
AD9 7 34 BHE/S7
AD8 8 33 MN/MX Vcc AD8 8
8086
33 MN/MX
GND
AD7
AD6
9
10
8086 32
31
RD
HOLD
AD7
AD6
9
10
32
31
RD
RQ/GT0
AD5 11 30 RQ/GT1
AD5 11 30 HLDA
AD4 12 29 LOCK
AD4 12 29 WR
AD3 13 28 S2
AD3 13 28 M/IO
AD2 14 27 S1
AD2 14 27 DT/R
AD1 15 26 S0
AD1 15 26 DEN
AD0 16 25 QS0
AD0 16 25 ALE
NMI 17 24 QS1
NMI 17 24 INTA
INTR 18 23 TEST
INTR 18 23 TEST
CLK 19 22 READY
CLK 19 22 READY
GND 20 21 RESET
GND 20 21 RESET

Min Mode Max Mode

 8086 System Minimum mode
PCLK

+5V
Clock CLK M/IO
READY Control
generator INTA
RES RESET Bus
RD
AEN2 WR
AEN1
F/C MN/MX +5V

Wait-State ALE STB A0 - A19

Generator OE
Address Bus

8086 CPU
8282
AD0-AD15 Latch
A16-A19
BHE BHE

D0 - D15

8286 16
DT/R T
DEN OE
 8086 System Maximum Mode
+5V
MN/MX Gnd CLK MRDC
CLK
S0 S0
Clock READY MWTC
RES S1 S1

Bus Controller
generator AMWC
S2 S2

8288
RESET IORC
DEN IOWC
DT/R AIOWC
Wait-State ALE INTA
Generator

8086 CPU
STB A0 - A19
OE
Address Bus
8282
AD0-AD15
Latch BHE
A16-A19

T
OE DATA

8286
Transceiver
 Description of the Pins

GND 1 40 VCC
GND 1 40 VCC
AD14 2 39 AD15
AD14 2 39 AD15
AD13 3 38 A16/S3
AD13 3 38 A16/S3
AD12 4 37 A17/S4
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD11 5 36 A18/S5
AD10 6 35 A19/S6
AD10 6 35 A19/S6
AD9 7 34 BHE/S7
AD9 7 34 BHE/S7
AD8 8 33 MN/MX Vcc AD8 8
8086
33 MN/MX
GND
AD7
AD6
9
10
8086 32
31
RD
HOLD
AD7
AD6
9
10
32
31
RD
RQ/GT0
AD5 11 30 RQ/GT1
AD5 11 30 HLDA
AD4 12 29 LOCK
AD4 12 29 WR
AD3 13 28 S2
AD3 13 28 M/IO
AD2 14 27 S1
AD2 14 27 DT/R
AD1 15 26 S0
AD1 15 26 DEN
AD0 16 25 QS0
AD0 16 25 ALE
NMI 17 24 QS1
NMI 17 24 INTA
INTR 18 23 TEST
INTR 18 23 TEST
CLK 19 22 READY
CLK 19 22 READY
GND 20 21 RESET
GND 20 21 RESET

Min Mode Max Mode

RESET Operation results

CPU component Contents

Flags Cleared
Instruction Pointer 0000H
CS FFFFH
DS, SS and ES 0000H
Queue Empty
 S0, S1 and S2 Signals
S2 S1 S0 Characteristics
Interrupt
0 0 0
acknowledge
0 0 1 Read I/O port
0 1 0 Write I/O port
0 1 1 Halt
1 0 0 Code access
1 0 1 Read memory
1 1 0 Write memory
1 1 1 Passive State
 QS1 and QS2 Signals

QS1 QS1 Characteristics

0 0 No operation
0 1 First byte of opcode from queue
1 0 Empty the queue
1 1 Subsequent byte from queue
 Read Write Control Signals
IO/M DT/R SSO CHARACTERISTICS

0 0 0 Code Access
0 0 1 Read Memory
0 1 0 Write Memory
0 1 1 Passive
1 0 0 Interrupt Acknowledge
1 0 1 Read I/O port
1 1 0 Write I/O port
1 1 1 Halt
 TIMING SEQUENCE
AN EXTERNAL CLOCK GENERATOR DEVICE IS
CONNECTED TO 8086 TO PROVIDE CLOCK SIGNALS
THROUGHOUT THE SYSTEM.
ONE CYCLE OF CLOCK IS CALLED A STATE OR T-
STATE.
EACH BASIC OPERATION SUCH AS READING A
MEMORY LOCATION OR WRITING TO A PORT
REQUIRES SEVERAL STATES.THIS GROUP OF STATES IS
CALLED A MACHINE CYCLE.
THE TOTAL TIME REQUIRED TO FETCH AND EXECUTE
AN INSTRUCTION IS CALLED AN INSTRUCTION CYCLE.
AN INSTRUCTION CYCLE CONSISTS OF ONE OR MORE
MACHINE CYCLE.
BASIC SIGNAL FLOW ON 8086 BUSES

BASICALLY THERE ARE TWO OPERATIONS TO SEE:

1.READ OPERATION
2. WRITE OPERATION
WILL SEE WHAT IS GOING ON DURING THIS TWO
CYCLES OF OPERATION.
 READ CYCLE
HERE WE WILL SEE THE ACTIVITIES CARRIED OUT
ON 8086 BUSES AT VARIOUS TIME INSTANTS WHEN IT
READS FROM A MEMORY LOCATION OR FROM A
PORT.
HERE WE WILL ASSUME THAT THE 8086 IS OPERATED
IN IS MINIMUM MODE.
 T1 T2 T3 TW T4

CLK

M/IO

ALE
MEMORY ACCESS TIME
ADDR/
RESERVED VALID
A15-A0
DATA FOR DATA D15-D0

ADDR/
A19-A16
STATUS
RD/INTA
READY
DT/R
DEN
 WRITE CYCLE
HERE WE WILL SEE THE ACTIVITIES CARRIED OUT
ON 8086 BUS AT VARIOUS TIME INSTANTS WHEN IT
WRITES TO A PORT OR A MEMORY LOCATION.

HERE WE WILL ASSUME THAT THE 8086 IS

OPERATED IN IS MINIMUM MODE.
 T1 T2 T3 TW T4

CLK

M/IO

ALE

ADDR/
A15-A0 DATA OUT (D15-D0)
DATA
ADDR/
A19-A16
STATUS
WR
READY
DT/R
DEN
 8086 Memory Addressing

Data can be accessed from the memory in four

different ways:
• 8 - bit data from Lower (Even) address Bank.
• 8 - bit data from Higher (Odd) address Bank.
• 16 - bit data starting from Even Address.
• 16 - bit data starting from Odd Address.
 Treating Even and Odd Addresses

Higher Lower
Address Address
Bank Bank
(512K x 8) BHE (512K x 8) A0
ODD EVEN

A1-A19 D8-D15 D0-D7

Address Bus

Data Bus (D0 - D15)

 8-bit data from Even address Bank
Odd Bank Even Bank

x+1 x
x+3 x+2
x+5 x+4

BHE = 1 A0 = 0
D8-D15 D0-D7
A1-A19

D0-D15

MOV SI,4000H
MOV AL,[SI+2]
8-bit Data from Odd Address Bank
Odd Bank Even Bank

x+1 x
x+3 x+2

BHE =0 A0 = 1
A1-A19
D0-D7
D8-D15
D0-D15

MOV SI,4000H
MOV AL,[SI+3]
16-bit Data Access starting from Even Address
Odd Bank Even Bank

x+1 x
x+3 x+2

A0 = 0
BHE =0
A1-A19 D8-D15
D0-D7

D0-D15

MOV SI,4000H
MOV AX,[SI+2]
 16-bit Data Access starting from Odd Address
Odd Bank Even Bank Odd Bank Even Bank

0005 0004 0005 0004

0007 0006 0007 0006
0009 0008 0009 0008

A1-A19 A1-A19

A1-A9 A1-A9
D0-D7 D0-D7
D8-D15 D8-D15

(a) First Access from Odd Address (b) Next Access from Even Address

MOV SI,4000H
MOV AX,[SI+5]
 Read Timing Diagram
T1 T2 T3 Twait T4

CLK

AD0-AD15

BHE

ALE

S2-S0

M/IO

RD

READY

DT/R

DEN

WR
Write Machine Cycle
 INTR (input)
Hardware Interrupt Request Pin
• INTR is used to request a hardware interrupt.
• It is recognized by the processor only when IF =
1, otherwise it is ignored (STI instruction sets this flag bit).
• The request on this line can be disabled (or
masked) by making IF = 0 (use instruction CLI)
• If INTR becomes high and IF = 1, the 8086
enters an interrupt acknowledge cycle (INTA
becomes active) after the current instruction has
completed execution.
 For Discussion
• If I/O peripheral wants to interrupt the processor,
the “interrupt controller” will send high pulse to
the 8086 INTR pin.

• What about if a simple system to be built and

hardware interrupts are not needed;

What to do with INTR and INTA?

 NMI (input) Non-Maskable
Interrupt line
• The Non Maskable Interrupt input is similar to
INTR except that the NMI interrupt does not
check to see if the IF flag bit is at logic 1.

• This interrupt cannot be masked (or disabled)

and no acknowledgment is required.

• It should be reserved for “catastrophic” events

such as power failure or memory errors.
 8086 External Interrupt Connections
NMI - Non-Maskable Interrupt INTR - Interrupt Request

Programmable
NMI Requesting Interrupt Controller
Device (part of chipset)

NMI
8086 CPU
Intel
INTR
Interrupt Logic 8259A
PIC
Divide Single
int into
Error Step

Software Traps
 TEST (input)
• The TEST pin is an input that is tested by the
WAIT instruction.
• If TEST is at logic 0, the WAIT instruction
functions as a NOP.
• If TEST is at logic 1, then the WAIT instruction
causes the 8086 to idle, until TEST input
becomes a logic 0.
• This pin is normally driven by the 8087 co-
processor (numeric coprocessor) .
• This prevents the CPU from accessing a memory
result before the NDP has finished its calculation
 Ready (input)
• This input is used to insert wait states into
processor Bus Cycle.
• If the READY pin is placed at a logic 0 level,
the microprocessor enters into wait states and
remains idle.
• If the READY pin is placed at a logic 1 level, it
has no effect on the operation of the processor.
• It is sampled at the end of the T2 clock pulse
• Usually driven by a slow memory device
 8284 Connected to 8086 Mp

X1
Ready
X2
AEN1 CLK

8086 Microprocessor
AEN2
F/C 8284
Reset
RDY1
RDY2
RES
R
+5V
RESET KEY C
 HOLD (input)
• The HOLD input is used by DMA controller to
request a Direct Memory Access (DMA) operation.

• If the HOLD signal is at logic 1, the microprocessor

places its address, data and control bus at the high
impedance state.

• If the HOLD pin is at logic 0, the microprocessor

works normally.
 HLDA (output)
Hold Acknowledge Output

• Hold acknowledge is made high to indicate to

the DMA controller that the processor has
entered hold state and it can take control over the
system bus for DMA operation.
DMA Operation