circuit cellar COMPLEXITY TAMED BY LATEST PCB DESIGN TOOLS D Datasheet: IoT Interface Modules P FPGA and GPU Technologies for AI | ii, 97> Calibrating an MCU's RTC Using GPS | Tool Estimates IoT Battery Life | ill IW IoT Design Challenges | NTSC Video Racing Game | Simplifying FMEDAs | D SoundFont MIDI Synthesizer (Part 2) | Build the ChipJabber-Unplugged | Oil Tank Gauge Uses Ultrasonic Sensing ) The Future of Smart TelematicsYou can take it almost anywhere. a Ltt ii Pat MV os a ‘DRONE DESIGNS REACH PRO acessING WEI NR ERR cre eater Ue Reo Pee ee eC a RUS Cea mn ote iY ? a keep your CC Vault archive up to date by purchasing subsequent issues from our webshop or by downloading issues with a Circuit Cellar Digital iets CUMS ee ere ea CT Cee eet en et et eee i it cc-webshop.com to purchaseCall for Speakers & Sponsors Bae hae CecteiTleCli TEN eae eo MeL letter} September 1 & 2, 2020 - UC Irvine - Calit2 RO a oo Ce Ree Tee z, S| lag Og is ; coy Microsoft Ce aan President Ce ee ars AI, Machine Learning & HPC. paar cireniarieasio per ae www.SoGconference-comi Please submit your proposed abstract for 30-min technical presentation for the Technical Advisory Board review to: [email protected] Platinum Sponsors i *BLOCKCHAIN 5 & morecaNovocysummit SAVANT — (Tied Farhad Mafie, President & CEO, Savant Company Inc. & International SoC Conference Chairman, Moderating Three Informative Panels ‘= RISC-V Realities, Opportunities and Challenges in the Complex and Crowded CPU Market, circuit cellar * How AI and Machine Learning will Drive the Semiconductors Market to the Next Level. Is Blockchain of Things IoT 2.0? Could Blockchain of Things be the Security solution that the industry has been looking for? The SoC Conference Technical Advisory Board and Organizing Committee are seoking submissions on all aspects of IC & IP Design and Development, Emerging RF & THz Techniques, Semiconductor Technology, AI Chips, Machine Learning solutions, Mixed-Signal design, FPGA Solutions, eFPGA, ASSP, ASIC, Analog Design Techniques, High-Speed Interfaces and Challenges, High-Performance Transceivers, CPU/DSP/MCU Cores, RISC-V, GPUs, NPUs, Leading-Edge IPs, Digital Power Delivery & Clocking Circuits, Network-on-Chip (NoC), Leading Foundries Services, Sub 7 am Desig ges, Ulra-High-Speed Wireline. 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Contact Hugh Heinsohn ([email protected], Phone: 757-525-3677, Fax: 888-980-1303) to reserve space in the next issue of Circuit Cellar, THE TEAM PRESIDENT KC Prescott C4, 77 EDITOR-IN-CHIEF Jeff Child ADVERTISING COORDINATOR Nathaniel Black CONTROLLER Chuck Fellows SENIOR ASSOCIATE EDITOR Shannon Becker ADVERTISING SALES REP. Hugh Heinsohn FOUNDER TECHNICAL COPY EDITOR PROJECT EDITORS Steve Clarcla Carol Bower Chris Coulston Leyte: Ken Davidson David Tweed Grace Chen COLUMNISTS Jeff Bachiochi (From the Bench), Bob Japenga (Embedded in Thin Slices), Robert Lacoste (The Darker Side), Brian Miller (Picking Up Mixed Signals), and Colin O'Flynn (Embedded Systems Essentials) {issue 360 Duly 202 | 1580 252-0608 [RUT CLARE 1528-09 ene ety igh ire Prone OS ‘frealr smb ret ted oon oe esr of aon publied in cas HOR Mad Crp. 200 Prats inte Ute SaterGites case Highlighter Markers and X-Acto Knives hen I think about electronics technology, and its evolution through the decades, I can't help feel that there's something pretty neat about being in the Gen X generation—or just barely a Gen X in ‘my case. Us early Gen-Xers have had a vivid perspective on just how dramatically technology has changed over cur lifetimes. We lived through the start of computers becoming something a household could own and use Because I was born in the mid-60s, Iremember watching black and white TV as a kid, but also helping my dad choose which Intel 286 computer with monochrome ‘monitor to buy when I was a teenager. Two years later, T successfully sold him on the idea of upgrading to a 386 PC with color EGA monitor. This straddling between two eras of technology happened in my professional career as well. I went to Northeastern University as an EE major, and that school has a fantastic co-op program—both my father and my father-in-law did the co-op program there as well. The co-op system is where you alternate between semesters of school and a co-op job. The co-op job is, an actual paid job at a company in your field of study. Graduating with real job experience was a real leg up. During most of my years at Northeastern, my co- op job was at the same small company, a specialist in data acquisition boards. My entry level role was unofficially called “drafting dog" and it involved all sorts of mundane tasks such as making blueprint copies (remember blueprints?) of assembly drawings, updating parts lists databases and documenting ECOs (engineering change orders). The job evalved to include drawing schematics, ‘mechanical assembly drawings and other duties. was thinking about those days just recently while talking to PCB design tool vendors for this month's Special Feature. I remembered just how primitive PCB design was back in the mid-1980s. When T first started that co-op job, the company was only just starting to use PC-based PCB software to design and layout PCBS. Mind you, this was a small company and not able to invest in the state-of-the-art PCB CAD tools as early as larger firms. Before switching completely over to CAD tools, 1 remember we used X-Acto knives and red Rubylith tape to physicaly implement a PCB board layout that could then be used as photo master for a PCB production plate. Another memory I have of that time is the manual way we would do PCB "verifcation—verify that the PCB layout traces properly matched what was in the schematic drawing's circuit diagrams. How did we do it? Well, my boss Elaine would sit at her drafting table with the schematic blueprint. And I'd sit at my adjacent drafting table with the PCB layout blueprint. With our respective highlighter markers in hand, we'd then begin. laine would call out "PICI6-2 Pin 1 to 74LS157/4 Pin5"—or something lke that—and1'd use my highlighter to color the PCB trace that went from PICI6/2 Pin 1 to 741S157-4 Pin 5 and say "check." Elaine would then ‘mark those off on her schematic, and then call out the next one. Then, rinse and repeat for perhaps hundreds ‘of PCB traces, and the process could easily take an hour to complete for “complex” boards. And we're talking just 1- or 2-layer boards at most back then, There was something about this kind of repetitive exercise that made one's brain a little giddy and loopy by about 20 minutes in. Elaine and I called the phenomenon the “Checking Disease" because it often resulted in silliness, requiring a break to get back in gear. Fast forward to today, and doing PCB verification ‘may not be as "fun," but the tools continue to get more and more powerful. Certainly, PCB functions ike intelligent auto-tracing and sophisticated PCB verification are old hat, and have been so for decades. But, with today's PCB design tool technology, engineers can collaborate on PCB designs together over the Internet in realtime, design complete multi-board assemblies as complete units and even run simulations while you design. Today, for my part, I'm only experiencing these wonders as a technology journalist and not a user. Even so, once again it's pretty cool being Gen-Xer because I've had the privilege to witness technology evolve in such fascinating ways. ©49 TECHNOLOGY SPOTLIGHT FPGAs and GPUs Flex Their AI Muscles Chip-Level Supercomputing DATASHEET ToT Interface Modules Wireless Wonders 52 60 66 74 : PRODUCT NEWS Picking Up Mixed Signals Build a SoundFont MIDI Synthesizer (Part 2) The Firmware and Circuitry Embedded System Essentials Building the ChipJabber- Unplugged Old-School Glitching From the Bench Oil Tank Gauge Uses Ultrasonic Sensing Arduino in Action TECH THE FUTURE The Future of Intelligent Vehicle Telematics Telematics: The Auto Industry's Black Box 78 : TEST YOUR EQCalibrating an MCU’s RTC Using GPS Put Time on Your Side Tool Estimates IoT Device Battery Life BattLab-One ToT System Design Challenges Connected Complexities Build an NTSC Racing Video Game Using a PIC32 MCU Auto Design Safety Analysis: Reloaded Understanding and Simplifying FMEDAs SPECIAL FEATURE PCB Design Tools Up Their Systems Game Coping with Complexities TECHNOLOGY SPOTLIGHT FPGAs and GPUs Flex Their AI Muscles CChip-Level Supercomputing ey Getitor ce W cciccuitcetor Haid circvitcatorand long run ‘ometimes a microcontroller (MCU) design needs to track the time accurately. Applications range from periodically waking up the processor from a low-power sleep state, to ‘making measurements or performing some other task. Sometimes you need to maintain time and date, both as part of normal operation and in @ backup mode when some other form of time keeping is unavailable Most bedside digital clocks are accurate because they use the power line frequency (6042 in the US) to keep time. Although this tea 2768 1020p Many embedded applications require an accurate real-time clock (RTC). But rating an MCU’s internal RTC often requires expensive tes es. In this article, Stuart describes how you can use a low- cost GPS module to achieve a good RTC calibration in a short time. struments frequency can vary throughout the day, it is adjusted to be accurate over a 24-hour Period. Many of these clocks have battery backup in case of power failure. I had one several years ago with battery backup, but the one time it lost power, the time was off by several minutes the next morning. The battery backup just wasn't very accurate. There are several ways to keep accurate time in an MCU design. They include: * 60Hz power line * Add a GPS to the design * Connect to the Internet + 60kHz time signal from WWVB Al of these will work, and all have their drawbacks. Your equipment might be in a building where GPS reception is unavailable. You might not have an Internet connection available. Or you may just want to avoid the ‘cost of adding these extra parts to the design to get such timekeeping capability. And even with one of those, you may need a way to maintain accurate time during power outages ‘or loss of connection, THE CRYSTAL Many MCUs can use a standard 32.768kHz ‘crystal for timekeeping. But calibrating the crystal to maintain accuracy over days or weeks can be a challenge. The 32.76BkHz crystal has been around since the earliestrf a a ovation Drade oy sre [IRE tol ie ain = fs electronic wales. 1 fs osu lagely capacitors ar Op to 20F UL shown because a binary divisor of 32,768 (21) produces a 1Hz output. But, like all crystals, the common 32.768kHz crystal has limited frequency accuracy—typically #20ppm (parts peer million) at room temperature. This means that the frequency of any random crystal may vary from 32,767.3Hz to 32,768.7Hz. This is a tiny change, and for most crystal applications it is not an issue. But for a crystal in an RIC it matters 2 lot, because any error is ‘cumulative—it adds up over time. There are 604,800 seconds in a week, so a 20ppm error adds up to a timekeeping error of 12 seconds per week, In some applications, this is irrelevant. In others, it's important Figure 1 shows a typical crystal oscillator. For a 32.76BkHz crystal, typical values for the logic inverter, but it could also be a transistor amplifier or other amplification circuit. In some timekeeping devices, the frequency can be adjusted by making C1 or C2 a variable capacitor, and adjusting it manually. Depending on the application, the buil in accuracy of the crystal may be adequate. But in others, more accurate timekeeping is needed. The Texas Instruments (TI) TMAC ‘Arm MCUs have an input for a 32.768kHz crystal, which can be used to drive the RTC. The TM4C parts also include a calibration register to compensate for crystal inaccuracy. Figure 2 shows a partial block diagram of the TM4C RTC. This diagram illustrates how calibration works, so it doesn’t show every part of the RTC, such as the match = LS i EE Ic Ure Haste ; 4 d Lt. eseeg, Baa PPP PRT IoURE2 Simglifid Bock diagram of the TMICAZASD8 etme cock the mesciz305 sc inthe atl, 7rLouRES Poa ofthe GPS mele ud inthe registers or power control. The TM4C RTC is part of the hibernation module that includes features such as low-power deep sleep, wake ‘on interrupt, and other features to support low-power operation. For this discussion, only the RTC portion is important. The 32.768KHz oscillator drives a 15-bit prescaler that counts 0 to 7FFF to divide by 32,768 (0x8000), producing a 1Hz signal. This signal drives the RTC counter, which is just a 32-bit counter that can be read by the MCU. The RTC counts elapsed seconds, while date and day are calculated in software from the RTC count, if needed. Every 64 seconds, the contents of the trim register are substituted for the divisor. So, if the trim register contains Ox7FFF, the count is not altered. But if the trim register is set to ‘0x8004 (Ox7FFF + 5), then every 64 seconds the 1Hz output is extended by five periods of the oscillator. The effect is that every 64 seconds, the 1Hz signal is a little longer than normal. This compensates for the variation in the crystal frequency. A trim value less than Ox7FFF results in a shorter period, to compensate for crystals that are below 32.768kHz, and a value greater than Ox7FFF is for crystals that are faster than 32.768kHz. CALIBRATING WITH GPS The schematic of a TMACL23305 MCU with 2 32.768kHe crystal and a GPS module connected to itis shown in Figure 3. The GPS module is just an inexpensive unit purchased ‘on eBay, with an inexpensive GPS antenna attached (also from eBay). Figure 4 is a photo ‘of the GPS module. The GPS module has a serial interface and a 1PPS (pulse-per-second) ‘output. In this application, only the PPS signal is connected to the TM4C. Serial port O—on PAO/PAL of the TM4C— is used for programming the device and for sending the calibration information to 2 PC. ‘A jumper, W, is grounded to put the TM4C into programming mode. 32 i for an external RS-232 converter to connect to the host serial port, as described in my article "Debugging 278 qs a 1K dh alk). os ay sd to canna the THC board to the host Cor dounlating firmware and colecting caren output ea SeraPROTEUS ~w ny = High Speed Design Features Selmore} Oe erm Mae} + Length Matching / Net Tuning »* Use for USB, Ethernet, DDR3 etc. the price premium. erica by: EDASIM, LLC. AEC Bote) ily [email protected] www.labcenter.comEmbedded systems with Minimal Resources” (Circuit Cellar 312, July 2016) [1]. Figure 5 is a schematic ofthe programming adapter. ‘Athough the GPS module is inexpensive, the 1PPS signal from the GPS is accurate, because it is derived from the atomic clock on the GPS satellites. All the expense needed for this accuracy embedded in the satellites is courtesy of American taxpayers. That accuracy is used as the standard for calibrating the RTC on the THAC. The key to this calibration technique is that the divide-by-32,768 prescaler resister inthe RTC can be read by the CPU, Calibration is performed by counting how many cycles af the crystal oscillator occur in one GPS PPS Period. With the trim registor sot to Ox7FFF the prescaler divisor in the TMAC is 32,768. The difference in prescaler counts between successive PPS signals indicates the crystal's accuracy. The calibration firmware causes the CPU to read the count in the prescaler register every ten PPS signals. The count of 10-second PPS intervals, the RTC register value and the content of the prescaler register are sent to the host via the serial port. You can capture the serial output with a terminal program such as PUTTY. The actual serial port output looks like the following (with header line in bold added above the output to identify the three value Crystal Parameters Crystals have many parameters, but for the purposes of this article, here are the ones that are relevant for 32.768kHz crystals: Turnover temperature: The temperature at which the crystal is closest to its nominal frequency. Typically, 25°C with #5°C variation (so it ‘can be 20°C to 30°C, with a nominal value of 25°C). Operating temperature: Temperature range over which the crystal can safely operate. Typically -10°C to 50°C Frequency tolerance: Frequency variation at turnover temperature, typically £20ppm, but ranging from Sppm to 100ppm depending on manufacturer and crystal part number. You can think of this as being like the tolerance of a resistor, except that it's measured in parts per million instead of percent. Parabolic coefficient: The amount the frequency varies with the square of temperature difference from nominal temperature. Typical value is 0.040ppm, +0.005ppm, per °C2. So, with tolerance included, a temperature change of 10°C might result in a frequency change from 3.5ppm (100 x .035) to 4.5ppm. Recommended load capacitance: The capacitance from the terminals to ground in a typical MCU circuit. Typically, 12pF to 15pF. Note that in a typical MCU circuit with one capacitor fram each terminal to ground, the capacitance at the crystal terminals is the series capacitance of the two Capacitors, Two 20pF capacitors have a series capacitance of 10pF. PPS RTC RTC prescaler (000.0001: 0009-0000.1A02 (000.0002: 0013-0000.1424 (000.0003: 001D-0000.1447 == Snipped lines for brevity == (000.0081: 0509-0000.2857 All values are in hex. Therefore, for the first output, the PPS count is 1 (indicating that ten PPS signals have occurred), the value in the RTC register is 9 and the divisor count is Ox1A02. Ten seconds later, the divisor count is Ox1A24. If the crystal were exactly 32.768kHz, the divisor count would be 1AD2 fon every output (maybe £1). But this crystal frequency is high, so the divisor count is running faster than the 1PPS GPS signal, by about 34-35 counts every 10 seconds. The final output is shown below the first three, By the time 1,280 seconds (0x80 x 40) seconds have elapsed, the divisor count is 0x2B57. The total difference is 0x2B57 ~ Ox1A02 (11,095-6,658), or 4,437 counts in 41,280 seconds. In reality, it could be very close to 4,436 (11,095.0 ~ 6,658.99) or 4,438 (11,095.99 ~ 6,658.0), but 4,437 is as close as we can get. Each divisor count is 1 cycle of the 32.768kHz clock, so the total error is 4,437/1,280 or 3.46 cycles per second. This means the crystal is really operating at about 32,771.46Hz2. This is an error of 3.46/32768 * 106 or 105.7ppm. This is just a generic crystal so I don't have the specifications for it, but it’s probably a 100ppm part. It’s also possible that the 15pF capacitors are the wrong value for the part, although the TM4C1233D5 specifies a minimum load capacitance of 12pF. If used in a digital clock, this crystal would result in an error of about 64 seconds per week (24 x 7 x 3,600 x 105.778/106). To correct this error, we need to set the TMAC RIC trim register to @ value greater than Ox7FFF, so that it slightly retards the 1Hz clock every 64 seconds. In the 1,280 second sample interval, 1280/64 = 20 corrections will occur. We need a total of 4,437 counts to be removed from the crystal output every 1,280 seconds, so each correction must be 4437/20 or 221.85 counts per correction. Rounding up gives 222 counts per correction. We can‘t quite get to Oppm, but the result will be a lot better. With a correction, the count will be adjusted by 222 x 20, or 4,440 counts over the 1,280-second measurement period. This will make the clock about 3 counts slow over 1,280 seconds, instead of 4,437 counts fast. Three counts over 1,280 seconds is 0.071ppm, or .043 seconds per week (a bit ‘over 2 seconds per year). Again, it could be that we need something closer to 4,436 or 4,438, but 4,440 is as close as we can get.The output of the circuit after the trim the circuit continue to run for 5,120 seconds register is set to 32,989 (Ox7FFF + 222) looks and it resulted in the same -0.i9ppm error. like this: Given the 2-count ambiguity in the needed correction, this is very good. Trim corrections PPS —RTC_RTC prescaler of 221 and 223 would be worse, and an error (000.0001: 0009-0000.1388 of 0.115 seconds/week is 500 times better (000.0002: 0013-0000.13E than the original 64 second-per-week error. (000.0003: 001D-0000.1400 If the error had been the other direction— (000.0004: 0027-0000.1423 with the crystal 4,437 counts low over 1,280 (000.0005: 0031-0000.1445 seconds—then the trim adjustment of 222 (000.0006: 0038-0000.1468 would be subtracted from Ox7FFF, resulting in (000.0007: 0045-0000.13AD <- Trim adjust _a trim value of 32,545. ~- Snipped lines for brevity ~~ (000.0081: 0509-0000.1383 PRACTICAL USE This method allows you to calibrate the You can see that the first six outputs (60 TMC RTC relatively quickly. In a production seconds), the divisor value increases as it did environment—where you mightbe calibrating before, about 35 counts every 10seconds.Butby 10 or 100 units ata time—you would have one the 70-second mark, itis reduced significantly. GPS module driving all the circuits (through In that interval, the first 64-second correction appropriate buffers, of course), so they could was applied. The ending count isnt quite the all be calibrated in about 20 minutes. same as the starting count, because the RTC In this case, I did all the calibration Counter continues to run for S seconds between calculations manually, and then changed the the correction at 64 seconds and the output of trim value in the source code and recompiled the next sample at 70 seconds. it. In a production environment, you would By thetime 1,280 seconds have elapsed, 20 store the trim value in the TM4C EEPROM, corrections have been applied, and the divisor so the code could be the same on all the count is 0x13B3, which is an error of -8 counts boards. You could even perform the trim or -0.19ppm or -0.115 seconds per week. Ilet value calculation in the TMAC, itself, with Preset email: [email protected] Sle mes TCL 7203 Here)YourDesign|omesjirue! One-stop Electronics Manufacturing Service -PCB Fabrication -BOM Kitting -Testing We do much more. -Design Checking -PCB Coating -MCU/CPLD/FLASH/EEPROM Programming iret ee error certs taes treet er sere) -Printing -Labeling -Packaging -Certification -Stocking -Distribution -Shipping -Customs Declaration Ds ee Ae ae aa2 PPM Error 25 50 75 t Tumover temperature sarin frm the For detailed ar ture POM err oferta, The PP ror increase wth the quae of the temperate no need for the serial port connection. Once calibrated, the operating firmware would read the trim value from the EEPROM and set the trim register at startup. It is important to note that the purpose of the trim register isn’t to force the prescaler to be correct on every one-second interval. Rather, it is to periodically adjust the prescale value, so the long-term value of the RTC register—counting 1Hz clocks— is correct. There will be short-term errors, since the 1Hz clock is still wrong 63 out of every 64 seconds. TEMPERATURE The calibration so far was all performed at one temperature. But the crystal frequency varies with temperature, so for accuracy over a wide temperature range, you need temperature compensation. The variation in frequency is @ parabolic curve, with the nominal (or turnover) temperature at the peak of the curve, and the frequency accuracy (in ppm) changing on either side of that midpoint. Parts per million varies with the square of the temperature difference from nominal. As illustrated in Figure 6, a iele references and additional resources go to: worw.circulteellaricom/article-materials Reference [1] as marked in the RESOURCES ECS | wow.ecsxtalicom ticle can be Found there. Maxim Integrated | www.maximintegrated.com Texas Instruments | wwwati.com temperature of 0°C corresponds to an error of 25ppm. The crystal T used was just a generic part and I don’t know the temperature Coefficient, but a typical value is about 0.040ppm ‘per degree squared. So, with a nominal (turnover) temperature of 25°C, 2 temperature drop of 3°C (down to 22°C) would result in a variation of 32 x .040, or 0.36ppm. Not a lot, but if the temperature swing is 10°C, the error would be increased by 2.4 seconds per week. In a car, where temperatures can range fram below freezing to over 30°C, the accuracy can therefore vary considerably. In many applications, you probably don't need to worry about temperature. If you wanted to build a homemade digital alarm clock, room temperature is fairly constant, so temperature compensation typically is not needed. This is especially true if the 60Hz line frequency is used for timekeeping, and the RTC is just for battery backup. With such clocks available for around $10, you probably wouldn't build your own, although I think it would make a good senior project for an EE student. As a project, it contains a lot of the system, circuit and firmware trade-offs of a more complicated design, but at 2 student- manageable level of complexity. If your application does need temperature compensation, then you need to add a temperature sensor tothe circuit. Youcanthen characterize the temperature characteristics of the crystal by using the same method to measure the uncalibrated crystal error, but do it at different temperatures. You then store a table in the TM4C EEPROM of the trim value for each temperature band. However, creating the table requires some kind of ‘oven to hold the temperature of the circuit constant while taking the measurements. Another way to compensate for temperature is to calculate a new trim value, based on the original trim value, the temperature and the crystal manufacturer's ppm-to-temperature specification. You still need a temperature sensor, and this is less accurate, because the temperature variation of the crystal frequency has its own tolerance. But it may be close enough, depending on your application, and it eliminates the expense and calibration time of using an oven. There are also other ways to get temperature compensation. Instead of using an RTC crystal, you can use a temperature controlled oscillator, such as the ECS XC315ECT, which is a CMOS temperature compensated oscillator. That, of course, obviates the entire purpose of this article, but it’s an easy solution if it fits yourapplication. The Maxim Integrated DS3234 RIC contains a TCXO, time/date calculation and SPI interface in a single package. OTHER MCUs The calibration method I've illustrated here is unique to the TITM4C family of parts, which has the ability to directly read the RIC prescaler value. But the same process could be applied to any MCU that will allow the crystal oscillator to drive an internal or external timer. The Microchip Technology ATmegaxx08 parts can drive a CLKOUT pin from the 32.768kHz oscillator, which can then be used to drive an internal timer/counter, or even an external timer in another MCU With the GPS PPS signal on an input pin, the same method used on the TM4C part can be used on these and similar parts. Note that some MCUs support use of a 32.768kHz crystal, but do not have any way to compensate for variations in crystal frequency. There isn’t anything you can do about those, except pick a good crystal or make periodic corrections to the RTC counter itself in firmware. You can also read the crystal frequency and calculate the trim value from that. You can’t connect directly to the crystal, since that will change the frequency. If you can’t program the crystal output to drive an output pin, you would have to build a buffer for one of the crystal pins and add it to your design. However, design of such a buffer is tricky, because the pins aren’t logic-level voltages, and the impedance has to be high. One drawback to measuring the frequency directly is that the frequency counter has to be more accurate than the accuracy you need from the RTC. Generally, such counters will be expensive, CONCLUSION ‘Sometimes you need an accurate RTC. Calibrating 2 32.768kHz crystal in an MCU RIC often requires expensive test equipment and long run times. But using an inexpensive GPS module and taking advantage of the ability to measure the period of the RTC prescaler, you can get good calibration in a short time. © ABOUT THE AUTHOR Stuart Ball is a registered professional enginee! has more than 30 years of experience in e! a principal engineer at Seagate Technologies. ENA TO " a BSEE and an MBA. He jn. He is currently Designing with Passion. Engineering with Precision. Working together to design the ideal display for your application. Let's get started an your next projectTool Estimates IoT Device Battery Life — BattLab-one Protte: Votage = 4:2 vos, Time = 123 seconds Seenhot othe BatLab-Ore user interface, showing apt with competed same current eof nd a estimate tery We Estimating the battery life of a device can be a daunting task. With that in mind, Doug set out to design and build a tool that easily provides an estimate of battery life for his projects. He steps through each element of his design ig current profiling, battery emulation, Python software development and more. process, inclu 's anyone who has ever designed battery-powered devices can attest, many factors determine battery life. They — include battery chemistry, number of cells, hardware component selection, processor sleep current, firmware active events (such as wake up, read sensor, process information, transmit/receive data) and time between active events—not to mention other environmental factors, such as temperature, aging and charging lifecycle. Inmy experience building battery-powered devices over the past few years, T have learned that the process of measuring and estimating battery life can be labor intensive. The process is tedious, with multiple test ‘equipment arrangements to capture current profiles for different firmware states, manual data logging, and spreadsheets for data input and calculations, to get to an estimate of battery life for my device under test (DUT). I needed a better way, which drove me to build the BattLab-One (Battery Laboratory). My goal was to deliver a design tool that quickly and effortlessly provides an estimate of battery life for my projects, enabling me to ‘spend more time on design and less time on measuring and calculating battery life. PROBLEM STATEMENT Capturing and profiling current on battery Powered devices can be challenging due tomany factors. Typically, the DUT has @ large dynamic current consumption range—from hundreds of nanoamps in deep sleep mode to hundreds of milliamps during active events. In addition, many rapid current transitions and long periods between active events can add to the complexity of determining battery life, Understanding how different aspects of the DUT firmware affect battery life requires capturing each firmware state separately (processor wake-up, wireless transmit/receive, sensor read, data processing and so on) Traditional test methods, such as a multimeter or an oscilloscope with sense resistor, can get the jab done, but can be time consuming and cumbersome. Because I'm working with battery-powered voltage levels, multimeter burden voltage often becomes an issue. It's also cumbersome and may have limited data-logging capabilities (depending on your multimeter). An oscilloscope with a current shunt resistor helps, but again, it’s cumbersome and lacks the “what-if” analysis capabilities I need. It becomes tiresome to have to plug the captured current profiles from these separate acquisition methods into a spreadsheet and then calculate an estimated battery life. OF course, products designed specifically for this type of measurement are available, but they ‘can be quite pricey. Solutions like the Keysight CX3322A Device Current Waveform Analyzer (1} cost well aver $20,000 at the time of writing this article. It has incredible specifications and features, but it is way outside my budget! While these more ‘expensive solutions provide amazing results, my personal projects (and budget) drove me toa simpler, less expensive, faster solution to get a reasonable estimate of battery life. The BattLab-One allows me to get to an estimate quickly, tweak my design parameters, and come up with a new approach to meet my product design goals. DESIGN APPROACH Estimating battery life requires the ability tocapture current profiles during active events, sleep made current, a method for capturing the long intervals between active events and a model for calculating battery life. In addition, providing the ability to identify high impact (in terms of battery consumption) firmware states and comparisons of previous current profiles is extremely helpful. Finally, an ideal solution would provide the ability to optimize a design by tweaking the variables and do “what-if” analysis scenarios on the project's battery life. Essentially, i's a software laboratory for batterylife estimation. My idea was to develop a battery emulator that I could use to power my device under test, and capture current profiles directly from the power supply unit (PSU), emulating the battery voltage. My overall approach was to design a data acquisition device connected ‘via USB to a PC for data logging, and with an ability to do “what-if” analysis on my captured current profiles. In the process of designing my solution, 1 learned there's a reason why accurately measuring and auto-ranging across a 140d8 dynamic current range is so difficult. My goal was to develop a tool that would get me to a “reasonable” estimate of how long my DUT (device under test) would live in the wild without breaking the bank. So instead of a 140dB dynamic range, I decided on a smaller, 74¢8 dynamic range. Capturing current profiles from the 500mA down ta the 100A range would meet the characteristics that most of my battery-powered devices typically consume. The S00mA upper bound represents about 13 0.2C discharge rate for a typical lithium-ion (Li-ion) 18650 battery, about 0.3C for typical ‘AA batteries and 0.7C to 0.9C for AAA alkaline batteries. The 100A on the lower end ensures there's enough room within an ADC's dynamic range. That gave mea more reasonable 5000:1 dynamic range (7448) to work with. The upper bound was perfect for me, since many of my projects use the Espressif Systems ESP8265 Wi-Fi chip for communication, so 1 could capture the 4300mA spikes for transmitting and receiving on Wi-Fi. The distribution of the rest of my DUT power budget is usually in the hundreds of microamps to tens of milliamps range for reading sensors, driving logic and doing some calculations on the processor. While sleep current can be the most important determinant of battery life, it's typically just a single value that occurs over long stretches of time. The nature of sleep current meant that instead of designing a complex auto-ranging feature, I could use a manual approach. I decided to deploy a software-selectable sense resistor to capture sleep currents (tens of nanoamps to tens of microamps), and I provided a field for entering the sleep interval time manually. With the dynamic-range approach resolved (or at least rationalized), 1 focused on other areas of process improvement. I thought a feature to enter a pre-determined capture duration, from 1 second up to many hours (dependent on PC disk space), and the ability to trigger the BattLab from the DUT firmware or other external source would give the user greater flexibility for data logging. The trigger feature allows the user to see the effects of iferent firmware states on overall battery life. I also decided on a feature to save and compare profiles and do “what-if” analysis. A screenshot of the BattLab-One user interface is shown in Figure 4.6 HARDWARE SOLUTION I decided to architect my current sensing solution around the Texas Instruments (TT) 1NA233 chip. It's high-side/low-side current, voltage and power monitoring device with 2 16-bit delta-sigma ADC and I2C for control It provides data capture of shunt voltage and bus voltage, plus calculated power output. It has 2 9648 dynamic range, user-selectable ADC conversion rate (from 140s to 8.244ms) and a sampling averaging feature, Tt requires an external shunt resistor, and [ am using 2 0.109 sense resistor to meet my dynamic range specification (more on that short). To capture the sleep state of my DUT, 1 added a MOSFET to switch in a 1009 sense resistor (via software) and then prompt the user to manually enter the sleep interval in the user interface. The MOSFET Rosoy actually adds to the overall sense resistance, or a total of about 0.159 (the 0.109 sense resistor plus the 0.050 Rysoy of the MOSFET). This gives me a worst case (at 500mA) burden voltage of 0.075y, which represents about 6.25% at 1.2¥ output (0.075/1.2 x 100), and a 1.7% burden voltage at 4.5V output (0.075/4.5 x 100). The {good news is, since I’m controlling the output voltage, I can tweak the 1.2V output to about 1.25V to alleviate some of the burden voltage Impact at the low-voltage ranges. used a TI MSP430G2553 MCU as the main processor and an FT232RI from FTDI Chip for UART-to-USB translation for communication with the PC. The MSP430 supports I°C and is Plenty fast enough at 16MHz I used the 3.3V LDO of the FT232RL for powering the MSP430 ‘and other logic on the primary side (USB side) ‘of the PCB. Digital isolation (power and data) is important and something to be mindful of when using USB to power your projects. Dave Jones provides a great video blog on "How not to blow up your oscilloscope,” which is related to this issue [2]. The video is posted on Circuit Cellar’s article materials webpage. For the power supply that emulates the battery for the DUT, I used an AP2318, which isan adjustable LDO linear supply from Diodes Incorporated. The AP2318 supplies 600mA, but in practice BattLab can provide only about 450mA of continuous current at the various output voltages—t.2V, 1.25V, 1.5V, 2.4V, 3V, 3.6V, 3.7V and 4.5V. The selectable voltages ‘emulate combinations of up to three AA or AAA (alkaline, NiMh, NiCd) batteries or a single cell Li-ion battery (CR2032 or 18650). To power the components on the secondary isolated side of the board, I used a TI SN6505 DC-DC converter and a Wurth | = r | ree ert ida vrouRe2 Sererate oF Bat. OneElektronik 750315371 transformer to provide ‘a +5V, approximately 500mA power supply. Since T kept the MSP430 on the primary isolation side of the board, I needed to add a TI 1501540 for PC signal isolation. I used a TI 1507742 4-channel digital isolator for other isolated logic. I used one channel of the 1507742 for the MSP430, to control the gate on the MOSFET for switching the 1009 sense resistor, one for controlling the AP2318 (turning on and off the power supply output to the DUT), one from the DUT to the MSP430 for triggering, and one extra channel just in case need it in the future. The AP2318 has a dropout voltage of 0.35V at the maximum rated output current, so the ‘maximum 4.5V output just fits just within my USB +5V power budget (5 - 0.35 = 4.65V). T used an Analog Devices AD5248 dual digital potentiometer as the adjustment resistors to set the LDO output, again using I2C for control ‘As mentioned earlier, Iam often powering ‘an ESP8266 device for my projects, so I placed aa beefy 1000uF output capacitor to handle the power-surge demand of that device. It does ‘cause some RC time constant issues when re~ setting from a large PSU output voltage (4.5V) to a lower PSU voltage setting (1.2V), since it takes a while for that capacitor to discharge. Figure 2 shows a schematic of the BattLab- One and Figure 3 shows the completed hardware. THE SOFTWARE The PC application software for BattLab is written in Python 3.6 using the Tkinter GUI toolkit. All the graphing is based on ‘Matplotib, which has a great navigation bar at the bottom to let you zoom in/out, pan, return home, navigate and even save the current profile graph as an image file, The MSP430 firmware is written in C and can be updated, since I've brought the MSP430 ground, Test and Reset pins out to a header. You can use a TI Launchpad to program it, The software is intended to be intuitive, and basically walks the user through a four- step process: Step 1. Step 1 prompts the user to set the battery type, quantity, DUT cut-off voltage, and capacity of the battery cells you will be supplying as power output to your DUT. Effectively, you're setting the output voltage of the BattLab’s PSU to power the DUT. The user then clicks the On button to turn on the PSU. Step 2. This step has the user select the amount of time for the profile capture (1 second through many hours, depending ‘on your PC's disk space) or have it triggered by the DUT. If triggering is selected, BattLab waits for 2 low-to-high event on the trigger port to start the capture, and then a high- to-low event to stop it. You'll need a spare pin on your DUT processor to start and stop the trigger. You'll also need to program your firmware to trigger the pin. The input trigger can accept +3.3V to +5V, and has input protection. The user then clicks the Capture button to start capturing the current profile of the DUT. ‘Step 3. After you've captured the current profile of the active states of your DUT in Step 2, Step 3 prompts the user to capture the sleep current. Basically, the BattLab switches in the 1002 sense resistor to measure current at the nanoamp scale. BattLab assumes you've put your DUT into sleep mode to capture this data. The application then prompts the user to enter the sleep interval between active events. Step 4, This is the fun part. Once the battery profile data has been captured in Step 1, and the active and sleep event current profiles have been captured in Steps 2 and 3, an estimate of your battery life is presented. You can select and alter all variables in “what- if" scenarios to see how the battery life would compare to the captured profile. You can save profiles and compare multiple graph outputs in the chart. A plot with a completed sample current profile and an estimated battery life is shown in Figure 1. The INA233 ADC is multiplexed to take two voltage measurements for each ADC conversion, Vsjuyr and Vays. I am only using Veyuyr readings in Release 1 of the BattLab. Unfortunately, there is no way to turn off the Vays read time. This means I must add the additional Vays conversion rate to the Vsyunr conversion rate. I set the ADC conversion rate for both Vsyyxr and Vyys to 140ys for a total single capture rate of 280s. iguRE 3function read_sensors() gplo.write(4, gpio.HIGH) -- Trigger BattLab-One to start capturing data doorstatus = gpio.read(6); temp = 0 for i=1,3,1 do temp'="temp + ade.read(0) end tempc = ((temp/3)-500)/10 tempF = ((tempC*9)/5) +32 voltage = ade.read(0)/1024 return doorstat, volt, tempFs gpio.write(4, gpio.LOW) end usrnes Aad spet used fr rer he tab-One i my La cade for Te espe Te fixed the number of averages to 4 per sample, so the overall the capture rate is about 960s (280ys x 4). Add another 80s to 100ps to transfer the 2-byte sample via I2C to the MSP430, and the BattLab is operating at about a 1kHz sample rate. Is it possible that BattLab will drop some short duration current spikes? Yes, for sure, But it’s proven fast enough to get a reasonable estimate of battery life. To calibrate the BattLab, I use several precision current sources (1O0nA, 100A and 100mA) and set a calibration factor within the MSP430 firmware. REAL-WORLD EXAMPLE T recently designed 2 device that tweets out (to my own private Twitter account) the status on my garage door (open or closed plus temperature and humidity of the garage) Since my DUT uses a Li-ion battery (18650), chose 4.2V (fully charged 18650) for Step 1. My cutoff voltage is 3.4¥, and I then enter the battery capacity of my Li-ion (2,300mA~ For detailed article references and additional resources go to: .circuitcellar.com/article-materials References {1] through [3] as marked in the article can be found there. RESOURCES Analog Devices | vaww.analog.com Diodes incorporated | wwn.diodes.com Espressif Systems | wivn.espressificom FIDL Chip | woweftichip.com Keysight Technologies | wort eysight.com Texas Instruments | www.ti.com Worth Elektronik | vavs.we-online.com Trigger BattLab-One to stop capturing data hours) and turn on the PSU. In Step 2, instead of setting a duration for capture time, I used a spare pin on the ESP8266 module to trigger the BattLab to capture the current profile, from when the unit boots up until sleep made. I connect my DUT to the BattLab and then click Capture, turn on my DUT—wiich triggers the BattLab— ‘and the resulting current profile is plotted. A code snippet used for triggering the BattLab- ‘One in my Lua code for the ESP&266 is shown in Listing 4—in this case, the firmware event for reading the sensors. Next, the software prompts the user to capture the sleep current of the DUT. I make sure the unit is powered and my device is in sleep mode. (It should be, given that I've completed Steps 1 and 2.) select the Capture Sleep button and BattLab captures data over ‘25 second duration and averages it over that time. For my sleep event interval, I entered 71 minutes (4,250 seconds), since 1 use the maximum sleep time of the ESP8266. Finally, the fun part. In Step 4 T click Analyze and my estimated battery life is displayed in days and hours. Ican now adjust parameters such as sleep duration, type and capacity of battery, temperature, sleep time ‘and so forth. Ican save and compare profiles to use for my design goals. Using the BattLab ‘on_my garage door sensor enabled me to quickly understand the firmware and other design changes on my product's battery life. IDEAS FOR FUTURE ENHANCEMENT Ideas for new features would be to leverage more of what the INA233 provides. Today I am only capturing the shunt voltage from the INA233 device through my sense resistor. 1 ‘would like to integrate with the SMBus moreiouRE4 The fished Satlab-One tightly, to get the Vays and power measurements from this device. 1’ also like to allow the user to set the averaging mode used and the ADC conversion time. Currently, the BattLab uses a default discharge rate (based on the average current profile) and a percentage of the entered value for battery capacity (based on the DUT cutoff voltage). In the Future, I would like to include a battery specification library, based on real-world testing of multiple battery types over time. The idea ‘would be to capture the discharge profile by changing multiple variables—such as. average current consumption, temperature and humidity—and capturing statistics ‘over multiple battery types. This would provide BattLab with a look-up table of values to draw from to improve the accuracy of the battery-lfe estimation. In addition, I would like to add more advanced triggering capabilities. One thought is to use a positive edge trigger to start the capture of the Wake event of the DUT (as it does now). Then, on the negative slope trigger event (the last active state before deep sleep mode), it could auto-enable my 1009 sense resistor for capturing sleep current. The auto-range speed is not as important in this scenario, since the sleep mode typically lasts for minutes to hours. One of the unplanned benefits of the BattLab-One is that it makes a decent USB-icolated power supply with a 0.8V to 4.5V output at approximately 450mA. In the future, I may provide more selectable voltages, rather than just those associated with specific battery types. This would make the BattLab more usable ‘as a general-purpose, mobile power supply. IN CONCLUSION The finished product of the BattLab-One device is shown in Figure 4. For me, this was an extremely successful project. I learned a lot on the journey, and was able to develop a tool that I can use to quickly estimate battery life for my battery- powered designs Tam currently in the process of getting my design approved for the Open Source Hardware Association (mww.oshwa.org), because I think the BattLab-One could be a great platform for other projects. In the meantime, my source code, schematics and board layout are all available on my GitHub site [3]. If you have interest in this project, please feel free to reach out to me by email at dpeters@ bluebird-labs.com. © ABOUT THE AUTHOR Doug Peters is the Founder of Bluebird Labs, LLC in Eden Prairie, MN. He has @ BS degree in Electrical Engineering from Northeastern University in Boston, MA. and an MS certificate in Applied Statistics, from Penn State University. He warked for 10 years at GE in Telematics, and worked at NeXT computer as a systems engineer many, many years ago. Contact him via www. blusbird-labs.com or by email at [email protected] LCR-Reader #4 Digital Multimeter ‘cones LCR-Reader-MPA Ultimate PCB Debugging Tool + LCR AODC VoltagesCurent + LED/Diode/Continuity Test f cxsloseape sipoRed. Pees) eo ST TaSi aac id IoT System Pen ae ea (ed xities Pent | SU Gpinvle -/? SSO un mes LR mura oc) Ce UCR CaCI Rea en aes ait ee Oe Pee ECM Tec eum coe rae sc See Oe Re ae Ou ed RnR eae mee een other hurdles. In this article, Nishant discusses these and other Cee neue ee unc ne Ruy Coe oe OTs y N By N ie ac < he intersection of the Internet and TOT vs. NON IoT DESIGN wireless technology has changed To better understand the difference significantly with the advancement between an ToT and non-IoT product, let's of embedded systems, optical examine a use case. Consider a home fiber and VLSI. The term Internet of Things automation example. Family A has a home (lot) has gained tremendous momentum automation system that provides a variety as convexity technologies continue to _ of functions. The user has an IR remote that proliferate—including FTH (ber to home) — control: ing lights on and off. It has technology, Li-Fi (light fidelity), Wi-Fi, an infrared sensor that detects the presence Bluetooth, voice-contralled beaming devices and absence of people, and switches lights and many others. That's driven engineers on or off accordingly. There is an entry door, across a wide variety of market segments to which is controlled using a switch connected Create innovative products for the ToT. Using wire through the walls to the bedroom All that said, the system design process of to open the door. Note that in this example ‘an [oT product is vastly different compared to that most of the automation is done either other electronic products. Every part of an IoT wired point-to-point or using analog or digital design—including hardware, software, testing sensors. It involves no wireless technologies and certfication—are more difficult simply or the Internet. due to the presence of wireless components Now let's consider an example where fon board, Such components increase the — Family Bhasa home automation system where design challenges tenfold and adds time- the user controls the light using an android to-market pressures. In this article, I'll talk phone that has a Bluetooth transmitter. There about all these hurdles engineers can face are sensors used to detect entries to home. during the design cycle of an lol product: Entries to the home are tracked and emailedto the owner using Wi-Fi technology. The homeowner can use the Internet to switch off the lights in the home even when he or she is several miles away. And, last but not the least, the homeowner can even use voice commands to control the lights. This is a typical example of an IoT product. We'll be discussing the more technical aspects of such products as we go, DESIGN AND CHALLENGES Let'slookcloser atthedesignofan IoT-based home automation system, Figure 1 shows the block diagram of the probable system for ‘an Internet connected home. A typical home automation system consists of a controller which provides Bluetooth or Wi-Fi functionality. For our example, I've selected a Cypress Semiconductor PS0C 6 microcontroller (MCU) BLE with Wi-Fi module ‘on-chip. Although T've selected this device, it’s very important to understand the budget requirements of an implementation. The Cypress PS0C 6 comes packed with Bluetooth built-in, but it comes at a cost. There are other low-cost solutions—including an MCU combined with an external Bluetooth module. Either way, the selection of this central controller device is very important because it affects the system's power requirements, interfacing capabilities, feature sets and number of external components required. Choosing the controller even involves knowing the scope of the interfaces and applications of the system. For example, if the requirement is to only control a light, then a smaller solution could be used— interfaced with a Bluetooth module and then controlled using a relay. In our use case, we're looking at a system that has a lot of interfaces along with Wi-Fi, As a result, we need a somewhat complex controller that can handle wireless as well as ADCs and DACs for sensors processing. Because the PSoC MCU also has elements like all the required analog and digital components built in, it is quite cost effective for our use case. All that said, as a system designer, we need to consider the question of whether such a powerful device is really required? You cauld go for a simpler Atmel chip powered by Arduino with some basic relays and a cheaper Bluetooth module and WiFi module. It all comes down to budget vs. the requirements. Up until now we were only talking about the board that we're designing to integrate into our home automation system. Beyond this, there are multiple subsystems to be integrated in order to makea home automation a true ToT-powered system. For instance, to implement a computer vision-controlled system to track humans, we could integrate the system with Xilinx’s Ultra96 board. The Ultra96 is an Arm-based, Xilinx Zynq UltraScale+ MPSOC development board based on the Linaro 96Boards specification. Because we want a completely real-time system, using an Al-based, trained real-time solution to Standard tt router FTH For seamiess wifl at home e _o)— ar ec g and FIGURE agra ofa typical oT SystemXilinx Ultra96 Kit FIGURE? FIGURES Quarter ‘Artenna on aground plane Signal generator Laon turn current Image conductor detect a variety of stuff could be a game changer. With that in mind, we would connect the Xilinx Ultra96 board with intel's Movidius device which has a VPU to train the system real time. Figure 2 shows a typical connection of the two systems. PCB DESIGN CHALLENGES ‘A board design containing wireless components must follow very restricted guidelines. A poor PCB design could cause radiation from traces to interfere with the analog components onboard causing lot of noise interference. Moreover, a bad PCB design of a wireless system could fail to pass radiation certifications. ‘A typical PCB could look like as shown in Figure 2. At minimum, the board design would have the MCU (PS0C BLE) as close to the antenna as possible. To provide power, there is a regulator circuit localized on one side. We have added some WS2812 LEDs in several places around the board's edge for aesthetic purposes (to light up the unit when ‘operating, for example). Beam microphones ‘are placed in multiple directions so that an audio response system can be implemented by the system. Such an added feature could be replaced with an Alexa device to avoid the need for additional complex coding. There are also motor control circuits for controlling various areas of house like doors or relays or switches, There are few guidelines that should be reviewed when designing a PCB with a radiating element. An antenna designed into a PCB is generally a quarter-wave antenna,‘A quarter-wave antenna looks something like what's shown in Figure 3. These types of antennas take up less space than external antennas. While these aren't the best antennas in terms of omnidirectional radiation patterns, they solve many problems in terms of design and interference. Placement of these antennas is a very important factor in determining what your radiation pattern will look lke. The PCB antenna should be placed on the edge of the PCB for the least interference with the neighboring components or the rails, Antennas should be far off the ground plane because the ground attracts a lot of the radiation, causing the Bluetooth range to be reduced, for example, For these applications, a Meandered Inverted-F Antenna (MIFA) or a Planar Inverted-F antenna (PIFA) are the two most recommended antennas because they are designed using multiple turns—which helps in achieving a lambda-by-4 value (1/4) in a smaller space. There are even guidelines for the height an antenna or a Bluetooth module, which should be above the PCB's surface, The deeper details of this subject are outside the scope of this article. But NXP Semiconductors provides a document called "RF Design Considerations for 802.154 Hardware Development" [1] which gives a good short training tutorial on designing antennas on PCBs. A link is provided on Circuit Cellar's article materials webpage. Once the hardware design is complete, it's important to analyze the power budgeting of the system—especially given that Bluetooth consumes a lot of power. For a batter powered application, such power "sponge: could be dangerous on a board. Software should be written such that the Bluetooth circuitry is used only when required and is placed in a deep sleep mode the rest of the time, Reserving Bluetooth for burst transfers could help with lowering power consumption and extending battery life. TESTS AND CERTIFICATIONS Testing and certification are important parts of the process of designing any product related to Jol. Any board that has a wireless component—or any radiating component— must undergo strict certification processes before they are permitted to be sold in different parts of the world. These certification rules may vary from continent to continent ABOUT THE AUTHOR Nishant Mittal is a hardware systen ns engineer When it comes to robotics, the future is now! Advanced Control Robotics si Rene eset Brie era cae oa Meena ence lathes PMC ee Lc Beeman ree teen) ee Dies Oi Cee Get it today, cc-webshop.com n Hyderabad,ricune4 For detailed article references and adi cr even from country to country. Aside from being a tedious process, this requires a good ‘amount of cost—costs that the system designer should include when planning budgets for their ircuit designs. For any Bluetooth module or chip present onboard, several certifications are required—from the FCC (for the US), CE (for European countries), IC (for Canada) and the list goes on, To provide the setup for certification, special preparations must be done. Certification companies provide specifications to help you configure your board design so that the certification process is easier—for example, they may require you to make all the pins high impedance so that only the radiating element is the Bluetooth circuitry. They could also ask you to program certain onal resources go to: www.circulteellar.com/article-materials References [1] and [2] as marked in the article can be found there. RESOURCES Cypress Semiconductor | www.cypress.com Inte | wir. intel. com NXP Semiconeuctors | wwww.nxp.com behaviors of code so that they can more easily test for expected results. You may also have to provide some visualization components like LEDs, an LCD or some other device to indicate operations. Those are needed because these setups are tested for EMI and EMC in a radiative environment. They generally keep ‘a camera in the setup room and then track the activities that occur because of radiation and how the radiation affects operation. Other certifications are needed for boards containing a Wi-Fi—such as WPA2 (Wi-Fi Protected Setup) and WMM (Wi-Fi Multimedia) to name a few. Apart from these mandatory tests required for selling the praducts, there are many others that are necessary for ensuring the safety of the customer. Among these are Head SAR and Body SSAR calculations, which measure the amount of radiation that can penetrate from the device to the human body. There are maximum limits allowed that are set by responsible bodies. Selling products that exceed such limits could be declared illegal. Performance testing is another pillar of testing that's important. In this article, I won't discuss about how to test for error free performance of a board. I have discussed that in my previous articles on manufacturing tests including "Designing Manufacturing Test Systems" (Circuit Cellar352, November 2019) [2] and "system Controller Manufacturing Test (Parts 1 and 2) (Circuit Cellar 354 and 355, January and February 2020) [3] [4]. If there are wireless components like Bluetooth on a board, it follows that it also has a radiating antenna. A properly designed antenna should give a uniform lobe and should ideally have an omnidirectional radiation pattern. It should have practically a circular loop in one direction and non-uniform lobe against that direction. This can be tested using an anechaic ‘chamber with one side containing a transmitter that has a rotating handle. The other side has a receiver antenna, The transmitter antenna rotates 360 degrees at a certain speed. The receiver gets the signal and plots the radiation pattern. This is an effective way of testing and designing a good performance antenna, Figure 4 shows one of such setup [5] With advancement in technology comes lot of responsibility for engineers and system designers~responsivities to society, to nature and to the environment. Electronic waste and radiation have been ongoing concerns with regard to the environment. Radiation is known to have affected a lot of wildlife and bird life. Proper limits to electromagnetic radiations should be taken into concern, It is true that more radiation will provide better performance for the user, but it comes at the cost of environmental troubles. Meanwhile, electronic waste accumulations add a lot of cancerous and non-renewable agents to environment. With that in mind, we should be responsible engineers while making prototypes as well, and not create unnecessary prototype units. CONCLUSION In this article, we explored the key factors jn designing an ToT product—challenges jn design lifecycle, production challenges, testing and certifications. Such IoT designs can be complemented with multiple sensors, gesture recognition and so on. The innovations that are possible are beyond the limits of imagination. While doing so, we need to be responsible for how our designs affect and interact with the environment. We also examined the cost challenges as well as the important testing strategies required to create the ideal IoT board/product. Editor's Note: All Circuit Cellar articles from 1988 to present can be found on the CC Vault, a pocket-sized USB available from wwww.cc-webshop.com. & Work hands-free Osciloscopes with mere than two ‘channels present 2 common problem: inone of us have enough hands to hold ‘more than two probes in place. Pico has an ingenious solution to hold a PCB under test firmly in place ‘and accurately position 2s many test probes as required, so that the user test equipment Find out more at www.picotech.com/A553 with our new multi-channel probe Pl COF SY Technologyand Haley Lee Brandon Guo, Dustin Hwang FIGURE. ioe maken em it hed. This des enable the In today’s digital world, hardly anyone uses analog televisions anymore. In this project article, learn how three Cornell students make use of this antiquated technology in conjunction with the Microchip PIC32 MCU to create their own racing video game. sagroupofavidgameenthusiasts, tthe choice to design our own game for our final project was obvious. ‘Our intent was to use Microchip Technology's PIC32. microcontroller (MCU) to develop a complete game from beginning to end in the designated time period. The objective of our game is to move a car across the finish line in the shortest amount of time, using controls that simulate the experience of driving. The reason behind our game choice was that we wanted to make a game that could be feasibly completed within the time constraints and still be entertaining. We also realized that if we decided to create a racing game, there would be many different reference materials we could draw from for tthe game physics. The central motivation behind our design was game playability. Rather than designing fan elaborately complex racing game full of bugs, we opted to create a simpler project with higher quality game play. With that in mind, we focused on ensuring a smooth interface between our hardware components ‘and the actual movement of the pixelated car. In this article, we further discuss the thought process and rationale behind the design choices made throughout the project Our hope is that others can draw inspiration and advice fram our work as they develop their own games,FIGURE? HARDWARE DESIGN The primary focus of the hardware design were the pedals and the steering wheel that enable the user to control the car's movernent. To best simulate the experience of driving, we wanted the pedals to be as realistic as possible. Specifically, we wanted the user to be able to adjust the compression of the pedals and have the car move forward and backward accordingly. We built two pedals—accelerator and brake—by connecting two pieces of wood with ‘a metal joint at one end and a compressible spring at the other (Figure 4). This enables users to control the degree of compression, and thereby the motion of the car, by exerting different amounts of pressure with their feet. To measure the position of each pedal, we attached a slide potentiometer to the spring, so the degree of compression would be proportional to the amount of movement of the potentiometer. The pedals were then attached to a baseboard to prevent them from moving when pressed. In the setup, a PIC32 MCU was located next to the pedals on the base (Figure 1), so we simply connected them with wires to an analog pin. To control left and right movement, we designed and 3D-printed 2 steering wheel (Figure 2). We used a simple circular design with a connecting piece across the diameter. To communicate between the wheel and the CRT, we used an Adafruit MMA8451 accelerometer, which we hot glued to the backside. We chose to use an accelerometer ‘5 opposed to a rotary potentiometer because it did not require the wheel to be mounted to othe back oF th tering heat gue the usa a stand. This meant that the wheel could be held and turned in mid-air like the controller in the popular racing game Mario Kart. To allow the user a better driving experience, we connected long wires to the NCU, allowing the wheel to be relatively mobile, bHT S00m\ icuRe 3 31 an the primary laying ald in Figure Se isattached to the rot of the steering wheel fo ens a Mi00ys M Pos: 34.40,us __ CHT xd output pont ofthe CRT cect‘The main output of our game was the CRT display, which we connected to the MCU using ‘an RCA connector. We chose a CRT display because it was easy to drive from the PIC32 with SPI, and because it had a low cost and FIGURE 4 The fl schematic of cur project. We haced ou project on Sean Carl PICS2 Smal Dev Baad [2] ard odded the slide pateriometrs, CRT ret, DAC, Ardina Now and Start Reset uta, ABOUT THE AUTHORS Haley Lee is a senior studying Electrical and Computer Engineering at Cornell University. She plans on graduating early and immediately start working, Dus Hwang is a senior studying Computer Science at Comell University. He plans to complete his Masters of Engineering degree and enter industry afterwards, Brandon Guo is a senior studying Computer Science. He wants to work on the West Coast after graduation and spend his time cooking and playing volleyball. high refresh rate. We used an adaptation ‘of Di Jasio's method of generating sync pulses [1], using one output-compare unit to ‘output to the screen with easy control over the video content timing. The CRT operates by combining the video and sync signal into ‘one output signal. The voltage of the nominal ‘output is either at 0, 1.0 or -0.3V. When itis at 0V, black is drawn to the screen, and when the output is at 1V, white is drawn to the screen: ‘An image of the voltage signal is shown in Figure 3. We connected the CRT sync (SYNC pin 14) and input (VIDEO pin 3) to ports RBS ‘and RAL, respectively, as illustrated in our ful schematic (Figure 4). We also decided to have a Start-Reset button so the game could be replayed. This button allowed the user to go between the instruction and the game screen when pressed. It was hot-glued to the steering wheel to keep the controls consolidated and close to the user, The input was connected to RBA on the MCU (Figure 4) ‘The last major hardware component added to our project was a DAC for sound effects. The SPI DAC we used was the Microchip Technology's MCP4822. We connected DAC SPI Sclock to RBIS, chip select to RB3, and Sdata to RBIL. The main motivation for adding the DAC hardware was to allow the user to have a more immersive sensory experience ‘SOFTWARE DESIGN ‘A big part of our work on this project was determining the game design and its programming. To display to the CRT, we used ‘an NTSC library [3]. This library implemented the SPI interface used to communicate to the TV, and provided functions for drawing letters, lines and pixels. The driver code, which we used as the base of our project, operates by displaying through DMA channel 4, and it triggers the ISR operating at 15,725MHz, the NTSC/line rate. For each frame, the ISR will ‘output 262 lines, at which point it will reset the image memory pointer and begin the next frame. Because the rest of the game was made from scratch, we had to design our own illustrations in pixel art form. To facilitate this process, we wrote multiple video functions that covered more area than just a line or a point. We drew an aerial view of the car, so that when playing the game, the user could better perceive the vehicle's speed. After determining the relative size of the car to the screen, we created the background, which consisted of a four-lane road with grass on both sides. The final illustration we added to the playing screen was the rectangles that appeared in the middle of each laneto obstructthe car from going forward. To simulate the movernent of the car and obstacles, we erased the image of the car at the beginning of each frame, and then recalculated and updated the new positions of the cars and obstacles. Finally, to ensure that the car appeared at the top layer of the screen, we redrew the entire background and then the car over it. ‘final touch we added to our game was a start screen containing the game rules, which appears upon reset. Upon pressing the Start button from the start screen, the program counts down from three before the game actually begins. We had to draw these numbers pixel by pixel, because the provided video text functions made the numbers too ‘small. The initial start screen and the main playing field are shown in Figure 5. For the sound output, we used the second SPI channel to connectthe DAC. We used RB13, and sent sine waves through an additional ISR. We created three different notes in particular, all at different frequencies and/ or durations. The most common sound is the sound of the user hitting an obstacle. We set the direct digital synthesis (DDS) increment [4] to the lowest frequency for this note. A high-pitched tone was used for reaching the finish line, and a tone in the middie was for losing all the player's lives (see DESIGN/GAME MECHANICS section). The sine wave outputted to the DAC would change based on the DDS increment value. The other key software component of our project was programming the steering wheel controls. For this, we used an Arduino Nano CEA CE EEE peprasppspppsst pepe stp! iB Ipepreeepersprespenp yee!2» For detailed article reference: that functioned as a device driver to transmit data from the MMA8451 accelerometer on the wheel. We used the Adafruit Arduino device library [5] for the MMA8451, to easily connect to the Arduino and record orientation of the wheel, and a simple 2-bit digital parallel interface between the Arduino and the PIC32. We chose to use this 2-bit interface over Serial because we wanted to keep the game controls as simple as possible. There are only four possible steering positions (one left, one right and two center positions). Despite this rough translation, the game was still extremely playable, and the change in sideways direction was smooth due to a ‘numerical integration calculation. Although this 2-bit interface prevents the player from executing sharp turns, we found this level of detail was not necessary due to the nature of ‘our game. DESIGN/GAME MECHANICS ‘Our game was a simple top-down racing game. The main objective was to reach the finish line in the quickest time, while avoiding the randomly generated obstacles along the way. Since the obstacles were sometimes hard to avoid, we gave the player nine lives so that winning would be possible. Hitting an obstacle would result in a time penalty and the loss of one life. When the game was over, it would display whether the player won or lost and the score, To start and restart the game, the user presses the Start-Reset button attached to the steering wheel, which brings the game back to the starting instruction screen. Our program had multiple protothreads [6], but when we tried to use a round-robin scheduler, we found that it interfered with the timing of the DMA writing to the CRT. To deal with this issue, instead of running multiple threads at once, we wrote our own custom scheduler. This had a single main thread, from which we spawned an additional thread when needed. The separate thread was spawned in the case of collision, causing the main thread to stop, yield to the spawned thread and only resume after the spawned thread was finished. By doing this, we satisfied the timing of the video generation. ‘A large portion of the project was spent writing the logic for car movement and its wwrw.circulteellar.comarticle-materials References [1] through [6] as marked in the article can be found there. RESOURCES Adair industries | wwn.adafr it.com Microchip Technology | wwrw.microchip.com Interaction with the environment. The first objective we tackled was associating the user's interaction with the pedals and wheel with the movement of the car. We figured that both acceleration and velocity values are necessary for a complete game. We controlled the vertical motion of the car with an acceleration value that directly corresponded to the degree the pedal is pressed. From the acceleration pedal, the ADC reads in values approximately between 0 and 300 ADC units, where 0 is the resting state ‘of the pedal and 300 is the fully compressed state. In our mapping, we had this range map to a value between -0.08 and 0.15 pixels/ frame?. This is because in the resting state, the car should slowly decelerate. The reason for this decision was that it more closely imitates how a car actually works. At first, we considered mapping the pedal ADC directly to the acceleration and thus the position of the car on the screen, but we soon realized that mapping to acceleration was better. This is because using a direct map to velocity, the car would just stop if the acceleration pedal were released. This does rot reflect the behavior of a real car, which ‘would begin to slow down. For the movement of the wheel, however, we mapped the left and right values to the directions sensed from the Arduino. This is because we wanted the user to be able to quickly dodge obstacles. Tt doesn't make much sense for a user to put the wheel in a neutral position and continue drifting, because it was turning previously. ADDING COMPLEXITY To add more complexity to the game, we designed obstacles that randomly block different areas of each lane. To create these obstacles, we made a struct that grouped together the X-position, Y-position and valid bit variables. We also made an array of size four, corresponding to the X-position of the middle of each lane in the playing field. Based ‘on a random seed, obstacles were generated at the top of the screen at one of the four Positions in the array. The valid bit was used to control whether the obstacle should be drawn ‘or not. When the valid bit is 0, the obstacle is not drawn, However, after a certain number Of ticks based on a modulus calculation, the ‘obstacle is made valid and thus appears in the playing screen. When the obstacle reaches the bottom of the screen or collides with the cat, the obstacle is erased and made invalid, and its Y-position is reset to the top of the screen. We designed the obstacles as squares that descended from the top of the screen. The square design allowed for an easy hitbox detection with the car. We also based the movement off that of the car. This gave the cara semblance of velocity relative to the objects around it, We made this design decision because as the car speeds up, it should be harder to avoid the obstacles. Naturally, their velocities should be relative to each other, so we did a one-to-one mapping. To encourage the user to stay on the main oad, we incorporated arass that was next to the roads. We thought this would be a good decision, because it prevents the playing field from getting too large. Besides this, grass is a common aspect in many popular racing games. A user who decides to drive in the grass will decelerate and end up not moving at all. Therefore, the user may choose to go into the grass, despite this deceleration, to save some time if collision with an obstacle is anticipated. Generally, though, it is wiser for the player to stay on the road. We implemented a nine-lives system to ive the player a better chance to beat the game. For the life system, we simply added a counter to the bottom corner of the screen. Each collision subtracts one life, and when the player has 0 lives left, the game immediately ends and displays the losing end screen that reads “Game Over.” Every time the game restarted, the number of lives resets to nine. To win the game, the player must reach a specified distance of 18,000 pixels without losing all nine lives. This distance was calculated by taking the double integral of the acceleration values from the accelerator edal. We made this calculation easier by simply summing the velocities we already calculated. Once this distance is reached, a finish line spawns at the top of the road and moves towards the car at the same velacity as that of the obstacles. When the front of the car and the finish line meet, the user has effectively “crossed the finish line” and wins the game. A final end-game screen appears, displaying the user's total time to cross that distance. RESULTS In just over one month, we were able to complete a fully functioning game with minimal bugs. It contained responsive hardware components along with software that allowed the user smooth control of the game. With regard to game logic, there were few bugs that affected the user experience. The final result was a game with good playability. The controls were smoothly integrated with the CRT, and there was no visible trouble between the game contrals and the display on the screen. Even though the wheel has only four levels, turning the whee! feels smooth, Because there is limited space for the player to turn left and right, itis not necessary for there to be extremely precise controls for the wheel. However, we wanted the controls for the pedals to feel much more responsive. Accordingly, after a certain degree of pedal compression, any small additional difference causes the car to speed up. In addition to controls for accelerating, we have additional layers of complexity that make the game more interesting. The features give the users motivation to accelerate and turn to improve their scores. The obstacles are also randomly generated, which makes the game less static, Each time a game is played, the path that the user takes to get a better score is always changing. By not having one set optimal path, the game becomes more interesting and dynamic. Overall, we were able to design a complete game. We were able to produce an entire base game with a clear goal and simple controls. To get a better feel of our game, please check out our video of the project using the QR in Figure 6. The video is also posted on Circuit Cellar’s article materials webpage. FUTURE POSSIBILITIES A lot of improvements could be added to make the game more functional and more entertaining. The main bug in the existing project came from using two separate interrupts. Because the DMA for the CRT requires strict timing from the ISR, using fan extra interrupt caused slight static in the game screen, This static dd not interfere with the game play, however. Another possible change concerns the complexity of the obstacles. They were designed as simple squares that would come down with the same velocity as the car However, the obstacles could be made slightly more dynamic and possibly have different shapes or different velocities relative to the car's velocity. During the project, we intentionally chose to avoid some options, due to difficulty and time constraints. However, there definitely could be possible improvements. One such idea would be to make the steering wheel and the baseboard wireless by implementing radio communication between the modules. We considered using XBee radios to link the whee! with the rest ofthe project, but decided against this in the interest of Saving time. Also, we could remove the sound effects to add the wireless radio communication, which might further improve the project. We hope that if readers decide to implement a game of their own, they will incorporate these suggestions. Se aS FIGURES San this QR cade to 90 a vdeo of the game beng olaed. Video is ao ported an Gc Cals article aBy Cee re C rem ee mL erm ene te Failure Modes, Effects and Diagnostic Analysis (FMEDA) documents are critical tools used to acl ve the safety requirements of automotive designs. But wri ing an FMEDA is a time consuming and difficult task. By automating this task, you can spend more time improving your design's safety readiness. In this article, Chuck and Doug introduce a solution for smoothing the FMEDA process. utomotive designs require functional safety analysis, typically accomplished using Failure Modes, Effects and Diagnostic Analysis (FMEDA). FMEDAs are used to determine each safety goal’s architectural metrics, which in turn determines if the design will meet the targeted Automotive Safety Integrity Level (ASIL) requirements. However, if you have ever written an FMEDA, you know how tedious a task this can be. By automating this time consuming and difficult task, engineers can spend more time on exploring and developing a design's safety readiness and figuring out how to more effectively safety-harden their designs. In this article, we introduce a push- button solution for creating and automating the FMEDA process, VENTURING INTO FMEDA The ISO 26262 standard requires quantitative analysis of safety related automotive IC designs. This analysis is used to generate the key functional safety metrics: probability metric for random hardware failures (PMHF), the single-point fault metric (GPEM) and the latent fault metric (LFM). The standard provides targets for each of these metrics based on the ASIL requirements of the top-level system that automotive manufacturers expect the IC design to meet. In the case of PMHF, automotive manufacturers will allocate a portion of their system PMHF to your design. Determining these metrics is accomplished by looking at ways the design can fail and result in a hazard—a source of potential harm or malfunctioning behavior. The standard and industry practice is to analyze the failure modes using a table where each design component is broken out land the effects of the failure is quantified in terms of failure rates or failures in time (FIT). This table is referred to as a Failure Modes, Effects and Diagnostic Analysis, or FMEDA. The FMEDA lists each component and the percentage each failure mode contributes to the overall FIT rate. By including safety mechanisms in your design, you can mitigate the effect of the failure modes and reduce their contribution to the FIT rate. Each failure mode needs to be evaluated according to the following criteria: is it safety related, what percentage of the design is affected by the failure mode, is it covered by a safety mechanism and’ what percentage of the design is covered by the safety mechanism?Table 1 defines the common terms used in the creation of an FMEDA. Having this information, the failure mode's FIT rate, residual/single-point FIT rate, safe FIT rate, multi-point FIT rate and latent FIT rate can be calculated. For example, an FMEDA spreadsheet might take the form shown in Figure 4. Using an FMEDA allows the key safety metrics to be determined for a design, but FMEDAs come with their challenges. The first challenge is determining the base failure rate for all the different logic used within a design: standard cell, analog logicand different memory types (high speed/high density, read-only memories, one-time programmable memories and so forth). Estimating the base failure rate cy ‘The base failure rate (BFR, measured in FIT) is technology dependent and is the inherent FIT of the design without any protection. PMHF requirements can be considered a target FIT. Since BFR. is typically much larger than the target FIT for a design, safety mechanisms are used to protect Base Failure Rate a design and effectively reduce the BFR to meet the target FIT. Within an integrated circuit (IC), «am logic, analog/mixed signal circuits, and memories will have a different BFR. The BFR is assumed the same for registers and combinational logic. BFR will also be different for permanent and transient faults Typically, within an integrated circuit, the BFR is distributed across the design uniformly, based on area. ‘A top-level requirement of a design to address functional safety. In an IC there may be multiple Safety Goal ‘safety goals. Since most ICs are not designed in the context of an automobile, safety goals are typically assumed for the purposes of determining what is safety related and if faults would impact safety. iid Kelstel Is the design component safety related? Would they impact the safety goal? Do they protect safety ee related functions? Typically, ICs will have both safety related and non-safety related logic. Failure Modes All the ways the component could fail. Example of failure modes are: generated data is wrong, wrong address provided, data not provided when required, etc. Failure Mode For each failure mode identified for a component, the percentage chance ofthat specific failure Distribution mode occurring. Potential to Violate e 2 1a Safety Goal Can the failure violate the safety goal? Safety Mechanisms | List ofall safety mechanisms in place to prevent violation of safety goals. Diagnostic Percentage of failure mode covered (protected) by the identified safety mechanisms. The aggregate Coverage of all safety mechanisms is used. ase. VEDA ifmation nese foreach ale made FIGURE FHEDA preaches 2ey is described in detail in 15026262:2018-11, Clause 4.6. Calculating it involves numerous Greek symbols representing various technology dependent values. Figure 2 shows an example worksheet for calculating the base failure rate. ‘A BETTER WAY ‘As automotive functional safety consultants, we created the base failure rate table in Figure 2 by hand, But we are always looking for a better and more efficient way to simplify the FMEDA process, which is ‘one area where an EDA tool can really help. Such a tool must have the ability to read in a design, determine its transistor count for each specific technology type, measure the diagnostic coverage of each safety mechanism and perform the base failure rate calculation ricune2 Wirshest for calaating the base flr ate arene (rot) # of Transistors Saver] selene gL SE naan Sho foc Liw*ia 10C e200 PIT Equation Peptcaion Type _[Tempaverage (ag) [neon tractor | Motor Cont 2 ‘02 Motor Cont © ‘ons Motor cont 8 ‘ons PusengerCompertnent 27 0006 DassengerComparient| 30 ‘DAs _PassengerCompartment 0006 FIGURE? TEC 660 FT cationracune + using either industry standard or custom mission profiles and technology values to automatically compute the FIT rates for each design component. ‘These tools should allow us to either use defaults taken from standards like TEC 62380 (which TSO 26262:2018 is derived from) or SN 29500, or input values provided by a customer. After the tool determines the number of transistors for the logic and memory, it plugs that value into the equation, as shown in the TEC 62380 example in Figure 3. The beauty of this kind of tool is that ‘maintenance and repeatability of the base failure rate calculations have been dramatically improved. The tool allows the consolidation of all the common variables in ‘one place, and the design itself becomes the source for the transistor counts. In addition, {as can be seen in Figure 3, the equations for creating the base failure rate are complex. Using spreadsheets to manage the creation of all terms and variables along the way can be error prone and a major support issue. Again, ‘a toal that creates the final number based on provided information improves the review and documentation processes. It is necessary to control and manage only a small set of the key parameters. The FIT calculation report simplifies the FMEDA calculations for each design component (Figure 4). The lambda values for stuck-at and transient failure modes (LambdaPermanent and LambdaTransient) and diagnostic coverage (DiagCoveragePerm and DiagCoverageTran) plug right into the SPF/RF FIT rates formula as described in 15026262:2018-5, Clause C.3: With the righ designing a microprocessor can be easy. Okay, maybe not easy, but certainly NUIT) Using less complicated, Monte Dalrymple has taken his years of experience designing embedded architecture and. microprocessors and compiled his knowledge into one comprehensive guide to processor design in the real world. Monte demonstrates how Verilog ‘hardware description language (HDL) enables you to depict, simulate, and synthesize an electronic design so you can reduce your workload and Increase productivity. cc-webshop.com Lh fel et tey Design s236 caRCUTCELAR «Ly 200 350 i mae = at oo i ieee ‘Tower isis oom toe 2 Fae ieee 2 ae aoe z ————_ a 2 fee 3m stat FIGURES EDA with hundreis of compares to araye Note: The data in edurns A ane Bs intentional lured to potct prepritary ination, ABOUT THE AUTHORS Ideally, the tool should automatically determine the percentage of transistors that apply to each design component. With that in mind, the lambda (2) values shown in Figure 4 already factor in the component's contribution or area percentage of the base failure rate (BFR), as seen in tis formula used to calculate lambda for SPF and RF faults: pe oe 100 Decocnin GOING FURTHER WITH FMEDA Now that we have removed the first challenge of determining the base failure (Chuck Battikha has more than 35 years ‘of experience in the high technology industry and has been with the Mentor, 2 Siemens Business, Consulting Division for the last eight years, with a focus ‘on functional verification consulting. His areas of expertise range from CPU development and fault tolerant computing verification to semicanductor ‘and IP development. Over the past five years Chuck has further specialized in functional safety, including work in the medical, nuclear and automotive industries. Chuck earned a BSEE at Northeastern University. rate, we must deal with the daunting task of performing all the FIT calculations to create the SPFM, LFM and PMHF. Even more challenging is the fact that there are typically hundreds of modules in an integrated circuit (10), resulting in hundreds and hundreds of lines in an FMEDA spreadsheet for all modules ‘or components that need called out, along with their various failure modes (Figure 5). Therefore, the second challenge is finding fan easier and automated way to create the FMEDA spreadsheet intuitively, allowing the user to traverse through the design, select what components are safety-related and need analyzed and perform all the necessary calculations using the FIT rates, It should be Doug Smith is a functional verification consultant for Mentor, A Siemens Business, with expertise in UVM and formal technologies. Doug holds a master's degree in Computer Engineering from the University of Cincinnati and a bachelor's degree in Physics from Northern Kentucky University.noted that the FMEDA is an artifact of the safety analysis requirements of ISO 26262. ‘As such, automotive manufacturers and their Tier 1 providers look for detail within the FMEDA to show and justify the results achieved. Simply calling out a final number is not sufficient. Think back to those high school exams, where show all your work was required ‘AS consultants, we get tasked with the tedious job of creating the hundreds and hundreds of lines in an FMEDA. Since FMEDAs tend to be spreadsheet-based, we decided to automate the process using Visual Basic inside of Microsoft Excel. To learn more, we encourage you to read the following papers. Links to all of these are available on Circuit Cellar's article materials webpage. We describe the steps of this automated push-button FMEDA solution in our paper Push-Button FMEDAS for Automotive Safety: Automating a Tedious Task [1]. A more detailed and accurate analysis is made by specifying the cone of influence of a safety mechanism instead of just the surrounding module. You can read 2 full treatment on this topic in our paper How Formal Reduces Fault Analysis for ISO 26262 (2]. Of course, the true diagnostic coverage will only be obtainable by using an PCBWay is a leading PCB manufacturer in Shenzhen, specializing in PCB prototyping and PCBWay _ sseemsiservoe, and having boon ove by over 1M engineer arcund the wold fork actual fault campaign that injects faults and classifies the results. You will find extensive details on this in the paper It’s Not My Fault! How to Run a Better Fault Campaign Using Formal (3). By automating the tedious task of FMEDA creation, using the tools and methods described in this article, you have more time to focus on exploring your design's safety readiness and figuring out how you can better safety-harden your design. If you need help starting, automating, or performing your Functional safety process, Mentor Consulting services is available to help you successfully bring your automotive design to market. For mare information on our mission and haw to contact us, please visit us at the link provided on Circuit Cllar's article materials webpage [4]. © For detailed article references and additional resources go to: ‘www.circultcellar.com/article-materials References [1] through [4] as marked RESOURCES Mentor, A Siemens Business | ww.menter.cam comprehensive advantages. ow as 10 PCBs for only 5 USD ‘Tumaround time can be as short as 24 hours Get an instant quote online: www.PCBWay.com Email: [email protected] the article can be found there.a : a ee Ol erly Systems Game Coping with etl ty Cerda Editor-in-Chief d circuit boards continue to grow more elaborate, with the chips populating them gaining complexity as well. To support these designs, PCB tool vendors are enhancing their software suites to support higher-speed signals, collaborative team designs and many other challenges. here's alot on the plates of today's PCB design tool providers. As PCBs get ever more complicated, efforts continue to address more facets of the PCB design process while improving basic functions such as automated chip placement and intelligent routing. New versions of PCB tools are addressing high: speed design, multi-board designs, 3D designs, component management, IC-PCB co- design more. If there's a theme over the past 12 months for PCB tool enhancements, it's about systems. New features continue to roll out that treat PCB design in more of a systems context. This means not just PCBs a a physical object within a system, but also the system processes revolving around PCBs, including collaborative team design support and greater integration with PCB analysis and verification solutions. HIGH-SPEED DESIGN FEATURES Exemplifying those trends, in December Altium rolled out version 20 of its flagship PCB design software Altium Designer. The new version’s features include a faster schematic editor, high-speed design improvements and enhanced interactive router capabilities enabling faster board design, ‘Among Altium Designer 20 (ADZ0)'s enhanced interactive routing features are new “push & shove" capabilities that enable routing ‘of complex HDI boards and speed-up design times by over 20%, even for simple PCBs (Figure 1). To support high-speed PCB routing, the tool enables users to efficiently design high density and high-speed boards using madern ‘SerDes ike PCT 4.0/5.0, USB3.2, 1006 Ethernet and parallel buses like DDR3/4/5. In a multi-board design context, one of the most insidious issues is not just connector alignment, but the correct assignment of signals on the connector pins. When working with standards, this is not as much ofa problem because signal assignments are predetermined. But when designing new multi-board systems, the connector pin-to-signal assignment is up to the system designer, and many projects have been derailed because of swapped pins or incorrect connector pin numbering on one of the boards. In a Native 3D Mulit-Board design environment, signals are traced through connections from board-to-board and board: to-cable-to-board, allowing errors to be found and assignment to be fully synchronized across all PCB designs in the system, before prototypes are built (ee the Cover image of this issue, Gircuit Cellar 360, July 2020) For applications where high-voltage design is critical—such as spacecraft, high-altitude aircraft and high-tech lasers—AD20 provides new creepage rules that help maintain high- voltage clearances across the PCB surfaces for prevention of electrical arcing hazards for power supply and mixed-signal device designs.SHARED CANVAS APPROACH Among the interesting features in the latest version of Cadence’s Allegro software is its Allegro PCB Symphony Team Design Option (Figure 2). Tt enables collaborative placement, routing, auto-interactive routing, interactive routing and shape design. This lets design teams dedicate their time and efforts to get designs done faster through real-time concurrent design collaboration, This Allegro option operates as a shared canvas providing a low-overhead environment in which multiple designers can work on the same design, on the same canvas and at the same time without the set-up requirements of a partitioned project. The more routing engineers you add, the faster your team can finish routing. By connecting multiple PCB designers to ‘a common Allegro PCB layout database, any changes made on their canvases are reflected fon the server and seen by other designers, eliminating copy/paste “chaos.” You can bring other team members into a design on ‘a moment's notice. Join or leave the session at any time, knowing that all design updates have been updated to the master database. Designs are hosted ona network server where multiple designers can access the server and start the concurrent design process. PCB designs can be managed centrally without requiring user intervention. Many tasks—such as netlist updates, MCAD updates, constraint updates and so forth— frequently interrupt the PCB implementation process. The constraint editing capability in the Allegro PCB Symphony Team Design Option allows a client exclusive access to Constraint Manager while everyone continues their design work concurrently. You can leverage netlist import and MCAD import within the Symphony Team Design Option session without disconnecting team members from the session. If the shared canvas approach isn't ideal for your design team, Cadence also provides its Allegro PCB Design Partitioning Option {available separately). It lets designers work on individual design sections exported from a master design. Partitioning @ design for layout and editing by several design team members accelerates the time to complete the layout process. Each designer can see all partitioned sections and update the design View for monitoring the status and progress of other users’ sections Design Partitioning Concurrent Team Design FIGURE. 8 rating, 40850, U ricuRe2riouRE3 PCB LAYOUT FLEXIBILITY In March, Mentor announced that the latest release of its Xpedition, VX2.7, was available for download. According to the company, Xpedition VX.2.7 is enhanced with many new features that improve product usability and efficiency as well as improvements in the UL and overall usability. Like other vendors, Mentor has added ideas submitted from users. The new features comprise several aspects including multi-board system design, design creation, schematic capture simulation, layout, library management, layout and design for manufacturing (DFM). For the purposes of an overview, in this article we'll look at a couple of those areas. In terms of layout, the latest release of Xpedition VX.2.7 offers features that span from component placement to sketch planning ‘and beyond. Selection of connections for assignment to a sketch path or sketch plan can now be done by selecting pins. You can also now manually place parts one after the ‘ther or with auto-arrange. There's also a new option while routing nets which allows for For detailed article references and additional resources go to: wwrn.circuiteellar.com/article-materials wwwemento’ RESOURCES Altium | wwwwaltium.com Cadence Desian Systems + Mentor, @ Siemens Company Zuken | wwe zuken.com pin swapping. This works for single nets and differential pairs. Meander editing in Xpedition VX27 (Figure 3) now supports connection points in complex vias to get a consistent user experience with other routing commands. Xpedition VX2.7 has also enhanced its support for multi-board system design. The association of multiple PCBs to the system design can now be completed with a single check-in of the system design. The algorithm to manage each board's synchronization states has also been optimized to significantly reduce the time to analyze the design's synchronization. For large systems, this new process can take minutes off the verification time in checking each board. Also, a new design rule check (DRC) has been created to verify mated connectors. This ensures the ‘mating on the schematic matches the mating in the library, On the schematic capture side, the VX2.7 version provides improvements to ease-of- use and flexibility. The new release contains ‘multiple usability improvements. Grid options, tab closures, and keyboard shortcuts are enhanced and made simpler. New additions to the Partlister definition files create a report showing which parts in a design have been created using PartQuest. Meanwhile, the software's designer verify toal now analyzes the schematic-level (and block-level) pin type, rather than only analyzing the symbol pin type. The priority order is: Instance > Block > Symbol. The tool also supports pin type overrides from 1/0 Optimizer. This enables you to make use of any pin type changes directly from your schematicPCB DESIGN VERIFICATION Mentor’s new VX2.7 version of Xpedition also offers enhancements to PCB design verification. This takes the form of new integration features between Xpedition and Mentor’sdesign verification (analysis) tool called Hyperlynx. Hyperlynx is a complete family of analysis tools for high-speed electronic design including electrical design rule checking (DRC/ ERC), signal integrity (SI), power integrity (PI) with integrated 20/2.5D/3D electromagnetic modeling (3 EM), Users can launch Hyperlynx from Xpedition’s EDM (engineering data management) tool suite and manage data from simulation “sand boxes’ based on user (Figure 4). Results are also tracked if Hyperlynx is launched from within Xpedition’s authoring tools. Users can now also work with Hyperlynx versions out of sync with the last two releases of Xpedition. This allows more frequent updates to analysis tools, while maintaining a stable authoring flow longer. Custom FPGA devices can naw be modeled automatically for schematic analysis. An online database of Altera and Xilinx FPGA components is available for free to download. This greatly reduces the time it takes to model large, customized components. In Xpedition VX27, you can open your datasheet directly from your schematic analysis project. The datasheet location can be specified directly on the bill of materials (BOM) or in your Designer properties. Analysis of results is made simpler by quickly locating your datasheet for review, says Mentor. Another feature lets you design your BOM for schematic analysis. This new functionality allows you to maintain model assignment connections to parts that have a different part number for schematic analysis. IC-PCB CO-DESIGN ‘Among the interesting features in the latest version of CR-8000, Zuken’s 3D PCB and IC tool suite are capabilities for comprehensive system co-design. Called Design Force, these capabilities recognize the interaction between chip, package and board data to reduce complexity, size and cost of the overall system (Figure 5), In addition to advanced PCB layout capabilities, Design Force provides chip, package and board co-design capabilities to enable real time 3D hierarchical design. This allows design teams to concurrently create any combination of advanced die stacks, packages and PCBs. A multi-board constraint browser lets you view and analyze system level Interconnects. Automatic ball assignment lets you optimize complex routing solutions. Using a single environment, you can do high-speed design with constraint management and signal integrity (SI) and PI power integrity (PI) analysis. The tool's routing engines can do rapid feasibility studies or detailed redistribution layer (ROL) and bump escape routing of signals, as well as power and ground nets, Long gone are the old days when just placement and routing were the entire scope of PCB design tools. Both PCB designs themselves and the ICs populating them continue to grow more and more complex. PCB design tool vendors must keep pace with advanced, integrated tool solutions, viguRe s cr-s000 besan of the sta fem smultien “sand cid on ed if Hyperlyiaunched Fam a Yo Fests are ako Bottom-upChip-Level Supercomputing AL is quickly infiltrating every corner of embedded system design. Butimplementing the technology can be challenging. To help smooth the way, processing solutions including FPGAs, GPUs and dedicated AI SoCs are evolving to meet the needs of AI edge applications. ren i oop nce relegated to the realm of supercomputers built from rooms full of compute racks, today’s artificial intelligence (AD, machine learning (ML) and neural networking technologies now routinely are implemented at the chip and board level. Supplying the technology for these efforts are the makers of leading-edge embedded processors, FPGAs and GPUs. In these tasks, GPUs are being used for "general-purpose computing on GPUs," a technique also known as GPGPU computing. And, while the trend toward FPGAs with general-purpose CPU cores embedded on them is nothing new, the latest crop FPGAs have shifted their’ architectures toward configurations that support AI and ML types of processing, To keep pace with demands for “intelligent” system functionality, embedded processor, GPU and FPGA companies have rolled out a variety of solutions over the last 12 months, aimed at performing AI, ML and other advanced computing functions for several demanding embedded system application segments. arming (Ml capable are able foc the Min Ze pablles fr Minx Pro AY ntlgent dg ition fomaic abet tracking MACHINE LEARNING FOR AV Two years ago, leading FPGA vendor Xilinx introduced its adaptive compute acceleration platform (ACAP) approach to FPGAs. It’s Versal line ACAPs devices combine scalar processing engines and adaptable hardware engines with enhanced memory and interfacing technologies to provide heterogeneous acceleration for any application. Since then, the company has been enhancing this technology, targeting a variety of applications. ‘Along just such lines, in February, the company announced a range of new’ and advanced ML capabilities for Xilinx devices targeted at the professional audio/video (Pro AV) and broadcast markets, At the same time, Xilinx unvelled the industry's. first demonstration of a programmable HDMI 2.1 implementation on its 7nm Versal devices (Figure 1). These and other highly adaptable Xilinx solutions for the Pro AV and broadcast markets are designed to help customers reduce costs and future proof investments while keeping pace with new usage models and evolving industry standards, says Xilinx. The new ML capabilities for Xilinx Pro AV ‘and broadcast platforms include region-of-interest encoding, inteligent digital signage, automatic object tracking and window cropping and speech recognition. System developers can now take advantage of these ML capabilities on Xilinx devices, including the already highly integrated Zynq UltraScale+ 'MPSOC platform, for AI edge processing. The combination of ‘real-time audio and video processing, AV connectivity interfaces, codecs, IP networking, CPU and GFU into an adaptable and scalable single-chip solution can provide users with significant space, power and cost savings, says Xilinx. Pro AV system developers can apply the new ML capabilities across many applications and workloads. Region-of-interest enc: can be used to detect faces and features using ML and the Zynq UltraScale+ MPSoC integrated H.264/H.265 codec to keep video quality high in those areas and apply compression for backgrounds. This reduces the overall bitrate and saves significant costs in live streaming. ML models for gender, age and gesture detection can be used to provide targeted interactive advertising in digital signage. The result is a higher return fon investment for advertisers as well as ‘monetizable behavior metrics. With data rates up to 48Gbps, HOME 2.1 supports a range of higher video resolutions and frame rates, including 8K60 and 4K120, for a more immersive experience in LED walls, large format displays, digital signage and applications that rely ‘on fast-moving video such as live sports. Developed in preparation for this, HDMI 2.1 support on Versal ACAP allows customers to transmit, receive and process up to 8K (7680 x 4320 pixels) ultra- igh-definition (UHD) video. The 7am Versal ACAP offers scalar adaptable and intelligent engines in a software- programmable silicon infrastructure, providing 2 tight coupling between embedded software, ‘multichannel AV processing pipelines and AL inferencing, Additionally, combining real video processing, AV connectivity interfaces, codecs, IP networking, CPU, GPU and more into a single-chip solution means that developers can save space, power and cost, says Xilinx. AI INFERENCE ENGINE Flex Logix Technologies last fall announced its InferX X1 edge inference co-processor. According to the company, it has been optimized for what the edge needs: large models and large models at batch=1. The device is programmed using TensorFlow Lite and ONNX and performance modeler for it is available now. InferX Xi is based on Flex Logix’s nnMAX architecture integrating four tiles for 4K MACs and 8MB L2 SRAM. Inferk X1 connects to a single x32 LPDDR4 DRAM (Figure 2). Four lanes of PCIe Gen3 connect to the host processor. A X32 GPIO link is available for hosts without PCIe. Two Xis can work together to increase throughput up to 2x. The InferX X1 is expected to begin sampling in Q3 2020 as a chip and as a PCle board. In April, Flex Logix announced real-world benchmarks for the InferX Xt, showing significant price/performance _advantages when compared to Nvidia's Tesla T4 and Xavier NX when run on actual customer models. The details were presented at the Linley Spring Processor Conference. The InferX X1 has @ very small die size: 1/7th the area of Nvidia's Xavier NX and 1/1ith the area of Nvidia's Tesla T4, says Flex Logix. Despite being so much smaller, the InferX X1 has latency for YOLOv3, an open source model that many customers plan to use, similar to Xavier NX. On two real customer models, Inferx X1 was much faster, as much as 10x faster in one ‘case, says Flex Logix. LOW POWER FOR EDGE AI For its part Lattice Semiconductor's FPGA-based AI technologies place a strong emphasis on low power. In May, the company launched the latest version of its complete 4MB L3 SRAM Ca Xe} EVy Clears ee acune2 x32 Taye Daa) rey) info XL eige inference co-processor is hase en Flex Logi’ nai architecture integrating fou thes fr 4K MACS and BMB L2 SRAM. Lf Xi connects oa single x32 LBOORS DRAM, Fur ans of Pe ef, 4x32 GIO Ink aalable or oss wits Pe Two Xiscan work together omc ate hast proces increase throughput upto 2 a“ FIGURES The Latce sensAl 30 cs complite sldions support forthe Crest version of stack fr ‘AL procesing nce jy of FGA fr bw poner sort iin ects ae Fees a Reb acceerator Ita tsps Implmertation of commen GAN networks and is ote leverage the ral! abies of FPGAS, to ther prcesing solutions stack for on-device AI processing at the Edge, Lattice sensAI 3.0 (Figure 3). The latest version of the stack includes support for the CrossLink-NX family of FPGAs for low-power smart vision applications and features customized convolutional neural network (CNN) IP, a flexible accelerator IP that simplifies implementation of common CNN networks and is optimized to further leverage the parallel processing capabilities of FPGAS. To address data security, latency and privacy issues, developers want to move the AL processing that powers their smart vision and other AI applications from the cloud to the edge, says Lattice. And most edge devices are battery-powered or otherwise sensitive to power consumption, so developers need hardware and software solutions that deliver the processing capabilities needed for AL applications, while keeping power consumption as low as possible. By enhancing the sensAI stack, Lattice hopes to widening the range ‘of power and performance options available to embedded developers. For applications like smart vision that require higher Edge AL Performance, Lattice CrossLink-NX FPGAs running sensAI software deliver twice the performance at half the power when compared to prior releases of the solutions stack. (CUSTOMIZED CNN ACCELERATOR IP The new and updated features of the sensAL solutions stack include several elements. The stack now supports a customized CNN accelerator IP running on a CrossLink-NX FPGA that takes advantage of the underlying parallel processing architecture of the FPGA. Updates to the NN (neural network) compiler software tool let developers easily compile a trained NN model and download it to a CrossLink-NX FPGA, [A VGG-based object counting demo operating on a CrossLink-NX FPGA delivers 10"ps while consuming only 200mW. Object counting is a common smart vision application used in the surveilance/security, industria, automotive and robotics systems. When running on a. CrossLink-NX FPGA, the sensAl solutions stack offers up to 2.5Mb of distributed memory and block RAM and additional DSP resources for efficient on-chip implementation of AI workloads to reduce the need for cloud-based analytics. CrossLink-NX FPGAs are manufactured in a 28m FD-SOL process that provides a 75% reduction in power in comparison to similar competing FPGAs. Many components—image sensors, applications processors and so forth—used in smart vision systems require support for the MIPL 1/0 standard. One of the target applications for sensAl is smart vision, and CrossLink-NX devices are currently the only low-power FPGAs to deliver MIPI 1/0 speeds of up to 2.5Gbps, says Lattice. This makes the FPGAs well suited as a hardware platform for sensAl applications requiring MIPL support. ‘The FPGA's I/Os offer instant-on performance and are able to configure themselves in less than 3ms, with full-device configuration in as little as 8ms. Previous versions of sensAI supported the VGG and MobileNet vi neural network models. The latest version of the stack adds support for the MobileNet v2, SSD and ResNet models on the Lattice ECPS fomily of general-purpose FPGAs. AI TECH FIGHTS COVID-19 For its part, QuickLogic's FPGA-based AT solution revolves around its QuickAI platform for endpoint AI applications. The QuickAL platform features technology, software and oe Tem SS vbatoolkits from various AI software providers, including QuickLogic’s own subsidiary SensiML. Th May, SensiM announced that it is collaborating on an effort to use its AT technology to help predict whether people are showing symptoms of COVID-19 infection. One such capability involves using crowdsourcing to collect cough sounds from a. large number of volunteers and then analyzing that data combined with other datasets from the consortium using the SensiML Analytics Toolkit t identity the unique cough patterns associated with COVID-19 infections (Figure 4). The goa of the initiative isto give businesses, governments, healthcare and ather public facilities access to multi-sensor pre-dingnostic screening mechanisms to help slow the spread of the disease. ‘The initiative is supported by a consortium of companies, universities and health arganizatians including Asymmetric Return Capital, SkyWater Technology and Upward Health, an in-home and virtual care medical provider. In addition to its work with the Consortium to build an enhanced screening application, SensiMlL plans to open-source its wn crowdsourced cough sound dataset for researchers at large to access, “The conceptof utilizing Al for pre-diagnostic screening of cough acoustic samples has been studied and validated in recently published academic research and is supported by ongoing projects at multiple esteemed universities, says QuickLogic. Early published results suggest that using AI to identity coughs as a COVID-19 screening mechanism has significant potential, because the pathomorphology of the disease is distinctive from that of other respiratory diseases, 5G-ERA FPGA SOLUTION Long gone are the days when FPGAs were simple devices used for interfaces. Today's leading-edge FPGAs can do Al processing while supporting the speeds of the 5G era and enabling accelerated data analytics. Along those lines, in August, Intel began shipments of the first Intel Agilex line of FPGAs (Figure 5). In the data-centric, SG-fueled era, networking throughput must increase, and latency must decrease, says Intel. The Agilex FPGAs provide the flexibility and agility required to meet these challenges by delivering significant gains in performance and inherent low latency. Reconfigurable and with reduced Power consumption, Intel Agilex FPGAs have computation and high-speed interfacing capabilities that enable the creation of smarter, higher bandwidth networks and help deliver real-time actionable insights via accelerated AL and other analytics performed at the edge, in the cloud and throughout the network. The Intel Agilex family combines several Intel technologies including the second- generation HyperFlex FPGA fabric built on Intel's 10nm process, and heterogeneous 30 silicon-in-package (SiP) technology based on Intel's embedded multi-die interconnect bridge (EMIB) technology. This combination of advanced technologies allows Intel to integrate analog, memory, custom computing, custom 1/0 and Intel eASIC device tiles into a sae Comet Lastevent detected igure + SensiM. i colaberating onan ear to sympemns of COMD-1 rete. The: seca wth COMID-19 necore, is At tectnoogy to hap predict whether people ae showing IML Anais Tek is used dey the unica cough patterns rroures Alec FPGAs hae campiaton and high-oee interfacing caoabltes tha enable the creat of smacter, higher bendwath neers and hap delnerrea-tme artenaleiights via acebrated Al and eter anal performed thee, nthe oud and teaughat the network “6“6 FIGURES The VecrPath S706 accelerator cand fe OE 00 FIGURE? The Vector ted for high-bandwidth data aceera slerator Sotvare Deepa of Mirchi’ Plire FRGAS fr creatirg koro the Tho Soe 8 bare of DOR 7 acm gate bandivdth of AT making single package along with the FPGA fabric. Intel Agilex FPGAs are the first FPGA to ‘support Compute Express Link (CXL), a cache ‘and memory coherent interconnect to future Intel Xeon Scalable processors. The FPGAs support hardened BFLOATI6, with up to 40 teraflops of DSP performance. The FPGAs support PCTe Gen 5 as well as up to 112Gbps data rates for high-speed networking requirements for 400GE and beyond. Support is provided for several memory types, including the current DDR4 and upcoming DDRS, HBM and Intel Optane DC persistent memory. Design development tool support for Intel Agilex FPGAS is available today via Intel Quartus Prime Design Software. Weigel ey VectorBlox Accelerator i (SOK) is dened to hep develops take acrartage FPGA ACCELERATION There's no doubt that FPGAs are excellent implementation vehicles for AI/ML algorithms. FPGAs are both programmable and reconfigurable, giving them an advantage over GPUs when implementing newly developed AI/ML algorithms. With thatin mind, ‘Achronix Semiconductor says its Speedster7t FPGAs were designed for AI/ML application acceleration. Built with high-performance SerDes, high-bandwidth memory interfaces, dedicated ML processors and high-speed PCIe Gen5 ports, the Speedster7t FPGA family can handle the most demanding workloads. Speedster7t FPGAs were designed to address key design AI/ML challenges. The devices can ingest massive amounts of data from multiple high-speed input sources. They can then store and retrieve this input data, along with the DNN models, partial results from each layer computation, and completed computations. Those can then be rapidly distributed to on-chip resources that ‘can perform the layer computations quickly. Finally, the computed results are output in a high-speed fashion, Speedster7t FPGAs feature a 2D network- on-chip (NoC) with greater than 20Tbps bandwidth capacity for moving data from the high-speed interfaces to and across the FPGA fabric. The 2D NoC alleviates data bottlenecks with 256-bit, unidirectional buses in each direction for a total of 512Gbps for each NoC row and column, The primary interface for the NoC is industry-standard AXI channels. In October, Achronix and BittWare announced an FPGA accelerator card targeting high-performance compute and data acceleration applications. The VectorPath ‘S7tVG6 accelerator card features the 7nm Speedster7t AC7t1500 FPGA and offers the industry's highest performance interfaces available on a PCle FPGA accelerator card, ssays Achronix (Figure 6). The VectorPath accelerator card was designed for high-performance and_high- bandwidth data applications. It offers 400GbE QSFP-DD and 100GbE QSFP56 interfaces. For DRAM memory, there are 8 banks of GODR6 memory delivering 4Tbps aggregate bandwidth and 1 bank of DDR4 running at 2666MHz with ECC. Aside from the 20Tbps two-NoC mentioned earlier, the Speedster7t FPGA on board also puts to use its 692K G-input LUTs and 40K Int8 MACs that deliver over 80 tera operations per second (TOPS) performance. A 4-lane PCIe Gen 4 connector for is available for connecting expansion cards The VectorPath accelerator card includes a full suite of Achronix’s ACE development tools ‘along with BittWare's board management controller and developer toolkit, which includesthe API, PCle drivers, diagnostic self-test and application example designs to enable a rapid out-of-the-box experience. Designed for prototyping as well as high-volume production applications, the VectorPath S7t- VG6 accelerator card provides designers the ability to pracess massive amounts of data not possible with previous generations of FPGAs. FPGA KIT FOR AI VISION With the rise of AI, ML and oT, applications are moving to the network edge where data Is collected, requiring power efficient solutions to deliver more computational performance in ever smaller, thermally constrained form factors. To meet those needs, Microchip Technology in May released its VectorBlox Accelerator Software Development Kit (SDK) (Figure 7). It's designed to help developers take advantage of Microchip's PolarFire FPGAs for creating low-power, flexible overlay-based neural network applications without learning an FPGA tool flow, ‘According to the company, FPGAs are ideal for edge AI applications, such as inferencing in power-constrained compute environments, because they can perform more giga operations pper second (GOPS) with greater power efficiency than a CPU fr graphics processing unit (GPU), but they require specialized hardware design skills. Microchip’s VectorBlox Accelerator SDK is designed to enable developers to code in C/C++ and program power-efficient neural networks without prior FPGA design experience, The toolkit can execute models in TensorFlow and the open neural network exchange (ONNX) format, which offers the widest framework interoperability. ONNX supports many frameworks such as Caffe2, MXNet, PyTorch, and MATLAB. Unlike alternative FPGA solutions, Microchip's VectorBlox Accelerator SDK is supported on Linux and Windows operating systems, and it also includes a bit accurate simulator, which provides the user the opportunity to validate the accuracy of the hardware while in the software environment. The neural network IP included with the kit also supports the ability to load different network models at run time. For inferencing at the edge, Microchip says its Polarfire FPGAs deliver up to 50% lower total power than competing devices, while also offering 25% higher-capacity math blocks that can deliver up to 1.STOPS. By using FPGAs, developers also have greater opportunities for customization and differentiation through the devices’ inherent upgradability and ability to integrate functions on a single chip. The PolarFire FPGA neural network IP is available in a range of sizes to match the performance, power, and package size trade-offs for the application, enabling developers to implement their solutions in package sizes as small as 1mm x 11mm. GPUs FOR REAL-TIME AI GPUs have proven themselves as engines for performing AT and deep learning duties. Serving such needs, in May Nvidia announced two products for its EGX Edge AI platform—the EGX {A100 for larger commercial off-the-shelf servers and the tiny EGX Jetson Xavier NX (Figure 8) for micro-edge servers—designed for high-performance, secure AI processing at the edge. Using the Nvidia EGX Edge Al platform, hospitals, stores, farms and factories can carry out real-time processing and protection of the massive amounts of data streaming from trillions of edge sensors, says Nvidia, The platform makes it possible to securely deploy, manage and update fleets of servers remotely. Servers powered by the EGX A100 can manage hundreds of cameras in IR RGANBoards} ono SAVING COST-TIME with KES dena me boards + Basic and simple features, single power supply operation See ee oe try Prone Nel Ve 208 mek clone 10 LP F780 FPGA board INTEL SIZE x 2.126" (86 x 54 mm) ACM-208 is an FPGA board with Intel high performance FPGA Cyclone 10 LP. It's compact and very simple 3.3V single power supply operation. Spartan-7) CD XCM-210 is an FPGA board with Xilinx high performance FPGA Spartan-7. It's compact and very simple. 3.3V single power supply operation. Pe ee Pee ee eae et www2.hdl.co.jp/C20GFIGURE he energy-efcien to suppor Al worlnds bu are " ‘RESOURCES: ‘Achronix | www.achronix.com AMD | ww.amd.com BittWare | nwwbittware.com Flex Logix Intel | ve ot by Sze, weight o power budget airports, for example, while the EGX Jetson Xavier NX is built to manage a handful of cameras in convenience stores. Cloud-native support ensures the entire EGX lineup can use the same optimized AI software to easily build and deploy AI applications. The EGX A100 is the first edge AI product based on the Nvidia Ampere architecture. As AL ‘moves increasingly to the edge, organizations can include EGX A100 in their servers to carry out real-time processing and protection of the massive amounts of streaming data from edge sensors. It combines the high computing performance of the Nvidia Ampere architecture with the accelerated networking and critical security capabilities of the Nvidia Mellanox ConnectX-6 Dx SmartNIC to transform standard and purpose-built edge servers into secure, cloud-native AI supercomputers. vn flexogix.com Lattice Semiconductor | www.Jatticesemi.com Microchip Technologies | wwww.micachip.com Nvidia | www.nvigia.com Quicklogic | wwn.quieklagie.com Xilinx | wwe xlinx.com NVIDIA AMPERE ARCHITECTURE The Nvidia Ampere architecture—the company’s 8th-generation GPU architecture boasts its largest-ever generational leap in performance for 2 wide range of compute- intensive workloads, including AI inference and 5G applications running at the edge. This allows the EGX A100 to process high-volume streaming data in real time from cameras and other IoT sensors to drive faster insights and higher business efficiency. Nvidia's EGX Jetson Xavier NX serves as a small, powerful AI supercomputer for microservers and edge AloT boxes, with more than 20 solutions naw available from ecosystem partners. It packs the power of an Nvidia Xavier SoC into a credit card-size module. EGX Jetson Xavier NX, running the EGX cloud-native software stack, can quickly process streaming data from multiple high- resolution sensors. The energy-efficient module delivers up to 21T0PS at 15W, or 14TOPS at 10W. As a result, EGX Jetson Xavier NX opens the door for embedded edge-computing devices that demand increased performance to support AT workloads but are constrained by size, weight, power budget or cost. The EGX A100 will be available at the end of 2020. Ready-to-deploy micro-edge servers based on the EGX Jetson Xavier NX are available naw for companies leoking to create high-volume production edge systems, HPC EMBEDDED PROCESSORS Nvidia technologies aren’t the only GPU solutions targeting the embedded space. In April 2019, AMD launched an expansion to the Ryzen Embedded processor lineup with the AMD Ryzen Embedded R100 SoC. Built fon “Zen” CPU and Radeon “Vega” graphics cores, the Ryzen Embedded R1000 processor delivers 3x better CPU performance per watt compared to the previous generation AMD Reseries Embedded processor, and 4x better CPU and graphics performance per dollar than the competition, says AMD, In February of this year, AMD expanded the product line with two new AMD Ryzen Embedded R1000 low-power processors. The two new chips, designed for efficient power envelopes, are the Ryzen Embedded R1102G and R1305G processors. The new processors scale from 6W up to 10W of TDP respectively, while also giving embedded developers the ability to reduce system costs with less ‘memory DIMMs and lower power requirements. With this low power envelope, these embedded processors give system designers the ability to create fanless systems, opening new markets that can leverage the high-performance Ryzen Embedded processors.Pee Cts oy Maro) bi htd | WirelessWonders As the IoT phenomenon cont ange ts cbr and pf sound, wher Sif SPD ced NodeHCU E stan dance Te ey crponents ft ues to gather momentum, so too is the demand for highly integrated modules designed for the IoT edge. Feeding those needs, a new crop of IoT modules have emerged that offer pre-certified solutions reading for design in. he Internet of Things (IoT) has become fone of the most dynamic segments of today's embedded system design. The scope that comprises IoT edge devices includes a combination of embedded processors and microcontrollers (MCUs) that provide intelligence, Those are combined with various wireless, cellular and other connectivity solutions to connect to the network. To get to market quickly, ToT system designers are looking to modular solutions that combine intelligence and connectivity, while also taking fon the vital certifications needed to get IoT implementations up and running. Over the past 12 ‘months, a new crop of module-based products have emerged aimed directly at [oT. The product gallery in the next two pages provides a representative look at some of these modules. ‘An example application using modular IoT technology, is an ESP8266-based, distance monitor designed to help people properly maintain the official guidelines for social distancing during the COVID-19 crisis. ESP8266 is an integrated Wi-Fi MCU for ToT applications from Espressif Systems. Since the beginning of the COVID-19 outbreak, the World Health Organization (WHO) has issued 2 number of basic protective measures against the new coronavirus. Along with practicing meticulous personal hygiene and wearing a mask as appropriate, one important piece of advice from the WHO experts has been to maintain social distancing. This has been specified as keeping a specified distance between yourself and other people. With that in mind, Sabil Rastogi and his team at Random Stuff We Make! (RSWM!) in Delhi, India, built 2 gadget that can help people properly implement the WHO guidelines about social distancing. The gadget that RSWM! created is called “Wearable Corona Distance Monitor” (Figure 1) This simple wearable device changes its color and pitch of sound, whenever a person comes closer than one meter to you. The key components of the device are an Espressif ESP8266-based NodeMCU ESP8266 breakout board and an Adafruit WS2812 5050 RGB LED NeoPixe! Ring, ror‘System Module Sports NXP .MX8M Nano Processor Based on the NXP i.MX8M Nano application processor, the Digi ConnectCore 8M Nano from Digi is an integrated system-on-module (SoM) platform. The Nano is designed for a wide range of industrial, medical, agricultural ‘and transportation applications, including ToT, human-machine interface (HMI), equipment monitoring, audio(voice, edge computing and machine learning (for ‘example anomaly detection). ‘= Industrial i,MX8M Nano quad/dual- core SoM ‘= Digi SMTplus form factor (40mm x 45mm) ‘+ Power management with both HiW and SW support for low-power designs ‘= Multi-display and camera capabilities with hardware acceleration + Pre-certified dual-band 802.11a/b/ g/nfac 1x1 and Bluetooth 5 connectivity ‘* Seamless cellular modem and Digi XBee integration ‘Built-in device security, identity and privacy with Digi TrustFence ‘+ Remote monitoring and management. with Digi Remote Manager Digi www.digi.com Module Uses Espressif's ESP32-DevKitC-32D The ESP Module from Edge Devices leverages benefits of Espressif’s ESP32- DevKitC-320, which lies at the heart of the ESP Module, The module's circuitry allows for the control of four Panasonic SPOT relays via GPIO pins. SV circuitry protection allows ESP32 to be powered from the screw terminals. Two more screw terminals function as grounds for power and GPIO pins. * Based on ESP32-DevKitC-320, with ‘an ESP32 dual-core processor, 32Mb SPI flash + 4x Panasonic SPOT relays controlled via GPIO pins * Screw terminals for relay outputs, ‘6x analag inputs and 2x analog outputs + 5V input, 3.3V and GND + 5V input via terminal or Micro USB port; 5V circuitry protection * DIN rail enclosure Edge Devices www.edgedevices.io BLE Module Serves Up Arm Cortex Processor InnoComm BM20 module is based fon Nordic Semiconductor's nRF52832 Bluetooth Low-Energy (Bluetooth LE) ‘SoC. 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This uniquely provides highly reliable, accurate Positioning data simultaneously with LTE communications * Secure Cloud LTE-M, NB-IoT and EGPRS module * Integrated M8 GNSS receiver for multiregional use * End-to-end security with root of trust + Software-based configurability within each hardware design + Simultaneous LTE communication with GNSS positioning * Future-proof solutions via LWM2M and uFOTA U-blox www.u-blox.com,Salo ieee) PM Ice! ay Cr] eer eet MIDI Tt izer (Part-2) Cus Mure rte Rs od heavy lifting. By lee no NS ey FIGURE 1 my last article (Circuit Cellar 358, May 2020 [1)), I described how a common musical "instrument synthesizer— the wavetable _synthesizer—worked I covered the origin of the SoundFont file standard, which is commonly used by such synthesizers. Because these SoundFont files are quite complex and not rigily structured, it is useful to have a decoder program that converts SoundFont files into a format that the microcontroller (MCU)—which i implementing the synthesizer—can readily handle. In Part 4, 1 described a Python program that 1 had modified to perform this task, and outlined how to install and use it. In this article, Vl describe the Teensy 4 firmware that I wrote, which implements a MIDI Wavetable Synthesizer. Then I'll cover Cee PTR Tie ee es SS Pik vara NXP iMRTIOS2 Ary MCU, I rune a GOON the schematic diagram of the project, which is quite simple, since the Teensy 4's MCU handles most of the functionality itself TEENSY 4 FIRMWARE The Teensy 4 is the latest member of the Teensy MCU module family. It uses NXP Semiconductors’ iMxRT1062 MCU, which runs at 600MHz and contains 2MB of program flash memory and MB of SRAM. Unlike the earlier Teensy 3.6 module, the Teensy 4 module uses a smaller PCB in a DIP28 format. This keeps the price of the module low ($20), although I preferred the greater 1/0 capability of the Teensy 3.6. That said, for this project, there were sufficient 1/0 pins to handle everything. Figure 1 shows the Teensy 4 module. While not visible in the image, the underside of the PCB contains footprints for more 1/0 capability, including a footprint for a full-speed (S010) SO card interface The firmware running on the Teensy 4 consists of three main components: 1) The AudioSynthWavetable object, which Is part of the Teensy Audio library. This was written by a group of Portland University students. I modified it for this project, as mentioned in Part 1. 2) The MIDI note handling engine, which handles incoming MIDI messages. It parses the Note On/Off messages, and assigns each playing note to a dedicated ‘AudioSynthWavetable object. MIDI control messages for Modulation (’Mod” wheel) ‘and Channel Aftertouch are routed to thevibrato function. MIDI volume messages adjust the gain of the output mixer. Seven ‘other midi controller slider messages are mapped (using the "Learn" Menu) to adjust the 7-band Graphic EQ filters. 3) Seven-band Graphic EQ. 1 implemented this totally in software, using the Audio library's Biduad filter objects (Figure 2) all filters are 4-stage biquad filters configured as bandpass filters. T set the 0 values for ach filter to allow that filter to provide an adequate response up or down to the adjacent filters. All the center frequency and Q values can be modified, if desired, by changing values in the setFilters() routine (at the end of the program listing). Now, let's look at each program section in more detail, The Aud oSynthWavetable object is a complex bit of code. Apart from some parameter-initializing routines, its main function is handled—as are all Audio library objects—in the update member of the class. ‘The update routine gets called automatically at the 44,100Hz sample rate. It is responsible for stepping through the selected voice's wavetable at arate that will produce the desired note frequency. This is done basically by using the DDS (Direct Digital Synthesis) principle. For any given voice, there will be several sample waveform tables—one for each “region” of the keyboard. So, depending upon the frequency of the note being played, a pointer to the correct waveform array must be determined, ‘As mentioned in Part 1, when the MIDI keyboard sends a Note-On message, the sound synthesis process must break down the waveform generation into two parts: the initial “attack” portion, which consists of the first "x" samples in the wavetable array, and the "loop" section, which consists of the rest of the wavetable array. After taking samples from the beginning of the array (the attack), for a period of time defined by that voice's attack- time parameter, the wave generation is pointed to the loop section of the array. It then loops through this section of the array continuously, until a Note-Off message is received from the keyboard controller. Then it enters the “release” phase, in which it repeatedly scans the loop section of the waveform array, but gradually introduces attenuation to the waveform to allow it to fede out exponentially. This would occur with an acoustic musical instrument played in an actual room (with reverberation). A new Teensy 4.1 module came out since I wrote this article. This module uses the larger Teensy 3.6 footprint, and contains more memory, 1/0 lines, a built in SD card socket and an Ethernet port. Modulation effects such as. vibrato, which are specified in certain sections of the SoundFont file, must also be handled by the update routine. While the original AudioSynthWavetable object handled any vibrato that was specified in the SoundFont file, it did not allow for vibrato to be introduced by the MIDI keyboard’s Modulation controller (Mod wheel) or Channel Aftertouch. T added that feature in the main section of my program, in conjunction with a slightly modified AudioSynthWavetable library object. MIDI NOTE HANDLING The MIDI note-handling engine is. performed using the MIDI class itself. The MIDI class is set up to handle incoming MIDI messages on an interrupt-driven basis. So, whenever 2 MIDI message comes in, a sone Wovetabid represents Woretabie object mined ‘ogee 7-Band Graphic EO. Fer amplitudes, for each band, are set byvaring the ie of ach ofthe inputs oftnert 2 MiDivoume resiages are opted ere racuRe2 Layout of the audo Hoste used for the shes, as they appear the ‘dio Design Tos. Al ofthe sund ‘gereration is doe by the Wavetable Bleck, The recto the Hacks ae ut 1 Thand Graphic EQ mace up of ‘irate bina =“ background routine picks up that message ‘and parses it into one of many different MIDI message types. My program basically recognizes the following MIDI messages: 2) Note On/Off 2) Continuous Controller: MIDI Volume, Mod wheel and EQ settings are recognized 3) Program Change: selects the different voices available on the SD card 4) Channel Aftertouch: if you press down hard on (any) key, the Channel Aftertouch ‘message will be sent. This program responds by introducing vibrato at an amplitude dependent upon the key pressure exerted. ‘We must define callback routines for each of the above types of messages. In the case of Note On/Off messages, a note allocation routine must be performed. Basically, every Note-On message results in assigning one of 48 discrete Aud ioSynthWove orm objects to that particular note. When a Note-Off message arrives, the program must scan through all 48, AudioSynthkaveform objects to determine ‘which one of them is “playing” that particular note. Then, that particular object is sent a “Stop playing” command. But it’s a bit more complicated than that Even after you release a key corresponding to 2 particular note, the wavetable object that is playing that note isnot yet finished with it. Tt has merely gone into the release phase, where itis still sounding the note, but at a decaying amplitude. The amount of this release time is entirely dependent on the release-time parameter in the SoundFont file, Additionally, that release time can vary, depending upon the frequency of the note being played (that is, what region of the keyboard has triggered the playing ofthat particular note). Therefore, you must call a function—1s?1aying()—to etermine whether a particular wavetable object is still playing a note. The routine freevoices() must be called repeatedly. It looks at each active wavetable object, using isPlaying(), and once it returns a false condition, ‘that particular wavetable object can be returned to the idle (free) group. Once freed up, it can be re- assigned, as necessary, for future incoming notes. Because of this release time, many voices can be sounding at any given time, even though you only have 10 fingers with which to play the keyboard. Granted, many sounds will be virtually inaudible at the end ofthe release. This explains why I allocate 48. wavetable objects to handle so many sounding voices. The Control Change message for Volume is easily handled by adjusting the gain ofthe two inputs of the final mixer object. This mixer combines all seven signals from the 7-band ‘graphic EQ. The Control Change message for the Mod wheel is more complicated. I must basically take the Mod wheel value (0-127) and store it in the following two variables {efter dividing it by 1,024) sd0[x].MODULATION_PITCH_COEFFICTENT_ INITIAL sdO[x].MODULATION_PITGH_COEFFICTENT_ SECOND where x goes from 0 to the number of keyboard regions minus 1. This is necessary so that notes that fall into all the various regions (based on frequency), will each respond to the Mod wheel (vibrato) messages. PROGRAM CHANGE The last type of controller message is the Program Change message. This takes the form of a number in the 0-127 range, which correspond to various “programs” (voices). When these messages are received, the program attempts to load in a SoundFont file from the SD card, with a primary filename from "1" to" 127.” Two filesare loaded: an xxx-h file and an xxx.cpp file (where xxx is in the 0-127 range). These extensions were defined inthe original Python program, written by the developers of the AudioSynthWaveform ‘object. As mentioned in Part 1, that Python program converted standard SoundFont files into two files with .cpp and .h extensions that were meant to be “included” in the synthesizer program itself. The original developer's firmware could play only the one voice that was included in the program code, itself. Even though I have changed both the Python program and the Teensy 4 firmware to enable loading user-selected voices into ‘SRAM, Trretained the original .cpp and .f file~ ‘naming convention. When I first heard of the Teensy 4 module, ‘one of the impressive specs—in addition to the smoking 600MHz clock speed—was the large amount of on-board memory: 2MB of program flash and 1MB of SRAM. A Wavetable synthesizer requires a lot of SRAM to handle complex musical instrument voices. I'll be honest—commercial wavetable synthesizers contain many megabytes of SRAM, and that's part of the reason they are so expensive. I felt that the 1MB of SRAM on the Teensy 4 would bbe enough to handle many useful samples. It turns out that the Teensy 4's IMB of ‘SRAM is not just one big block of memory that is completely free to use for your program's variables and arrays. (The Stack and Heap take up a small amount of it, of course.) Instead, it is broken up into two S12KB sections. At run time, the MCU copies the program code fromflash memory into the lower 512KB section of SRAM memory to boost execution speed It allocates this program SRAM in discrete 32KB blocks. For this program, that is about 81KB, so it uses up a 96KB block of the lower '512KB block of memory. Allowing for other miscellaneous variables and Stack space, it turns out that only about 380KB of SRAM are available for the sample wavetable, from within this 512KB block. The upper 512KB biack is physically coupled to the CPU in a different fashion than the lower S12KB. It is labeled as DMA memory. It turns ‘out you can use this DMA memory for your sample wavetable, by using the “DMAMEM” directive when declaring that array. However, you can only allocate 512KB for this array. You can’t combine it with whatever is left of the lower 512KB section after the program is transferred there from flash, So, the maximum sample wavetable is 512KB minus the Heap size. I settled on a sample array of 120,000 elements consisting of 32-bit integers, The sample wavetable array actually stores 16-bit samples, packed two per 32-bit element, so that’s 240,000 discrete samples. Lots of useful voices require sample sizes less than this, but you won't be able to load in a really good piano voice, as those are quite complex. The Python program that generates the files used by this synthesizer shows the size (in bytes) of the sample file that you are considering. Each SoundFont file defines the number of regions that were used in producing the file. Each ragion covers a range of MIDI notes. If you have chosen a Soundfile for a ‘complex instrument, you may have to pick just a subset of all the available regions, to stay within the 240,000 16-bit sample limit (which the Python would show as 480,000 bytes). 7-BAND GRAPHIC EQ The last functional block is the 7-band Graphic EQ. I did a lot of experimenting with various filter configurations before settling on the configuration shown in Figure 2. Initially, I thought it would be interesting to try to implement a multi-band parametric EQ using a single, 513-tap FIR filter. In my article "Faney Filtering with the Teensy 3.6" (Circuit Cellar 346, May 2019 [2]}, I described a convolution filter object, which I had designed for the Teensy Audio library, that emulated a 513-tap FIR filter (using FFT/iFFT techniques). Although that design worked well for some applications, it turned out that trying to force it to handle a multi-band parametric EQ was not particularly successful. The 16~ bit, integer-based FIR impulse array did not have the required precision to handle so many different frequency bands. Also, it turns out that a 513-tap FIR filter, using a sampling rate of 44,100Hz, has an FFT (fast Fourier transform) bin size of about 86H2. The lowest filter frequency that would work at all must be at least 3 times that bin size, or 258Hz. A lot of musical instrument content lies below this frequency, so the FIR filter idea was abandoned. Instead, I decided to use a bank of seven, 4-stage biquad filters. There is a Teensy Audio library object for the biquad filter. It is easy to use: you just load the object with the type of filter (band-pass in this case), the center frequency and filter “Q," and it does the rest. Each of the four sections of the filter must be initialized this way. The diagram of this from the Audio Designer application, including the frequencies that I chose for each band, is shown in Figure 2. All seven filters are fed to individual inputs of Mixerl and Mixer2, ‘and thase two mixers are combined in Final Mixer3. You adjust the gain for each of the seven bands by setting the input gains of Mixer and 2. In use, I “map” seven of the MIDI keyboard's sliders to the seven EQ bands, using the Learn option available when you press the Menu button. This needs to be done just once, when you first power up the synth after programming the Teensy 4's firmware. After performing that “learn” function, the program saves the MIDI control numbers of the seven sliders you chose to assign to the 7-band EQ. That mapping is stored in the config.txt file on the SD card. Figure 3 shows in| rouRe3 “dno6 the bank of sliders on my MIDI keyboard controller. They are nicely suited to setting a Graphic EQ filter. When playing the synthesizer, moving any or all of those sliders will adjust the frequency response of the 7-band EQ. Also, if you hit the SAVE button, that frequency response curve will be stored in the config.txt file, indexed to the current program number. In other words, the 7-band EQ settings can be uniquely saved for each voice Initially, I had decided to save both the keyboard slider mapping and the seven EQ filter gains (x127 voices) to EEPROM, because there were less than 1,000 values to store, and those parameters mustbe non-volatile. Teensy 4's iMXRT1062 MCU does not contain any real EEPROM memory. The EEPROM library handles this by using a 64KB block of program flash for EEPROM emiatan spreading your data space for wear-leveling purposes. ound that attempting to use this EEPROM library resulted in my program crashing, and, if my memory serves me correctly, I think it also “bricked” the MCU (which is reversable by re-flashing the device using a 15 second press of the Program button on the Teensy 4). On the Teensy Forum [3], Tran into others who had experienced the same problem, so I decided to abandon the EEPROM route and instead store this data to the SD card (in the config. txt file) I expect that this bug has been fixed by now. There is a Menu option to set the MIDI port ‘on which the synthesizer will respond. If you select “0,” the MIDI OMNI mode will be active, This will respond to MIDI messages on all 16 channels. Otherwise, MIDI channels 1 through 16 can be selected. The LCD display will show what MIDI channel the synthesizer is set to respond to. The MIDI channel selection is non-volatile, and is stored in the canfig.txt fle fon the SD card, As a troubleshooting aid, whenever a key is pressed on the MIDI keyboard, an LED on the synth will turn on, and stay lit until the key is released. If this doesn’t occur, then you have the synthesizer set to the wrong MIDI channel, or there is some hardware issue in tthe MIDI input port circuitry. nella, eee re FIGURES Shown hae isthe cae schema ‘4D notatthe time I dsgne the pr weer, des nan proc. used the legay type of MIDE part (Spin ON canes, Wo ie eater Teeny mecBecause I made some changes and enhancementstotheaudioSynthWavetable object, it is imperative that you replace the following two original files—synth_wavetable. cpp and synth_wavetable.h—with the same- named files that I provide for this project on the Circuit Cellar article code and files webpage [f]. These two files are located at: C:\Arduino- 1.8,9\hardware\teensy\avr\, libraries\Audio [1] Note that the initial part of the path shown above should be amended to the folder where your existing Arduino IDE is located, which ‘may be different than on my PC. T have not tried to run this program on a Teensy 3.6, which would be the only other Teensy module that had anywhere near enough SRAM. The original Audio Synth Wavetable library will work on the Teensy 3.x modules, but must be quite limited by the smaller amount of SRAM available on those modules. To compile programs for the Teensy 4, you must be running Arduino 1.8.9 or newer, and Teensyduino version 1.47 or newer. CIRCUITRY The schematic diagram of the unit is shown in Figure 4. There is no power supply shown, because power for the whole unit is supplied by a SV USB adapter that plugs into the Teensy 4 micro-USB socket. The Teensy 4 module contains a low-dropout, 3.3V regulator that provides power to the Princeton Technology PT8211 Stereo DAC. All the remaining circuitry is powered from the Teensy 4's SV pin, The Teensy 4 module contains a footprint for 2 flex cable that can be connected to an SD card socket. This is found on the underside of the module. This footprint is connected to the MCU’s SDIO (4-bit) native SD port. I thought it was advantageous to use this high-speed SD card port rather than connect an SD card to the standard SPI port on the MCU for two reasons. First, the wavetable samples can be quite large, and the higher speed of the SDIO port is advantageous (over 4x faster). Second, The Teensy 4 has many fewer 1/0 pins compared to the earlier Teensy 3.6/3.6 modules. I needed the SPI pins for other purposes. Choosing to use the SDIO SD card interface was a tough decision, since the SDIO PCB footprint is quite small—the pads use Imm spacing. T don’t agree with PIRC’s decision to squeeze this module into such a small size, equal to that of the earlier Teensy 3.2 module. If you want to use an SD card with the SDIO port, you need a couple of tiny FPC (flexible printed circuit) sockets, an FPC flex cable and a separate PCB on which to mount the SD card. This adds $10 to the cost, and requires some tricky soldering. Now that the Teensy 4.1 module is available, it would make sense to use it and avoid this external socket issue. I chose instead to do it my own way. In Figure 5, you can see where I've soldered eight wire-wrap wires to the SDIO footprint, and connected them toa small breakout board containing an SD card socket. I applied some black epoxy over the wire bundle, close to the SDIO footprint, to act as a strain relief. The wires are about 4" long—enough to allow me to mount the SD card socket at an accessible point on the enclosure. The SDIO interface is a fast one, so I don’t think it's a good idea to make the connecting wires any longer than this. T don’t believe it was any harder to solder those eight wires than to solder a tiny FPC socket in place on the Teensy board, and another one at the SD card PCB. T happened to have an SD card breakout board handy, but it’s easy to solder the wires toa microSD-to-SD card adapter (which comes with most microSD cards). This provides a free microSD card socket without requiring a FIGURES The ear Teensy 3:56 modes cntained 3 bultin SD card socket, However, Thad to mate up 2 sm ‘SD cr socket tothe very tiny 5D cad fontrit onthe batt othe Tetsy 40 module naw Teeny 4.1 ale includes an SD sce, Honerer, th the Teeny 40, had to make op enteral socket and cable assemblyse FIGURES Ts i the complete sythescer at rogram. four siches navgote trough the vrious configiration/perfarmance meri and 9 rotary der aust porerecer values en my deck ring the wesks that spent wring the custom PCB and conventional microSD card socket. While I use color TFT displays for many Projects, commercial synthesizer modules generally just use modest LCD alphanumeric displays. The user interface is pretty basic, so I settled on a 20 character x 2-line LCD display. Tt requires a 6-wire interface to the Teensy’s GPIO lines, and a good Arduino library is available for it. ARM MCUs I didn’t have a lot of choice about the type cof MIDI port I could use. While earlier Teensy modules supported USB-MIDI (using the on- board micro-USB connector), the Teensy 4 is different, The NXP iMXRTL062 Arm MCU used fon the Teensy 4 module is quite different from the Freescale Arm MCUs used on the Teensy 3.x modules, It took some time to develop the multiple USB profiles that were available on the Teensy 3.x modules (Serial, MIDI, Keyboard, Joystick and others). The For detailed article references and additional resources go to: wwrw.circuitcellar.com/article-materials References [1] through [4] as marked in the article can be found there. RESOURCES Microchip Technology | wwrw.microchip.com INKP Semiconductors | wwaw.xp.com IRC | wn pire.com Princeton Technology | wwcprinceton.com.tw latest version of the Teensyduino program ‘now contains @ USB-MIDI profile, but when I developed this project, that was not available. Therefore, I used a legacy-style MIDI port consisting of a 5-pin DIN socket and a 6N138 ‘opto-coupler. Note that the 6N138 requires 5V of power to run properly, but the open collector output must be returned to the 3.3V supply (via R2), since the MCU GPIO pins are not 5V-tolerant. When I started this project, I connected the Teensy 4 to PIRC’s audio adaptor board. I had one on hand, and there was some discussion on the Teensy Forum about whether it would work with the much faster NXP iMXRT1062 MCU. I had no trouble getting it to work, but for this project, 1 only needed a DAC for an analog output signal—not a full codec as is found on the audio adaptor board. Therefore, I replaced the audio adaptor board with a PT8211 16-bit audio DAC, which also interfaces with the NXP IMXRT1062 MCU via its PS bus. The PT82L1 driver, part of PIRC's extensive Audio Library, uses 4x oversampling (6 x 44,100 =176,400H2 SR) for better sound quality. The PT82i1 chip, itself, is a bargain at less than $1, but is not readily available from US distributors. I was able to get a pack of 10 ‘of them from eBay some time ago. However, PIRC sells a tiny breakout board containing the PT8211 and a few passive components for less than $3. ‘The PT8211's stereo output is sent to a 3+pole Butterworth low-pass filter made up of passive components and Microchip Technology dual op amp MCP6002. Since most musical instruments—apart from cymbals and the like—don’t produce harmonics beyond 10kHz, the filter is set for about 12kHz. It effectively removes any of the DAC clock signal and high-frequency hiss that can be introduced by limitations in the resolution of the sample wavetables. It also removes noise introduced by all of the 16-bit processing that the MCU ‘must do to implement the 20 software-based mixers needed for the design. The MCP6002 is a single-rail op-amp capable of rail-to-rail input and output. No negative power supply is needed for this op amp. The SoundFont files are monaural, as is the whole signal generation/processing chain in firmware. You can only get audio DACS in a stereo configuration, and I decided to filter both output channels individually, and provide stereo output sockets. The Teensy 4 is only using 1% to 10% of its available horsepower for this program (depending on how many notes are being played at one time). You could add additional effects like reverb or chorus to the program. In this case, the included stereo hardware may be utilized more fully. All user input/adjustments are performedusing a rotary encoder to choose between various menus and to adjust parameters. Four push buttons are implemented: Menu, Enter, Save and Exit. I am not using Exit currently. ‘The 20*4 LCD display requires SV of power to operate properly. I get that from the 5V pin on the Teensy 4 module, sourced from the USB port which, in this project, is connected toa 5Y USB power adapter. Even though the LOD display is powered from 5Y, its logic pins require only TTL signal levels. Therefore, the 3.3V logic levels coming from the MCU's GPIO output pins are perfectly fine without any need for level-shifting The circuit board containing the circuitry, as well as the external components before mounting in an enclosure are shown in Figure 6. CONCLUSIONS T must congratulate the four students at Portland University, who developed the Python program to convert the complex SoundFont file format into something that the Teensy could use, and to write the actual Teensy Audio library routine itself. T've written several Teensy Audio library routines, and can appreciate how complicated they are to understand and write, Start yo 1 think that the versatility of this library was limited by its ability to emulate only one musical instrument voice. The modifications that I made to allow for multiple voices, loaded from an 8D card, make the whole concept much more useful. Also, my addition of Mod wheel and Channel Aftertouch capability is something that most musicians would require. The 7-band Graphic EQ is also a nice feature to have. Having used such an EQ (one is included in my professional-orade digital mixer), I acknowledge that the implementation found in this program, using anly 2 four-section biguad fier per bond, is not as sonically acurate. But in my opinion, i ‘works reasonably wel “Ten years ago, it would have been unthinkable to get an MCU as powerful as the iMXRT1062 on a module that costs only $20. The Teensy 4, with its associated Audio library, will certainly see a ot of use in many different audio projects. © ABOUT THE AUTHOR Brian Miller runs Computer Interface Consultants. He was an instrumentation engineer in the Department of Chemistry at Dalhousie University (Hlifax, NS, Canada) for 2 years. is learning journey. BS Cota cei even) Pee oar Precacg ee earn DN aeae RE eee Cree ss Tea Deets Peet Tena cue! Pe eas akaEmbedded System Essentials Building the ChipJabber-Unplugged Old-School Glitchi By Colin O'Flynn ; — The Chipebber-nluged ina ts glony—net 2 steface mount component ght Voltage glitching might seem like the latest security threat, where attackers are using complicated FPGA and digital logic designs to perform the fault injection. But at its core the idea is simple. In this article, Colin demonstrates how you can build a classic project, using only through-hole ICs and zero programmable logic. 1 past articles, I've talked about my threats, I wanted to see how “old-school” T ChipWhisperer project (for side-channel could go and stil build a useful fault injection Power analysis and certain types of circuit. So, we're going to reproduce the fault injection), as well as ChipSHOUTER attack from my article “Recreating Code (for electromagnetic fault injection). Protection Bypass” in the September 2018 Another ongoing project is something called (Circuit Cellar 338) [1]. In that article Tused my ChipJabber—which performs voltage fault — ChipWhisperer device, which has an FPGA to injection. But, for a bit of fun, I've also built generate pulses with specific time offsets and a simplified version of the tool that anyone widths. Instead of using an FPGA, we're going ‘can make, to generate those pulses the old-fashioned This month I'm taking you on a bit of a way with RC delay circuits and discrete logic throwback to more classic magazine articles— chips. Instead of a programmable computer when you had home-etched PCB art alongside interface, you'll have to twiddle a variable something you could build with discrete parts. resistor knob to adjust the delay values, It might be just what you need to complete a Tim going to cheat a little in this article project on your own with things you've already and will use two recent devices—a Microchip ‘got on hand. In fact, you can easily build this Technology MCP1825 LDO adjustable voltage Circuit in a breadboard or on prefboard—it has regulator (introduced in 2008) and a Maxim ro surface-mount device (SMD) parts at all. Integrated MAX4619 multiplexor (introduced While many of my articles reference the in 1999), Neither are critical for building a most recent devices and the latest security working circuit—for example the LDO hasfa smaller (less than 0.5V) drop-out than a classic Texas Instruments LM317 (greater than 2V) drop-out. This makes the design mare practical since it can be powered from three AA cells, and avoids needing more expensive 9V batteries. For the multiplexor, it’s possible to use older devices, or even Use a single MOSFET as part of the output driver. Figure 4 shows the final result—the CChiplabber-Unplugged in all its glory. This PCB has a minimum number of vias to make it possible to build in a home-etch tank, or in my example, it’s been milled out with Bantam Tools PCB Mill But 1 will still be presenting you with a Circuit that uses all through-hole circuits, and has a minimum number of vias (perfect if you need to etch or mill your own boards). Most of iy logic is going to be using newer technology (working at 2V-6V range). The chips are all available in older technology versions, in case you want to build the true vintage version of this design. We'll discuss those changes later, let's first remember what we need to do. BEGIN AT THE END T can't include all the details of the background of the attack in this one article. But luckily, it's something I covered in my previous article from September 2018. If you don’t have that handy, I can refer you to the tutorial posted as part of ChipWhisperer [2], or @ more detailed walk-through will be linked as part of the Chiplabber-Unplugged material [3]. This attack is also detailed in my upcoming book “The Hardware Hacking Handbook” (published by No Starch Press), but unless you have a time machine you are better sticking with the already published sources. The quick summary is that the LPCLI14 device from NXP Semiconductors (along with several related parts) use a special "magic value” programmed into flash location Ox2FC to indicate that read-protect is active. If that value is corrupted, the device thinks that no code protection is enabled, and the device will respond to read requests. ‘To do this attack, we will reset the device, and insert a fault during the boot-up process. Once the device boots, we force the device to go into the built-in bootloader. From this bootloader, we'll check to see if a read of flash ‘memory is allowed. Ifthe read-protect worked as expected, it will block the read. But if we ‘managed to corrupt the code read protect (CRP), well instead read the corrupted value ‘To inject the glitch, we will drop the core voltage of the device slightly during the boot process at a specific instance in time. This causes a perturbation on the power supply rail, which is enough to somehow corrupt the Paso Peo | ue poe | Oupt Generator 1 Generator 2 ricure2 checking of the read protect value. In this case we don’t know the specific effect we cause. For example, we could be causing instructions to be skipped, or we could be causing only the value to become garbled. Both will have the same effect. MAKING PULSES AND TAKING NAMES The core of the logic is a pulse generator built using the SN74AHC123A from Texas Instruments (introduced July 1997—the original 74123 introduced in 1983) monostable multivibrator. This device allows us to trigger on ising and falling edge pulses, and generate a specific output width pulse as set with an RC circuit. Using two such blocks in series allows us to generate first a pulse with a specific delay from the initial trigger edge, and then with a certain width. As you can see in Figure 2, this means we can generate a width and delay dependent on the individual pulse generator settings. By using adjustable RC values to adjust each pulse width, we now have an adjustable width and delay from the trigger event. ‘Our goal here is to insert faults on specific cycles of the target device. This means we actually would like an ability to shift the pulse around on a very small time-scale to target specific operations—meaning adjustments in the range of hundreds of nanoseconds. But at the same point, we may need to offset where the fault occurs from the trigger on a larger time-scale, because the device may perform ‘many operations before we reach our specific operation of interest, which could mean waiting tens or hundreds of microseconds. For this reason, the architecture has both a fine and a coarse adjustment method for the pulse delay and pulse width. ‘An easy solution would have been to use a variable capacitor for the fine adjust, but this would add significantly to the cost. And for me (and I assume most people) they are less. igh ee occ dagram of puse with and fet ung the tao dey Hacks, The fst block wriggts the seen allowing the creation af 2 pulse with acuta with ant oft aa FacuRe3 The monatatle —mutivtraor (SNAAPCLD) use hare has ing eeane foling-edge triggered inputs, and by charg them together wean create a puis with beth coarse and Fetes: The are ce rage 1 Ae Sle +} ie AE Le) | mn } Sed fee] len a [Xenon neccn a likely to have a variable capacitor around of the correct value. Instead, we use one _monostable rmultivibrator to trigger the second. The first delay is used for the fine adjust, and after the fine adjust delay is over it triggers the long adjust delay. We combine the two ‘outputs to form a single large pulse. Because the SN74AHC123A contains two monostable mmultivibrators, we can implement the two delays using one chip. The schematic diagram for a single delay block (with both fine and coast adjust) is shown in Figure 3. Note a limitation of this design is the trigger input must be held high long enough for the second rmultivibrator to trigger—very narrow triggers won't work. In our use case that won't be a problem, but a later iteration of this design features. an additional single-shot pulse stretcher on the input. Our design has a total of two SN74AHC123A chips. The first implements the “offset delay” (Pulse Generator #1 from Figure 2), and the second implements the "pulse width" (Pulse Generator #2 from Figure 2). Both the offset and width have coarse and fine adjusts. To provide further flexibility, the coarse adjust uses a switch to select between several “ranges” on the coarse adjust. On the lowest range the coarse adjust is bypassed fully, allowing you to generate a pulse down to about 100ns width, ‘ABOUT THE AUTHOR Colin O'Flynn ([email protected]) has been building and breaking electronic devices for many years. He is an assistant professor at Dalhousie University, and also CTO of NewAE Technology both based in Halifax, NS, Canada. Some of his work is posted on his website at www.colinoflynn, com, ‘SWITCHING VOLTAGES We now have the question of the output driver. We could simply implement the MOSFET crowbar I used in the ChipWhisperer- Lite, as discussed in my September 2018 article. This would actually be the easiest solution. But while we are building a discrete version, why not extend this a litle further? The final version offers the MOSFET output still, but also has a selectable output driver that allows more complex waveforms. Here we use the MAX4619 multiplexor, which was demonstrated by Chris Gerlinsky in his seminal presentation "Breaking Code Read Protection on the NXP LPC-family MCUs" [4] ‘on which this entire project is based. This simply switches the output between two voltage levels. I've chosen to use two linear regulators to select those voltages. While you might use the classic LM317, it has a relatively high drop-out voltage and can only go down to 1.2V. Instead, I'm using the more recent MCP1825, which has a lower drop-out voltage and can go down to 0.4V (it's only specified to 0.8V, but in practice it goes lower). Watch the input voltage with the MCP1825. It’s rated only to a 6V input. For this reason, we use only three AA batteries as a power source which, when brand new, should generate about 1.6V each, for an input of 4.8V, If you use four AA batteries when they are new, it could blow up the MCP1825. PUTTING IT TOGETHER ‘Some final touches on the circuit include an option to choose rising or falling edge trigger modes, a push-button manual trigger, and an LED that indicates when a glitch was inserted. ‘The LED has a simple pulse-stretcher in front of it that makes it easier to visibly see the very narrow glitches. I won't include the full schematic here, but instead will direct you to the project website [3]. ‘We need a few mare things for this to work. We need our target board with a LPCLi14microcontroller (MCU), we need a way to program the MCU and we need to understand a little more about the MCU itself. Let's start with the development board preparation required. The development board we will use is made by Olimex, and is the LPC-P1L14 development board for the LPCL114 MCU. You could use any development board (or even the raw chip), because we don't need any features beyond being able to access the serial port pins and an ability to force the bootloader to Forcing the bootloader to run means setting pin PIO0_1 and PIO0_3 to 0. The former is done with the BLOE jumper, the latter will require you to add an extra jumper wire. The other modifications are to remove capacitor C4 and Cl, open up the two jumpers 3.3V.CORE, add a jumper to route the two core voltage pins together and out to a header and to route the reset pin to 2 or 3 header pins. The reset pin is routed to multiple header pins as we'll use it both as a driven signal (from the computer), and we'll also trigger the Chiplabber-Unplugged. The end result is shown in Figure 4. Compared to the modifications from September 2018, there is one difference: before we added a shunt resistor since we're only shorting the 3.3V.CORE to ground, now we are actively driving 3.3V_CORE. So, we simply cut open the jumper, and don’t add a resistor as before. You'll also need a serial adapter here to talk to the 3.3V logic levels of the LPC1L14 rrouRes rrouresry device. Few people have access to a real RS~ 232 serial port on their computer anymore, 0 T'll avoid trying to recommend using a MAX232 as would be standard for the articles of Circuit Cellar past. But, in keeping with the theme of using through-hole electronics, I'll recommend the Microchip MCP2221A. This import time import serial from PyMCP2221A import PyMCP2221A gpio = PyMCP2221A. PyMCP2221A() gpio.@PI0_Init() gpio.GP10_2_QutputMode() with serial.Serial('CONS7", 38400. timeout=1) as ser while(True) gpi0.GP10_2_utput(a) gpio.GP10_2_utput(1) time. sleep(0.05) ser. flush() ser.write(b"?") line = ser.readline() print (line) if line != b'Synchronized\r\n': continue #Error on Sync - skip this run ser.write(b’Synchronized\r\n") print(ser.readline(}) ser.write(b’12000\r\n") print(ser.readline(}) ‘#Sync’d up - Issue read, see If we got different response ser.write(b'R 0 4\r\n"} resp = str(ser.read(10), ‘UTF-8").1strip() if resp.startswith('R 0 4\rl9") is False: print(resp) print(*Possibly OK - run dump script now") raise ValueError("Done?") ume This simple seriot tages the an esto read fash that should return the staus cade “1S raat te deve socked. Any alert satus coe nacaes he dee may now be nlc ‘Additional materials from the author are available at: ‘www.circuitcellar.com/article-materials References [1] through [7] as marked in the article can be found there. ‘RESOURCES: Maxim Integrated | www.maximintegrated com Microchip Technology | sww.microchip.com NXP Semiconductors | vwa.nxp.com Olimex | wwolimex.com Texas Instruments | wwerti.com |é-pin DIP package IC provides @ USB to UART conversion, with the bonus of a few extra GPIO pins. We'll use these GPIO pins to toggle the device reset line. ‘SETTING UP THE ATTACK In order to bypass the fuse bytes, we need to first configure them, If this was a “real-life” attack of course the device would already be locked. But first we need to actually program four test device to set it up like in real life, Luckily, we can do this through the provided on- device bootloader. We simply need to program a hexfile which has the value 0x12345678 at Ox2FC to trigger the code read protection. A suitable file is present on the project website (Chipabber-Unplugged.com (3). Our setup is then as shown in Figure 5. Here the ChipJabber-Unplugged is set to have a “normal” core voltage of 2.00V. This is routed to the LPC1114 core voltage. The VCC ‘and GND are routed to the USB serial dongle (here implemented with the MCP2221A as mentioned). Finally, the nRST pin for the LPCL114 is routed to both the MCP2221A GPI02 pin, and also to the trigger input to the Chiplabber-Unplugged. This allows us to toggle the reset pin of the LPC1114. On the rising edge of the reset, well adjust the delay of the fault to try and find where the actual loading or check of the read protection value happens. To test our fault, we can implement some very minimal parts ofthe bootloader program. Ive shown you in Listing 1 the basic Python 3 code. This uses an open-source PyMCP2221A library to toggle the GPIO2 pin, and then a standard serial driver (PySerial) to talk to the LPC1114. The most important command is the "R 0 4\r\n"— this is asking to read 4 bytes from address 0 (flash). The device will respond with code "19" if the device is locked. If the device response with any other code, it might indicate a successful glitch. ‘A more complete version of this code uses a library that Is capable of doing the complete code read. That code is available in the ChipWhisperer tutorial [2], so I haven't recreated it here. The important part is just detecting if we have gotten an odd read value. TUNING THE GLITCH SETTINGS The most critical aspect is to tune the glitch settings. Too powerful a glitch means we'll be resetting the device—not a useful cffect. To do this, I use the same trick I talked about before, which is to perform power analysis at the same time. Instead of using ‘my ChipWhisperer hardware as normal, I've attached an oscilloscope to the power pin. Setting the oscilloscope to AC-coupled and with a small input scale lets me see the power of the device during boot.‘To start with, I set turned the *Normal” voltage that is driving 3.3V.CORE down until near where the device stopped running ‘normally (stopped responding to the bootloader commands). I found around 2,00V worked OK here. I then turned the “glitch” voltage to ‘minimum to start (which is about 0.41V).. ‘The next step is to tune the glitch width. To do this I triggered my oscilloscope off the rising edge of the reset pin (same trigger used by ChipJabber-Unplugged). I then monitored two outputs. The first was the output of the Chiplabber-Unplugged, measured using a DC-coupled measurement. This measurement lets me see the size of the pulse inserted. The second measurement is the same output but ‘measured nearer to the device, and measured using an AC-coupled input that won't be able to capture the full glitch waveform, because I'm zooming in on a small (SOm¥) scale. This second measurement is trying to observe the boot sequence of the device. Starting with the narrowest glitch setting, I observed the device during boot. As you widen the glitch out, you will see different effects. You can see in Figure 6 an example where the glitch width has been increased too far, and the device has “flat-lined.” You are actually seeing me trip some sort of reset circuitry here and the device will reboot. If I reduce the glitch width slightly, the oscilloscope trace now looks like Figure 7. Here the device has booted without interruption. Sweeping the location of this glitch around eventually finds a successful glitch. In my case, I ended up inserting a glitch at 52.2us from the rising edge of reset, a glitch width of 142ns, a normal operating voltage of 2.00V, and a glitch voltage of 0.41V. The actual successful glitch will require some experimentation on your part. Because T haven't gone into as much detail about the search strategy, there are a number of references and resources provided for you, available on Circuit Cellar's article materials webpage. I've already mentioned a few of these earlier, such as my September 2018 article [1], Chris Gerlinsky’s original presentation [4] and the ChipWhisperer tutorial [2]. Beyond that, you can see 2 series of blog posts by Dmitry Nedospasov fn Toothless.co [5], which later evolved into a ‘more complete presentation by Thomas Roth, Josh Datko, and Dmitry Nedospasov called Chip.Fail (6). Finally, another glitch circuit I'l direct you to is Samy Kamkar’s GlitchSink [7]. Itimplements another variation of the voltage glitch hardware. Of course, you can also use your trusty ChipWhisperer hardware with the more advanced Chiplabber (not “unplugged” edition) if you want complete control BUILDING YOUR OWN Now that you've seen all the fun you can have, you must want to build your ov, right? While you might have noticed there is'no full schematic and PCB artwork in these pages. T'll direct you instead to the project website at ChipJabber-Unplugged.com [3]. Here you can find the full schematic “and. Gerber fies, including ones T used in these photos, which are optimized for homemade PCBs. If you're interested in a ready-made parts kit or PCBs, you can find more information on that website as wel. Hopefully youl enjoy this chance to prove that even “old tech" can still create many of the attacks that people have only recently started paying attention to. (© FLCURE 6 The tip ine shone the wage eu ore vkage, where you can sx the device wt ve ip (leh The mide ine shoves cee up ete device ns" due tothe lth causing a Wks FIGURE? Compared to Figure 6, you as sen bythe power trace, 7s that, after the glitch visible the top ne, the device continues execution 6After Jeff replaced his home heating oil eae eae me ec Ba PER ue etn arm acs reer ee ania new project. In this article, Jeff describes Tecate an Teeny measure how much oil was left in his es Steen Ut or ee sees Pre enen states by Jeff Bachiochi rne of my chores as a lad was filling the kerosene heaters in our house. We could get kerosene delivered to our '55-gallon drums in the basement, but I'd have to lug the heater tanks down to the cellar to refill them. I never paid any mind to running ‘ut, since there always seemed to be kerosene available. We had two drums, so I guess my dad just bought more whenever we swapped an empty tank for a full one. Not many households that I know of use kerosene any more. The other options— electricity, oil and natural gas/propane—now all share in the total energy needs of our ration. While coal has also been widely used (my family's second home had a coal bin and ash pit), we are beginning to phase out those fuels that are the most environmentally unfriendly, Nuclear energy became a big player while I was child, I can remember talk of every family having their own mini nuclear plant in their home. That was also at a time of potential of nuclear war. While we are still at risk of this from some fanatical group, most countries understand this to be a no- win situation, Ae sae Today, green energy, such as solar, wind and hydro, have given us a new view of our potential future. Getting there is not an easy road, and many, including myself, are stil dependent on oil and other fossil fuels. While my furnace might be highly efficient, it stil requires its oll reserves to be constantly replenished. There was a time when every oil tank had a fuel gauge on it. It was up to you to monitor the tank and call for an oll delivery whenever it got low. Today, many delivery companies use the "degree day" to calculate when you will need a delivery, and automatically plan for it—provided that your account is up to date. DEGREE DAYS Degree days are measures of how cold or warm a location is, referenced to a standard temperature—usually 65°F (Figure 1). The more extreme the outside temperature, the higher the number of degree days. Degree days are separated by days when the average daily temperature is above and below norm. Cooling Degree Days are required when temperatures are warmer than 65° (CDD65) and Heating Degree Days when temperatureseating Degree Days and Cooling Degre Oays (Base 65°F) ‘avenge Aout MOOS. 4817 ii tdi are less than 65° (HDD65). Individual degree days tell us how much warmer or colder the day has been from a normal of 65°. During those times of the year when the temperature drops below normal, HDD65 indicates how much energy in the form of heating is required to bring our indoor temperature up to the norm. During those times of the year when the temperature rises above normal, CDD65 indicates how much energy is required in the form of cooling to bring our indoor temperature down to the norm, This is all an attempt to keep our living environment at a particular comfortable level. We can calculate the energy we will need to do this based on our living space's size, insulation factors and fuel type. However, you can easily determine this by monitoring your fuel consumption for a period of time (while maintaining said norm of 659), and dividing the energy used by the total degree days for that period, Let's say, for example, the last 30 days the outside temperature was freezing 32°F. That's 65° ~ 32° = 43° x 30 days or 41290HDDGS. If you used 100 gallons of fuel ail for that period, 100 gallons/1290KDD65 0.08 gallons/HDD65 (each degree day). Now by keeping track ofthe accumulated (Heating) 26.875 1343" il tank 1 round tank = area circle x length 3.14 x (19.43" x 18.43") x 60" = 93,980.75 cu" '33,980:75 cu'/231 cu/gal = 147 gallons Total capacity 147 gallons + 124 gallons = 271 gallons 1 rectangular tank = area rectangle x length 27875 x 17125" x 60" = 28,546.58 cu" 28,646.58 cu'/231 cu/gal = 124 gallons acuRe oaing Degree Days (COOKS) Is a runneg total of the terpeatue Giference when the average of the ay sone SEF, Heating Deore Days (HD055) is a runing toa ef the temperature diference when the erage of the day Ie tow &5°F These numbers Indste how mh enargy i requed to keep an area at a combrtatle temperature (5) threugh heating or colng. acure2 used the tark specs ta figure ut ts slum, The tank's ship is ide io tree sgments—o nal barrels and a rectangular segment, Keeping the segments simple makes. for Simple cautions. ou,b chiles cu 0753 monkey mate plore fect forthe It mightbe oft glue. The cs Degree Days, you could predict your oil usage ‘and know when it was time to fill your tank Thad my oll tank replaced a few years ‘ago. It was previously buried in the ground. I brad just added on to my basement area and, with the extra space, I had a standing tank put inside. I dida’t think of it at the time and bythe sce rend ofthe tank |r any inerfrenee. [oun col, in tf card PC), nd because wes sft and sem-exte,[ rel lg as 2 05 threaded hoe nits center and was sy didn't ask to have @ mechanical gauge put into the tank. While I regret that now, it did sive me reason for this project. TANK OIL LEVEL Since one of my super powers isn't x-ray vision, T needed a way to see inside this oll tank. While the UL label is on the side of my oll tank, inconveniently located against a wall, it still had a paper label with the product #204201 written on it. A quick search of that number led me to Granby Industries, a maker of steel and fiberglass storage tanks. According to its online PDF of that tank, it was spec’d out at 275 gallons. Using the dimensions given, I wanted to verify the tank's volume. A quick calculation is shown in Figure 2. My calculations are based fon using regular shapes. I thought I might be a bit on the high side using the exterior dimensions on the print. However, it looks as though my calculations are about 2% under. Close enough: For measurement purposes, I'll be using ultrasonic acoustic measurement. While most ultrasonics I've used have been transmitter/ receiver pairs, T located a circuit that uses a single-sealed transceiver for $11. This is similar to the devices found on today's car bumpers used for presence alarms. Since I didn’t have a spare oil tank hanging around, needed to verify how it operates within the dimensions of the tank. I needed to mock up an actual-sized tank using some cardboard— lots of cardboard. After rounding up a number of large corrugated cardboard cartons, I proceeded to mock-up a full-sized tank according to the specs I had downloaded. With one bunghole free on the left end of the tank, I needed to know if the ultrasonics would reach the bottom of the tank without interference from the sides or the end of the tank As you can see from the photo in Figure 3, the tank model has a fairly open top desian, ssuch that I could reach into the interior easily. ‘A couple of wooden rails at the top hold up the movable band that will hold the sensor. Being able to slide this band along the length of the tank allowed me to position the sensor for testing. I was able to receive echoes from the 44" bottom of the tank with the sensor set at the first bung hole position. I also placed a 1’ cardboard surface at various heights under the sensor, and was able to get some accurate distance measurements. The time and effort to test the instrumentation was important to prove the viability of the idea. ACOUSTIC TIME OF FLIGHT The ability of the ultrasonic system to measure distance has to do with measuring the time of flight for an acoustic signal. Upon‘asuea These ae the smartghene peripherals heel) that are superted by Shed onthe nod app ‘Accelerometer Buzzer Camera Clock Color Detector Data Logger Email Face Detection | Facebook Foursquare Gamepad LCD cy Gravity Gyroscope Internet Keyboard Keypad cD LED Light: Magnetometer Mic ‘Music Player NFC Notification Orientation Pattern Phone Pressure Proximity Push Button | Seven Segment | _ Skype Slider ‘Temperatures Terminal ‘Text to Speech | Toggle Button Twitter Vibration Voice Recognizer request, the system sends out a 40kHz burst {an ultrasonic transmitter, and if an object is within the path, an echo bounces back to the ultrasonic receiver. Ultrasonic systems may use a single transceiver or separate transmitter receivers to measure this. When a transmitter has been pulsed, there is a tendency for the transmitting element to continue ringing for a short period of time. ‘Therefore, in a single-transceiver system, the transmitting device must be given a bit of time to stop all vibrations, since these may be seen asa reflection. ‘A single-transceiver system will therefore have some minimum time (distance) before its transceiver is enabled for receiving echoes. The system I am using has a minimum distance measurement due to this delay. If a separate transmitter and receiver are used, the receiver will never be excited during the transmission period, and therefore the receiver is ready immediately to listen for echoes. These systems have a minimal delay. Til be putting up with this inherent disadvantage, because the physical mounting limitations in'a single bunghole require using a single-transceiver system. As mentioned previously, the sensor is similar to those found in car bumpers. It comes sealed into plastic mounting hardware that pops into a hole. This allows it to easily mount into a bunghole cap that has a hole of the proper size in it (Figure 4). ‘The ultrasonic circuitry has four connections: power, ground, INIT and ECHO. If you bring the INIT line high for greater than 10ps, then the circuitry will send out a burst of 40kHz. The ECHO pin goes high and remains high until the echo pulse has been received. If you measure the width of the pulse, you can calculate the distance to the object (time of fight) Physics tells us that sound passes through air at a speed of approximately 767mph or 13,500in,/s. This means that it travels about 0.34mm/is. Sincea burst musttravel twice the distance to an object (out and back), distance to an object is half that (d=0.34mm/2us.) If we can measure this in microseconds, we can estimate distance to within a millimeter. 1SHEELD FOR ANDROID AND iOS As usual, I try to incorporate several different elements into each project. I'm nt sure where I first saw ASheeld, a shield board for the Arduino, since it's been around for about 5 years. It sounded like a different approach and I like unique products, so I bought one for under $30. The 1Sheeld is a peripheral board that mounts atop any Arduino processor board. It contains a Bluetooth module (HM-10-BTE4.0) and 9 Microchip Technology ATMEGAL62 8-bit microcontroller (MCU), The processor is preprogrammed with its own operating system, if you wil, that can link up with @ smartphone and gives the user access via UART. When plugged onto an Arduino, it ties its UART to the Arduino's UART. This hardware connection must be disconnected via an on- board switch, when you need to program a sketch into the Arduino, Once the sketch has been programmed, you fip the switch and your sketch talks to the 1Sheeld via the UART connection. Alternately (when the switch isolates the 1Sheeld's TX/RX pins from the Arduino header), you can jumper these to alternate serial pins on the Arduino header (05-D13). Your sketch can then talk to 1Sheeld via an alternate software serial port and avoid the hardware contention described above. 1 used the hardware port connection for this project. OneSheeld.begin(); OneSheeld. i sAppConnected() OneSheeld.wai tForAppCannection(); OneSheeld.delay(unsigned long); OneSheeld. isCal backs Interruptsset(); OneSheeld.enableCal lbacksInterrupts(). OneSheeld.disableCal1backs Interrupts); OneSheeld. setOnSelected(void (*userFunctian)(votd); usmiG 1 Shel suppor o” 7* defines for Sheeld. to limit space used by 1Sheeld*/ fidefine CUSTOM_SETTINGS fidefine INCLUDE_TERMINAL_SHIELD fidefine INCLUDE_TEXT_TO_SPEECH_SHIELD 7* Include 1Sheeld library. */ include 7* Define pins for the ultrasonic sensor */ const int trigPin = 9 const int echoPin = 10; 7* User constants */ const int TankCapacity = 275; JJ capacity of the tank in gallons const int EmptyDistance = 1118; // (nn) 44 inches inside height of the tank const int FullDistance = 180; // (am) 7 inches minimum distance reported const float NNPerGallon = (EmptyDistance-Ful1Distance)*1.00/TankCapacity J* Variables used to save the results */ int distance; /J (am) reported distance to oi1 surface int GallonsRemaining; // 011 reserves based on reported distance ustine 2 Here we indude the raresresued the utrasoricsansor cnntons we wil mae, soe predefined constants and a ciple of variables. void setup() ( pinMode(trigPin, OUTPUT); // Sets the trigPin as en Output pinModecechoPin, INPUT: 1/ Sets the echoPin as an Input /* Start 1Sheeld communication. */ GneSheeld.begin(); ’ Ww void 1o0p() ( /* Get the current distance from the ultrasonic */ distance = getUitrasonicDistance(); if(di stance>EmptyDistance! i distance=EmptyDi stance; ) if(distance Now you are open to using any of the support routines, including those in Listing 2. By default, the compiler will attempt to add support for every 1Sheeld peripheral to your sketch. While the support libraries for each peripheral are already in the 1sheeld's prepragrammed processor, some supporting functions will be compiled into your sketch for /* & function that operates the ultrasonic and returns a reflected distance in mm */ int getUl trasonicDi stance void) i every peripheral used. It only makes sense for you to limit these by specifically including only those that you are using. T'm going to use two of these peripherals for this project. First, the Terminal peripheral will display the actual distance measurements of the ultrasonic sensor. I use this as a debug tool to verify measurements. Second, the Text-to- Speech peripheral is the end product of this project: an audio message of cil reserves! MEASURING WITH ULTRASONICS ‘As mentioned earlier, most Arduino sketches begin with some basic definitions. {As shown in Listing 2, we include the libraries required, the ultrasonic sensor connections we will make, some predefined constants and a couple of variables. From the TankCapacity, EnptyDistance (inside height of the il tank) and the FullDistance (minimum distance that the sensor can measure), the NlPerGal ion can be calculated. This is the number that will et us calculate the rema oil reserves. This works out to: (L118 - 180) 275 3.4109mnvgallon Note that this is forced to be a floating- point number by including a floating-point term (1.00) in the equation. With the basic requirements satisfied, we can add the two required functions for /* Variable to save the sound wave travel time in microseconds */ nt duration; /* Variable to save the detected distance in cm */ int distanceReturned; /* Clocks the trigPin */ digitalWrite(trigPin, LOW): (* delay 2 micro seconds */ delayMi croseconds(2); 11 should already be low /* Sets the trigPin on HIGH state for 10 micro seconds */ digitalWrite(trigPin, HIGH); /* delay 10 micro seconds */ delayMicraseconds(10); /* Sets the trigPin on LOW state */ digitalWrite(trigPin, LOW): /* Reads the echoPin, returns the sound wave travel time in microseconds */ duration = pulseln(echoPin, HIGH); /* Calculating the distance */ distanceReturned = duration * 0.34 / 2; /* Returning return distanceReturned; ustiNe + he detected distance in mn */ This faction operates the utrasonic ane retusa refed dsance in iliesfan Arduino sketch (Listing 3). The setup function will initialize the necessary 1/0 (for the sensor) and the 1Sheeld support functions. The 100p() function handles all the processing that will be repeated in a forever loop. This is basically a call to the ultrasonic FIGURES an) ‘ABOUT THE AUTHOR Jeff Bachiachi (pronaunced BAH-key-AH-key) has been writing for Circuit Cellar since 1988. His background includes product design and manufacturing. You can reach him at: [email protected] or at: www.imaginethatnow.cam, Additional materials from the author are available at www.circultcellar.com/article-materials References [1] and [2] as marked in the article can be found there. RESOURCES 1Sheeld | www. tsheeld.com Microchip Technology | ww. function to get a distance measurement, calculate the gallons of oil in reserve, send the debug data to the Terminal peripheral and create a text string to send to the Text-to- Speech peripheral. Finally, let's look at the last function— retrieving a distance from the ultrasonic sensor (Listing 4). The INIT pin is raised to a logic 1, we wait a delay of 10ys and then lower the INIT pin to logic 0. This gets the sensor transmitting a short burst of 40kHz pulses. The ECHO pin creates high pulse with 2 duration corresponding to the time of flight for the echoed transmission burst. This high period, t(us), can be measured with the pulseIn() command. The distance d(mm) is then calculated using the formula: 7 (34) You may have noticed a few minor issues with the calculations here. My initial tank volume calculations took into account tank shape, whereas my calculations for oil reserves are based on a square tank—with linear volume/distance calculations. This could be made more accurate by determining the volume of oil reserves based on the distance when it falls into the upper and lower barrel- shaped regions. In reality, the decrease in cil level is nonlinear in both the upper and lower half-cylinder areas, so they should be calculated separately, For instructional purposes, I left this calculation simple. ASHEELD APP So, what is the 1Sheeld phone app? The ‘apps supplied by 1Sheeld for either Android and 0S allow the 1Sheeld hardware access to the peripherals on a smartphone. For this project and all those sketches that use ASheeld, your connection to the project hardware is through a Bluetooth link made between 1Sheeld hardware and the phone app. When you open the 1Sheeld application, you are prompted to scan for Bluetooth transmitters in the area. Mine shows up as 1Sheeld#99, The application lists all the peripherals available in the library (see Table 1 again). To the right of each is a selection button, which will enable the function if it is supported by your phone. My Motorola G5+ does not support three of the peripherals in Table 1: Temperature, NFC and Pressure. Once you've selected those peripherals used in your sketch, you can tap on the triple 1Sheeld ‘outline icon to go to a list of those selected peripherals. Tap on Terminal to bring up the Terminal peripheral. Figure 5 shows this screen displaying distance measurements,You have the option of time-stamping the data as it is being received. The distance measurements seem to be correct, so let's turn off the Terminal peripheral and enable the Text-to-Speech peripheral. Immediately, you should begin to hear a message informing you of the tank's status similar to: "Your 275-gallon oil tank has 72 gallons remaining.” This message is repeated every 5 seconds. You can change the delay in the sketch, or you could enable the Push Button peripheral in the phone and then test for this in the sketch. This would create a button you could press to get an audio ‘message on request. If your mind is anything like mine, it is beginning to run amok with other ways of using the 1Sheeld. CLOSING THOUGHTS It is convenient to use the ultrasonic sensor to measure something that is normally hidden from view. The sealed nature of this sensor makes it great for use in dirty environmental conditions. There is also a hazard of using electrical equipment, which can produce a spark, around flammable liquids. This sensor covers these bases quite nicely. I already have another home project { want to use this sensor on. It seems to work very well. I also want to try out the other modes available on this sensor, The ultrasonic module, along with the Arduino, 1Sheeld and a small prototyping board to make the four connections necessary for the ultrasonic module, ft fairly well into a 3ple Decker Case for Arduino with only minor modifications (Figure 6). The 1Sheeld is an interesting piggyback board for the Arduino. You can wire this up to other MCUs as well, using just power, ground, TX and RX. All that's necessary ‘is to look at github.com/ Integreight/1Sheelé-Firmuare website [1] to see how you make use of the preprogrammed library. You can find some examples on www.isheeld.com [2]. The phone application can also do an OTA (over the air) update of the preprogrammed library. There haven't been any updates since April 10, 2016 (V1.6) and ‘many links on the site—such as the Forum— seem to be broken. This isa bit disconcerting, ‘The app is meant to give the user a Playground in which to investigate use of the ‘1Sheeld board. It has some drawbacks—mainly you get single use of the peripherals. This ‘means you can't add multiple buttons, LEDs or seven-segment display characters. IF you wish to use more than one in an application, you must design your own using the available Android SDK. I'm not sure T want to develop my ‘own app for every litle project I make. But, for some things, you'll find this app is all you need. As always, too much to do, so litle time, icuREs From Microcontroller Theory to Design Projects If you've ever wanted to design and program with the ADUCE41 microcontroller, ‘or other microcontrollers in the 8051 family, this isthe book for you. With introductory and advanced labs, you'l soon master the many ways to use a microcontroller Perfect for academics! Buy it today! CSRPRODUCT NEWS PRODUCT NEWS ToT eSIM has Pre-Integrated Cell Coverage Infineon Technologies has launched a comprehensive turnkey eSIM solution for the plethora of IoT devices and applications. Cellular networks will be the communication backbone for billions of mobile devices and machines connected to the Internet of Things (IoT). At the core of this development is the embedded Subscriber Identity Module (eSIM), which securely connects devices to networks. Infineon’s new OPTIGA Connect eSIM IoT solution based on leading-edge security hardware comes with pre-integrated carrier-agnostic cellular coverage in ‘more than 200 countries and territories. Infineon has partnered with Tata Communications to offer its customers unparalleled global reach, leveraging the Tata Communications MOVE mobility and IoT platform. Infineon’s solution is pre-integrated with a bootstrap Tata Communications MOVE eSIM profile, At the core of the new eSIM solution is Infineon’s SLM97 security controller. Tt provides a high- performance and GSMA eSIM M2M V3.2 compliant operating system, as well as worldwide coverage of 26, 3G, 4G, 5G, LTE-M and NB-IoT. The new OPTIGA Connect eSIM IoT is available in a VOFN-8 (MFF2) package. Infineon Technologies | www.infineon.com Surface Mount DC-DC Converter is Ultra-Thin CUthas today announced the addition ofits first four contact, ‘surface mount, non-isolated converter to its DC-DC converter line, The ultra-thin VxO78-500-M features a SOOmA output current, no-load input current as low as 0.2mA and a wide -40 to +85°C temperature range, This regulated DC-DC converter offers a wide 4.75 to 36VDC input voltage range, short-circuit protection and 4-SMD reflow solderability in an ultra ‘compact SMT package with half- vias corners. Unlike linear regulators, this ultra-compact, surface mount BeagleBone Green SBC Offers LAN and Wi: Seeed has launched a new model in its line of BeagleBone compatibles that balances the feature sets of the $44 Seeed Studio BeagleBone Green and the $52.90 Seed Studio DC- DC converter offers a remote on/off pin and extreme efficiency (up to 95%). CUI says that makes the VXO78-500-M ‘an ideal solution for applications where board space is at a premium y and maximizing energy efficiency is a concern. General applications for the VXO78-500-M include ITE (commercial), controls and electronics that require a wide input at a low cost. The VXO78-500-M is available immediately with prices starting at $2.52 per unit at 100 Pieces through distribution. CUT | www.cui.com Fi BeagleBone Green Wireless. The $59.90 Seced Studio BeagleBone Green Gateway provides the 10/100 Ethernet port of the BB Green along with the BB Green Wireless’ TI Wilink® module with 2.4GHz 802.L1b/g/n and Bluetooth 4.1 LE. The open spec board is equipped with 2x USB 2.0 ports instead of fone port on the BB Green and 4x ports on the Wireless. ‘The BeagleBone Green Gateway was developed with the blessing of the Beagleboard.org community, which supports its flagship, $62 BeagleBone Black SBC and other compatibles. The SBC runs Debian, Ubuntu, or Android on the same 1GH2, Cortex-AB TI Sitara AM3358 SoC found on the BB Black, Green, and Green Wireless, and other BeagleBone compatibles, listed in our catalog of 136 Linux hacker boards. Loaded with industrial interfaces, the AM3358 offers dual programmable PRU real-time cores. The Seeed Studio BeagleBone Green Gateway is available for $59.90. Seeed Studio | www.seeedstudio.comPRODUCT NEWS STM32Cube MCU Software is Free on GitHub ‘STMicroelectronicsisnow publishingSTM32Cubeembedded taking advantage of GitHub’s change-handling structures. software on GitHub, the popular cloud-based service. This All current STM32Cube MCU packages are already ‘opens the STM32 software up to collaborative and community- online, as well as Hardware Abstraction Layer (HAL) code friendly development and leverages and MCU-independent —_CMSIS faster, more efficient distribution drivers. The remaining STM32Cube of updates, says ST. Publishing all embedded-software components STM32Cube original code through will be added over the coming GitHub lets users of more than 1,000, months. All STM32Cube embedded STM32.Arm Cortex-M microcontroller sT32 software on GitHub is available free variants and heterogeneous Cortex a of charge at _https://github.com/ M/-A microprocessors easily store, ers ‘STMicroelectronics. manage, track, and control their code. GitHub features such as Pull requests promote co-development, enabling the community to propose alternate solutions and new features STMicroelectronics www.st.com Power Modules Target Industrial Motor Drives ON Semiconductor has expanded its portfolio for industrial motor drive applications. ON Semiconductor announced the _NXH25C12012C2, NXH35C120L2C2/2C2E, and NXHS0CI20L2C2E, which are 25, 35 and 50 Ampere versions of Transfer-Molded Power Integrated Modules (TM-PIM) for 1200 Volt (V) applications. They are available in Converter-laverter-Brake (CIB) and Converter- Inverter (CI) configurations. The modules consist of six 1200V IGBTs, six 1600V rectifiers, and an NTC thermistor for system level temperature monitoring; the CIB versions use an additional 1200 V IGBT coupled with a diode. The new modules feature transfer- molded encapsulation, extending the cycling lifetime for both temperature and power. The modules measure just 73mm x 40mm x 8mm, have solderable pins and have a standardized pin-out for CIB and CI versions. ‘The company also announced the NFAM2012L.5B and NFALSO65L48, expanding its Intelligent Power Module (IPM) portfolio, which includes voltage ratings of 650V and 1200V, and current ratings from 10 to 75A. These 3-phase inverters—with integrated short circuit rated Trench IGBTs, fast recovery diode, gate driver, bootstrap circuits, optional NTC thermistor and protection—provide compact, reliable modules with UL 1557 certification via an isolation rating of 2500Vays/minute: ON Semiconductor | www.onsemi.com MCU Combines Cortex-M4 with Bluetooth 5.0 Renesas Electronics has introduced its first RA MCU with an integrated Bluetooth 5.0 Low Energy radio. The single-chip RAAW1 MCU includes a 48 MHz, 32-bit Arm Cortex-M4 core and Bluetooth 5.0 core delivered in a 56-pin QFN package. The single-chip RA4W1 MCU features field upgradeable 512KB flash memory, 96 KB SRAM and connectivity such as USB, CAN and Renesas’ HMI capacitive touch technology. It also includes Renesas’ Secure Crypto Engine supporting customers with symmetric encryption and decryption, hash functions, true random number generation (TRNG), and advanced key handling with key generation and MCU-unique key wrapping. The RAGW1 MCU includes full Bluetooth 5.0 functions such as 2Mbps data throughput, all advertising extension functions with maximum advertising length (1650 Byte), periodic advertisements and channel selection algorithm #2 for applications requiring large amounts of traffic. The RAW also offers superior low peak power consumption at 3.3mA during receiving and 4.5mA (at 0dBm) while transmitting. The RRAAWL is available now from Renesas Electronics’ worldwide distributors and is priced at $3.98 (10,0005) Renesas Electronics | www.renesas.comPRODUCT NEWS COMe Type 10 Board Boasts Extended Temps IBASE has announced its ET876 COM Express Type 10 CPU Module (R3.0) supporting Intel's energy-efficient Atom Processor £3900 series, Intel Celeron processor N3350 and Intel Pentium processor N4200. The highly integrated ET876 comes in a compact form factor (84mm x SSmm) and matches the performance requirements of cost-effective, small footprint embedded systems. It benefits from the Intel Gen9 graphics engine featuring DirectX 12, OpenGL 4.3 and OpenCL 2.0 to deliver stunning graphics and 4K resolution output, as well as simultaneous display combinations of DDI and LVDS or eDP. Connectivity options on the carrier board can include 8x USB 3.0, 2x USB 3.0 and 2x SATA III All models support Gbit connectivity, 4GB DDR3L with ECC standard, TPM hardware security and up to 32GB of eMMC storage. The ET876 operates with an extended temperature range of ~40°C to 85°C for remote outdoor deployments depending on the processor used and runs both Linux and Windows 10 operating systems. iBASE Technology | www.ibase.com.tw 6OOW Power Module is OVC III-Certified TDK has announced the TDK-Lambda PH600A280-24 DC-DC converter. Rated at 24V 600W, this further extends the 280VDC nominal input PH-A series, from SOW to 600W. The PH-A series is utilized in HVDC (High Voltage Direct Current) equipment for data communications, high voltage transmission, renewable energy applications, robot controllers and factory automation. Certification to the safety standard EN 62477-1 (Over Voltage Category I) benefits users requiring compliance to the machinery safety standard IEC 60204-1. The PH600A280 does not require an isolation transformer on the distribution panel, reducing cost, size and weight. The PH600A280-24 accepts a wide range 200VDC to 425VDC input delivering 24V at 12.5A. The output voltage can be set between 14.4V and 28.8V using the trim terminal. With an efficiency of 93%, the module can operate at full load with baseplate temperatures of -40°C to +85°C, derating linearly to 80% load at +100°C. Conduction cooling through the baseplate enables the PH-A to be used in outdoor sealed enclosures or liquid cooled equipment. ‘TDK-Lambda | www.us. mbda.tdk.com AVR MCU Boasts Safety-Ready Features Microchip Technology hasannounced ts next generation AVR DA family of microcontrollers (MCUS), its first Functional Safety Ready AVR MCU family with Peripheral Touch Controller (PTC). Microchip's Functional Safety Ready designation is applied to devices that incorporate the latest safety features and are supported by safety manuals, Fallure Modes, Effects, and Diagnostic Analysis (FMEDA) reports and in some cases, diagnostic software—reducing the time and cost of certifying safety end applications, Micrachip’s new AVR DA family of MCUs enables CPU speeds of 24MHz over the full supply voltage range, memory density of up to 128KB flash, 16KB SRAM and 512 bytes of EEPROM, 12-bit differential ADC, 10-bit DAC, analog comparators and zero cross detectors. The PTC enables capacitive touch interface designs supporting buttons, sliders, wheels, touchpads, smaller touch screens as well as gesture controls used in a wide range of consumer and industrial products and vehicles. ‘The AVR DA family of MCUs is available in volume production in 10,000 quantities starting at $0.87. Microchip Technology | www.microchip.com