54/74 Family

MSI/LSI Circuits

7-1
•

7·2
 MSI/LSI FUNCTIONS
FUNCTIONAL INDEX/SELECTION GUIDE

The following pages contain functional indexes and selection guides designed to simplify the choice of a particular
function to fit a specific application. Essential characteristics of similar or like functions are grouped for comparative
analysis, and the electrical specifications are referenced by page number. The following categories of functions are
covered:
Page

Adders ..................... . 7-4

Accumulators, arithmetic logic units, look·ahead carry generators 7-4
Multipliers . . . . . . 7-4
Comparators . . . . . . 7-4
Parity generators/checkers . 7-5
Other arithmetic operators 7-5
Quad,hex, and octal flip-flops 7-5
Register files .. 7-5
Shift registers . . . . 7-6
Other registers 7-6
Latches . . . . . . 7-7
Clock generator circuits 7-7
Code converters . . . 7-7
Priority encoders/registers 7-8
Data selectors/multiplexers 7-8
Decoders/demuitipiexers ............ . 7-9
Open-collector display decoders/drivers with counters/latches 7-9
Open-collector display decoders/drivers . . . . . . . . . 7-10
Bus transceivers and drivers ............ . 7-11
Asynchronous counters (ripple clock)-negative-ooge triggered 7-11
Synchronous counters-Positive-ooge triggered 7-12
Bipolar bit-slice processor elements 7-12
First-in first-out memories (FI Fa's) . . . . 7-12
Random-access read/write memories (RAM's) 7-13
Read-only memories (ROM's) ..... . 7-13
Programmable-read-only memories (PROM's) 7-14
Microprocessor controllers and support functions 7-14

1076

TEXAS INCORPORATED
INSTRUMENTS 7-3
POST OFFICE sOX 5012 • DALLAS. TEXAS 75222
 MSI/LSI FUNCTIONS
FUNCTIONAL INDEX/SELECTION GUIDE

ADDERS

TYPICAL TYPICAL TYP POWER DEVICE TYPE

PAGE
DESCRIPTION CARRY ADD DISSIPATION AND PACKAGE
NO.
TIME TIME PER BIT -55°C to 125°C O°C to 70°C
SINGLE l·BIT GATED FULL ADDERS 10.5 ns 52 ns 105mW SN5480 J,W SN7480 J, N 7-41
SINGLE 2-BIT FULL ADDERS 14.5 ns 25 ns 87 mW SN5482 J,W SN7482 J, N 7-49
10 ns 15 ns 24mW SN54LS83A J,W SN74LS83A J, N 7-53
10 ns 15 ns 24mW SN54LS283 J,W SN74LS283 J, N 7-415
SINGLE 4-BIT FULL ADDERS 11 ns 7 ns 124mW SN54S283 J SN74S283 J, N 7-415
10 ns 16 ns 76mW SN5483A J,W SN7483A J, N 7-53
10 ns 16 ns 76mW SN54283 J,W SN74283 J, N 7-415
11 ns 11 ns 110mW SN54H183 J,W SN74H183 J, N 7-287
DUAL l-BIT CARRY-SAVE FULL ADDERS
15 ns 15 ns 23mW SN54LS183* J,W SN74LS183 * J, N 7-287

ACCUMULATORS, ARITHMETIC LOGIC UNITS, LOOK-AHEAD CARRY GENERATORS

TYPICAL TYPICAL TYPTOTAL DEVICE TYPE

PAGE
DESCRIPTION CARRY ADD POWER AND PACKAGE
NO.
TIME TIME DISSIPATION -55°C to 125°C O°C to 70°C
4-BIT PARALLEL
10 ns 20 ns 720mW SN54S281 J,W SN74S281 J, N 7-410
BINARY ACCUMULATORS
11 ns 20 ns 525mW SN74S381 N 7-484
4-BIT ARITHMETIC LOGIC UNITSI 7 ns 11 ns 600mW SN54S181 J,W SN74S181 J, N 7-271
FUNCTION GENERATORS 12.5 ns 24 ns 455mW SN54181 J,W SN74181 J, N 7·271
16 ns 24 ns 102mW SN54LS181 J,W SN74LS181 J, N 7-271
7 ns 260mW SN54S182 J,W SN74S182 J, N
LOOK-AHEAD CARRY GENERATORS 7-282
13ns 180mW SN54182 J,W SN74182 J, N

• !
DESCRIPTION

2-BIT-BY-4-B!T PARALLEL BINARY MULTIPLIERS

4-BIT-BY-4-BIT PARALLEL BINARY MULTIPLIERS

MUL TlPLlERS

SN54LS261
DEVICE TYPE AND PACKAGE
_55°C to 125°C

SN54284, SN54285
SN54S274
SN54LS275
J,W
J, W
J
J
SN74LS261
O°C to 70°C

SN74284, SN74285I J, N
SN74S274
SN74LS275
I J, N
J, N

J, N
I
PAGE
NO.
7-380
7-420
7-391
i
I

7-BIT-SLICE WALLACE TREES 7-391

SN54S275 J SN74S275 J, N
25-MHz 6-BIT-BINARY RATE MULTIPLIERS SN5497 J,W SN7497 J, N 7-102
25-MHz DECADE RATE MULTIPLIERS SN54167 J, W SN74167 J, N 7-222

COMPARATORS

TYPICAL TYPTOTAL DEVICE TYPE

PAGE
DESCRIPTION COMPARE POWER AND PACKAGE
NO.
TIME DISSIPATION _55°C to 125°C O°C to 70°C
11.5 ns 365mW SN54S85 J,W SN74S85 J, N
21 ns 275mW SN5485 J,W SN7485 J, N
4-BIT MAGNITUDE COMPARATORS 7-57
23.5 ns 52mW SN54LS85 J,W SN74LS85 J, N
82 ns 20mW SN54L85 J SN74L85 J, N

'New product in development as of October 1976.

1076

7-4 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 MSI/LSI FUNCTIONS
FUNCTIONAL INDEX/SELECTION GUIDE

PARITY GENERATORS/CHECKERS

TYPICAL TYP TOTAL DEVICE TYPE

PAGE
DESCRIPTION DELAY POWER
NO.
TIME DISSIPATION -55°C to 125°C O°C to 70°C

9·BIT ODD/EVEN PARITY GENERATORS/CHECKERS

31 ns 80mW SN54LS280 I J, W SN74LS280 IJ, N
7-406
13 ns 335mW SN54S280 J, W SN74S280 J, N
8-BIT ODD/EVEN PARITY GENERATORS/CHECKERS 35 ns 170mW SN54180 I J,W SN74180 I J, N 7·269
OTHER ARITHMETIC OPERATORS

TYPICAL TYPTOTAL DEVICE TYPE

PAGE
DESCRIPTION DELAY POWER AND PACKAGE
NO.
TIME DISSIPATION
7 ns 250mW SN54S86 J, W SN74S86 J, N 7-65
10 ns 30mW SN54LS86 J, W SN74LS86 J, N 7·65
QUADRUPLE 2·INPUT EXCLUSIVE-OR
10 ns 30mW SN54LS386 J, W SN74LS386 J, N 7-487
GATES WITH TOTEM·POLE OUTPUTS
14 ns i50mW SN5486 J, W SN7486 I j, N I 7·65
55 ns 15mW SN54L86 J, T SN74L86 J, N 7-65
QUADRUPLE 2·INPUT EXCLUSIVE-OR GATES 18 ns 30mW SN54LS136 J, W SN74LS136! J, N ! 7.131

~~:~~~66 ~: ~ !:~~:~~~66 !~: ~ !

WITH OPEN·COLLECTOR OUTPUTS 27 ns 150mW
nUADRupl 1= 2·!NPUT EXCLUS!VE·NOR GATES 18 ns 40mW ' 7·386 !
QUADRUPLE EXCLUSIVE OR/NOR GATES 8 ns 325mW SN54S135 J, W SN74S135 J, N 7·129
4-BIT TRUE/COMPLEMENT, ZERO/ONE ELEMENT 14 ns 270mW SN54H87 J, W SN74H87 J, N 7·70

QUAD, HEX, AND OCTAL FLlP·FLOPS

F·F POWER DATA TIMES DEVICE TYPE

PAGE
DESCRIPTION PER FREQ PER SETUP HOLD AND PACKAGE
NO.
PKG FLlp·FLOP ns ns -55°C to 125°C O°C to 70°C
50 MHz 26mW 20t Ot SN54LS364' J SN74LS364' J, N 7-467
I D TYPE 3·STATE WITH ENABLE 8 50 MHz 17mW 20t Ot I SN54LS374' J SN74LS374' J. N I 7-471 I
I 100 MHz 56mW 51 21 I SN54S374 J SN74S374 J: N I 7-471
I
8 40 MHz 10.6mW 20t 51 ! SN54LS377 J SN74LS377 J, N 7-481
D TYPE WITH ENABLE 6 40 MHz 10.6mW 201 51 SN54LS378 J,W SN74LS378 J, N 7-481
4 40 MHz

I
10.6mW 201 51 SN54LS379 J SN74LS379 J, N 7-481
40 MHz 39mW 201 51 SN54273 J SN74273 J, N,
8 7·388
40 MHz 10.6mW 201 51 SN54LS273 J SN74LS273 J, N
35 MHz 38mW 201 51 SN54174 J,W SN74174 J, N
6 40 MHz 10.6mW 20t 51 SN54LS174 J,W SN74LS174 J, N 7·253
D TYPE WITH CLEAR
110MHz 75mW 51 31 SN54S174 J,W SN74S174 J, N
35 MHz 38mW 201 51 SN54175 J,W SN74175 J, N
4 40 MHz 10.6mW 201 51 SN54LS175 J,W SN74LS175 J, N 7·253
110MHz 75mW 5t 31 SN54S175 J, W SN74S175 J, N
J·K TYPE WITH SEPARATE CLOCK 4 50 MHz 75mW 31 101 SN54276 J SN74276 J, N 7-401
J·K TYPE WITH COMMON CLOCK 4 45 MHz 65mW Ot 20t SN54376 J,W SN74376 J, N 7-479

REGISTER FILES

TYPICAL TYP READ DATA TYPTOTAL DEVICE TYPE

DESCRIPTION ADDRESS PAGE
ENABLE INPUT POWER AND PACKAGE
NO.
TIME TIME RATE DISSIPATION -55°C to 125°C O°C to 70°C
EIGHT WORDS OF TWO BITS 33 ns 15 ns 20 MHz 560mW SN74172 J, N 7·245
27 ns 15 ns 20 MHz 125mW SN54LS170 J,W SN74LS170 J, N
FOUR WORDS OF FOUR BITS 7·237
30 ns 15 ns 20 MHz 635mW SN54170 J,W SN74170 J, N
FOUR WORDS OF FOUR BITS
24 ns 19 ns 20 MHz 135mW SN54LS670 J,W SN74LS670 J, N 7·526
(3-STATE OUTPUTS)

• New product in development as of October 1976.

1076

TEXAS INSTRUMENTS
Ir-.CORPORATED
7-5
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 MSI/LSIFUNCTIONS
FUNCTIONAL INDEX/SELECTION GUIDE

SHIFT REGISTERS

NO. SERIAL MODES TYP TOTAL DEVICE TYPE

SHIFT ASYNC PAGE
DESCRIPTION OF DATA ++ ++ ~9 POWER AND PACKAGE
FREO CLEAR a: ..J
o :I:0 DISSIPATION NO.
BITS INPUT th th ..J _55°C to 125°C O°C to 70°C
50 MHz 0 Low X X X X 750mW SN54S299 J,W SN74S299 J, N 7-437
35 MHz D Low X X X X 175mW SN54LS299* J SN74LS299* J, N 7-437
8
PARALLEL·IN, 35 MHz D Sync L X X X X 175mW SN54LS323* J SN74LS323* J, N 7-443
PARALLEL·OUT 25 MHz D Low X X X X 360mW SN54198 J,W SN74198 J N 7·338
(BIDIRECTIONAL) 70 MHz D Low X X X X 450mW SN54S194 J,W SN74S194 J, N
4 25 MHz D Low X X X X 75mW SN54LSl94A J,W SN74LSl94A J, N 7-316
25 MHz D Low X X X X 195mW SN54194 J,W SN74194 J, N
8 25 MHz J-K Low X X X 360mW SN54199 J,W SN74199 J, N 7-338
10MHz D Low X X 60mW SN54LS96 J,W SN74LS96 J, N
5 10MHz D Low X X 240mW SN5496 J,W SN7496 J, N 7-95
5MHz D Low X X 120mW SN54L96 J SN74L96 J N
70 MHz J-K Low X X 375mW SN54S195 J,W SN74S195 J, N 7-324
30 MHz J-K Low X X 195mW SN54195 J,W SN74195 J, N 7-324
25 MHz D Low X X 75mW SN54LS395A * J,W SN74LS395A * J, N 7-496
PARALLEL-IN,
25 MHz D None X X 195mW SN5495A J,W SN7495A J, N 7-89
PARALLEL-OUT
25 MHz D Low X X X 230mW SN54179 J,W SN74179 J, N 7-265
4 25 MHz D None X X X 230mW SN54178 J,W SN74178 J, N 7-265
30 MHz J-K Low X X 70mW SN54LS195A J,W SN74LS195A J, N 7-324
25 MHz D None X X 65mW SN54LS95B J,W SN74LS95B J, N 7-89
25 MHz D None X X 70mW SN54LS295B* J,W SN74LS295B* J, N 7-429
3 MHz J-K None X X 19mW SN54L99 J SN74L99 J, N 7-109
3MHz D None X X 19mW SN54L95 J,T SN74L95 J, N 7-89
25MHz Gated D Low X 80mW SN54LSl64 J,W SN74LSl64 J, N
SERIAL-IN,
8 25 MHz Gated D Low X 167mW SN54164 J,W SN74164 J, N 7-206
PARALLEL-OUT
12MHz Gated D Low X 84mW SN54L164 .J, T SN74Ll64 J, N
25 MHz D None X X X 210mW SN54165 J,W SN74165 J, N 7-212
35 MHz D None X X X 105mW SN54LS165 J,W SN74LS165 J, N 7-212

I PARALLEL-IN,
SERIAL-OUT
8

4
20 MHz
35 MHz
10MHz
D
D
D
Low
Low
High
X
X
X
X X

X
X X
360mW
110mW
175mW
SN54166
SN54LSl66
SN5494
J,W
J,W
J,W
SN74166
SN74LSl66
SN7494
J, N
J, N
J, N
7-217
7-217
7-86
25M Gated D None X 60mW SN54LS91 J,W SN74LS91 J, N
I I
I

I
I~ III I
SERIAL-IN,
SERIAL-OUT
8 110MHz
"'Gated D None 175mW SN5491 A J, W ISN7491A J, N 17-81
I 3MHz Gated D None I 17.5mW SN54L91 J, T SN74L91 J, N
~S-R '" shift right, SoL '" shift left

OTHER REGISTERS

TYP TOTAL I DEVICE TYPE T 1

DESCRIPTION FREO
ASYNC
POWER AND PACKAGE
I PAGE I
CLEAR NO.
DISSIPATION _55°C to 125°C O°C to 70°C
30MHz None 36.5 mW SN54LS398 J SN74LS398 J, N 7-499
30 MHz None 36.5 mW SN54LS399 J,W SN74LS399 J, N 7-499
QUADRUPLE MULTIPLEXERS
25 MHz None 65mW SN54LS298 J,W SN74LS298 J, N 7-432
WITH STORAGE
125 MHz None 195mW I SN54298 J,W SN74298
SN74L98
J, N
J, N
7-432
7-107
3 MHz None 25mW SN54L98 J
8-BIT UNIVERSAL SHIFT/STORAGE 35 MHz Low 175mW SN54LS299* J SN74LS299* J, N
7-437
REGISTERS 50 MHz Low 750mW SN54S299 J,W SN74S299 J, N
25 MHz High 250mW SN54173 J,W SN74173 J, N
QUADRUPLE BUS-BUFFER REGISTERS 7-249
50 MHz High 85mW SN54LS173* J,W SN74LS173* J, N
·New product in development as of October 1976.

1076

7-6 TEXAS I,,"CORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 MSI/LSI FUNCTIONS
FUNCTIONAL INDEX/SELECTION GUIDE

LATCHES

NO. TYPICAL TYPTOTAL DEVICE TYPE

PAGE
DESCRIPTION OF CLEAR OUTPUTS DELAY POWER AND PACKAGE
NO.
BITS TIME DISSIPATION -55°C to 125°C O°C to 70°C
MULTI-MODE BUFFERED 8 Low Q 11 ns 410mW SN54S412 J SN74S412 J, N 7-502
Low Q 12 ns 300mW SN54259 J,W SN74259 J, N
ADDRESSABLE 8 7-376
Low Q 17 ns 110mW SN54LS259 J,W SN74LS259 J, N
None Q 17 ns 210mW SN54LS363* J SN74LS363* J, N 7-467
TRANSPARENT 8 None Q 19 ns 120mW SN54LS373* J SN74LS373* J, N 7-471
None Q 7 ns 525mW SN54S373 J SN74S373 J, N 7-471
DUAL 4-BIT WITH Low Q 11 ns 250mW SN54116 J,W SN74116 J, N 7-115
8
INDEPENDENT ENABLE None Q 15 ns 320mW SN541 00 J,W SN74100 J, N 7-113
None Q,Q 15 ns 160mW SN5475 J,W SN7475 J, N 7-35
None Q,a 30 ns 80mW SN54L75 J SN74L75 J, N 7-35

I DUAL 2-BIT WITH

4
None
None
Q,a
Q
11 ns
15 ns
32mW
160mW
I SN54LS75
SN5477 IJ~W
SN74LS75
J, N I 7-35
7-35
INDEPENDENT ENABLE
None I Q I 30 ns 80mW SN54L77 7-35 I
I:~~~:~~51 j~W
None Q 10 ns 35mW I 7-35 I
I None ! a,a ! 12 ns 32mW
SN54279 J,W
SN74LS375
SN74279
j, N
J, N
i 7-478 i
None Q 12 ns 90mW
QUAD S-R (SSI) 4 6-60
None Q 12 ns 19mW SN54LS279 J,W SN74LS279 J, N

CLOCK GENERATOR CIRCUITS

I TYP TOTAL DEVICE TYPE

PAGE
DESCRIPTION POWER AND PACKAGE
NO.
I DISSIPATION -55°C to 125°C O°C to 70°C
(FOR TMS 9900) 669mW SN74LS362* J, N 7-460
CLOCK GENERATOR/DRIVERS
(FOR TMS 8080A) 719mW SN74LS424 J, N 7-507
90mW SN54LS124 J,W SN74LS124 J, N 7-123
DUAL VOLTAGE-CONTROLLED OSCILLATOR WITH ENABLE 525mW SN54S124 J, W SN74S12L' J, N 7-123

DUAL VOLTAGE-CONTROLLED OSCILLATOR

90mW
150mW
SN54LS326
SN54LS325
J,W
J,W
SN74 LS326
SN74LS325
J, N
J, N
7-445

7-445
I
150mW SN54LS327 J,W SN74LS327 J, N
VOLTAGE-CONTROLLED OSCILLATOR WITH ENABLE 90mW SN54LS324 J,W SN74 LS324 J, N 7-445
DUAL 30-MHz PULSE SYNCHRONIZERS/DRIVERS 255 mW SN54120 J, W SN74120 J, N 7-118
QUAD COMPLIMENTARY GATES (CLOCK/CLOCK) [SSI] 125mW SN54265 J, W SN74265 J, N 6-89

CODE CONVERTERS

TYPICAL
TYPICAL DEVICE TYPE
DELAY TIME PAGE
DESCRIPTION TOTAL POWER AND PACKAGE
PER PACKAGE NO.
DISSIPA TION
LEVEL -55°C to 125°C O°C to 70°C
S-LiNE-BCD TO S-LiNE
BINARY, OR 4-LlNE TO 4-LlNE 25 ns 280 mW SN54184 J,W SN74184 J, N 7-290
BCD 9's/BCD 10'5 CONVERTERS
S-BIT-BINARY TO S-BIT-BCD CONVERTERS 25 ns 280mW SN54185A J,W SN74185A J, N 7-290

"New product in development as of October 1976.

1076

TEXAS li'ooCORPORATED
INSTRUMENTS 7-7
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 MSI/LSI FUNCTIONS
FUNCTIONAL INDEX/SELECTION GUIDE

PRIORITY ENCODERS/REGISTERS

TYPICAL TYPTOTAL DEVICE TYPE

PAGE
DESCRIPTION DELAY POWER AND PACKAGE
NO.
TIME DISSIPATION _55°C to 125°C O°C to 70°C
10 ns 225mW SN54147 J,W SN74147 J, N
FULL BCD PRIORITY ENCODERS 7-151
15 ns 60mW SN54LS147* J,W SN74LS147* J, N
12 ns 190mW SN54148 J,W SN74148 J, N
CASCADABLE OCTAL PRIORITY ENCODERS 7-151
15 ns 60mW SN54LS148* J,W SN74LS148* J, N
CASCADABLE OCTAL PRIORITY ENCODERS
16 ns 63mW SN54LS348* J,W SN74LS348* J, N 7448
WITH 3-STATE OUTPUTS
4-BIT CASCADABLE PRIORITY REGISTERS 35 ns 275mW SN54278 J,W SN74278 J, N 7403

DATA SELECTORS/MULTIPLEXERS

TYPICAL DELAY TIMES

TYPE TYP TOTAL DEVICE TYPE
DATA TO DATA TO PAGE
DESCRIPTION OF FROM POWER AND PACKAGE
INV NON-INV NO.
OUTPUT ENABLE DISSIPATION
OUTPUT OUTPUT _55°C to 125°C oOe to 70°C
16-LlNE-TO-l-LiNE 2-State 11 ns 18 ns 200mW SN54150 J,W SN74150 J, N 7-157
DUAL
3-State 10 ns 17 ns 220mW SN74351 N 7451
8-LlNE-TO-l-LiNE
3-State 4.5 ns 8 ns 14 ns 275mW SN54S251 J,W SN74S251 J, N 7-362
3-State 17 ns 21 ns 21 ns 250mW SN54251 J,W SN74251 J, N 7-362
3-State 17 ns 21 ns 21 ns 35mW SN54LS251 J,W SN74LS251 J, N 7-362
2-State 4.5 ns 8 ns 9 ns 225mW SN54S151 J,W SN74S151 J, N 7-157
8-LlNE-TO-l-LiNE
2-State 8 ns 16 ns 22 ns 145mW SN54151A J,W SN74151A J, N 7-157
2-State 8 ns 130mW SN54152A W 7-157
2-State 11 ns 18 ns 27 ns 30mW SN54LS151 J,W SN74LS151 J, N 7-157
2-State 11 ns 18 ns 28mW SN54LS152 W 7-157
3-State 12 ns 16 ns 35mW SN54LS253 J,W SN74LS253 J, N 7-369

I DUAL
2-State
3-State
15 ns
12 ns
22 ns
21 ns
31 mW
43mW
SN54LS352
SN54LS353
J,W
J,W
SN74LS352
SN74LS353
J, N
J, N
7454
7457

4-LlNE-TO-l-LiNE
2-State I 6 ns 9.5 ns 225mW SN54S153 J,W SN74S153 J, N 7-165
2-State ! 14 ns ! 17 ns 180mW SN54153 J,W SN74153 I J, N 7- 1 65
2-State 14 ns 17 ns 31 mW SN54LS153 J,W SN74LS153 J, N 7-165
2-State 27 ns 34 ns 90mW SN541153 SN74L 153 J, N 7-165
2-State 20 nst 65mW SN54LS298 J,W SN74LS298 J, N 7432
QUADRUPLE 2-State 20 nst 195mW SN54298 J,W SN74298 J, N 7432
2-LlNE-TO-l-UNE 2-State 20 nst 32mW SN54LS398 J SN74 LS398 J, N 7499
WITH STORAGE 2-State 20 nst 20 nst 37mW SN54LS399 I
J, W SN74LS399 J, N 7499
2-State 120 nst 25mW SN54L98 J I SN74L98 J, N 7-107
3-State 4 ns 14 ns 280mW SN54S258 J,W SN74S258 J, N 7-372
3-State 5 ns 14 ns 320mW SN54S257 J,W SN74S257 J, N 7-372
2-State
2-State
4 ns
5 ns
7 ns
8 ns
195mW
250mW
I SN545158
SN54S157
J,W
J,W
SN74S158
SN74S157
J, N
J, N
7-181
7-181
QUADRUPLE 3-State 12 ns 20 ns 60mW SN54LS258A * J, W SN74LS258A' J, N 7-372
2-LlNE-TO-l-UNE 3-State 12 ns 20 ns 60mW SN54LS257A' J,W SN74LS257A' J, N 7-372
2-State 7 ns 12 ns 24mW SN54LSl58 J,W SN74LS158 J, N 7-181
2-State 9 ns 14 ns 49mW SN54LS157 J,W SN74LS157 J, N 7-181
2-State 9 ns 14 ns 150mW SN54157 J,W SN74157 J, N 7-181
2-State 18 ns 27 ns 75mW SN54L 157 J SN74L 157 J, N 7-181

tFrom clock .
• N!"w product in development as of October 1976.

1076

7-8 TEXAS INSTRUMENTS

I .... CORPORATED
!=JOST OFFICE BOX 5012 • CALLAS. TEXAS 75222
 MSI/LSI FUNCTIONS
FUNCTIONAL INDEX/SELECTION GUIDE

DECODERS/DEMUL TlPLEXERS

TYPICAL TYPICAL TYPTOTAL DEVICE TYPE

TYPE OF PAGE
DESCR IPTION SELECT ENABLE POWER AND PACKAGE
OUTPUT NO.
TIME TIME DISSIPATION -SSoC to 12SoC O°C to 70°C
Totem·Pole 23 ns 19 ns 170mW SN54154 J,W SN74154 J, N 7·171
4-lINE·TO-l6-lINE Totem·Pole 46 ns 38 ns 85mW SN54L154 J SN74L 154 J, N 7·171
Open·Coliector 24 ns 19 ns 170mW SN54159 J,W SN74159 J, N 7·188
Totem·Pole 17 ns 35mW SN54LS42 J,W SN54LS42 J, N
4-lINE·TO·l (}'lINE,
Totem-Pole 17 ns 140mW SN5442A J,W SN7442A J, N 7-15
BCD-TO-DECIMAL
Totem·Pole 34 ns 70mW SN54L42 J SN74L42 J, N
4-lINE·TO-l(}.lINE, Totem-Pole 17 ns 140mW SN5443A J,W SN7443A J, N
7-15
EXCESS-3-TO-DECI MAL Totem-Pole 34 ns 70mW SN54L43 J SN74L43 J, N
4-lINE-TO-l (}'lINE
Totem-Pole 17 ns 140mW SN5444A J.W SN7444A I J, N
EXCESS-3-GRA y- 7-15
Totem-Pole 34 ns 70mW SN54L44 J SN74L44 J, N
TO-DECIMAL
Totem-Pole 8 ns 7 ns 245mW SN54S138 J, W SN74S138 J, N 7-134
3-lINE-TO-8-lINE
Totem-Pole 22 ns 21 ns 31 mW SN54LS138 J,W SN74LS138 J, N 7-134
Totem-Pole 7.5 ns 6 ns 300mW SN54S139 .J,vv SN74Si39 I j, N 7-134
Totem-Pole 22 ns 19 ns 34mW SN54LSl39 J,W SN74LS139 J, N 7-134
Totem-Pole 18 ns 15 ns 30mW SN54LS155 J,W SN74LS155 J, N 7-175
DUAL 2-lINE-TO-4-lINE
Totem-Pole 21 ns 16 ns 125mW SN54155 J,W SN74155 J, N 7-175
Open-COllector 23 ns 18 ns 125mW SN54156 J,W SN74156 J, N 7-175
Open-Collector 33 ns 26ns 31 mW SN54LS156 J,W SN74LS156 J, N 7-175

OPEN-COLLECTOR DISPLAY DECODERS/DRIVERS WITH COUNTERS/LATCHES

OUTPUT OFF-STATE TYPTOTAL DEVICE TYPE

PAGE
DESCRIPTION SINK OUTPUT POWER BLANKING AND PACKAGE
NO.
CURRENT VOLTAGE DISSIPATION -55°C to 125"C OU C to 70°C
BCD COUNTER!

•
4-BIT LATCH!
BCD-TO-DECIMAL
7mA 55 V 340mW
I SN74142 J, N 7-140

DECODER/DRIVER
BCD COUNTER!
4-BIT LATCH/ Constant
BCD-TO-SEVEN- Current 7V 280mW Ripple SN54143 J,W SN74143 J, N 7-143
SEGMENT DECODER/ 15mA
LED DRIVER
BCD COUNTER/
4-BIT LATCH/
20mA 15V 280 mW Ripple SN54144 J,W
BCD-TO-SEVEN- 7-143
25mA 15V 280mW Ripple SN74144 J, N
SEGMENT DECODER!
LAMP DRIVER

RESUL TANT DISPLAYS USING '143, '144

1076

TEXAS)NSTRUMENTS I~CORI'ORArED
7-9
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 MSI/LSI FUNCTIONS
FUNCTIONAL INDEX/SELECTION GUIDE

OPEN-COLLECTOR DISPLAY DECODERS/DRIVERS

OUTPUT OFF-STATE TYPTOTAL DEVICE TYPE

PAGE
DESCRIPTION SINK OUTPUT POWER BLANKING AND PACKAGE
NO.
CURRENT VOLTAGE DISSIPATION -55°C to 125°C O°C to 70°C
SOmA 30V 215mW Invalid Codes SN5445 J,W SN7445 J, N 7-20
SOmA 15V 35mW Invalid Codes SN74LS145 J, N 7-148
BCD-TO-DECIMAL
12mA 15V 35mW Invalid Codes SN54LS145 J,W 7-148
DECODERS/DR IVERS
SOmA 15V 215mW Invlaid Codes SN54145 J,W SN74145 J, N 7-148
7 mA 60V 80mW Invalid Codes SN74141 J, N 7-138
40mA 30V 320mW Ripple SN5446A J,W SN7446A J, N 7-22
40mA 30V 320mW Ripple SN54246 J,W SN74246 J, N 7-22
40mA 15V 320mW Ripple SN5447A J,W SN7447A J, N 7-22
40mA 15V 320mW Ripple SN54247 J,W SN74247 J, N 7-351
24mA 15V 35mW Ripple SN74LS47 J, N 7-22
24mA 15V 35mW Ripple SN74LS247 J, N 7-351
12mA 15V 35mW Ripple SN54LS47 J,W 7-22
12mA 15V 35mW Ripple SN54LS247 J,W 7-351
20mA 30V 133mW Ripple SN54L46 J SN74L46 J, N 7-22
BCD-TO- 20 mA 15V 133mW Ripple SN54L47 J SN74L47 J, N 7-22
SEVEN·SEGMENT 6.4 mA 5.5V 265mW Ripple SN5448 J,W SN7448 J, N 7-22
DECODERS/DR IVERS 6.4 mA 5.5V 265mW Ripple SN54248 J,W SN74248 J, N 7-351
6mA 5.5 V 125mW Ripple SN74LS48 J, N 7-22
6mA 5.5V 125mW Ripple SN74LS248 J, N 7-351
2mA 5.5V 125mW Ripple SN54LS48 J,W 7·22
2mA 5.5 V 125mW Ripple SN54LS248 J,W 7-351
I lamA 5.5V 165mW Direct SN5449 W 7-22
I lamA 5.5V 265mW Direct SN54249 J,W SN74249 J, N 7-351

•
8mA 5.5V 40mW Direct SN74LS249 J, N 7-351
8mA 5.5 V 40mW Direct SN74LS49 J, N 7-22
4mA 5.5 V 40mW Direct SN54LS49 J,W 7-22
4mA 5.5 V 40mW Direct SN54LS249 J,W 7-351

RESULTANT DISPLAYS USING '46A, '47A, '48, '49, 'L46, 'L47, 'LS47, 'LS48, 'LS49

RESULTANT DISPLAYS USING '246, '247, '248, '249, 'LS247, 'LS248, 'LS249

1076

7-10 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 MSI/LSI FUNCTIONS
FUNCTIONAL INDEX/SELECTION GUIDE

BUS TRANSCEIVERS AND DRIVERS

TYPICAL MAXIMUM MAXIMUM DEVICE TYPE

PAGE
DESCRIPTION PROPAGATION SOURCE SINK AND PACKAGE
NO.
DELAY TIMES CURRENT CURRENT -55°C to 125°C O°C to 70°C
CONTROLLER AND BUS DRIVER -lmA 10mA SN74S428 N
7·514
FOR 8080A SYSTEMS -lmA 10mA SN74S438 N
OCTAL BUS TRANSCEIVERS 12 ns -12mA 12mA SN54LS245* J SN74LS245* J, N 7-349
4-BIT BUS TRANSCEIVERS
10 ns -6.5mA 20mA SN54S226* J,W SN74S226* J, N 7-345
WITH STORAGE

ASYNCHRONOUS COUNTERS (RIPPLE CLOCK)-NEGATIVE-EDGE TRIGGERED

TYP TOTAL DEVICE TYPE

COUNT PARALLEL PAGE
DESCRiPTiON CLEAR POWER AND PACKAGE
NO.
FREQ LOAD
DISSIPATION _55°C to 125°C I O°C to 70°C
50 MHz Yes Low 240mW SN54196 I J, W I SN74196 I J, N 7-331
100MHZ 1 Yes Low 375 mW SN54S196 J, W 1 SN74S196 1 J, N 1 7-331 1
1 ""
,:!O:;!IJI~
....... z .
Yoo ~.
_"
I ... w 15n ... -
... mIN 1 SN54 176
.- ... -- SN7417R
1 -,I W -
. _- ... ",I .N 7. ?59
-
32 MHz Set-to-9 High 40mW SN54LS90 J,W SN74LS90 J, N 7-72
DECADE 32 MHz Set-to-9 High 40mW SN54LS290 J,W SN74LS290 J, N 7-423
32 MHz Set-to-9 High 160mW SN5490A J,W SN7490A J, N 7-72
32 MHz Set-to-9 High 160mW SN54290 J,W SN74290 J, N 7-423
30 MHz Yes Low 60mW SN54LS196 J,W SN74LSl96 J, N 7-331
3 MHz Set-to,9 High 20mW SN54L90 J, T SN74L90 J, N 7-72
50 MHz Yes Low 240mW SN54197 J,W SN74197 J, N 7-331
100 MHz Yes Low 375mW SN54S197 J,W SN74S197 J, N 7-331
I I 35 MHz Yes Low I 150 mIN SN54177 I J, IN ~N74177 J, N I 7-259
I I
32 MHz None High 39mW SN54LS93 J,W ~~;~~S~3 I J, N 7-72
I 4-BiT BINARY I 32 MHz None High
I 39mW SN54LS293 J,W SN74LS293 J, N 7-423
32 MHz None High 160mW SN5493A J,W SN7493A J, N 7-72
32 MHz
30 MHz
3 MHz
None
Yes
None
High
Low
High
160mW
60mW
20mW
SN54293
SN54LS197
SN54L93
J,W
J,W
J, T
SN74293
SN74LS197
SN74L93
J, N
J, N
J, N
7-423
7-331
7-72
II
32 MHz None High 39mW SN54LS92 J,W SN74LS92 J, N
DIVIDE-BY-12 7-72
32 MHz None High 160mW SN5492A J,W SN7492A J, N
25 MHz None High 210mW SN54390 J,W SN74390 J, N 7-489
35 MHz None High 75mW SN54LS390 J,W SN74LS390 J, N 7-489
DUAL DECADE
25 MHz Set-to-9 High 225mW SN54490 J,W SN74490 J, N 7-520
35 MHz Set-to-9 High 75mW SN54LS490 J,W SN74LS490 J, N 7-520
25 MHz None High 190mW SN54393 J,W SN74393 J, N 7-489
DUAL 4-BIT BINARY
35 MHz None High 75mW SN54LS393 J,W SN74LS393 J, N 7-489

1076

TEXAS I"ICORPORATED
INSTRUMENTS 7-11
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 MSI/LSI FUNCTIONS
FUNCTIONAL INDEX/SELECTION GUIDE

SYNCHRONOUS COUNTERS-POSITIVE-EDGE TRIGGERED

TYP TOTAL DEVICE TYPE

COUNT PARALLEL PAGE
DESCRIPTION CLEAR POWER AND PACKAGE
FREQ LOAD NO_
DISSIPATION -SSoC to 12SoC O°C to 70°C
40 MHz Sync Sync-L 475mW SN54S162 J,W SN74S162 J, N
25 MHz Sync Sync-L 93mW SN54LS162A J,W SN74LS162A J, N
DECADE 25 MHz Sync Async-L 93mW SN54LS160A J, W SN74LS160A J, N 7-190
25 MHz Sync Sync-L 305mW SN54162 J,W SN74162 J, N
25 MHz Sync Async-L 305mW SN54160 J,W SN74160 J N
40 MHz Sync None 500mW SN54S168 J,W SN74S168 J, N 7-226
25 MHz Sync None 100mW SN54LS168A J,W SN74LS168A J, N 7-226
25 MHz Async Async-H 85mW SN54LS192 J,W SN74LS192 J, N 7-306
DECADE
25 MHz Async Async-H 325mW SN54192 J,W SN74192 J, N 7-306
UP/DOWN
20 MHz Async None 100mW SN54LS190 J,W SN74LS190 J, N 7-296
20 MHz Async None 325mW SN54190 J,W SN74190 J, N 7-296
3 MHz Async Async-H 42mW SN54l192 J SN74L 192 J, N 7-306
DECADE _1_
25 MHz Set-to-9 Async-H 270mW SN54167 J,W SN74167 J, N 7-222
RATE MULTIPLIER, N10
40 MHz Sync Sync-L 475mW SN54S163 J, W SN74S163 J, N
25 MHz Sync Sync-L 93mW SN54LS163A J,W SN74LS163A J, N
4-BIT BINARY 25 MHz Sync Async-L 93mW SN54LS161A J,W SN74LS161A J,N 7-190
25 MHz Sync Sync-L 305mW SN54163 J,W SN74163 J, N
25 MHz Sync Async-L 305 mW SN54161 J,W SN74161 J, N
40 MHz Sync None 500mW SN54S169 J,W SN74S169 J, N 7-226
25 MHz Sync None 100mW SN54LS169A J,W SN74LS169A J, N 7-226
25 MHz Async Async-H 85mW SN54LS193 J,W SN74LS193 J, N 7-306
4-BIT BINARY
25 MHz Async Async-H 325 mW SN54193 J,W SN74193 J, N 7-306
UP/DOWN
20 MHz Async None 90mW SN54LS191 J,W SN74LS191 J, N 7-296
20 MHz Async None 325mW SN54191 J, W SN74191 J, N 7-296

•
3 MHz Async Async-H 42mW SN54l193 J SN74l193 J, N 7-306
6-BIT BINARY
--1- 25 MHz Async-H 345mW SN5497 J,W SN7497 J, N 7-102
RATE MULTIPLIER, N2

BiPOLAR 8IT-SLICE PROCESSOR ElEMENTSt

CASCADABLE TYPICAL DEVICE TYPE

DESCRIPTION TO wOPERATION TECHNOLOGY AND PACKAGE

4-BIT SLICE
N-BITS
Yes
Yes
Yes
TIME
100 ns
230 ns
230 ns
STTL
12L
12L
SN545481
SBP0400AM
SBP0401AM
1
-SSoC to 12SOC

J
J
J
O°C to 70°C

SN74S481
SBP0400AC
SBP0401AC
IJ, N
J, N
J, N

FIRST-IN FIRST-OUT MEMORIES (FIFO'S)t

TYPE DELAY TIME TYP TOTAL DEVICE TYPE

DESCRIPTION OF FROM POWER AND PACKAGE
OUTPUT CLOCK DISSIPATION -SSoC to 12 SoC , O°C to 70°C
ASYNCHRONOUS 16 X 5 3-State 50 ns 400mW
1 I SN74S225 I J

tSee Bipolar Microcomputer Components Data Book, LCC4270.

1076

7-12 TEXAS I'oCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 MSI/LSI FUNCTIONS
FUNCTIONAL INDEX/SELECTION GUIDE

RANDOM-ACCESS READ-WRITE MEMORIES (RAM'SI

TYPE TYPICAL TYPICAL TYP POWER DEVICE TYPE

ORGANI- PAGE
DESCRIPTION OF ADDRESS ENABLE DISSIPATION AND PACKAGE
ZATION NO.
OUTPUT TIME TIME PER BIT -55°C to 125°C aOc to 7aoC
1024-BIT ARRAYS 1024 X 1 3-State 65 ns 20 ns 0.2/0.07 mW SN54LS215 JD SN74LS215 JD,N t
WITH POWER-DOWN 1024 X 1 O-C 65 ns 20 ns 0.2/0.07 mW SN54LS315 JD SN74LS315 JD,N t
1024 X 1 3-State 65 ns 20 ns 0.2mW SN54LS214 JD SN74LS214 JD,N t
1024 X 1 3-State 30 ns 15 ns 0.51 mW SN54S214 JD SN74S214 JD,N t
1024 X 1 O-C 65 ns 20 ns 0.2mW SN54LS314 JD SN74LS314 JD,N t
1024 X 1 O-C 30 ns 15 ns 0.51 mW SN54S314 JD SN74S314 JD,N t
1024-BIT ARRAYS
256 X4 3-State 60 ns 20 ns 0.3mW SN54LS207 J SN74LS207 J, N t
256 X 4 3-State 40 ns 15 ns 0.59 mW SN54S207 J SN74S207 J, N t
256 X4 3-State 60 ns 20 ns 0.3mW SN54LS208 J SN74LS208 J, N t
256 X4 3-State 40 ns 15 ns 0.59 mW SN54S208 J SN74S208 J, N t
256-BIT ARRAYS 256 Xl 3-State 35 ns 15 ns 1.1/0.39 mW SN54LS202 J,W SN74LS202 J, N t
WITH POWER-DOWN 256 Xl O-C 35 ns 15 ns 1.1/0.39 mW SN54LS302 J, W SN74LS302 J, N t
~~ .~ .. ... "'..................................
,
' o<OL''.!UVA I I "1",qL"LUUAI
. .. _ _ _-
....... ....... .... ...
':>""'",, I J, VV J, I"
256 X 1 I 3-State 25 ns 15 ns 1.9 mW ISN54S200A J, W SN74S200A J, N
256 Xl 3-State 42 ns 17 ns 1.9mW SN54S201 J,W SN74S201 J, N t
256-BIT ARRAYS
256 Xl O-C 35 ns 15 ns 1.1mW SN54LS300A J,W SN74 LS300A J, N t
256 X 1 O-C 25 ns 15 ns 1.9mW SN54S300A J,W SN74S300A J, N t
256 Xl O-C 42 ns 13 ns 1.9mW SN54S301 J,W SN74S301 J, N t
16 X4 3-State 25 ns 12 ns 5.9mW SN54S189 J,W SN74S189 J, N t
64·BIT ARRAYS 16X4 O-C 25 ns 12 ns 5.9mW SN54S289 J,W SN74S289 J, N t
16 X4 O-C 32 ns 30 ns 5.9mW SN7489 J, N t
16 X 1 O-C 15 ns 15 ns 14mW SN5481 A J,W SN7481A J, N t
16-BIT ARRAYS
I 16 X 1 O-C 15 ns I 15 ns I 14 mW ISN5484A I J, W I SN7484A I J, N I t I
16-BIT MULTIPLE·PORT I I I I
8X2 3-State 33 ns 15 ns
REGISTER FILE
35mW 1 1 SN74172
I J, N 7- 245 1

•
4X4 O-C 27 ns 15 ns 7.8mW SN54LS170 J,W SN74LS170 J, N 7-237
16-BIT REGISTER FILE 4X4 O-C 30 ns 15 ns 40mW SN54170 J,W SN74170 J, N 7-237
4X4 3-State 24 ns 19 ns 9.3mW SN54LS670 J,W SN74LS670 J, N 7-526

READ·ONL Y MEMORIES (ROM'Slt

TYPE TYPICAL TYPICAL TYP POWER DEVICE TYPE

ORGANI·
DESCRIPTION OF ADDRESS ENABLE DISSIPATION AND PACKAGE
ZATION
OUTPUT TIME TIME PER BIT _55°C to 125°C aOc to 7aoC
512 X 4 O-C 45 ns 15 ns 0.26 mW SN54S270 J SN74S270 J, N
256 X 8 O-C 45 ns 15 ns 0.26 mW SN54S271 J SN74S271 J, N
2048-BIT ARRAYS
512 X 4 3·State 45 ns 15 ns 0.26 mW SN54S370 J SN74S370 J, N
256 X 8 3-State 45 ns 15 ns 0.26 mW SN54S371 J SN74S371 J, N
1024-BIT ARRAYS 256 X 4 O-C 40 ns 20 ns 0.46 mW SN54187 J,W SN74187 J, N
256-BIT ARRAYS 32 X 8 O-C 26 ns 22 ns 1.1 mW SN5488A J,W SN7488A J, N

tSee Bipolar Microcomputer Components Data Book, LCC4270.

1076

TEXAS)NSTRUMENTS
I1'<CORPORATED
7-13
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN5442A THRU SN5444A, SN54l42 THRU SN54l44,
SN54lS42, SN7442A THRU SN7444A,
TTL SN74l42 TH RU SN74l44, SN74lS42
MSI 4-UNE-TO-10-UNE DECODERS (1-0F-10)
BULLETIN NO. DL-S 7611861, MARCH 1974-REVISED OCTOBER 1976

'42A, 'L42, 'LS42 ... BCD-TO-DECIMAL

'43A, 'L43 ... EXCESS-3-TO-DECIMAL
'44A, 'L44 ... EXCESS-3-GRAY-TO-DECIMAL
• All Outputs Are High for
Invalid Input Conditions SN5442A THRU SN5444A, SN54LS42 •.• J OR W PACKAGE
SN54L42 THRU SN54L44 ••• J PACKAGE
• Also for Application as SN7442A THRU SN7444A,
4-Line-to-16-Line Decoders SN74L42 THRU SN74L44, SN74LS42 ••• J OR N PACKAGE
(TOP VIEW)
3-Line-to-8-Line Decoders
• Diode-Clamped Inputs
INPUTS OUTPUTS
TYPES
TYPICAL TYPICAL
Vcc ~ ~
POWER DISSIPATION PROPAGATION DELAYS
'42A, '43A, '44A 140mW 17 ns
'L42, 'L43, 'L44 70mW 49 ns
'LS42 35mW 17 ns

description
These monolithic decimal decoders consist of eight
inverters and ten four-input NAND gates. The invert-
ers are connected in pairs to make BCD input data
available for decoding by the NAND gates. Full
decoding of valid input logic ensures that all outputs
remain off for all invalid input conditions.

The '42A, 'L42, and 'LS42 BCD-to-decimal decoders, positive logic: see function table
the '43A and 'L43 excess-3-to-decimal decoders, and
the '44A and 'L44 excess-3-gray-to-decimal decoders feature inputs and outputs that are compatible for use with most
TTL and other saturated low-level logic circuits. D-c noise margins are typically one volt.

•
Series 54, 54L, and 54LS circuits are characterized for operation over the full military temperature range of -55°C to
125°C; Series 74, 74L, and 74LS circuits are characterized for operation from O°C to 70°C.
FUNCTION TABLE
'42A, 'L42, 'LS42 ;43A, 'L43 '44A, 'L44 ALL TYPES
NO. BCD INPUT EXC.ESS-3-INPUT EXCESS-3-GRAY INPUT DECIMAL OUTPUT
'De B ...
Ai n e A ' ... DeB A '0 . .. 455 u
'"
0 L L L L L L H H L L H L L H H H H H H H H H
1 L L L H L H L L L H H L H L H H H H H H H H
j
2 L L H L L H L H L H H H H H L H H H H H H H
3 L L H H L H H L L H L H H H H L H H H H H H
4 L H L L L H H H L H L L H H H H L H H H H H
I 5 IL H L L L H L L I H H H H H L H H H H I

~ I~
H H L L H L H H H H H L H H

I 8 H
H
L
H
L I-.
L
L
H
H
H
H
H
H
: I:
I-. H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
L
:I
H
9 H L L H H H L L H L H L H H H H H H H H H L
H L H L H H L H H L H H H H H H H H H H H H

e
..J
H
H
L
H
H
L
H
L
H
H
H
H
H
H
L
H
H
H
L
L
L
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
«
> H H L H L L L L L L L L H H H H H H H H H H
~
H H H L L L L H L L L H H H H H H H H H H H
H H H H L L H L L L H H H H H H H H H H H H
H = hIgh level, L = low level

)76

TEXAS INSTRUMENTS 7-15

INCORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 ~
C)
I
en-4
~~ z-<
§- ~r-~."

-""~~l;:
~ Ul-~m
_. ~ Z r- en
g om en
III n.!.t ~ en
~ dC) ~~
Z
o m-en~
- til I

~ ~c;:» Z ~
a. tOr- ...... N
~. ~ zm t
""""'i>1{;:
):II
@
3
:
= ::c
m-4::a
N-4
):II

5. n::c c
II>

g. =
C)
c
en ::a

'~'"~~: CD m Z
~
..g ----i 3 ::aent
-I
[TI
>< g. en!i ~
~ > ~ ):II
I~ ..
II> -::::.
o
~ (IJ - C) ~
~ z_
:i'
""):lien
'-"'"~Efj~
"C
~8Z r:: .!... .. Z
lit Cen~
~~(IJ III -Z~
.o~ ::I
g~~
C.
o ~~
~~c::: r:: ~N

~o~
r+
"C ~-4
r::
r+ N::c
~ [TI '42A, 'L42, 'LS42 "43A, 'L43 '44A, 'L44
~ Z BCD-TO-DECIMAL DECODERS EXCESS-3-TO·DECIMAL DECODERS EXCESS-3-GRAY-TO-DECIMAL DECODERS
II>
-4::a
::Cc
~ ::a
(IJ '42A THRU '44A '42A THRU '44A Cen
'L42 THRU 'L44 'LS42 'L42 THRU 'L44 'LS42
en Z
EQUIVALENT OF EQUIVALENT OF TYPICAL OF TYPICAL OF Z~
EACH INPUT EACH INPUT ALL OUTPUTS ALL OUTPUTS ...... ~
~~
Vee Vee t~
vee3-- Req 17 kn. NOM
en
Z
INPUT
~
INPUT --
-OUTPUT OUTPUT

i
N

'42A THRU '44A: Req ~ 4 kn. NOM '42A THRU '44A: R = 130 n. NOM
'L42 THRU 'L44: Req ~ 8 kn. NOM 'L42 TH RU 'L44: R ~ 260 n. NOM

s
 TYPES SN5442A, SN5443A, SN5444A, SN7442A, SN7443A, SN7444A
4-LlNE-TO-10-LlNE DECODERS (1-0F-10)

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) ...... . 7V
I nput voltage . . . . . . . ...... . 5.5 V
Operating free·air temperature range: SN54' Circuits -55°C to 125°C
SN74' Circuits aOc to 7aoC
Storage temperature range -65°C to 15aoC
NOTE 1: Voltage values are with respect to netyvork ground terminal.

recommended operating conditions

SN5442A SN7442A
SN5443A SN7443A
UNIT
SN5444A SN7444A
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -800 800 }.LA
I ____ 1_. __ 1 _ ..... _ . • • ___ _ _. I
L.UVV-It;:Vt::1 UUlfJUlt,;urrt~lll, tOl io 16 mA
Operating free-air temperature, T A -55 125 0 70 De

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN5442A SN7442A
SN5443A SN7443A
PARAMETER TEST CONDITIONSt UNIT
SN5444A SN7444A
MIN TYP:j: MAX MIN TYP:j: MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
ViK !nput clamp voltage Vee = ~v~IN, Ij=-12mA -1.5 -i.5 V
Vee= MIN, VIH = 2 V,
VOH High-level output voltage 2.4 3.4 2.4 3.4 V

•
VIL = 0.8 V, 10H = -800}.LA
Vee = MIN, VIH=2V,
VOL Low-level output voltage 0.2 0.4 0.2 0.4 V
VIL = 0.8V, IOL=16mA
II Input current at maximum input voltage Vee = MAX, VI = 5.5V 1 1 mA
IIH High-level input current Vee= MAX, VI=2.4V 40 40 }.LA
IlL Low level input current Vee = MAX, VI = 0.4 V -1.6 -1.6 mA

lOS Short-circuit output current § Vee= MAX -20 -55 -18 -55 mA
lee Supply current Vee= MAX, See Note 2 28 41 28 56 mA

: For conditions shown as M IN or MAX, use t~e appropriate values specified under recommended operating conditions.
+AII typical values are at Vee = 5 V, T A = 25 e.
§ Not more than one output should be shorted at a time.
NOTE 2: ICC is measured with all outputs open and all inputs grounded.

switching characteristics, Vee = 5 V, TA = 25°e

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Propagation delay time, high-to-Iow-Ievel
tpHL 14 25 ns
output from A, B, e, or D through 2 levels of logic
Propagation delay time, high-to-Iow-Ievel
tpHL eL=15pF, 17 30 ns
output from A, B, e, or D through 3 levels of logic
RL=400 n,
Propagation delay time, low-to-high-Ievel
tpLH See Note 3 10 25 ns
output from A, B, e, and D through 2 levels of logic
Propagation delay time, low-to-high-Ievel
tPLH 17 30 ns
output from A, B, e, and D through 3 levels of logic
NOTE 3: Load CirCUits and waveforms are shown on page 3-10.

1076

TEXAS INCORPORATED
INSTRUMENTS 7-17
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54L42, SN54L43, SN54L44, SN74L42, SN74L43, SN74L44
4-LlNE-TO-10-LlNE DECODERS (1-0F-10)

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V CC (see Note 1) 7V
Input voltage . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range: SN54L' Circuits. -55°C to 125°C
SN74L' Circuits aOc to 7aoC
Storage temperature range -65°C to 15aoC
NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54L42 SN74L42
SN54L43 SN74L43
UNIT
SN54L44 SN74L44
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -400 -400 /lA
Low-level output current, 10L 8 8 mA
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONSt MIN TYPt MAX UNIT
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
VIK I nput clamp voltage Vee = MIN, II = -12 mA -1.5 V
Vee= MIN, VIH = 2 V,
VOH High-level output voltage 2.4 3.4 V
VIL = 0.8 V, 10H = -400JJA
Vce= MIN, VIH = 2 V,
VOL Low-level output voltage 0.2 0.4 V
VIL = 0_8 V, 10L = 8mA
II Input current at maximum input voltage Vee= MAX, VI=5.5V 1 mA
IIH High-level input current Vec = MAX, VI = 2.4 V 20 /lA

•
IlL Low-level input current Vec = MAX, VI = 0.4 V -0.8 mA
lOS Short-circuit output current § Vee= MAX -9 -28 mA

Supply Current
Vec - MAX, I SN54L' 14 22
mA
lee
See Note 2 I SN74L' 14 28

tFor conditions shown as rv1:N or ~1AX, use the appropriate values specified under recommended operating conditions.
tAli typical values are at Vee = 5 V, T A = 25°e.
§Not more than one output should beshorted at a time.
NOTE 2: Ice is measured with all outputs open and inputs grounded.

switching characteristics, Vee = 5 V, TA = 25°e

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

tpHL
Propagation delay time, high-to-Iow-Ievel
output from A, B, e, or D through 2 levels of logic
I 10 44 60 ns

Propagation delay time, high-to-Iow-Ievel

tpHL eL=15pF, 46 70 ns
output from A, B, C, or D through 3 levels of logic
Propagation delay time, low-to-high-Ievel
RL = 800 n,
tpLH See Note 3 10 J4 50 ns
output from A, B, e, and D through 2 levels of logic
Propagation delay time, low-to-high-Ievel
tpLH 52 70 ns
output from A, B, e, and D through 3 levels of logic
NOTE 3: Load circuit and voltage waveforms are shown on page 3-10.

1076

7-18 TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54LS42, SN74LS42
4-UNE-TO-l0-UNE DECODERS (1-0F-1O)
REVISED OCTOBER 1976

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, Vee (see Note 1) ..... . 7V

Input voltage . . . . . . . . . . . . . . 7V
Operating free-air temperature range: SN54LS42 -55°C to 125°C
SN74LS42 oOe to 70°C
Storage temperature range -65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54LS42 SN74LS42
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -400 -400 p.A
Low-level output current, 10L 4 8 mA
o~
I Operating free-air temperature, T A ,-55 I":::''''' C 70 I v

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS42 SN74LS42
PARAMETER TEST CONDITIONSt UNIT
MIN TYP+ MAX MIN TYP+ MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
VIK Input clamp voltage Vee= MIN, II = -18mA -1.5 -1.5 V
Vee= MIN, VIH=2V,
VOH High-level output voltage 2.5 3.5 2.7 3.5 V
VIL=VILmax,IOH=-400p.A
Vec= MIN, VIH=2V, \IOL=4mA 0.25 0.4 0.25 0.4 I
VOL Lo\'\'!-!eve! output voltage V
I
VIL = VIL max jlOL = 8 mA 0.35 0.5
Input current at
II Vee= MAX, VI = 7 V 0.1 0.1 mA
maximum input voltage
IIH High-level input current Vec= MAX, VI = 2.7 V 20 20 p.A
IlL
lOS
Low-level input current
Short-circuit output current§
Vee= MAX,
Vee = MAX
VI = 0.4 V
-20
-0.4
-100 -20
-0.4
-100
mA
mA
II
ICC Supply current Vee= MAX, See Note 2 7 13 7 13 mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
0
tAli typical vah./es are at V C:C: = 5 V, T A = 25 C.
§ Not mOre than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
NOTE 2. ICC is measured with all outputs open and inputs grounded.

switching characteristics, Vee = 5 V, T A = 25° C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Propagation delay time, high-to-Iow-Ievel
tPHL 15 25 ns
output from A, B, e, or 0 through 2 levels of logic
Propagation delay time, high-to-Iow-Ievel
tPHL eL = 15 pF, 20 30 ns
output from A, B, e, or 0 through 3 levels of logic
RL = 2 kn,
Propagation delay time, low-to-high-Ievel
tPLH See Note 4 15 25 ns
output from A, B, e, and 0 through 2 levels of logic
Propagation delay time, low-to-high-Ievel
tpLH 20 30 ns
output from A, B, e, and 0 through 3 levels of logic

NOTE 4: Load circuit and voltage waveforms are shown on page 3-11.

1076

TEXAS INSTRUMENTS
II'<CORPORATED
7-19
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TTL TYPES SN5445, SN7445
MSI BCD-TO-DECIMAL DECODERS/DRIVERS
BULLETIN NO. DL-S 7211816. DECEMBER 1972

FOR USE AS LAMP, RELAY, OR MOS DRIVERS

featuring SN5445 .•• J OR W PACKAGE

SN7445 ••• J OR N PACKAGE
• Full Decoding of Input Logic (TOP VIEW)

• SO-rnA Sink-Current Capability

• All Outputs Are Off for Invalid
BCD Input Conditions
logic

FUNCTION TABLE
INPUTS OUTPUTS
NO.
0 C B A 0 2 3 4
1 5 6 7 8 9
0 L L L L L H H H H H H H H H
1 L L L H H L H H H H H H H H
2 L L H L H H L H H H H H H H
3 L L H H H H H L H H H H H H
4 L H L L H H H H L H H H H H
5 L H L H H H H H H L H H H H ..
6 L H H L H H H H H H L H H H OUTPUTS
7 L H H H H H H H H H H L H H
8 H L L L H H H H H H H H L H
J.lositive logic: see function table
9 H L L H H H H H H H H H L
H
H L H L H H H H H H H H H H
0 H L H H H H H H H H H H H H
:J H H L L H H H H H H H H H H
<t: functional block diagram
> H H L H H H H H H H H H H H
:!:: H H H L H H H H H H H H H H

•
H H H H H H H H H H H H H H

H = high level (off). L = low level (on)

description
These monolithic BCD-to-decimal decoders/drivers
consist of eight inverters and ten four-input NAND
gates. The inverters are connected in pairs to make
BCD input data available for decoding by the NAND
gates. Full decoding of valid BCD input logic ensures
that all outputs remain off for all invalid binary input
conditions. These decoders feature TTL inputs and
high-performance, n-p-n output transistors designed
for use as indicator/reillY drivers or as open-collector
logic-circuit drivers. Each of the high-breakdown
output transistors (30 volts) will sink up to 80
milliamperes of current. Each input is one normalized
Series 54/74 load. Inputs and outputs are entirely
compatible for use with TTL or DTL logic circuits,
and the outputs are compatible for interfacing with
most MOS integrated circuits. Power dissipation is
typically 215 milliwatts.

1076

7-20 TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 • OALLAS. TEXAS 75222
 lYPES SN5445, SN7445
BCD-lO-DECIMAL DECODERS/DRIVERS
REVISED OCTOBER 1976

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1) 7V
Input voltage . . . . . . . . 5.5 V
Maximum current into any output (off-state) 1 mA
Operating free-air temperature range: SN5445 Circuits -55°C to 125°C
SN7445 Circuits aOc to 7aoC
Storage temperature range -65°C to 15aoC
NOTE1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN5445 SN7445
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, V CC 4.5 5 5.5 4.75 5 5.25 V
Off-state output voltage 30 30 V
Operating free-air temperature, T A I -55 125 0 70 °c
I I I
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
I !>A RAM I=t:!
... _._.ET_ .. ( .reT r-nMruT.,"U\U:.. t
....... """"n""""VI ... ,,-
I •. no
IVIII~
_ ._+
11'1"'+
u
iviAA t Ui\iil- i
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
VIK Input clamp voltage Vee = MIN, 11=-12mA -1.5 V

Va (on) On-state output voltage

Vce= MIN, VIH = 2 V, I IO(on) = 80 mA 0.5 0.9
V
VIL=0.8V
1 IO(on) = 20 mA 0.4
Vee = MIN, VIH=2V,
I a (off) Off-5tate output current 250 IlA
VIL = 0.8 V, Va (off) = 30 V
II Input current at maximum input voltage Vce= MAX, VI=5.5V 1 mA
IIH High-level input current Vee = MAX, VI = 2.4 V 40 IlA
IlL Low-level input current IVee= MAX, VI-OAV I -1.6 I mA

lee Supply current Vee = MAX, See Note 2 I SN5445 43 62

70 I mA
I SN7445 43

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type .
:j:AII typical values are at V CC = 5 V, T A = 25°C.
NOTE 2: ICC is measured with all inputs grounded and outputs open.

switching characteristics, Vee = 5 V, TA = 25°e

I
I tpLH
PARAMETER
Propagation delay time, low-to-high-Ievel output
eL=15pF,
TEST CONDITIONS

RL=100n, See Note 3

I MIN
I
TYP MAX UNIT
50
I
I ns
•
I tpHL Propagation delay time, high-to-Iow-Ievel output
I 50 I ns

NOTE 3: Load circuit and waveforms are shown on page 3-10.

schematics of inputs and outputs

EQUIVALENT OF ALL INPUTS TYPICAL OF ALL OUTPUTS
Vcc--____- .______

INPUT

1076

TEXAS INSTRUMENTS INCORPORATED

7-21
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN5446A, '47A, '48, '49, SN54L46, 'L47, SN54LS47, 'LS48, 'LS49,
SN7446A, '47A, '48, SN74L46, 'L47, SN74 LS47, 'LS48, 'LS49
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
BULLETIN NO. DL-S 7611811. MARCH 1974-REVISED OCTOBER 1976

'46A, '47A, 'L46, 'L47, 'LS47 '48, 'LS48 '49, 'LS49

feature feature feature

• Open-Collector Outputs • Internal Pull-Ups Eliminate • Open-Collector Outputs

Drive Indicators Directly Need for External Resistors • Blanking Input
• Lamp-Test Provision • Lamp-Test Provision
• Leading/Trailing Zero • Leading/Trailing Zero
Suppression Suppression
• All Circuit Types Feature Lamp Intensity Modulation Capability

DRIVER OUTPUTS TYPICAL

TYPE ACTIVE OUTPUT SINK MAX POWER PACKAGES
LEVEL CONFIGURATION CURRENT VOLTAGE DISSIPATION
SN5446A low open-collector 40mA 30V 320mW J,W
SN5447A low open-collector 40mA l5V 320mW J,W
SN5448 high 2-k!"! pull·up 6.4mA 5.5 V 265mW J,W
SN5449 high open-collector 10mA 5.5 V l65mW W
SN54L46 low open-collector 20mA 30V 160mW J
SN54L47 low open-collector 20mA l5V l60mW J
SN54LS47 low open-collector l2mA l5V 35mW J,W
SN54LS48 high 2-kn pull-up 2mA 5.5 V l25mW J,W
SN54LS49 high open-collector 4mA 5.5 V 40mW J,W
SN7446A low open-collector 40mA 30V 320mW J, N
SN7447A low open-collector 40mA l5V 320mW J, N
SN7448 high 2-k!"! pull-up 6.4mA 5.5V 265mW J, N
SN74L46 low open-collector 20mA 30V l60mW J, N
SN74L47 low open-collector 20 mA l5V l60mW J, N
SN74LS47 low open-collector 24mA 15V 35mW J,N

•
SN74LS48 high 2-k!"! pull-up 6mA 5.5 V l25mW J, N
SN74LS49 high open-collector SmA 5.5V 40mW J, N

'46A, '47 A, 'L46, 'L47, 'LS47 '48, 'LS48 '49, 'LS49

(TOP VIEW) (TOP VIEW) (TOP VIEW)

O<.rTPtJTS
r -_ _ _ _ _ _~A~________,

~BT. :~
PUT PUT INPUTS

positive logic: see function tables

1076

7-22 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN5446A, '47A, '48, '49, SN54L46, 'L47, SN54LS47, 'LS48, 'LS49,
SN7446A, '47A, '48, SN74L46, 'L47, SN74LS47, 'LS4~, 'LS49
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
description
The '46A, 'L46, '47A, 'L47, and 'LS47 feature active-low outputs designed for driving common-anode VLEDs or
incandescent indicators directly, and the '48, '49, 'LS48, 'LS49 feature active-high outputs for driving lamp buffers or
common-cathode VLEDs. All of the circuits except '49 and 'LS49 have full ripple-blanking input/output controls and a
lamp test input. The '49 and 'LS49 circuits incorporate a direct blanking input. Segment identification and resultant
displays are shown below. Display patterns for BCD input counts above 9 are unique symbols to authenticate input
conditions.
The '46A, '47A, '48, 'L46, 'L47, 'LS47, and 'LS48 circuits incorporate automatic leading and/or trailing-edge
zero-blanking control (RBI and RBO). Lamp test (LT) of these types may be performed at any time when the BI/RBO
node is at a high level. All types (including the '49 and 'LS49) contain an overriding blanking input (BI) which can be
used to control the lamp intensity by pulsing or to inhibit the outputs. Inputs and outputs are entirely compatible for
use with TTL or DTL logic outputs.
The SN54246/SN74246 through '249 and the SN54LS247/SN74LS247 through 'LS249 compose the 5 and
the 9 with tails and have been designed to offer the designer a choice between two indicator fonts. The
SN54249/SN74249 and SN54LS249/SN74LS249 are 16-pin versions of the 14-pin SN5449 and 'LS49. Included in the
'249 circuit and 'LS249 circuits are the full functional capability for lamp test and ripple blanking, which is
not available in the '49 or 'LS49 circuit.
a
I-I II .J
tl 9 Ib Ii il
1--1
3 4 5 6 8 9 iO 11 i2 13 14 15
el IC
-d- NUMERICAL DESIGNATIONS AND RESULTANT DISPLAYS
SEGMENT
IDENTIFICATION

'46A, '47A, 'L46, 'L47, 'LS47 FUNCTION TABLE

DECIMAL
INPUTS OUTPUTS
OR BI/RBOt NOTE
FUNCTION LT RBI D C B A a b c d e f 9
0 H H L L L L H ON ON ON ON ON OFF
ION
1 H X L L L H H OFF ON ON OFF OFF .oFF OFF

•
2 H X L L H L H ON ON OFF ON ON OFF ON
3 H X L L H H H ON ON ON ON OFF OFF ON
4 H X L H L L H OFF ON ON OFF OFF ON ON
5 H X L H L H H ON OFF ON ON OFF ON ON
6 H X L H H L H OFF OFF ON ON ON ON ON
7 H X L H H H H ON ON ON OFF OFF OFF OFF
1
8 H X H L L L H ON ON ON ON ON ON ON
9 H X H L L H H ON ON ON OFF OFF ON ON
10 H X H L H L H OFF OFF OFF ON ON OFF ON
11 H X H L H H H OFF OFF ON ON OFF OFF ON
12 H X H H L L H OFF ON OFF OFF OFF ON ON
13 H X H H L H H ON OFF OFF ON OFF ON ON
14 H X H H H L H OFF OFF OFF ON ON ON ON
15 H X H H H H H OFF OFF OFF OFF OFF OFF OFF
BI X X X X X X L OFF OFF OFF OFF OFF OFF OFF 2
RBI H L L L L L L OFF OFF OFF OFF OFF OFF OFF 3
LT L X X X X X H ON ON ON ON ON ON ON 4
H = pigh level, L = low level, X = irrelevant
NOTi=S: 1. The blanking input (BI) must be open or held at a high logic level when output functions 0 through 15 are desired. The
ripple-blanking input (RBI) must be open or high if blanking of a decimal zero is not desired.
2. When a low logic level is applied directly to the blanking input (BI), all segment outputs are off regardless of the level of any
other input.
3. When ripple·blanking input (RBI) and inputs A, B, C, and D are at a low level with the lamp test input high, ali segment outputs
go off and the ripple·blanking output (RBO) goes to a low level (response condition)'
4. When the blanking input/ripple blanking output (BI/RBO) is open or held high and a low is applied to the lamp-test input, ali
segment outputs are on.
tBI/RBO is wire-AND logic serving as blanking input (BI) and/or ripple-blanking output (RBO).

1076

TEXAS INCORPORATED
INSTRUMENTS 7-23
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN5446A, '47A, '48, '49, SN54L46, 'L47, SN54LS47, 'LS48, 'LS49,
SN7446A, '47A, '48, SN74L46, 'L47, SN74LS47, 'LS48, 'LS49
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS

'48, 'LS48
FUNCTION TABLE

DECIMAL
INPUTS OUTPUTS
OR BI/RBOt NOTE
FUNCTION LT RBI D C B A a b c d e f 9
0 H H L L L L H H H H H H H L
1 H X L L L H H L H H L L L L
2 H X L L H L H H H L H H L H
3 H X L L H H H H H H H L L H
4 H X L H L L H L H H L L H H
5 H X L H L H H H L H H L H H
6 H X L H H L H L L H H H H H
7 H X L H H H H H H H L L L L
1
8 H X H L L L H H H H H H H H
9 H X H L L H H H H H L L H H
10 H X H L H L H L L L H H L H
11 H X H L H H H L L H H L L H
12 H X H H L L H L H L L L H H
13 H X H H L H H H L L H L H H
14 H X H H H L H L L L H H H H
15 H X H H H H H L L L L L L L
BI X X X X X X L L L L L L L L 2
RBI H L L L L L L L L L L L L L 3
LT L X X X X X H H H H H H H H 4

H = high level, L = low level, X = irrelevant

NOTES: 1. The blanking input (61) must be open or held at a high logic level when output functions 0 through 15 are desired. The
ripple-blanking input (R61) must be open or high, if blanking of a decimal zero is not desired,
2. When a low logic level is applied directly to the blanking input (61). all segment outputs are low regardless of the level of any
other input.
3. When ripple-blanking input (RBI) and inputs A, B, C, and D are at a low level with the lamp-test input high, all segment outputs
go low and the ripple-blanking output (RBO) goes to a low level (response condition!'
4. When the blanking input/ripple-blanking output (BI/RBO) is open or held high and a low is applied to the lamp-test input, all
segment outputs are high.
t 61/RBO is wire-AN D logic serving as blanking input (61) and/or ripple·blanking output (R60).

•
'49, 'LS49
FUNCTION TABLE
DECIMAL INPUTS OUTPUTS
OR NOTE
FUNCTION D C B A BI a b c d e f 9
0 L L L L ' H 'H H H H H H L
1 L L L H H L H H L L L L
2 L L H L H H H L H H L H
3 L L H H H H H H H L L H
4 L H L L H L H H L L H H
5 L H L H H H L H H L H H
6 L H H L H L L H H H H H
7 L H H H H H H H L L L L
1
8 H L L L H H H H H H H H
9 H L L H H H H H L L H H
10 H L H L H L L L H H L H
11 H L H H H L L H H L L H
12 H H L L H L H L L L H H
13 H H L H H H L L H L H H
14 H H H L H L L L H H H H
15 H H H H H L L L L L L L
BI X X X X L L L L L L L L 2
H = high level, L = low level, X = irrelevant
NOTES: 1. The blanking input (61) must be open or held at a high logic level when output functions 0 through 15 are desired.
2. When a low logic level is applied directly to the blanking input (61), all segment outputs are low regardless of the level of any
other input.

374

7-24 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN5446A, '47A, '48, '49, SN54L46, 'L47, SN54LS47, 'LS48, 'LS49,
SN7446A, '47A, '48, SN74L46, 'L47, SN74LS47, 'LS48, 'LS49
BCD-TO -SEVEN -SEGM ENT DECO DERS/D RIVE RS

functional block diagrams

'46A, '47A, 'L46, 'L47, 'LS47 '48, 'LS48

BLANKING

RIPP~P!~~ING

RIPPLEi~~KING ..>:(5"-}--Lf-_-_-_-_~ _____ __l._./

'49, 'LS49

374

TEXAS INCORPORATED
INSTRUMENTS 7-25
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN5446A, '47A, '48, '49, SN54L46, 'L47,
SN7446A, '47A, '48, SN74L46, 'L47
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
schematics of inputs and outputs
'46A, '47A, '48, '49, 'L46, 'L47 '46A, '47A, '48 'L46, 'L47

-
EQUIVALENT OF EACH INPUT EQUIVALENT OF BI/RBO EQUIVALENT OF BI/RBO
EXCEPT BI/RBO
Vee
Vee
vee

Q
2.4 kn 6 kn
Req
NOM NOM

INPUT --

SN54'/SN74': Req =6 kn NOM

SN54L'/SN74L': Req =8 kn NOM

'46A, '47A 'L46, 'L47

TYPICAL OF OUTPUTS TYPICAL OF OUTPUTS

aTHRU 9 a THRU 9

----------~~~~---vee

OUTPUT ----------~~-------Vee

OUTPUT

• '48 '49

TYPICAL OF OUTPUTS TYPICAL OF ALL OUTPUTS

a THRU 9

----------~.---~~vee ----------~~----vec

2kn
NOM

OUTPUT OUTPUT

374

7-26 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES .SN54LS47, 'LS48, 'LS49, SN74LS47, 'LS48, 'LS49
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS

schematics of inputs and outputs

'LS47, 'LS48, 'LS49 'LS47, 'LS48, 'LS49

EQUIVALENT OF EACH INPUT

EXCEPT BI/RBO

_- EQUIVALENT OF BI/RBO

Vee

q
vee
Req
20 kn 10 kn
INPUT -- NOM
NOM

L T and RBI ('LS47, 'LS48): Req = 20 kn NOM

BI/RBO----'
BI ('LS49): Req = 20 kn NOM
1\ 0 ,....
_. c, v, allU
_ _ ..... r""I......
L.,.I.
_ .....
r-
neq - "::::0
I.r">.
r;,..),{,
&,_ ...
I"IIUIVI

'LS47 'LS48

TYPICAL OF OUTPUTS TYPICAL OF OUTPUTS

a THRU 9 a THRU 9

-------.--~--vee

OUTPUT

'LS49
•
TYPICAL OF OUTPUTS
a THRU 9

-------.----vee

OUTPUT

374

TEXASINCORPORATED
INSTRUMENTS 7-27
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN5446A. SN5447A. SN7446A. SN7447A
BCD-TO-SEVEN-SEGM ENT 0 ECODERS/DR IVERS

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1) . . . . . 7V
Input voltage . . . . . . . .... . 5.5V
Current forced into any output in the off state 1 mA
Operating free-air temperature range: SN5446A, SN5447A -55°C to 125°C
SN7446A, SN7447A O°C to 70°C
Storage temperature range -65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN5446A SN5447A SN7446A SN7447A
UNIT
MIN NOM MAX MIN NOM MAX MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.5 5 5.5 4.75 5 5.25 4.75 5 5.25 V
Off-state output voltage, VO(off) a thru g 30 15 30 15 V
On-state output current, 10(on) a thru g 40 40 40 40 rnA
High-level output current, 10H BI/RBO -200 -200 -200 -200 !LA
Low-level output current, 10L BI/RBO 8 8 8 8 rnA
Operating free-air temperature, T A -55 125 -55 125 0 70 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONSt MIN TYP+ MAX UNIT
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
VIK Input clamp voltage Vee = MIN, II =-12mA -1.5 V
Vee= MIN, VIH = 2V,
VOH High-level output voltage BI/RBO 2.4 3.7 V
VIL = 0.8 V, 10H = -200 !LA
Vee=MIN, VIH=2V,
VOL Low-level output voltage BI/RBO 0.27 0.4 V
VIL = 0.8 V, 10L = 8mA
Vee = MAX, VIH = 2V,
10 (oft) Off-state output current a thru g 250 !LA

•
VIL = 0.8 v. VO(off) = MAX
Vee = MAX. VIH=2V,
VO(on) On-state output voltage a thru g 0.3 0.4 V
VIL = 0.8 V, 10(on) = 40 rnA
Any input
II Input current at maximum input voltage Vee = MAX. VI=5.5V 1 rnA
except B I/R BO
Any input
IIH High-level input current VCC= MAX, VI = 2.4 V 40 !LA
except B I/R BO
Any input
-1.6
IlL Low-level input current except BI/RBO Vee= MAX. VI = 0.4 V rnA
BI/RBO --4
lOS Short-circuit output current BI/RBO Vee= MAX --4 rnA

ICC Supply current

Vee = MAX, l SN54' 64 85
rnA
See Note 2 l SN74' 64 103
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operatin~ conditions.
+AII typical values are at V CC = 5 V, T A = 25° C.
NOTE 2: ICC is measured with all outputs open and all inputs at 4.5 V.

switching characteristics, Vee = 5 V, T A = 25°e

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
toff Turn-off time from A input 100
ns
ton Turn-on time from A input eL = 15pF. RL = 120 n. 100

toft Turn-off time from RBI input See Note 3 100

ns
ton Turn-on time from RBI input 100

NOTE 3: Load circuit and voltage waveforms are shown on page 3-10; toff corresponds to tpLH and ton ·corresponds to tpH L'

1076

7·28 TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54L46, SN54L47, SN74L46, SN74L47
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1) 7V
Input voltage . . . . . . . . . . . . . . . 5.5 V
Peak output current (tw ~ 1 ms, duty cycle ~ 10%) 200 rnA
Current forced into any output in the off state . 1 rnA
Operating free-air temperature range: SN54L46, SN54L47 -55°C to 125°C
O°C to 70 e
0
SN74L46, SN74L47
Storage temperature range -65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54L46 SN54L47 SN74L46 SN74L47
UNIT
MIN NOM MAX MIN NOM MAX MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.5 5 5.5 4.75 5 5.25 4.75 5 5.25 V
Off-state output voitage, VO(off) a thru g 30 i5 30 15 V
On-state output current, 10(on) a thru g 20 20 20 20 rnA
High-level output current, 10H BI/RBO -100 -100 -100 -100 J.LA
Low-level output current, 10L BI/RBO 4 4 4 4 rnA
n '7n n '7n or
1"\ ...............+: ...... -'=_............. : ...
I '"' .... c:laull~ l i c e - a i l + ......................... + .........
LCllltJCIQLII.oIIt;;,
T_
'A I -"'"
....~ 1
.2", " I -"" oJoJ
1
"!
.2.... ..... I ...... ,

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONSt MIN TYP+ MAX UNIT
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
Any input
VIK I nput clamp voltage Vee = MIN, 11= -12 rnA -1.5 V
except BI/RBO
Vee - MIN, VIH - 2 V,
VOH High-level output voltage BI/RBO 2.4 3.4 V
VIL = 0.8 V, 10H = -100 iJ.A I
Vee = MIN, VIH=2V,
VOL Low-level output voltage BI/RBO 0.2 0.4 V
V!L=0.8V, 10L =4 rnA

•
Vee - MAX, VIH-2V,
10(off) Off-state output current a thru g 250 iJ.A
VIL = 0.8 V, VO(off) = MAX
Vee - MAX, VIH-2V,
VO(on) On-state output voltage a thru g 0.3 0.4 V
VIL = 0.8 V, 10(on) = 20 rnA
Any input
II Input current at maximum input voltage Vee = MAX, VI = 5.5 V 1 rnA
except BI/RBO
Any input
IIH High-level input current Vee = MAX, VI = 2.4 V 20 iJ.A
except BI/RBO
Any input
-0.8
IlL Low-level input current except BI/RBO Vee = MAX, VI = 0.4 V rnA
BI/RBO -2
lOS Short-circuit output cu rrent BI/RBO Vee = MAX -2 rnA
Vee - MAX, ISN54L' 32 43
lee Supply current rnA
See Note 2 ISN74L' 32 52

t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at Vee = 5 V, TA = 25°C.
NOTE 2: ICC is measured with all outputs open and all inputs at 4.5 v.
switching characteristics, Vee = 5 V, T A = 25° C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
toff Turn-off time from A input 200
ns
ton Turn·on time from A input CL=15pF, RL = 280 n, 200

toff Turn-off time from RBI input See Note 3 200

ns
ton Turn-on time from RBI input 200

NOTE 3: Load circuit and voltage waveforms are shown on page 3-10; toft corresponds to tpLH and ton corresponds to tpHL'

1076

TEXAS INCORPORATED
INSTRUMENTS 7-29
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54LS47, SN74LS47
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
REVISED OCTOBER 1976

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) ...... . 7V
Input voltage . . . . . . . . . . . . . . . 7V
Peak output current (tw <; 1 ms, duty cycle <; 10%) 200mA
Current forced into any output in the off state . . . . 1 mA
Operating free-air temperature range: SN54LS4 7 -55°C to 125°C
SN74LS47 . O°C to 70°C
Storage temperature range -65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54LS47 SN74LS47
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
Off-state output voltage, VO(off) a thru g 15 15 V
On-state output current, 10(on) a thru g 12 24 mA
High-level output current, 10H BI/RBO -50 -50 p.A
Low-level output current, 10L BI/RBO 1.6 3.2 mA
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS47 SN74LS47
PARAMETER TEST eONDITIONSt
MIN TVP:\: MAX MIN TV!>:\: MAX UNIT
High-level input voltage 2 V
VIL Low-level input voltage 0.7 0.8 V
VIK Input clamp VOltage Vee= MIN, II =-18mA -1.5 -1.5 V

VOH High-level output voltage BI/RBO 2.4 4.2 2.4 4.2 V

Vee = MIN, \IOL = 1.6 mA 0.25 0.4 0.25 0.4

VOL Low-Ieveloutputvoltage BI/RBO VIH = 2 V, 1------+-------+--------1 V
VIL = VIL max IIOL = 3.2 mA 0.35 0.5

•
Vee = MAX, VIH = 2 V,
10(off) Off-state output current a thru 9 250 250 p.A
VIL = VIL max, VO(off) = 15 V

Va (on) On-state output voltage a thru 9

Vee- MAX '
VIH = 2 V,
l
10(on) = 12 mA 0.25 0.4
1------+-------+--------1
0.25 0.4
V
VIL = VIL max 110(on) = 24 mA I 0.35 0.5
, I, Input current at maxim m inout voltage V f'f' = MAX V = 7V 0 1 I 01 mA
High-level input current Vee = MAX, VI = 2.7 V 20 I 20 p.A
Any input
-0.4 -0.4
Low-level input current except BI/RBO Vee = MAX, VI = 0.4 V mA
BI/RBO -1.2 -1.2
Short-circuit
lOS BI/RBO Vee = MAX -0.3 -2 -0.3 -2 mA
output current
lee Supply current Vee = MAX, See Note 2 13 13 rnA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:\: All typical values are at V CC = 5 V, T A = 25° C.
NOTE 2: ICC is measured with all outputs open and all inputs at 4.5 v.

switching characteristics, Vee = 5 V, TA = 25°e

PARAMETER TEST eONDITIONS MIN TVP MAX UNIT
toff Turn-off time from A input 100
ns
ton Turn-on time from A input eL=15pF, RL=665n, 100
toft Turn-off time from RBI input See Note 4 100
ns
ton Turn-on time from RBI input 100

NOTE 4: Load circuit and voltage waveforms are shown on page 3-11; toft corresponds to tpLH and ton corresponds to tpHL'

107

7-30 TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN5448, SN7448
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) 7V
Input voltage . . . . . . . .... . 5.5 V
Operating free-air temperature range: SN5448 -55°C to 125°C
SN7448 oOe to 70°C
Storage temperature range -65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN5448 SN7448
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
a thru g -400 -400
High-!eve! output current, tOH j.i.,A
BI/RBO -200 -200
a thru g 6.4 6.4
Low-level output current, 10L rnA
R!/RRO 8 8
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST eONDITIONSt MIN TYP+ MAX UNIT
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
VIK Input clamp voltage Vee = MIN, 11=-12mA -1.5 V
a thru g Vee = MIN, VIH=2V, 2.4 4.2
VOH High-level output voltage V
BI/RBO VIL = 0.8 V, 10H = MAX 2.4 3.7

10 Output current a thru g

Vee = MIN, Vo = 0.85 V,
-1.3 -2 rnA
I
Input conditions as for VOH

•
Vee = MIN, VIH=2V,
VOL Low-level output voltage 0.27 0.4 V
VIL=0.8V, 10L = MAX
Any input
II Input current at maximum input voltage Vee = MAX, VI = 5.5 V 1 rnA
except BI/RBO
Any input
IIH High-level input current Vee = MAX, VI = 2.4 V 40 Il A
except BI/RBO
Any input
-1.6
IlL Low-level input current except BI/RBO Vee = MAX, VI = 0.4 V mA
BI/RBO -4
lOS Short-circuit output current BI/RBO Vee = MAX -4 rnA

Supply current
Vee - MIN, LSN5448 53 76
rnA
ICC
See Note 2 I SN7448 53 90

t For conditions shown as MI N or MAX, use the appropriate value specified under recommended operatrng conditions.
+AII typical values are at Vee = 5 V, T A = 25°e.
NOTE 2: lee is measured with all outputs open and all inputs at 4.5 V"

switching characteristics, Vee = 5 V, T A = 25° C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPHL Propagation delay time, high-to-Iow-Ievel output from A input 100
ns
tPLH Propagation delay time, low-to-high-Ievel output from A"input eL=15pF, RL = 1 kn, 100
tPHL Propagation delay time, high-to-Iow-Ievel output from RBI input See Note 5 100
ns
tpLH Propagation delay time, low-to-high-Ievel output from RBI input 100

NOTE 5: Load circuit and voltage waveforms are shown on page 3-10.

1076

TEXASINCORPORATED
INSTRUMENTS 7-31
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54lS48, SN74lS48
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
REVISED OCTOBER 1976

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ..... . 7V
Input voltage . . . . . . . . . . . . . . ... , 7V
Operating free·air temperature range: SN54LS48 -55°C to 125°C
SN74LS48 . oOe to 70°C
Storage temperature range -65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54LS48 SN74LS48
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
a thru 9 -100 -100
High-level output current, 10H IlA
BI/RBO -50 -50
a thru 9 2 6
Low-level output current, 10L mA
BI/RBO 1.6 3.2
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristiCS over recommended operatmg free-air temperature range (unless otherwise noted)
SN54LS48 SN74LS48
PARAMETER TEST CONDITIONSt UNIT
MIN TYP+ MAX MIN TYP+ MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
VIK Input clamp voltage Vee= MIN, 11=-18mA -1.5 -1.5 V
a thru g and Vee= MIN, VIH=2V,
VOH High-level output voltage 2.4 4.2 2.4 4.2 V
BI/RBO VIL = VIL max, 10H = MAX
Vee = MIN, Vo = 0.85 V,
10 Output current a thru 9 -1.3 -2 -1.3 -2 rnA
Input conditions as for VOH
Vee= MIN, 0.25 0.25
10L = 2mA 0.4 0.4
a thru 9 VIH=2V, V
10L = 6 mA 0.35 0.5
VIL = VIL max
VOL Low-level output voltage

•
Vec- MIN,
10L = 1.6 mA 0.25 0.4 0.25 0.4
BI/RBO VIH = 2 V, V
10L = 3.2mA 0.35 0.5
VIL = VIL max
Input current at Any input
II Vee = MAX, VI = 7 V 0.1 0.1 mA
maximum input voltage except BI/BRO

High-ieve; input current ' Any input '''~ ~ ~'A Y!

ilH except BI/RBO Yl,;C •• ",
VI=2.7V 20 20 i jlA

Any input
-0.4 -0.4
IlL Low-level input current except BI/RBO Vee= MAX, VI = 0.4 V mA
BI/RBO -1.2 -1.2
Short-circuit
lOS BI/RBO Vee= MAX -0.3 -2 -0.3 -2 mA
output current
lee Supply current Vee= MAX, See Note 2 25 38 25 38 rnA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at V CC = 5 V. T A 25° C.
NOTE 2: ICC is measured with all outputs open and all inputs at 4.5 V.

switching characteristics, Vee = 5 V, T A = 25° C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tpHL Propagation delay time, high-to-Iow-Ievel output from A input eL=15pF, RL = 4 kn, 100
ns
tPLH Propagation delay time, low-to-high-Ievel output from A input See Note 6 100
tpHL Propagation delay time, high-to-Iow-Ievel output from RBI input eL-15pF, RL-6kn, 100
ns
tpLH Propagation delay time, low-to-high-Ievel output from RBI input See Note 6 100

NOTE 6: Load circuit and voltage waveforms are shown on page 3-11.

1071

7-32 TEXAS I!,;COHPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • D,4.LLAS. TEXAS 75222
 TYPE SN5449
BCD-TO-SEVEN-SEGMENT DECODER/DRIVER

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, Vcc (see Note 1) 7V

Input voltage . . . . . . . . 5.5 V
Current forced into any output in the off state 1 mA
Operating free-air temperature range -55°C to 125°C
Storage temperature range -65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN5449
UNIT
MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 V
High-level output voltage, VOH 5.5 V
Low-level output current, IOL 10 mA
Operating free-air temperature, T A -55 125 °e
------- --------

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN5449
PARAMETER TEST CONDITIONSt UNIT
MIN TYP:j: MAX
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.6 V
VIK Input clamp voltage Vee - MIN, 11--10mA -1.5 V
Vee- MIN, VIH - 2 V,
IOH High-level output current 250 p.A
VIL=0.8V, VOH = 5.5 V
Vee= MIN, VIH=2V,
I VOL Low-level output voltage 0.27 0.4 V
ViL = 0.8 V, !OL = 10 mA 1 I

II Input current at maximum input voltage Vee = MAX, VI = 5.5 V 1 mA

IIH High-level input current Vee - MAX, VI - 2.4 V 40 p.A

•
IlL Low-level input current Vee - MAX, VI-O.4V -1.6 mA
lee Supply current Vee = MAX, See Note 2 33 47 mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
fAil typical values are at V CC = 5 V, T A = 25° C.
NOTE 2: ICC is measured with all outputs open and all inputs at 4.5 V.

switching characteristics, Vee = 5 V, T A = 25°e

PARAMETER TEST eONDITIONS MIN TYP MAX UNIT
tPHL Propagation delay time, high-to-Iow-Ievel output from A input 100
ns
tpLH Propagation delay time, low-to-high-Ievel output from A input eL=15pF, RL=667n, 100
tPHL Propagation delay time, high-to-Iow-Ievel output from RBI input See Note 5 100
ns
tPLH Propagation delay time, low-to-high-Ievel output from RBI input 100

NOTE 5: Load circuit and voltage waveforms are shown on page 3-10.

1076

TEXAS INSTRUMENTS
I~CORPORATED
7-33
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54LS49, SN74LS49
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
REVISED OCTOBER 1976

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
SUl?ply voltage, V cc (see Note 1) . . . . . 7V
Input voltage . . . . . . . . . . . . . . . 7V
Curr.!'lnt forced into any output in the off state . . . . 1mA
Operating free-air temperature range: SN54LS49 -55°C to 125°C
SN74LS49 . O°C to 70°C
Storage temperature range _65° C to 150° C
NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54LS49 SN74LS49
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output voltage, VOH 5.5 5.5 V
Low-level output current, IOL 4 8 rnA
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
,
SN54LS49 SN74LS49
PARAMETER TEST CONDITIONSt
MIN TYP:!: MAX MIN TYP:!: MAX UNIT
High-level input voltage 2 2 V
Low-level input voltage 0.7 0.8 V
Input clamp voltage Vee = MIN, 11= -18mA -1.5 -1.5 V
Vee = MIN,
IOH High-level output current 250 250 IJ.A
VIL = VIL max, VOH = 5.5 V
Vee = MIN, IIOL = 4 rnA 0.25 0.4 0.25 0.4
Low-level output voltage VIH = 2 V, If------+--------+---------l V
VIL = VIL max IOL = 8 rnA 0.35 0.5
Input current at maximum input voltage Vee = MAX, VI = 7 V 0.1 0.1 rnA
High-level input current Vee = MAX, VI = 2.7 V 20
Low-level input current Vee = MAX, VI = 0.4 V -0.4 -0.4 rnA

•
ICC Supply current Vec = MAX, See Note 2 8 15 8 15 rnA
tFor conditions shown as M IN or MAX, use the appropriate value specified under recommended operating conditions.
:j: All typical values are at V CC = 5 V, T A = 25° C.
NOTE 2: ICC is meastJred with all outputs open and all inputs at 4.5 V.

switching characteristics, Vee = 5 V T A = 25° C

1

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

tpHL Propagation delay time, high-to-Iow-Ievel output from A input CL = 15pF, RL=2kn, 100
ns
tpLH Propagation delay time,low-to-high-level output from A input See Note 6 100
tpHL Propagation delay time, high-to-Iow-Ievel output from RBI input CL = 15 pF" RL=6kn, 100
ns
tPLH Propagation delay time, low-to-high-Ievel output from RBI input See Note 6 100

NOTE 6: Load circuit and voltage waveforms are shown on page 3-11.

1076

7-34 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TTL TYPES SN5475. SN5477. SN54L75. SN54Ln. SN54LS75. SN54LS77.
SN7475. SN74L75. SN74L77. -SN74LS75
MSI 4-BIT BISTABLE LATCHES
BULLETIN NO. DL-S 7611851, MARCH 1974-REVISED OCTOBER 1976

SN5475, SN54LS75 ••• J OR W PACKAGE

logic
SN54L75. _ . J PACKAGE
SN7475, SN74L75, SN74LS75 •.. J OR N PACKAGE
FUNCTION TABLE
(TOP VIEW)
(Each Latch)
ENABLE
INPUTS OUTPUTS 10 20 20 1·2 GNO 30 30 40
D G a a
L H L H
H H H L
X L 00 00
H = high level, L = low level, X = irrelevant
00 = the level of 0 before the high-to-Iow transition of G G

Q Q
description

These latches are ideally suited for use as temporary

storage for binary information beiween processing I ~I~Hz~H~~
~I
vee
units and input/output or indicator units. Informa-
tion present at a data (0) input is transferred to the Q
I 10 10 20 ENABLE
3-4

logic: see function table

output when the enable (G) is high and the Q output
will follow the data input as long as the enable SN54ii, SN54LS77 ... W PACKAGE
remains high. When the enable goes low, the informa- SN54L77, SN74L77 ... T PACKAGE
tion (that was present at the data input at the time ENABLE
the transition occurred) is retained at the Q output 10 20 1-2 GND NC 30 40

~
until the enable is permitted to go high.

The '75, 'L75, and 'LS75 feature complementary Q

and Q outputs from a 4-bit latch, and are available in
various 16-pin packages. For higher component I

•
density applications, the '77, 'L77, and 'LS77 4-bit
latches are available in 14-pin flat packages.

These circuits are completely compatible with all

popular TTL or DTL families. All inputs are diode-
clamped to minimize transmission-line effects and
simplify system design. Series 54, 54L, and 54LS
devices are characterized for operation over the full 1D 2D 4D NC
ENABLE Vcc 3D
military temperature range of -55°C to 125°C; 3·4
Series 74, 74L, and 74LS devices are characterized
logic: see function table
for operation from O°C to 70°C.
NC-No internal connection

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, VCC (see Note 1) 7V

Input voltage: '75, 'L75, '77, 'L77 5.5 V
'LS75, 'LS77 7V
Interemitter voltage (see Note 2) 5.5 V
Operating free-air temperature range: SN54', SN54L', SN54LS' Circuits -55°C to 125°C
SN74', SN74L', SN74LS' Circuits O°C to 70°C
Storage temperature range -65°C to 150°C

NOTES: 1. Voltage values, except interemitter voltage, are with respect to network ground terminal.
2. This is the voltage between two emitters of a multiple-emitter input transistor and is not applicable to the 'LS75 and 'LS77.

076

TEXAS INSTRUMENTS 7-35

INCORPORATED
POST OFFICE BOX 5012 • DAL.LAS. TEXAS 75222
 TYPES SN5475, SN5477, SN54L75, SN54Ln, SN54LS75, SN54LS77,
SN7475, SN74L75, SN74Ln, SN74LS75 .
4-BI1 BISTABLE LATCHES·
REVISED OCTOBER 1976

functional block diagrams (each latch)

'75,77, 'L75, 'L77

Q
<L
('75 and 'L75)

ENABLE DATA

;~~; ENABLE
: ~;~~ ~Q ENABLE
schematics of inputs and outputs
75,'77 'L75, 'L77 'LS75, 'LS77

EQUIVALENT OF EACH INPUT EQUIVALENT OF EACH INPUT EQUIVALENT OF EACH INPUT

V C C - - - -.....- -
VCC------~----- VCC-------~-------
Req

INPUT --I~_"'-"'"
INPUT INPUT

• ~_______
Data: Peq =2
En_a_b_le_:_R_eq_=

75,77
___
kn NOM
1_kn N_O_M______~1 1~
___
Data: Peq =4 kn NOM
______E_n_ab_l_e:___Re_q_=_2_k_n___N_O_M______~
'L75, 'L77
Data: Req = 17 kn
~__________E_n_ab_le_:_R_e_q_=_4_.2_k_~_l________

'LS75, 'LS77
TYPICAL OF ALL OUTPUTS TYPICAL OF ALL OUTPUTS TYPICAL OF ALL OUTPUTS

-----------.------.VCC
---4~----V CC ----4~----V CC 120n
__-----.... NOM

......._ ...._ _ OUTPUT

OUTPUT OUTPUT

107

7-36 TEXAS I,",CORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN5415, SN5411, SN1415
4-BIT BISTABLE LATCHES

recommended operating conditions

SN5475, SN5477 SN7475
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High·level output current, IOH -400 -400 J.LA
Low·level output current, IOL 16 16 mA
Width of enabling pulse, tw 20 20 ns
Setup time, tsu 20 20 ns
Hold time, th 5 5 ns
Operating free·air temperature, T A -55 125 0 70 ~e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONSt I MIN TYp:j: MAX UNIT I I
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
VIK Input clamp voltage Vee; MIN, II; -12 mA -1.5 V
Vee; MIN VIH;2V.
VOH High-level output voltage 2.4 3.4 V
VIL; 0.8 V, 10H; -400J.LA
Vee; MIN, VIH; 2 V,
VOL Low-level output voltage 0.2 0.4 V
VIL; 0.8 V, 10L; 16mA
II Input current at maximum input voltage Vee; MAX, VI; 5.5 V 1 mA
D input 80
IIH High-level input current Vee; MAX, VI;2.4V J.LA
G input 160
o input -3.2
IlL Low-level input current Vee; MAX, VI;O.4V mA
G input -6.4
SN54' -20 -57
lOS Short-circuit output current§ Vee; MAX mA
SN74' -18 -57
Vee; MAX, SN54' 32 46

•
lee Supply current mA
See Note 3 SN74' 32 53

t For conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at VCC; 5 V, TA; 25°C.
§ Not more than one output should be shorted at a time.
NOTE 3: ICC is tested with all inputs grounded and all outputs open.

switching characteristics, Vee = 5 V, TA = 25°e

FROM TO
PARAMETERO TEST CONDITIONS MIN TYP MAX UNIT
(INPUT) (OUTPUT)
tPLH 16 30
0 Q ns
tpHL 14 25
tPLH~ 24 40
D Q eL;15pF, ns
tpHL ~ 7 15
RL;400.l1,
tPLH 16 30
G Q See Figure 1 ns
tpHL 7 15
tPLH~ 16 30
G Q ns
tPHL ~ 7 15

°tPLH == propagation delay time, low·to·high-Ievel output

tpH L == propagation delay time, high·to-Iow-Ievel output
~ These parameters are not applicable for the SN5477.

1076

TEXAS '-"CORPORATED
INSTRUMENTS 7-37
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54L75, SN54Ln, SN74L75, SN74Ln
4-BIT BISTABLE LATCHES

recommended operating conditions

SN54L75, SN54L77 SN74L75, SN74L77
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -200 -200 /JA
Low-level output current, 10L 8 8 mA
Width of enabling pulse, tw 100 100 ns
Setup time, tsu 40 40 ns
Hold time, th 10 10 ns
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONSt MIN TYP+ MAX UNIT
VIH High-Ievel.input voltage 2 V
VIL Low-level input voltage 0.8 V
VIK Input clamp voltage Vce= MIN, 11=-12mA ,1.5 V
Vee = MIN, VIH = 2V,
VOH High-level output voltage 2.4 3.4 V
VIL = 0.8 V, 10H = -200/JA
Vee= MIN, VIH=2V,
VOL Low-level output voltage 0.2 0.4 V
VIL = 0_8 V, 10L = 8mA
II Input current at maximum input voltage Vee= MAX, VI = 5.5 V 1 mA
o input 40
IIH High-level input current Vee= MAX, VI = 2.4 V /JA
G input 80
o input -1.6
IlL Low-level input current Vee= MAX, VI = 0.4 V mA
G input -3.2
SN54L' -10 -29
lOS Short-circuit output current§ Vee = MAX mA
SN74L' -9 -29

• Vee = MAX, SN54L' 16 23

lee Supply current mA
See Note 3 SN74L' 16 27

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at VCC = 5 V, T A = 25°C.
§Nor more than one output should be shorted at a time.
NOTE 3: iCC is tested with aii inputs grounded and aii outputs open.

switching characteristics, Vee = 5 V, T A = 25° C

FROM TO
PARAMETERO TEST CONDITIONS MIN TYP MAX UNIT
II NPUT) (OUTPUT)
tPLH
0 Q I 32 60 I
ns
I
I
tpHL 28 50 1
tpLHlI - 48 80
0 Q eL = 15 pF, ns
tpHL 11 14 30
RL=800n,
tPLH 32 60
G Q See Figure 1 ns
tPHL 14 30

tPLHlI - 32 60
G Q
ns
tPHL 11 14 30

0tPLH == propagation delay time, low-to-high-Ievel output

tpHL == propagation delay time, high-to-Iow-Ievel output
11 These parameters are not applicable for the SN54L77 and SN74L77.

1071

7-38 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54LS75, SN54LS77, SN74LS75
4-BIT BISTABLE LATCHES

recommended operating conditions

SN54LS75
SN74LS75
SN54LS77 UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -400 -400 /JA
Low-level output current, 10L 4 8 mA
Width of enabling pulse, tw 20 20 ns
Setup time, tsu 20 20 ns
Hold time, th 0 0 ns
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS75
SN74LS75
PARAMETER TEST CONDITIONSt SN54LS77
MIN TYP+ MAX MIN TYP+ MAX
VII·j Hi~h-Ievel input volta~e 2 2
I V;~ Low-level input voltage
VIK input ciamp voitage Vee = iviiN, il = -18mA -1.5 -1.5 V
Vee= MIN, VIH = 2 V,
VOH High-level output voltage 2.5 3.5 2.7 3.5 V
VIL = VIL max, 10H = -400p.A
Vee= MIN, VIH = 2 V, 10L = 4 mA 0.25 0.4 0.25 0.4
VOL Low-level output voltage V
VIL = VIL max 10L = 8mA 0.35 0.5
Input cu rrent at D input 0.1 0.1
II Vee= MAX, VI = 7 V mA
maximum input voltage G input 0.4 0.4
D input 20 20
IIH High-level input current Vee = MAX, VI=2.7V /J A
G input 80 80
I D input -0.4 I -0.4
IIIL Low-level input current I Vee= MAX, VI=O.4V mA
G input -1.6 -1.6
i lOS Short-circuit output currentS Vee = MAX -20 -100 -20 -100 mA

•
'LS75 6.3 12 6.3 12
Ice Supply current Vee = MAX, See Note 2 mA
'LS77 6.9 13

t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at V CC = 5 V, T A = 25°C.
§ Not more than one output should be shorted at a time, and du ration of the short-circuit should not exceed one second
NOTE 2: ICC is tested with all inputs grounded and all outputs open.

switching characteristics, Vee = 5 V, TA = 25°e

FROM TO 'LS75 'LS77
PARAMETERO TEST CONDITIONS UNIT
(INPUT) (OUTPUT) MIN TYP MAX MIN TYP MAX
tPLH 15 27 11 19
D Q ns
tPHL 9 17 9 17
tPLH - 12 20
D Q eL = 15 pF, ns
tpHL 7 15
RL = 2 kil,
tPLH 15 27 10 18
G Q See Figure 1 ns
tpHL 14 25 10 18
tpLH - 16 30
G Q ns
tPHL 7 15

°tPLH == propagation delay time, low-to-high-Ievel output

tpH L == propagation delay time, high·to-Iow-Ievel output

1076

TEXAS INCORPORATED
INSTRUMENTS 7-39
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN6476. SN6477, SN64L76, SN64L77, SN54LS76, SN54LS77,
SN7476, SN74L76, SN74L77, SN74LS75
4-BIT BISTABLE LATCHES
PARAMETER MEASUREMENT INFORMATION
switching characteristics
OUTPUTS
~
a a
1
PULSE
GENERATOR
(See Note A)
0 a - ~
RL RL
..... ..... .....
(See Note C)
;fC:=15 PF
4~G
-=
~
(See Note B)

Q ..
~ .
r
... ...
r
aoL

T
PULSE
GENERATOR B
(See Note A)
- - CL = 15 pF

IS"",,,.B'
~ -- -:.:
TEST CIRCUIT

1jlS

3V

o INPUT
I
~ OV
I~ tsu ---.I
GINPUT
-- -- -l- - -- - r~=","""--"';~I
I I
.----.-~~---
I
-- - ---- 3V

•
(See
Note OJ I

OUTPUT a
~-------------------'
JI-: tpLH
r VOH

VOL

OUTPUT(j /Vref
~ ________________- J

VOLTAGE WAVEFORMS

NOTES: A. The pulse generators have the following characteristics: Zout"'" 50 n; for pulse generator A, PRR .;; 500 kHz; for pulse
generator B, PRR .;; 1 MHz. Positions of D and G input pulses are varied with respect to each other to verify setup times.
B. CL includes probe and jig capacitance.
C. All diodes are 1 N3064.
D. When measuring propagation delay times from the D input, the corresponding G input must be held high.
E. For '75, '77, 'L75, and 'L77, Vref = 1.5 V; for 'LS75 and 'LS77, Vref = 1.3 V.
tComplementary 0: outputs are on the '75. 'L75, and 'LS75 only.

FIGURE 1

1076

7-40 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TTL TYPES SN5480, SN7480
MSI GATED FULL ADDERS
BULLETIN NO. DL-S 7211809, DECEMBER 1972

logic SN5480 ••• J PACKAGE

SN7480 ••• J OR N PACKAGE SN5480 ••• W PACKAGE
(TOP VIEW) (TOP VIEW)
FUNCTION TABLE
(See Notes 1,2, and 3)
INPUTS OUTPUTS
Cn B A C n +1 ~ ~

L L L H H L
L L H H L H
L H L H L H
L H H L H L
H L L H L H
H L H L H L
H H L L H L
IH H HI L L HI
positive logic: see function table
H = high level, L = low level

NOTES: 1. A=AC+A*+A1·A2,B=BC+B*+B1·B2.
2. When A* is used as an input, A1 or A2 must be low. When B* is used as an input, B1 or B2 must be low.
3. When A 1 and A2 or B1 and B2 are used as inputs, A* or B*, respectively, must be open or used to perform dot-AN D logic.

description
These single-bit, high-speed, binary full adders with gated complementary inputs, complementary sum (~ and ~)
outputs and inverted carry output are designed for medium- and high-speed, multiple-bit, parallel~add/serial-carry
applications. These circuits (see schematic) utilize diode-transistor logic (DTL) for the gated inputs, and high-speed,
high-fan-out transistor-transistor logic (TTL) for the sum and carry outputs and are entirely compatible with both DTL
and TTL logic families. The implementation of a single-inversion, high-speed, Darlington-connected serial-carry circuit
minimizes the necessity for extensive "look-ahead" and carry-cascading circuits.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, VCC (see Note 4)

Input voltage (see Note 5)
Operating free-air temperature range: SN5480 Circuit~

Storage temperature range

SN7480 Circuits
7V
5.5V
-55°C to 125°C
G
. . 0° to 70 C
-65°C to 150°C
•
NOTES: 4. Voltage values are with respect to network ground terminal.
5. Input signals must be zero or positive with respect to network ground terminal.

recommended operating conditions

SN5480 SN7480
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, V CC 4.5 5 5.5 4.75 5 5.25 V
~or~ -400 -400
High-level output current, IOH Cn +1 -200 -200 itA
A* or B* -120 -120
~ or~ 16 16
Low-level output current, IOL Cn+1 8 8 rnA
A* or B* 4.8 4.8
Operating free-air temperature, T A -55 125 0 70 °c

1076

TEXAS INSTRUMENTS 7-41

INCORPORATED
POST OFFICE BOX 5012 • DAL.LAS. TEXAS 75222
 TYPES SN5480, SN7480
GATED FULL ADDERS

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN5480 SN7480
PARAMETER TEST CONDITIONSt UNIT
MIN TYP:j: MAX MIN TYP:j: MAX
VIH High-level input voltage 2 2 V
Vil low-level input voltage 0.8 0.8 V
~ or ~ VCC - MAX, 10H; -400 p.A
High-level
VOH Cn+l VIH;2V, 10H; -200 p.A 2.4 3.5 2.4 3.5 V
output voltage
A* or B* Vll;0.8V 10H; -120 p.A
~ or ~ Vcc; MAX, 10l; 16 mA
low-level
VOL C n +l VIH; 2 V, 10l; 8 mA 0.22 0.4 0.22 0.4 V
output voltage
A* or B* Vll; 0.8 V 10l; 4.8mA
II Input current at maximum input voltage Vee - MAX, VI - 5.5 V 1 1 mA
Al, A2, Bl, B2,
15 15
High-level Ae, or Be
IIH Vce; MAX, VI; 2.4 V p.A
input current A* or B* -1.1 -1.1
Cn 200 200
Al, A2, Bl, B2,
-1.6 -1.6
low-level Ae, or BC
III VCC; MAX, VI; 0.4 V mA
input current A* or B* -2.6 -2.6
Cn -8 -8
~ or ~ -20 -57 -18 -57
Short-circuit
lOS Cn +l Vee; MAX -20 -70 -18 -70 mA
output-current §
A* or B* -0.9 -2.9 -0.9 -2.9
ICC Supply current Vee; MAX, See Note 6 21 31 21 35 mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
+AII typical values are at VCC; 5 V, T A; 25°C.
§ Not more than one output should be shorted at a time.
NOTE 6: ICC is measured with all inputs and outputs open.

switching characteristics, Vee = 5 V, TA = 25°e

• ,
PARAMETERlI

tplH
tpHl
tpLH
tpHl
tPlH
tpHl
FROM
INPUT

en

Be

AC
-
TO
OUTPUT

Cn+l

e n +l

~
TEST CONDITIONS

Cl; 15 pF,
See Note 7

el;15pF,
Rl; 780

Rl; 400
n,

n,
MIN TYP

13
8
18
38
52
62
MAX

17
12
25
55
70
80
UNIT

ns

ns
tplH See Note 7 38 55
BC "f
tpHl 56 75
tplH 48 65
tpHl
Al A*
I Cl=15pF, See Note 7
17 25
ns
tPlH 48 65
Bl B*
tpHl 17 25

11 tpLH ;; propagation delay time, low-to-high-Ievel output

tpH L ;; propagation delay time, high-to-Iow-Ievel output
NOTE 7: The load for testing outputs A* and B* consists only of capacitance CL to ground. The load circuit for the other outputs and
voltage waveforms are shown on page 3-10.

1272

7-42 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN5480, SN7480
GATED FULL ADDERS

functional block diagram

(DUAL-IN-L1NE) [FLAT PACKAGE)
(8)(12)
A1
(9}[13)
A2
(10) [141
A*
(11)[1) r -_ _{_6_}[_10_1_ f
AC
(5)[9)
>----~

(12}[21
B1
(13)[3)
B2
(1) [5)
B*
(2)[6]
BC

(3)[7)
en (4)[8]
JO-.....- - - ' - - - - Cn+1

schematic
(3) [7]
~
~~lk
n

e _
Vee (14) [4]
_
_ _
1 130

W1 ~
A1 (8)[12] I 'V'
~~ ~ I I 1

A2 (9)[13] I0Il (4)[8] _

~-_-------en+1

•
(10)[14]
A*

(11)[1]
Ae -'---'-'---14--'

4k

B1 (12)[2]

B2 (13)[3]

B* (1)[5]

Be (2)[6]

(7)[11]
GND------~

9- .. Vee bus

Resistor values shown are nominal and in ohms.

1272

TEXAS)NSTRUMENTS
INCORPORATED
7-43
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TTL TYPES SN5481A. SN5484A. SN1481A. SN1484A
MSI 16-81T RANDOM-ACCESS MEMORIES
BULLETIN NO. DL-S 7211581, DECEMBER 1972

description

Each of these 16-bit active-element memories is a

high-speed, monolithic, transistor-transistor-Iogic SN5481A •• , J OR W PACKAGE
(TTL) array of 16 flip-flops and two write amplifiers SN7481A .,. J OR N PACKAGE
(TOP VIEW)
interconnected to form a scratch-pad memory with
ADDRESS WRITE WRITE ADDRESS
direct-address and nondestructive read-out. These X4 1 GND 0 Y4
devices are interchangeable with and replace SN5481,
SN7481, SN5484, and SN7484, but feature
diode-clamped inputs, improved switching speeds,
and lower supply current requirements.

The flip-flops are arranged in a four-by-four matrix

with each flip-flop representing one bit of 16 words.
Four X·address lines and four Y-address lines permit
the address of one bit at a time. Each flip·flop,
composed of two cross-coupled three-emitter tran-
sistors, is used to store one bit. To determine if a
logic 1 or logic 0 has been stored, it is necessary to ~vcc~
know which one of the two flip-flop transistors is ADDRESS ADDRESS
conducting. One emitter of each of these transistors
serves as the sensing output. All 16 of the logic 1 logic: See logic diagram
sensing outputs are connected to the sense 1 (S1)
amplifier input and all 16 of the logic 0 sensing
outputs are connected to the sense 0 (SO) amplifier
input. The two remaining emitters of each transistor SN5484A ••• J OR W PACKAGE
are used to complete the matrix connections neces- SN7484A ••• J OR N PACKAGE
sary for the X- and V-address lines. Address line (TOP VIEW)
inputs are normally held low and currents from all WRITE SENSE WRITE ADDRESS
conducting flip-flop transistors flow out of these ~~GND~Y4

•
address lines .

To address a flip-flop both the X- and V-address lines

associated with that flip-flop are taken to a high level.
Due to the matrix nature of the circuit, at least one
address iine of aii fiip-fiops except the one being
addressed will continue to remain at a low level and
no change will occur in those flip-flops. But, in the
addressed flip-flop, the current in the conducting
transistor diverts from the address lines to the
appropriate sense line and then to one of the sense ~Vcc y,~

amplifiers. Thus, either the sense 1 amplifier or the ADDRESS ADDRESS

sense 0 amplifier is activated. When this occurs, the
output of the activated sense amplifier drops from a logic: See logic diagram
high logic level to a low logic level. The memory is
nondestructive as the states of the flip-flops are not
disturbed during sensing. The memory is volatile and
information will be lost if the supply voltage is
removed.

To store new information in a flip-flop, it is necessary to address it and apply a high-level voltage to the appropriate
write amplifier. (The SN5484A and SN7484A have gated write-amplifier inputs). The output of the write amplifier
responds by dropping to a low logic level. Since all Sense 0 lines are connected to the output of the write 0 amplifier
and all sense 1 lines are connected to the output of the write 1 amplifier, a low level at the output of a write amplifier

076

7-44 TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 • CALLAS. TEXAS 75222
 TYPES SN5481A, SN5484A, SN7481A, SN7484A
16-81T RANDOM-ACCESS MEMORIES

description (continued)

will cause the emitters of all flip-flop transistors connected to that amplifier to go low. In all the flip·flops except the
one being addressed, this low voltage has no effect since at least one other emitter on each of the flip-flop transistors is
held low by the address lines. Two possibilities exist with the flip·flop that is addressed. The flip·flop may already be in
the desired state, in which case no change occurs. If the flip-flop must be changed from one state to the other, the low
voltage applied to the emitter of the transistor which is not conducting turns that transistor on causing the other
transistor to turn off.

Since' the connection between the output of the write amplifier and the sense line is common to the input of the sense
amplifier, the memory cannot be used to provide information on the state of a bit while the write amplifiers are
activated.

A number of active-element memories may be paralleled to form the desired matrix size (number of words) and to form
the desired word length (number of bits). All inputs and outputs are compatible with most DTL and TTL circuits.
Average power dissipation is typically 225 milliwatts, and the open-collector outputs may be wire·AND connected to
similar outputs. Internal circuitry of the write and sense amplifiers are operated within their linear range to improve
speed. Sensing propagation delay tirnes are typically 12 Ili:mu~t:!(;uf1(js when operated at fuii fan-out and 30 picofarads of
circuit capacitance. The SN5481 A and SN5484A circuits are designed for operation over the full military temperature
range of -55°C to 125°C; the SN7481A circuits are designed for operation from O°C to 70°C.

logic diagram

•
Y1 Y2 Y3 Y4

1272

TEXAS INSTRUMENTS
Il'oICORPORATED
7-45
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN5481A, SN5484A, SN7481A, SN7484A
16-81T RANDOM-ACCESS MEMORIES

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, Vcc (see Note 1) 7V

Input voltage . . . . . . . 5.5 V
Interemitter voltage (see Note 2) 5.5 V
High·level output voltage . . . 5.5 V
Operating free·air temperature range: SN5481A, SN5484A Circuits -55°C to 125°C
SN7481A, SN7484A Circuits O°C to 70°C
Storage temperature range -65°C to 150°C

NOTES: 1. Voltage values, except interemitter voltage, are with respect to network ground terminal.
2. This is the voltage between two emitters of a multiple·emitter transistor. For this circuit, this rating applies to any X input in
conjunction with any Y input.

recommended operating conditions

SN5481A, SN5484A SN7481A, SN7484A
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output voltage, VOH 5.5 5.5 V
Low-level output current, IOL 20 40 rnA
Width of write pulse, tw(write) (see Figure 1) 20 20 ns
Address input setup time, tsu (see Figure 1) 0 0 ns
Operating free-air temperature, T A -55 125 0 70 e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN5481A, SN5484A SN7481A,SN7484A
PARAMETER TEST CONDITIONSt UNIT
MIN TYP:j: MAX MIN TYP:j: MAX

VIH High-level voltage at any input 2 2 V

I

•
Low-level voltage to prevent writing 0.8 0.8
VIL V
at address inputs I to prevent sensing 1 1

VIL Low-level voltage at write inputs 0.8 1 V

VIK I nput clamp voltage Vee = MIN, 11= -12 rnA -1.5 -1.5 V

IOH High-level output current Vee = MIN, VOH = 5.5 V 250 250 IJA
VOL Low-!evel output voltage Vee = MIN, IOL = MAX 0.4 0.4 V
I nput current at Write 1 ' i
II Vee = MAX,VI = 5.5 V rnA
maximum input voltage Address 3 3
Write Vee = MAX,VI = 2.4 V 40 40
IIH High-level input current IJA
Address Vee = MAX,VI = 4.5 V 400 400
Write -1.6 -1.6
IlL Low-level input current Vee MAX, VI = 0.4 V rnA
Address -11 -11
Vee = MAX,AII inputs at 0 V 70 65
ICC Supply current rnA
Vee = 5 V, All inputs at 0 V 45 60 45 60

t For conditions shown as MIN or M AX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at VCC = 5 V, T A = 25°C.

7-46 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN5481A. SN5484A. SN7481A. SN7484A
16-81T RANDOM-ACCESS MEMORIES

switching characteristics, Vee = 5 V, IOL = MAxt, TA = 25°e, see figure 1

LOCATION SN5481A. SN5484A SN7481A. SN7484A
PARAMETER§ TEST CONDITIONS UNIT
ADDRESSED MIN TYP MAX MIN TYP MAX
CL = 30 pF 13 13
tSR X1-Y1 ns
CL = 200 pF 18 30 18 30
CL = 30 pF 11 19 12 20
tpHL
CL = 200 pF 17 26 18 27
X1-Y1 ns
CL = 30 pF 13 20 12 19
tPLH
CL = 200 pF 27 40 18 27
CL = 30 pF 10 18 11 19
tPHL
CL = 200pF 16 25 17 26
X1 thru X4 and Y1 ns
CL = 30 pF 13 20 13 20
tPLH
CL = 200pF 27 40 19 28

TFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device
type.
§tSR == Sense recovery time after writing
tpH L == Propagation delay time, high-to-Iow-Ievel output
tpLH == Propagation delay time, low-to-high-Ievel output

schematic
r-------~~~~-------l
11 OF 161

---'wv
rlI
m
ADDRE:.-----_t
~7k 7k~

OTHER CELLS
L ________ ___________
}
TOALL
OTHER CELLS

~
•
r - - - - - - - - - - - WRiTEANDSENse AMPURERS - - - - - - - - - - - - ,
I 110F21

I
I r--.-------.-~~v~
I
I
I So OTS 1
I
I
I
I
I ~
IL _____________________________ ~

tWO(B) and W1 (B) inputs (indicated with dashed lines) are applicable for the SN5484A, SN7484A only.

W... Vee bus

Resistor values shown are nominal and in ohms.

1272

TEXAS INSTRUMENTS 7-47

INCORPORATED
POST'OFFICE BOX 5012 • DALLAS, TeXAS 75222
 TYPES SN5481A, SN5484A, SN7481A, SN7484A
16-BIT RANDOM-ACCESS MEMORIES

PARAMETER MEASUREMENT INFORMATION

VCC=5V So°UTPUT

CIl
:2
a:
~
w Y4
~:3 Sor---~--------~----i
3:5
wZ X2
(!)o
<Cz
j<c
o
>
w
w
CIl r - LOAD c;- RCUlT2 - -,
(SeeNoteC) (Same as load circuit 1)
L _________ JI

TEST CIRCUIT

t4--100ns~

~ I ~<;;10ns ~: ~<;;10ns
ADDRESS ! 1t,90% 9O%~ i / "' 3V
INPUT ~ 1.5V 1.5V -{10% "' OV

tsu~ ~
<;;10 ns~ : i4- ~ 14-<;;10 n,
Wo INPUT
10% i ~~% 9Cn~tl:------------------------------3V
~'.' v~ OV

~20n'~ <;;10n' ......... ~ ~I *-<;;10n,

I I I
: } .790% 9O%"T----------3V
WllNPUT
I 10%:¥fl.5V 1.5V~10% ov
~ ~tSR (See Note D) ~20 n'~

So OUTPUT

~------------l--------- ::~
•
\ </-'\:.5 V ~ ~tsR (See NoteD)

r
I
VOH
'\. ,'-,1
S10UTPUT '\. ,/ 't~.5 V
SENSE-RECOVERY TIME VOLTAGE WAVEFORMS "--...;..--...;..---~ ---VOL

f"!!-- l OOo, :.-\

<;;10n'~ I ~ ~ I ~<;;10ns
ADDRESS ! K.~% ~~~~ ~5V 1,5~-------3V
INPUT ~1.~ v'\j.;l0% . I vl', OV
--.;
<;;10 ns~
~tsu
~
~I 1_ I 1

w.
1 --. ,....-<;;10 ns I I
90%~i-------------T---------J--------3V
WRITE
INPUT i 190%
(Woo rW l' ----"I I
10% 1.5 V
:~
*-20ns~
1,5 V 10% I
I
I4-tPHL~
I
:
~tPLH~
OV

OUTPUT
(SoorS l) \_-,_/_-"_\-"---_/ XI 5V
:
1.5r=VOL
VOH

PROPAGATION DELAY TIME VOLTAGE WAVEFORMS

NOTES: A. The pulse generators have the following characteristics: for the address pulse generator, PRR = 2 MHz; for the Wo and W l pulse
ge .. erators, PRR = 1 MHz,
B. C L includes probe and jig capacitance.
C. For the SN5484A and SN7484A, unused Wo and Wl inputs are at 3.5 V.
D. tSR "" sense-recovery time
E. FortheSN5481A and SN5484A: Rl = 240 nand R2 = 560 n. For theSN7481A and SN7484A: R1 = 120 nand R2 = 330 n.
FIGURE l-SWITCHING CHARACTERISTICS

1076

7-48 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TTL TYPES SN5482, SN7482
MSI 2-BIT BINARY FULL ADDERS
BULLETIN NO. DL-S 7211836, DECEMBER 1972

SN5482 ••• J OR W PACKAGE

For applications in: SN7482 ••• J OR N PACKAGE
(TOP VIEW)
• Digital Computer Systems
A2 B2 2:2 GND C2 NC NC
• Data-Handling Systems
• Control Systems
logic 2:2

A2
FUNCTION TABLE
INPUTS OUTPUTS
2:1
WHEN co= L WHEN co= H
A1 B1 A2 B2 l:1 l:2 C2 l:1 l:2 C2
L L L L L L L H L L
H L L L H L L L H L
L H L L H L L L H L
H H L L L H L H H L
L L u L L u L H H L
I H L H L I H H L ILL H I positive logic: see function table
L H H L H H L L L H
H H H L L L H H L H NC-No internal connection
L L L H L H L H H L
H L L H H H L L L H
L H L H H H L L L H
H H L H L L H H L H functional block diagram
L L H H L L H H L H
H L H H H L H L H H CO~~----~-1~
L H H H H L H L H H
I
IH H H H IL H H IH H H I A1~~---+-_-+--r'""\
H = high level, L = low level l:1

description

These full adders perform the addition of two 2-bit

II
binary numbers. The sum (2:) outputs are provided
for each bit and the resultant carry (C2) is obtained
from the second bit. Designed for medium-to-high-
speed, mUltiple-bit, parallel-add/serial-carry applica-
tions, these circuits utilize high-speed, high-fan-out
transistor-transistor logic (TTL) and are compatible
with both DTL and TTL logic families. The imple-
mentation of' a single-inversion, high-speed,
Darlington-connected serial-carry circuit within each
bit minimizes the necessity for extensive "Iook-
ahead" and carry~cascading circuits.

1076

TEXAS INSTRUMENTS 7-49

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN5482, SN7482
2-BIT BINARY FULL ADDERS

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1) 7V
Input voltage (see Note 2) 5.5 V
Operating free-air temperature range: SN5482 Circuits -55°C to 125°C
SN7482 Circuits O°C to 70°C
Storage temperature range -65°C to 150°C
NOTES: 1. Voltage values are with respect to network ground terminal.
2. Input signals must be zero or positive with respect to network ground terminal.

recommended operating conditions

SN5482 SN7482
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
:E1 or:E2 -400 -400
High-level output current, 10H IlA
e2 -200 -200
:E1 or:E2 16 16
Low-level output current, 10L mA
e2 8 8
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN5482 SN7482
PARAMETER TEST eONDITIONSt UNIT
MIN TYP+ MAX MIN TYP+ MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
:E1 or:E2 I Vee = MIN, 10H = -4001lA
High-level
VOH VIH = 2 V, 2.4 3.4 2.4 3.4 V
output voltage
e2 VIL = 0.4 V 10H = -2001lA

:E1 or:E2 Vee= MIN, 10L = 16mA

Low-level
VOL
output voltage
VIH = 2 V, 0.2 0.4 0.2 0.4 I V

•
e2 VIL=O.4V 10L = 8mA
II Input current at maximum input voltage Vee= MAX, VI = 5.5 V 1 1 mA
High-level A1, Bl, or eo 160 160
IIH Vee= MAX, VI=2.4V Il A
input current A2 or B2 40 40
Low-level A1, B1, or eo -6.4 -6.4
IlL Vee= MAX, VI = 0.4 V mA
input current ,A2 or B2 -1.6 -1.6
Short-circuit :E1 or:E2 -20 -55 -18 -55
lOS Vee= MAX mA
output current§ e2 -20 -70 -18 -70
lee Supply current Vee = MAX, See Note 3 35 50 35 58 mA

t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
+AII typical values are at Vee =5 V, T A = 25°C.
§ Not more than one output should be shorted at a time.
NOTE 3: ICC is measured with outputs open, 81 and 82 grounded, and 4.5 V applied to A1, A2, and CO.

1272

7-50 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN5482, SN7482
2-BI1 BINARY FULL ADDERS

switching characteristics, Vee = 5 V, TA = 25°e (see note 4)

FROM TO
PARAMETER~ TEST CONDITIONS MIN TYP MAX UNIT
(INPUT) (OUTPUT)
tpLH 34
CO E1 ns
tpHL 40
tPLH 40
82 E2 CL=15pF, RL = 400 n. ns
tpHL 35
tpLH 38
CO E2 ns
tpHL 42
tpLH 12 19
CO C2 CL=15pF, RL = 780 n. ns
tpHL 17 27

~ tp LH== propagation delay time, low-to-high-Ievel output

tpH L == propagation delay time, high-to-Iow-Ievel output
NOTE 4: Load circuit and voltage waveforms are shown on page 3-10_

schematics of inputs and outputs

EQUIVALENT OF ALL INPUTS C2 OUTPUT

Vee--------~------- ------------~--Vee

100 n. NOM

INPUT

OUTPUT

1
A1, 81, co: Req
A2, 82: Req
=1
=4
kn. NOM
kn. NOM

E1 AND E2 OUTPUTS
•
----~------ Vee

",---OUTPUT

1272

TEXAS INCORPORATED
INSTRUMENTS 7-51
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
•

7-52
 TTL TYPES SN5483A, SN54LS83A, SN7483A, SN74LS83A
MSI 4-BI1 BINARY FULL ADDERS WITH FAST CARRY
BULLETIN NO. DL-S 7611853, MARCH 1974-REVISED OCTOBER 1976

SN5483A, SN54LS83A ••• J OR W PACKAGE

• Full-Carry Look-Ahead across the Four Bits
SN7483A, SN74LS83A ••• J OR N PACKAGE
• Systems Achieve Partial Look-Ahead (TOP VIEW)
Performance with the Economy of
~4 ~1
Ripple Carry B4 e4 eo GND B1 A1

• SN54283/SN74283 and SN54LS283/SN74LS283

Are Recommended For New Designs as They
Feature Supply Voltage and Ground on Corner
Pins to Simplify Board Layout
TYPICAL ADD TIMES
TYPICAL POWER
TWO TWO
TYPE DISSIPATION PER
8-BIT 16-BIT
4-BITADDER
WORDS WORDS
'83A 23 ns 43 ns 310mW A4 r3 A3 83 Vee !2 82 A2
, LS83A 25 ns 45 ns 95 mltv

description positive logic: see function table

These improved fuB add~rs perform the addition of
two 4-bit binary numbers. The sum (L) outputs are FUNCTION TABLE
provided for each bit and the resultant carry (e4) is
obtained from the fourth bit. These adders feature
full internal look ahead across all four bits generating
the carry term in ten nanoseconds typically. This
provides the system designer with partial look-ahead
performance at the economy and reduced package
count of a ripple-carry implementation.

The adder logic, including the carry, is implemented

in its true form meaning that the end-around carry
can be accomplished without the need for logic or
level inversion.

Designed for medium-speed applications, the circuits

utilize transistor-transistor logic that is compatible
II
with most other TTL families and other saturated
low-level logic families.

Series 54 and 54LS circuits are characterized for

H = high level, L = low level
operation over the full military temperature range of
NOTE: Input conditions at A1, B1, A2, B2, and CO are used to
-55°C to 125°C, and Series 74 and 74LS circuits are determine outputs 2:1 and 2:2 and the value of the internal
characterized for operation from oOe to 70°C. carry C2. The values at C2, A3, B3, A4, and B4 are then
used to determine outputs 2:3, 2:4, and C4.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, Vee (see Note 1) 7V

Input voltage: '83A 5.5V
'LS83A 7V
Interemitter voltage (see Note 2) 5.5 V
Operating free-air temperature range: SN5483A, SN54LS83A -55°C to 125°C
SN7483A,SN74LS83A oOe to 70°C
Storage temperature range -65°C to 150°C
NOTES: 1. Voltage values, except interemitter VOltage, are with respect to network ground terminal.
2. This is the voltage between two emitters of a multiple-emitter transistor. This rating applies for the '83A only between the
following pairs: A 1 and B 1, A2 and B2, A3 and B3, A4 and B4.

1076

TEXAS INSTRUMENTS 7-53

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN5483A. SN54LS83A. SN7483A. SN74LS83A
4-BIT BINARY FULL ADDERS WITH FAST CARRY
REVISED OCTOBER 1976

functional block diagram

~_ _ _ _ _ _(~14--:..) C4

B4 (16)

(1)
A4
)-_---.:(_15..:..) ~4

B3 .....:.(4......:.)_----..--;r-----
P---~~~++--~,

A3 .....:.(......:.3)_ _ ~L..-/ (2)

~3

(7)
B2

(8) (6)
A2

I Bl
(11 )

(9)
(10) ~1
Al
(13)
CO !>o
schematics of inputs and outputs
'S3A 'S3A 'LSS3A 'LS83A
EQUIVALENT OF TYPICAL OF ALL EQUIVALENT OF TYPICAL OF
EACH INPUT OUTPUTS EACH INPUT ALL OUTPUTS

-----.. . .--VCC VCC---- 120 n NOM

VCC

VCC3-- Req
INPUT_...._ _ _ ~

INPUT --
OUTPUT OUTPUT

CO input: Req = 4 k!1 NOM C4 output: R = 100!1 NOM CO input: Req = 17 k!1 NOM
Any A or B: Req = 3.5 k!1 NOM Anyr::R=120nNOM Any A or B: Req = 8.5 kfi NOM

1076

7·54 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN5483A, SN7483A
4-BIT BINARY FULL ADDERS WITH FAST CARRY

recommended operating conditions

SN5483A SN7483A
UNIT
MIN NOM MAX MIN NOM MAX
Supply Voltage, VCC 4.5 5 5.5 4.75 5 5.25 V
Any output except C4 -800 -800
High-level output current, 10H p.A
Output C4 -400 -400
Any output except C4 16 16
Low-level output current, 10L rnA
Output C4 8 8
Operating free-air temperature, T A -55 125 0 70 °c

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN5483A SN7483A
PARAMETER TEST CONDITIONSt UNIT
MIN TYP:j: MAX MIN TYp:j: MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
V 11< Input clamp voltage VCC= MIN, II = -12mA -1.5 -1.5 V

I VOH High-level output voltage

\I
VCC = MIN,
I ·,L -
nA\I
...... '""
VIH = 2 V,

·un IlJiAY
''; ... '"
I 2.4 3.4 I 2.4 3.4 I I
V

VCC= MIN, VIH =2V,

VOL Low-level output voltage 0.2 0.4 0.2 0.4 V
VIL = 0.8 V, 10L = MAX
Input current at maximum
II VCC = MAX, VI = 5.5V 1 1 mA
input voltage
IIH High-level input current VCC = MAX, VI = 2.4 V 40 40 p.A
IlL Low-level input current VCC = MAX, VI = 0.4 V -1.6 -1.6 mA
Short-circuit I Any output except C4 -20 -55 -18 -55
mA
lOS VCC = MAX
output current§ I Output C4 -20 -70 -18 -70
Aii B iow, other I
II VCC = MAX, inputs at 4.5 V I 56
I 56
ICC Supply current
IOutputs open All jnputs at
mA

1
•
66 99 66 110
4.5V

t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at VCC = 5 V, T A = 25°C.
§ Only one output should be shorted at a time.

switching characteristics, Vee = 5 V, TA = 25°e

PARAMETERlI FROM (INPUT) TO (OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT
tPLH 14 21
CO Any 2: ns
tpHL CL=15pF, RL =400 n, 12 21
tpLH See Note 3 16 24
Ai or Bi 2:i ns
tpHL 16 24

tPLH 9 14
CO C4 ns
tPHL CL=15pF, RL=780n, 11 16
tpLH See Note 3 9 14
AiorBj C4 ns
tpHL 11 16

11 tpLH == Propagation delay time, low-to·high·level output

tpH L == Propagation delay time, high-to·low·level output
NOTE 3: Load circuit and voltage waveforms are shown on page 3-10.

1076

TEXAS INCORPORATED
INSTRUMENTS 7-55
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54LS83A, SN74LS83A
4-BIT BINARY FULL ADDERS WITH FAST CARRY
REVISED OCTOBER 1976

recommended operating conditions

SN54LS83A SN74LS83A
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -400 -400 !J.A
Low-level output current, 10L 4 S mA
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS83A SN74LS83A
PARAMETER TEST CONDITIONSt UNIT
MIN TYP:j: MAX MIN TYP:j: MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 O.S V
VIK Input clamp voltage Vec= MIN, 11=-lSmA -1.5 -1.5 V
Vee- MIN, VIH - 2V, VIL - VIL max,
VOH High-level output voltage 2.5 3.4 2.7 3.4 V
10H = -400!J. A
Vee- MIN, VIH-2V, 10L -4mA 0.25 0.4 0.25 0.4
VOL Low-level output voltage V
VIL = VIL max 10L = SmA 0.35 0.5
Input current 0.2
Any A or B 0.2
II at maximum Vee = MAX, VI = 7V mA
eo 0.1 0.1
input voltage
High-level Any A or B 40 40
IIH Vee = MAX, VI=2.7V !J. A
input current eo 20 20
Low-level Any A or B -0.8 -0.8
IlL Vee= MAX, VI = 0.4 V mA
input current eo -0.4 -0.4
lOS Short-circuit output current§ Vee= MAX -20 -100 -20 -100 mA
All inputs
22 39 22 39
grounded
Vee= MAX, All B low, other

•
lee Supply current 19 34 19 34 mA
Outputs open inputs at4.5 V
All inputs at
19 34 19 34
4.5V

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAli typical values are at V CC = 5 V, T A = 25° C.
~ Only one output should be shorted at a time, and duration of the short-cirCuit should not exceed one second.

switching characteristics, Vee = 5 V, TA = 25 0

C
PARAMETER~ FROM (INPUT) TO (OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT
tpLH 16 24
eo Any:E ns
tpHL 15 24
15 24
tpLH
AiorBi :l:i ns I
tpHL eL=15pF, RL = 2 kn, 15 24
tPLH See Note 4 11 17
eo C4 ns
tpHL 1.5 22
tPLH 11 17
Ai orBi C4 ns
tpHL 12 17

~tpLH == Propagation delay time, low-to-high-Ievel output

tpH L == Propagation delay time, high-to-Iow-Ievel output
Note 4: Load circuit and voltage waveforms are shown on page 3-11.

1076

7·56 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • OALLAS. TEXAS 75222
 TYPES SN5485, SN54L85, SN54LS85, SN54S85,
TTL SN7485, SN74L85, SN74LS85, SN74S85
MSI 4-81T MAGNITUDE COMPARATORS
BULLETIN NO. DL-S 7611810, MARCH 1974-REVISED OCTOBER 1976

SN5485, SN54LS85, SN54S85 ••• J OR W PACKAGE SN54L85 .•• J PACKAGE

SN7485, SN74LS85, SN74S85 ••• J OR N PACKAGE SN74L85 ••• J OR N PACKAGE
(TOP VIEW) (TOP VIEW)

DATA INPUTS INPUTS OUTPUTS INPUTS

A

vCC~~~
TYPICAL TYPICAL
POWER DELAY
TYPE
DISSI· (4·BIT
PATION WORDS)
'85 275mW 23 ns
'L85 20mW 90 ns
'LS85 52mW 24 ns
'585 365mW 11 ns
D.frA,A<B A;B A> B"A> B A:B A<B,GND
INPUT CASCADE INPUTS OUTPUTS

positive logic: see function tables positive logic: see function tables

description

These four-bit magnitude comparators perform comparison of straight binary and straight BCD (8-4-2-1) codes. Three
fully decoded decisions about two 4-bit words (A, B) are made and are externally available at three outputs. These
devices are fully expandable to any number of bits without external gates. Words of greater length may be compared by
connecting comparators in cascade. The A> B, A < B, and A = B outputs of a stage handling less-significant bits are
connected to the corresponding A> B, A < B, and A = B inputs of the next stage handling more-significant bits. The
stage handling the least-significant bits must have a high-level voltage applied to the A = B input and in addition for the
'L85, low-level voltages applied to the A> B and A < B inputs. The cascading paths of the '85, 'LS85, and 'S85 are
impiemented with only a two-gate-Ievel delay to reduce overall comparison times for long words. An alternate method
of cascading which further reduces the comparison time is shown in the typical application data.

•
FUNCTION TABLES
COMPARING CASCADING
OUTPUTS
INPUTS INPUTS
A3,B3 A2, B2 Al.Bl AO.BO A>B A<B A=B A>B A<B A=B
A3 > B3 X X X X X X H L L
A3< B3 x X X X X X L H L
A3= B3 A2 > B2 x X x x X H L L
A3= B3 A2 < B2 X X X X X L H L
A3= 82 A2= 82 A1 >81 x x x X H L L
A3= 83 A2= 82 A1 < 81 X X X X L H L
A3= 83 A2= 82 A1 = 81 AD> 80 X X X H L L
A3= 83 A2= 82 A1 = 81 AO< 80 x X X L H L
A3= 83 A2 = 82 A1 = 81 AO= 80 H L L H L L
A3= 83 A2= 82 A1 = 81 AO= 80 L H L L H L
A3= 83 A2= 82 A1 = 81 AO= 80 L L H L L H

'85, 'LS85, 'S85

X X H H
H H L
H H

'L85
A3= 83 A2= 82 A1 = 81 AO= 80 L H H L H H
A3= 83 A2= 82 A1 = 81 AO= 80 H L H H L H
A3 = 83 A2= 82 A1 = 81 AO= 80 H H H H H H
A3= 83 A2= 82 A1 = 81 AO= 80 H H L H H L
A3= 83 A2= 82 A1 = 81 AO= 80 L L L L L L
H = high level. L = low level. X = irrelevant

1076

TEXAS INSTRUMENTS 7-57

INCORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN5485, SN54L85, SN54LS85, SN54S85,
SN7485, SN74L85, SN74LS85, SN74S85
4-81T MAGNITUDE COMPARATORS
functional block diagrams

. ~,

•
o •• ; ; (,r-';;
i'L
t ~, I

"''''
<Co>

374

7-58 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN5485, SN54L85, SN54LS85, SN54S85,
SN7485, SN74L85, SN74LS85, SN74S85
4-81T MAGNITUDE COMPARATORS
schematics of inputs and outputs
~----------------~
EQUIVALENT OF EACH EQUIVALENT OF EACH EQUIVALENT OF EACH EQUIVALENT OF EACH
INPUT FOR '85 INPUT FOR 'L85 INPUT FOR 'LS85 INPUT FOR 'S85

VCC---~---
VCC------.----- v CC - - - - 1 . . - - - - v CC----1..----

INPUT--~~-e---.-
INPUT INPUT INPUT

A= B, Any A or B: Any A or B: I A B, Any A or B:

=
Req = 1.67 k.l1 NOM
A> B,A < B:
II
Req = 4 k.l1 N'l.~.
A=B,A>B,A<B:
Req = 40 k.l1 NOM
II
Rea = 16.7 k.l1 NOM
II Ran = 933.11 NOM
A>S:A<B:
Req = 2.8 k.l1 NOM
~----------------~I~I----------------_I~I------------------~II,--------------____~

TYPICAL OF ALL OUTPUTS TYPICAL OF ALL OUTPUTS TYPICAL OF ALL OUTPUTS

FOR '85, 'L85 FOR'LS85 FOR'S85

---------~----VCC -----.----VCC
--'~--VCC 120.11

' - - -.....--OUTPUT OUTPUT

OUTPUT

'85: Req = 100.11 NOM

'L85: Req = 500.11 NOM

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
SN54' SN74'
SN54L' SN54LS' SN74L' SN74LS' UNIT
SN54S' SN74S'
Supply voltage, Vee (see Note 1) 7 8 7 7 8 7 V
Input voltage (see Note 2) 5.5 5.5 7 5.5 5.5 7 V
Interemitter voltage (see Note 3) 5.5 5.5 V
Operating free-air temperature range -55 to 125 o to 70 °c
Storage temperature range -65 to 150 -65 to 150 °c

NOTES: 1. Voltage values, exceptinteremitter voltage, are with respect to network ground terminal.
2. Input voltages for 'L85 must be zero or positive with respect to network ground terminal.
3. This is the voltage between two emitters of a multiple-emitter input transistor. This rating applies to each A input in conjunction
with its respective B input of the '85 and 'SS5.

1076

TEXAS INCORPORATED
INSTRUMENTS 7-59
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN5485, SN7485
4-BIT MAGNITUDE COMPARATORS

recommended operating conditions

SN5485 SN7485
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, IOH -400 -400 !J.A
Low-level output current, IOL 16 16 mA
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST eONDITIONSt MIN TYP:j: MAX UNIT
VIH High-level input voltage 2 V
. VIL Low-level input voltage 0.8 V
VIK I nput clamp voltage Vee = MIN, 11=-12mA -1.5 V
Vee = MIN, VIH = 2 V,
VOH High-level output voltage 2.4 3.4 V
VIL = 0.8 V, IOH = - 4OO !J.A
Vee = MIN, VIH=2V,
VOL Low-level output voltage 0.2 0.4 V
VIL = 0.8 V, IOL = 16 mA
II Input current at maximum input voltage Vee = MAX, VI = 5.5 V 1 mA
A < B, A > B inputs 40
IIH High-level input current Vee = MAX, VI = 2.4 V !J.A
all other inputs 120
A < B, A > B inputs -1.6
IlL Low-level input current Vee = MAX, VI = 0.4 V mA
all other inputs -4.8

Short·circuit output current§ Vee = MAX, Vo =0

I SN5485 -20 -55
mA
lOS
I SN7485 -18 -55
ICC Supply current Vee = MAX, See Note 4 55 88 mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at Vee = 5 V, T A = 25°C.
§Not more than one output should be shorted at a time.
NOTE 4: ICC is measured with outputs open, A = B grounded, and all other inputs at 4.5 V.

I switching characteristics, Vee = 5 V, TA = 25°e

FROM TO NUMBER OF
PARAMETER~ TEST CONDITIONS MIN TYP MAX UNIT!
INPUT OUTPUT GATE LEVELS
1 7
A < B, A>B 2 12
tpLH Any A or B data input ns
3 17 26
A=B 4 23 35
1 11
A < B, A>B 2 15
tPHL i Any A or B data input I 3 I
eL = 15 pF,
20 30
ns
I
RL = 400 st,
A=B 4 20 30
See Note 5
tPLH A < B or A = B A>B 1 7 11 ns
tPHL A < B or A = B A>B 1 11 17 ns
tpLH A=B A=B 2 13 20 ns
tpHL A=B A=B 2 11 17 ns
tpLH A> B or A = B A<B 1 7 11 ns
tpHL A> B or A = B A<B 1 11 17 ns

~ tpLH '" propagation delay time, low·to·high·level output

tpHL '" propagation delay time, high·to·low·level output.
NOTE 5: Load circuit and voltage waveforms are shown on page 3-10.

1076

7-60 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54L85, SN74L85
4-81T MAGNITUDE COMPARATORS

recommended operating conditions

SN54L85 SN74L85
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -100 -200 JlA
Low-level output current, 10L 2 3.6 mA
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONSt MIN TYP+ MAX UNIT
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.7 V
Vee = MIN, V I H ~ 2 V, it-S_N_·5_4_L_8_5_+-_2_.4_ _3_._3_ _--i
VOH High-level output voltage V
VIL = 0.7 V, 10H = MAX I SN74L85 2.4 3.2
Vee= MIN, V I H = 2 V, I;-S_N_54_L_85_+-_ _ _0_.1_5_ _0_.3--i
LC~Ai-!eve! output voltage
1 VOL IVIL=0.7V, 10L = MAX ISN74L85 0.2 0.41 v

input current at A < B, A > B, or A = B 100

II Vee = MAX, VI = 5.5 V JlA
maximum input voltage A or B inputs 300
A < B, A < B, or A =B 10
IIH High-level input current Vee = MAX, VI = 2.4 V JlA
A or B inputs 30
A < B, A> B, or A = B -0.18
IlL Low-level input current Vee= MAX, VI = 0.3 V mA
A or B inputs -0.54
lOS Short-circuit output current§ Vee= MAX -3 -15 mA

Supply current
I Condition A 4.0 7.7
mA
ICC Vee = MAX, See Note 6
1Condition B 3.2 7.2

tfor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
0
+AII typical values are at V CC = 5 V, T A = 25 C.
§ Not more than one output should be shorted at a time.
NOTE 6: With all outputs open, ICC is measured for Condition A with all inputs at 4.5 V, and for Condition B with all inputs grounded.

switching characteristics, Vee

FROM
= 5 V, TA = 25°e
TO
II
PARAMETER~ TEST CONDITIONS MIN TYP MAX UNIT
(INPUT) (OUTPUT)
tpLH 90 150
Any A or B Any ns
tpHL eL = 50 pF, RL = 4 kS1, 75 150
tpLH A> B, A < B, See Note 7 75 150
Any ns
tpHL orA = B 55 100

~ tpLH == propagation delay time, low-to·high-Ievel output

tpH L == propagation delay time, high·to-Iow-Ievel output
NOTE 7: Load circuit and voltage waveforms are shown on page 3-11.

374

TEXAS INCORPORATED
INSTRUMENTS 7-61
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54LS85, SN74LS85
4-81T MAGNITUDE COMPARATORS
REVISED OCTOBER 1976

recommended operating conditions

SN54LS85 SN74LS85
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -400 -400 /lA
Low-level output current, 10L 4 8 mA
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS85 SN74LS85
PARAMETER TEST eONDITIONSt UNIT
MIN TYP+ MAX MIN TYP+ MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
VIK I nput clamp voltage Vee: MIN, II: -18mA -1.5 -1.5 V
Vee: MIN, VIH: 2 V,
VOH High-level output voltage 2.5 3.4 2.7 3.4 V
VIL: VIL max, 10H: -400/lA
Vee: MIN,
Il0L :4mA 0.25 0.4 0.25 0.4
VOL Low-level output voltage VIH: 2V, :1 V
VIL: VIL max 10L: 8 mA 0.35 0.5

I nput current
A < B, A > B inputs 0.1 0.1
II at maximum Vee: MAX, VI: 7V mA
all other inputs 0.3 0.3
input voltage
High·level A < B, A > B inputs 20 20
IIH Vee: MAX, VI :2.7V /lA
input current all other inputs 60 60
Low-level A < B, A > B inputs -0.4 -0.4
IlL Vee: MAX, VI: 0.4 V rnA
input current all other inputs -1.2 -1.2
lOS Short-circuit output current§ Vee: MAX -20 -100 -20 -100 mA
lee Supply current Vee: MAX, See Note 4 10.4 20 10.4 20 mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at V CC : 5 V, T A : 25°C.

I
§ Not more than One output should be shorted at a time, and duration of the short·circuit should not exceed one second.
NOTE 4: ICC is measured with outputs open, A : B grounded, and all other inputs at 4.5 V.

switching characteristics, Vee = 5 V, T A = 25° C

i i
FROM i
TO NUMBER Of : :
PARAMETER~ TEST CONDITIONS MIN TYP MAX UNIT
INPUT OUTPUT GATE LEVELS
1 14
A < B, A > B 2 19
tPLH Any A or B data input ns
3 24 36
A:B 4 27 45
I I 1 I 11
A < B, A> B 2 15
tpHL Any A or B data input CL:15pF, ns
3 20 30
RL: 2 kn,
A:B 4 23 45
See Note 7
tPLH A<BorA:B A>B 1 14 22 ns
tpHL A < B or A - B A>B 1 11 17 ns
tPLH A:B A:B 2 13 20 ns
tPHL A-B A-B 2 13 26 ns
tpLH A>BorA:B A<B 1 14 22 ns
tpHL A> B or A: B A<B 1 11 17 ns

,; tpLH == propagation delay time, low-to-high-Ievel output

tpH L == propagation delay time, high-to-Iow-Ievel output
NOTE 7: Load circuit and voltage waveforms are shown on page 3-11.

1076

7-62 TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54S85, SN74S85
4-81T MAGNITUDE COMPARATORS

recommended operating conditions

SN54S85 SN74S85
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -1 -1 mA
Low-level output current, 10L 20 20 mA
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONSt MIN TYp:j: MAX UNIT
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
VIK Input clamp voltage Vce- MIN, 11--18mA -1.2 V

High-ievei output voitage

Vee= MIN, V!H=2V, !SN54S85 2.5 3.4
V
VOH
VIL = 0.8 V, 10H = -1 mA 1SN74S85 2.7 3.4
Vee = MIN, VIH = 2V,
VOL Low-level output voltage 0.5 V
VIL - 0.8 V, iOL=20mA
II Input current at maximum input voltage Vee- MAX, VI- 5.5 V 1 mA
A < B, A > B inputs 50
IIH High-level input current Vee= MAX, VI=2.7V p.A
all other inputs 150
A < B, A > B inputs -2
IlL Low-level input current Vee = MAX, VI = 0.5 V mA
all other inputs -6
lOS Short-circuit output current§ Vee = MAX --40 -100 mA
Vee = MAX, See Note 4 73 115
ICC Supply current Vee = MAX, TA=125°e,
See Note 4
ISN54S85W 110
mA

TFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at V CC = 5 V, T A = 25° C.

•
§Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
NOTE 4: ICC is measured with outputs open, A = B grounded, and all other inputs at 4.5 V.

switching characteristics, Vee = 5 V, TA = 25°e

FROM TO NUMBER OF
PARAMETER~ TEST CONDITIONS MIN TYP MAX UNIT
INPUT OUTPUT GATE LEVELS
1 5
A < B, A > B 2 7.5
tpLH Any A or B data input ns
3 10.5 16
A=B 4 12 18
1 5.5
A < B, A> B 2 7
tpHL Any A or B data input eL=15pF, ns
3 11 16.5
RL = 280 n,
A=B 4 11 16.5
See Note 5
tPLH A < BorA = B A>B 1 5 7.5 ns
tpHL A < BorA - B A>B 1 5.5 8.5 ns
tPLH A=B A=B 2 7 10.5 ns
tpHL A-B A-B 2 5 7.5 ns
tpLH A> B or A - B A<B 1 5 7.5 ! ns
tpHL A> B or A - B A<B 1 5.5 8.5 ns

~ tp LH =: propagation delay time, low·to·h igh-Ievel output

tpHL =: propagation delay time, high·to·low·level output
NOTE 5: Load circuit and voltage waveforms are shown on page 3-10.

1076

TEXAS I!'<CORPORATED
INSTRUMENTS 7-63
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN5485, SN54L85, SN54LS85, SN54S85,
SN7485, SN74L85, SN74LS85, SN74S85
4-81T MAGNITUDE COMPARATORS

TYPICAL APPLICATION DATA

COMPARISON OF TWO N-BIT WORDS INPUTS

(MSB) B23 83
A23 A3
B22 B2
This application demonstrates how these magnitude A22 A2
B21 A<B
comparators can be cascaded to compare longer A21
Bl
Al A~B NC
words. The example illustrated shows the comparison H2O eo A>B
A20 AO
of two 24-bit words; however, the design is B19 A<B '85, 'L85,
A~ 'L585. '585
expandable to n-bits. As an example, one comparator A19 A>B
can be used with five of the 24-bit comparators
818 83
illustrated to expand the word length to 120-bits. A18 A3
817 B2
Typical comparison times for various word lengths A17 A2
using the '85, 'L85, 'LS85, or 'S85 are: 816 Bl A<B
A=B
A16 AI
B15 eo A>B
A15 AO
WORD NUMBER 814 A<B
'85 'L85 'LS85 'S85 A=B
'85, 'L85,
LENGTH OF PKGS A14 A>B
'LS85. '585

1-4 bits 23 ns 90 ns 24 ns 11 ns
B13 83 830
5-24 bits 2-6 46 ns 180 ns 48 ns 22 ns A13 A3 A3
25-120 bits 8-31 69 ns 270 ns 72 ns 33 ns B12 B2 B2
A2
A12 A2 OUTPUTS
Bl1 81 A<B Bl A<8
All Al A=8 AI A~
Bl0 eo A>8 SO- A>B
AID AO Ail
B9 A<B
'85, 'L85, '85, 'L85,
A=l'J
'L585, '585 'L585, '585
AS A>8

B8
AS
B7
A7
B6 A<B
A6 A=B
B5 A>B
AS
B4

•
A=B '85, 'L85,
'LS85, '585
A4 A>B

83 B3
A3 A3
B2 B2
A2 A2
Bl Bl A<B
Al A1 A=B
ILSB) eo eo A>B
AO AO
A<B
'85, 'L85
A=B
'L585, '585
A>B

COMPARISON OF TWO 24-BIT WORDS

374

7-64 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TTL TYPES SN5486, SN54L86, SN 54LS86, SN54S86,
MSI SN7486, SN74L86, SN74LS86, SN74S86
. QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
BULLETIN NO. DL-S 7611

••• J OR W PACKAG
schematics of inputs and outputs SN74', SN74LS', SN74S' .•• J OR N PACKAGE
'86 (TOP VIEW)
EQUIVALENT OF TYPICAL OF
EACH INPUT ALL OUTPUTS

Vee
Vee --~TI---

~ 4 k.l1 NOM

'N'UT-Cr OUTPUT

positive logic: Y = A <±:l B = AB + As

SN54L86 ••• J PACKAGE
SN74L86 ••• J OR NPACKAGE
'L86 (TOPVIEWI

EQUIVALENT OF TYPICAL OF VCC4B 4A 4Y 3Y 38 3A

EACH INPUT ALL OUTPUTS I ~

I I II [55J ldJ II

~
positive logic: Y = A <±:l B = AB + AB
SN54L86 ••• T PACKAGE (TOP VIEW)

'LS86
EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS

Vee--......- -
12.5 k.l1 NOM

I NPUT _.,..-+-----<l~ •
positive logic: Y = A (±) B = AB + As
FUNCTION TABLE

'S86 INPUTS OUTPUT

i-----
A B Y

0':"-
EQUIVALENT OF TYPICAL OF
EACH INPUT ALL OUTPUTS L L L
-----Vee L H H
H L H
2.8 k.l1 NOM H H L
Vee
H = high level, L = low level

INPUT -- OUTPUT TYPICAL AVERAGE TYPICAL

TYPE PROPAGATION TOTAL POWER
DELAY TIME DISSIPATION
'86 14 ns 150mW
'L86 55 ns 15mW
'LS86 10 ns 30.5 mW
'S86 7 ns 250 mW

1076

TEXAS INSTRUMENTS 7·65

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN5486, SN7486
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, Vee (see Note 1) .... . 7V

Input voltage . . . . . . . .... . 5.5 V
Operating free-air temperature range: SN5486 -55°C to 125°C
SN7486 O°C to 70°C
Storage temperature range -65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN5486 SN7486
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -SO~ -SO~ Il A
Low-level output current, 10L 16 16 rnA
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN5486 SN7486
PARAMETER TEST eONDITIONSt UNIT
MIN TYP+ MAX MIN TYP+ MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage O.S O.S V
VIK Input clamp voltage Vee = MIN, II =-SmA -1.5 -1.5 V
Vee= MIN, VIH=2V,
VOH High-level output voltage 2.4 3.4 2.4 3.4 V
VIL = O.S V, 10H = -SOOIlA
Vee- MIN, VIH = 2 V
VOL Low-level output voltage 0.2 0.4 0.2 0.4 V
VIL = O.S V, 10L = 16mA
II Input current at maximum input voltage Vee= MAX, VI = 5.5 V 1 1 mA
IIH High-level input current Vee - MAX, VI-2.4V 40 40 Il A

• IlL Low-level input current Vee = MAX, VI=O.4V -1.6 -1.6 rnA
lOS Short-circuit output currentS Vee = MAX -20 -55 -lS -55 mA
lee Supply current Vee = MAX, See Note 2 30 43 30 50 mA

t For co~ditions shown as MIN or MAX. use othe appropriate value specified under recommended operating conditions for the applicable type.
+AII typical values are at Vee = 5 V, T A = 25 C.
§ Not more than one output should be shorted at a time.
NOTE 2: ICC is measured with the inputs grounded and the outputs open.

switching characteristics, Vee = 5 V, TA = 25°e

FROM
PARAMETER~
I (INPUT)
TEST CONDITIONS MIN TYP MAX UNIT

tpLH 15 23
AorB Other input low eL=15pF, ns
tpHL 11 17
RL =400 n,
tPLH lS 30
Aor B Other input high See Note 3 ns
tpHL 13 22

~ tpLH "" propagation delay time, low·to-high·level output

tpH L== propagation delay time, high·to-Iow·level output
NOTE 3: Load circuit and voltage waveforms are shown on page 3-10.

1076

7-66 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DAL.LAS, TEXAS 75222
 TYPES SN54L86, SN74L86
QUADRUPLE 2~INPUT EXCLUSIVE-OR GATES

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, Vee (see Note 1) 7V

Input voltage (see Note 4) 5.5 V
Operating free-air temperature range: SN54L86 -55°C to 125°C
SN74L86 aOe to 7aoe
Storage temperature range -65°C to 15aoe

NOTES: 1. Voltage values are with respect to network ground terminal.

4. Input voltages must be zero or positive with respect to network ground terminal.

recommended operating conditions

SN54L86 SN74L86
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, IOH -100 -200 IlA
Low-level output current, 10L 2 3.6 mA
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54L86 SN74L86
PARAMETER TEST CONDITIONSt UNIT
MIN TYPt MAX MIN TYPt MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.7 V
Vee= MIN, VIH = 2 V,
VOH High-level output voltage 2.4 3.3 2.4 3.2 V
VIL = 0.7 V, 10H = MAX
Vee= MIN, VIH=2V,
VOL Low-level output voltage 0.15 0.3 0.2 0.4 V
VIL = 0.7 V, 10L = MAX
II Input current at maximum input voltage I Vee = MAX. V, = 5.5 V I 200 I 200 I IlA I

IIH High-level input current Vee = MAX, VI = 2.4 V 20 20 IlA

•
IlL Low-level input current Vee - MAX, VI- 0.3 V -0.36 -0.36 mA
lOS Short-circuit output current Vee = MAX -3 -15 ~3 -15 mA
leeH Supply current, all outputs high Vee = MAX, See Note 5 2.2 4.4 2.2 4.4 mA
leeL Supply current, all outputs low Vee - MAX, See Note 6 3.8 6.68 3.8 6.68 mA

t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at VCC = 5 V, T A = 25°C.
NOTES: 5. ICCH is measured with all outputs open, one input of each gate at 4.5 V, and the other inputs grounded.
6. ICCl is measured with all outputs open and all inputs at 4.5 V.

switching characteristics, Vee = 5 V, TA = 25°e

FROM
PARAMETER~ TEST CONDITIONS MIN TYP MAX UNIT
(INPUT)

tPLH 75 150
A or B Other input low eL=50pF, ns
tpHL 60 150
RL =4 kn,
tpLH 50 90
A orB Other input high See Note 7 ns
tpHL 35 60

~tplH == propagation delay time, low-to·high·level output

tpH l == propagation delay time, high-to·low-Ievel output
NOTE 7: load circuit and voltage waveforms are shown on page 3-11.

1076

TEXAS INCORPORATED
INSTRUMENTS 7·67
POST OFFICE B,?X 5012 • DALLAS. TEXAS 75222
 TYPES SN 54LS86. SN74LS86
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
REVISED OCTOBER 1976

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, Vee (see Note 1) 7V

Input voltage . . . . . . . 7V
Operating free-air temperature range: SN54LS86 -55°C to 125°C
SN74LS86 oOe to 70°C
Storage temperature range -65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54LS86 SN74LS86
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vec 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -400 -400 IlA
Low-level output current, 10L 4 B rnA
Operating free-air temperature, T A -55 125 0 70 °c

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54lS86 SN74lS86
PARAMETER TEST CONDITlONSt UNIT
MIN TYP+ MAX MIN TYP+ MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 O.B V
VIK Input clamp voltage VCC= MIN, II = -1BmA -1.5 -1.5 V
Vee= MIN, VIH=2V,
VOH High-level output voltage 2.5 3.4 2.7 3.4 V
VIL=VILmax,IOH=-4 00 IlA
Vce =MIN, 10L = 4mA 0.25 0.4 0.25 0.4
VOL Low-level output voltage VIH=2V, V
VIL = VIL mas 10l = BmA 0.35 0.5

•
II Input current at maximum input voltage Vec= MAX, VI =7 V 0.2 0.2 rnA
IIH High-level input current VCC=MAX, VI = 2.7 V 40 40 p.A
IlL low-level input current Vec = MAX, VI = 0.4 V -O.B -O.B rnA
lOS Short-circuit output currentS' Vec= MAX -6 -40 -5 -42 rnA
ICC Supply current VCC= MAX, See Note 2 6.1 10 6.1 10 rnA

tFor conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions for the appiicabie type.
+AII typical values are at V CC = 5 V, T A = 25° C.
§ Not more than one output should be shorted at a time.
NOTE 2: ICC is measured with the inputs grounded and the outputs open.

switching characteristics, Vee = 5 V, T A = 25° C

FROM
PARAMETER 11 TEST CONDITIONS IMIN TYP MAX UNIT I
(INPUT)
tpLH ;2 23
AorB Other input low el=15pF, ns
tpHL 10 17
RL = 2 kO,
tpLH 20 30
Aor B Other input high See Note 7 ns
tpHL 13 22

11 tpLH == propagation delay time, low-to-high-Ievel output

tpH L == propagation delay time, high-to-Iow-Ievel output
NOTE 7: Load circuit and voltage waveforms are shown on page 3-11.

107E

7-68 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BQX 5012 • DALLAS, TEXAS 75222
 TYPES SN54S86, SN74S86
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, Vee (see Note 1) 7V

Input voltage . . . . . . . 5.5 V
Operating free·air temperature range: SN54S86 -55°e to 125°e
SN74S86 oOe to 700e
Storage temperature range -65°e to 150°C
NOTE1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54S86 SN74S86
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -1 -1 mA
Low-level output current, 10L 20 20 mA
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54S86 SN74886
PARAMETER TEST CONDITlONSt UNIT
MIN TYP+ MAX MIN TYP+ MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage O.S O.S V
VIK Input clamp voltage Vee= MIN, 11=-1SmA -1.2 -1.2 V
Vee- MIN, VIH - 2 V,
VOH High-level output voltage 2.5 3.4 2.7 3.4 V
VIL = O.S V, IOH=-1mA
Vee- MIN, VIH - 2V
VOL Low-level output voltage 0.5 0.5 I V
I VIL=0.8V, 10L = 20 mA I I I

II Input current at maximum input voltage Vee= MAX, VI = 5.5 V 1 1 mA

High-level input current Vee = MAX, V,=2.7V 50 50 IJ.A

•
IIH
IlL Low-level input current Vee = MAX, VI = 0.5 V -2 -2 mA
lOS Short-circuit output current S Vee = MAX -40 -100 -40 -100 mA
ICC Supply current Vee = MAX, See Note 2 50 75 50 75 mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
:j:AII typical values are at V CC = 5 V, T A = 25° C.
§ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
NOTE 2: ICC is measured with the inputs grounded and the outputs open.

switching characteristics, Vee = 5 V, TA = 25°e

FROM
PARAMETER~ TEST CONDITIONS MIN TYP MAX UNIT
(INPUT)
tpLH 7 10.5
AorB Other input low eL=15pF, ns
tPHL 6.5 10
RL=2S0n,
tpLH 7 10.5
A orB Other input high See Note 3 ns
tpHL 6.5 10

~tpLH == propagation delay time, low-to-high-Ievel output

tpH L == propagation delay time, high-to-Iow-Ievel output
NOTE 3: Load circuit and voltage waveforms are shown on page 3-10.

1076

TEXAS INSTRUMENTS 7-69

INCORPORATED
POST OFFICE BC?X 5012 • DALLAS, TEXAS 75222
 TIL TYPES SN54H87, SN74H87
MSI 4-81T TRUE/COMPLEMENT, ZERO/ONE ELEMENTS
BULLETIN NO. DL-S 7211837, DECEMBER 1972

SN54H87 ...• JOR W PACKAGE

SN74H87 •.• J OR N PACKAGE
(TOP VIEW)
description
Operation of these monolithic 4-bit true/complement
elements is controlled by the Band C inputs. With
the B input low, the 4-bit binary input (A) is
transferred to the output (Y) in either complemen-
tary form (with C low) or true form (with C high).
When the B input is high, the output will be at the
complementary level of the C input regardless of the
levels of the data inputs.

These circuits are fully compatible for use with other

TTL or DTL circuits. Input clamping diodes are
A1 Y1 NC A2 Y2 GND
provided to minimize transmission line effects and
thereby simplify system design_ Each input represents
positive logic: see function table
only one normalized series 54H/74H load, and full
fan-out to 10 series 54H/74H loads is available from NC-No internal connection

each of the outputs in the low-level condition.

FUNCTION TABLE
Power dissipation is 270 mW typically with an CONTROL
OUTPUTS
average propagation delay of 14 ns from data inputs INPUTS
to output. B C V1 V2 V3 V4
L L A1 A2 A3 A4
The SN54H87 is characterized for operation over the L H A1 A2 A3 A4
full military temperature range of -55°C to 125°C, H L H H H H
and the SN74H87 is characterized for operation from H H L L L L
O°C to 70°C.

•
H = high level, L = low level
A 1, A2, A3, A4 = the level of the respective A input .

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) ........ . 7V
Input voltage . . . . . . . ........ . 5.5 V
Operating free-air temperature range: SN54H87 Circuits _55°C to 125°C
SN74H87 Circuits O°C to 70°C
Storage temperature range -65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54H87 SN74H87
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, IOH -1 -1 mA
Low-level output current, IOL 20 20 mA
Operating free-air temperature, T A -55 125 0 70 °e

1076

7-70 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN64H87, SN74H87
4-BIT TRUE/COMPLEMENT, ZERO/ONE ELEMENTS

electrical characteristics over recommended operating free-air temperature 1'ange (unless otherwise noted)
PARAMETER TEST CONDITIONSt MIN TYP+ MAX UNIT
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
VIK Input clamp voltage Vce= MIN, II =-8mA -1.5 V
Vee = MIN, VIH-2V,
VOH High-level output voltage 2.4 3.5 V
VIL = 0.8 V, IOH=-1 rnA
Vee= MIN, VIH=2V,
VOL Low-level output voltage 0.2 0.4 V
VIL=0.8V, 10L =20mA
II Input current at maximum input voltage Vce= MAX, VI,= 5.5V 1 rnA
IIH High-level input current Vee- MAX, VI- 2.4 V 50 IJA
IlL Low-level input current Vee= MAX, VI =0.4 V -2 rnA
lOS Short-circuit output current ~ Vee= MAX -40 -100 rnA

Supply current
Vee=MAX, I SN54H87 54 78
rnA
lee !I SN74H87
See Note 2 54

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
+AII tvoical values are at V r-r- = 5 V. T,.. = 25° c.
§ Not ;";ore than one outpu;;'ould be ;horted at a time and duration of the short-circuit should not exceed 1 second.
NOTE 2: ICG is measured for the following conditions:
a. All A inputs are at 4.5 V, Band C inputs are grounded, and all outputs are open.
b. Band C inputs are at 4.5 V, all A inputs are grounded, and all outputs are open.

switching characteristics, Vee = 5 V, TA = 25°e

PARAMETER TEST CONDITIONS MIN TYP MAX MAX
Propagation delay time, low-to-high-
tpLH 14 20 ns
level output from any A input
Propagation delay time, high-to-Iow-
tpHL 13 19 ns
level output from any A input eL = 25 pF, RL = 280 on,
Propagation delay time, low-to-high- See Note 3
tpLH
level output from B or e inputs I 17 25 ns

•
Propagation delay time, high-to-Iow-
tpHL 17 25 ns
level output from B or e inputs

NOTE 3: Load circuit and voltage waveforms are shown on page 3-10.

functional block diagram and schematics of inputs and outputs

A1 (2)
EQUIVALENT OF TYPICAL OF
EACH INPUT ALL OUTPUTS

A2 (5)
58 n Vee
Vee--.....- - -
NOM

INPUT

'--~..-- OUTPUT

A4~~-~-+--r~

1076

TEXAS INSTRUMENTS 7-71

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN5490A, SN5492A, SN5493A, SN54L90,SN54L93,
TTL SN54LS90, SN54LS92, SN54LS93, SN7490A, SN7492A, SN7493A,
MSI SN74L90, SN74L93, SN74LS90, SN74LS92, SN74LS93
DECADE, DIVIDE-BY-TWELVE, AND BINARY COUNTERS
BULLETIN NO. DL-S 7611807, MARCH 1974-REVISED OCTOBER 1976

SN54', SN54LS' ... J OR W PACKAGE

'90A, 'l90, 'lS90 ... DECADE COUNTERS SN54L' ••• J OR T PACKAGE
SN54', SN74L', SN74LS' ••• J OR N PACKAGE
'92A, 'lS92 ... DIVIDE-BY-TWElVE
'90A; 'L90, 'LS90 (TOP VIEW)
COUNTERS
'93A, 'l93, 'lS93 , .. 4-BIT BINARY
COUNTERS

TYPICAL
TYPES
POWER DISSIPATION
'90A 145mW
'L90 20mW
'LS90 45mW
'92A, '93A 130mW
'LS92, 'LS93 45mW
'L93 16mW '92A, 'LS92,(TOP VIEW)

description

Each of these monolithic counters contains four

master-slave flip-flops and additional gating to
provide a divide-by-two counter and a three-stage
binary counter for which the count cycle length is
divide-by-five for the '90A, 'L90, and 'LS90,
divide-by-six for the '92A and 'LS92, and
divide-by-eight for the '93A, 'L93, and 'LS93_

All of these counters have a gated zero reset and the

'93A, 'LS93 (TOP VIEW)
'90A, 'L90, and 'LS90 also have gated set-to-nine

•
inputs for use in BCD nine's complement
applications.

To use their maximum count length (decade, divide-

by-twelve, or four-bit binary) of these counters, the B
input is connected to the QA output. The input
count pulses are applied to input A and the outputs
are as described in the appropriate function table. A
symmetrical divide-by-ten count can be obtained
from the '90A, 'L90, or 'LS90 counters by
connecting the GD output to the A input and
applying the input count to the B input which gives a 'L93 (TOP VIEW)
divide-by-ten square wave at output GA.

positive logic: see function tables

NC-No internai connection

1076

7-72 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN5490A, '92A, '93A, SN54L90, 'L93, SN54LS90, 'LS92, 'LS93,
SN7490A, '92A, '93A, SN74L90, 'L93, SN74LS90, 'LS92, 'LS93
DECADE, DIVIDE-BY-TWELVE, AND BINARY COUNTERS
'90A, 'L90, 'LS90 '90A, 'L90, 'LS90
BCD COUNT SEQUENCE BI-OUINARY (5-2) '92A, 'LS92 '93A, 'L93, 'LS93
(See Note A) (See Note B)
COUNT SEQUENCE COUNT SEQUENCE
OUTPUT OUTPUT (See Note C) (See Note C)
COUNT COUNT
QO QC QB QA QA QO QC QB OUTPUT OUTPUT
COUNT COUNT
0
1
L
L
L
L
L
L
L
H
0
1
L
L
L
L
L
L
L
H
QO QC QB QA QO ac QB QA
0 L L L L 0 L L L L
2 L L H L 2 L L H L 1 L L L H 1 L H
L L
3 L L H H 3 L L H H 2 L L H L H
2 L L L
4 L H L L 4 L H L L 3 L L H H H H
3 L L
5 L H L H 5 H L L L 4 L H L L 4 L H L L
6 L H H L 6 H L L H 5 L H L H L H
5 L H
7 L H H H 7 H L H L 6 H L L L H L
6 L H
8 H L L L 8 H L H H 7 H L L H 7 L H H H
9 H L L H 9 H H L L 8 H L H L 8 H L L L
9 H L H H 9 H L L H
'90A, 'L90, 'LS90 10 H H L L 10 H L H L

:~ ~
11 IH H H I H

I H L
RO(1) RO(2) Rg(ll
I 13 H H L

I :: I:
X
I~
H

I H
X
H
X
X
H H H
L
L
L
L H
H H

X X L COUNT
COUNT
'92A, 'LS92, '93A, 'L93, 'LS93
X L
RESET/COUNT FUNCTION TABLE
L X X COUNT
RESET INPUTS OUTPUT
X X COUNT
ROil) RO(2) QO QC QB QA
H H L L L L
NOTES: A. Output QA is connected to input B for BCD count.
L X COUNT
B_ Output QD is connected to input A for bi-quinary
X L COUNT
count.
C. Output QA is connected to input B.
D. H = high level, L = low level, X = irrelevant

functional block diagrams

'gOA, 'L90, 'LS90 '92A, 'LS92 '93A, 'L93, 'LS93

("93A) ['L93]

INPUT A ...!(..:...14"-)['-'1-"4]'--_--<1I>
•
INPUT B . .).(.:. <)..c:[8~]
1 _ _--+-¢>

RO(l) (2)[1]
RO(2) (3)[2]

The J and K inputs shown without connection are for reference only and are functionally at a high level.

374

TEXASINCORPORATED
INSTRUMENTS 7-73
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN5490A, '92A, '93A, SN54L90, 'L93, SN54LS90, 'LS92, 'LS93,
SN7490A, '92A, '93A, SN74L90, 'L93, SN74LS90, 'LS92, 'LS93
DECADE, DIVIDE-BY-TWELVE, AND BINARY COUNTERS
REVISED OCTOBER 1976

schematics of inputs and outputs

'90A, '92A, '93A
EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS

vee3
Req - -

INPUT --

INPUT Req NOM

A 2.5 kH
B ('90A, '92A) 1.25 kH
B ('93A) 2.5 kH
All resets 6 kH

'L90, 'L93
EQUIVALENT OF EACH INPUT EQUIVALENT OF A AND B TYPICAL OF ALL OUTPUTS
EXCEPT A AND B OF 'L93 INPUTS OF 'L93

vee~_- Req
Vee-----.----~~-------

INPUT --

INPUT

INPUT Req NOM

A ('L90) 13.3 kH
B ('L90) 6.67 kH

•
All resets 40 kl1

'LS90, 'LS92, 'LS93

EQUIVALENT OF EACH RESET INPUT I EQUIVALENT OF A AND B INPUTS TYPICAL OF ALL OUTPUTS

---_Vee

ve~
U--
Vee T R1 R2 R3 120 l1 NOM
~NOM
INPUT -
'N'"T OUTPUT

NOMINAL VALUES
INPUT
R1 R2 R3
A 10kl1 10 kl1 10 kl1
B ('LS90, 'LS92) 6.7 kl1 6.7 kl1 5 kl1
B ('LS93) 15 kl1 15kl1 10kl1

107E

7·74 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN5490A, SN5492A, SN5493A, SN7490A, SN7492A, SN7493A
DECADE, DIVIDE-BY-TWELVE, AND BINARY COUNTERS

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) 7V
Input voltage . . . . . . . . 5.5 V
Interemitter voltage (see Note 2) 5.5 V
Operating free-air temperature range: SN5490A, SN5492A, SN5493A -55°e to 125°e
O°C to 70 e
0
SN7490A,SN7492A,SN7493A
0
Storage temperature range -65°e to 150 e
NOTES: 1. Voltage values, except interemitter voltage, are with respect to network ground terminal.
2. This is the voltage between two emitters of a multiple-emitter transistor. For these circuits, this rating applies between the two RO
inputs, and for the '90A circuit, it also applies between the two R9 inputs.

recommended operating conditions

I I
SN5490A, SN5492A SN7490A, SN7492A
SN5493A SN7493A
I I UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 1014 -800 -800 /LA
Low-level output current, 101 16 16 mA
A input 0 32 0 32
Count frequency, fcount (see Figure 1) MHz
B input 0 16 0 16
A input 15 15
Pulse width, tw B input 30 30 ns
Reset inputs 15 15
Reset inactive-state setup time, tsu 25 25 ns
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (un!ess otherwise noted)
'90A '92A '93A
PARAMETER TEST eONDITIONst UNIT

•
MIN TYP+ MAX MIN TYP+ MAX MIN TYP+ MAX
VIH High-level input voltage 2 2 2 V
VIL Low-level input voltage 0.8 0.8 0.8 V
V IK Input clamp voltage Vee= MIN, II = -12 mA -1.5 -1.5 -1.5 V
Vee= MIN, VIH = 2V,
VOH High-level output voltage 2.4 3.4 2.4 3.4 2.4 3.4 V
VIL = 0.8 V, IOH = -800 /.LA
Vee= MIN, VIH = 2 V,
VOL Low-level output voltage 0.2 0.4 0.2 0.4 0.2 0.4 V
VIL = 0.8 V, 10L = 16 mA1f
Input current at
II Vee= MAX, VI = 5.5 V 1 1 1 mA
maximum input voltage
Any reset 40 40 40
High-level
IIH A input Vee = MAX, VI = 2.4 V 80 80 80 /.LA
input current
B input 120 120 80
,Any reset -1.6 -1.6 -1.6
Low-level
IlL A input Vee= MAX, VI = 0.4 V -3.2 -3.2 -3.2 I mA
input current
B input -4.8 -4.8 -3.2 i
Short-circuit I SN54' -20 -57 -20 -57 -20 -57
lOS
output current§
Vee= MAX
I SN74' -18 -57 -18 -57 -18 -57! mA

ICC Supply current Vee = MAX, See Note 3 29 42 26 39 26 39: mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAli typical values are at Vee = 5 V, T A = 25° C.
§ Not more than one output should be shorted at a time.
~QA outputs are tested at IOL = 16 rnA plus the limit value for IlL for the B input. This permits driving the B input while maintaining full
fan-out capability.
NOTE 3: ICC is measured with all outputs open, both RO inputs grounded following momentary connection to 4.5 V, and all other inputs
grounded.

1076

TEXAS INCORPORATED
INSTRUMENTS 7-75
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN5490A, SN5492A, SN5493A, SN1490A, SN1492A, SN1493A
DECADE, DIVIDE-BY-TWELVE, AND BINARY COUNTERS
REVISED OCTOBER 1976

switching characteristics, Vee = 5 V, T A = 25° e

FROM TO '90A '92A '93A
PARAMETER~ TEST CONDITIONS UNIT
(INPUT) (OUTPUT) MIN TYP MAX MIN TYP MAX MIN TYP MAX
A QA 32 42 32 42 32 42
f max MHz
B QB 16 16 16
tpLH 10 16 10 16 10 16
A QA ns
tpHL 12 18 12 18 12 18
tpLH 32 48 32 48 46 70
A QD ns
tpHL 34 50 34 50 46 70
tpLH CL:15pF, 10 16 10 16 10 16
B QB ns
tpHL RL:400n, 14 21 14 21 14 21
tPLH See Figure 1 21 32 10 16 21 32
B Qc ns
tpHL 23 35 14 21 23 35
tpLH 21 32 21 32 34 51
B QD ns
tpHL 23 35 23 35 34 51
tpHL Set-to-O Any 26 40 26 40 26 40 ns
tpLH QA,QD 20 30
Set-to-9 ns
tpHL QB,QC 26 40

~fmax == maximum count frequency

tpLH == propagation delay time, low-to-high-Ievel output
tpH L == propagation delay time, high-to-Iow-Ievel output

1076

7-76 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54L90, SN54L93, SN74L90, SN74L93
DECADE AND BINARY COUNTERS

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 4) . . . . . . . . . . 8V
Input voltage (see Note 5) . . . . . . . . . 5.5V
Operating free-air temperature range: SN54L90, SN54L93 . -55°C to 125°C
SN74L90, SN74L93 oOe to 70°C
Storage temperature range -65°C to 150°C
NOTES: 4. Voltage values are with respect to network ground terminal.
5. Input voltages must be zero or positive with respect to network ground terminal.

recommended operating conditions

SN54L90, SN54L93 SN74L90, SN74L93
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, VCC 4.5 5 5.5 4.75 5 5.25 V
Count frequency, fcount 0 3 0 3 MHz
High-level output current, 10H -100 -200 !-LA
Low-level output current, 10L 2 3.6 mA
Width of input count pulse, tw(count) 200 200 ns
Width of reset puise, 1w(reset) zOu zOO ns
Operating free-air temperature, T A -55 125 0 70 °c

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
'L90 'L93
PARAMETER TEST CONDITIONSt UNIT
MIN TYP+ MAX MIN TYP+ MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.7 V
SN54L' Vee; MIN, VIH; 2 V, 2.4 3.3 2.4 3.3
VOH High-level output voltage -SN74L' VIL; 0.7 V, 10H; MAX 2.4 3.2 2.4 3.2
V

SN54L'
VOL Low-level output voltage -
SN74L'
Vee; MIN,
VIL; 0.7 V,
VIH;2V,
101 ; MAX~I
0.15
0.2
0.3
0.4
0.15
0.2
0.3
0.4
V

Any reset input 100 100

input cu rrent at

•
II A input VCC; MAX, VI; 5.5V 300 200 !-LA
maximum input voltage
B input 600 200
Any reset input 10 10
High-level input
IIH A input Vee; MAX, VI; 2.4 V 30 20 !-LA
current
B input 60 20
Any reset input -0.18 -0.18
Low-level input
IlL A input Vce; MAX, VI; 0.3 V -0.54 -0.36 mA
current
B input -1.08 -D.36
lOS Short-circuit output current§ Vce; MAX -3 -15 -3 -15 mA
ICC Supply current Vec; MAX, See Note 3 4 7.2 3.2 6.6 mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at VCC; 5 V, TA; 25°C.
§Not more than one output should be shorted at a time.
~QA outputs are tested at IOL; MAX plus the limit value for IlL for the B input. This permits driving the B input while maintaining full
fan-out capability.
NOTE 3: ICC is measured with all outputs open, both RO inputs grounded following momentary connection to 4.5 V, and all other inputs
grounded.

switching characteristics, Vee = 5 V, TA = 25° e

'L90 'L93
PARAMETER TEST CONDITIONS UNIT
MIN TYP MAX MIN TYP MAX
f max Maximum count frequency 3 6 3 6 MHz
Propagation delay time, low-to-high-Ievel QD
tpLH 230 340 280 450 ns
output from input A CL; 50 pF, RL;4kU,
Propagation delay time, high-to-Iow-Ievel QD See Figure 1
tpHL 230 340 280 450 ns
output from input A

374

TEXAS INCORPORATEO
INSTRUMENTS 7-77
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54LS90, SN54LS92, SN54LS93,
SN74LS90, SN14LS92, SN14LS93
DECADE, DIVIDE-BY-TWELVE, AND BINARY COUNTERS
REVISED OCTOBER 1976

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, Vcc (see Note 4) 7V

Input voltage: R inputs 7V
A and B inputs 5.5 V
Operating free-air temperature range: SN54LS' Circuits -55°C to 125°C
SN74LS' Circuits O°C to 70°C
Storage temperature range -65°C to 150°C
NOTE 4: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54LS90 SN74 LS90
SN54LS92 SN74 LS92
SN54LS93, SN74 LS93 UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, VCC 4,5 5 5.5 4.75 5 5.25 V
High·level output current, 10H -400 ,-400 j.LA
Low·level output current, 10L 4 8 mA
A input 0 32 0 32
Count frequency. fcount (see Figure 11 MHz
B input 0 16 0 16
A input 15 15
Pulse width. tw B input 30 30 ns
Reset inputs 15 15
Reset inactive-state setup time, tsu 25 25 ns
Operating free·air temperature. T A -55 125 0 70 °c

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS90 SN74LS90
PARAMETER TEST CONDITIONSt SN54 LS92 SN74LS92 UNIT
~M--IN---T-y-P-t--M-A--X~M--IN---T-y-P-t--M--A~X

•
VI H High-level input voltage 2 2 V
VI L Low-level input voltage 0,7 0.8 V
VIK Input clamp voltage Vcc = MIN. II = -18 mA -1.5 -1.5 V

VOH High-level output voltage 2.5 3.4 V

Vcr. = MIN VIH = 2 V 1i-,1.,:,:0",L:...=_4

__ m_A_~::-+______ 0._4-+1______
0_2_5____ 0_.4...;:
0_2_5____
v
IIOL=8mA~
VOL Low-level output voltage
iVI:=VILmax, I 0.350.51
7_V______________- t____________
I nput current I-A_n....:v_r_e_se_t__+V....:C"-'C"--=_M_A_X....:.'--__V...,:I'-=__ 0_.1-+1_ _ _ _ _ _ _ _ _ _ _ _0_,1---1
II at maximum A input 0.2 0.2 mA
input voltage B input VCC = MAX. VI = 5.5 V 0.4 0.4
Any reset 20 20
High·level
~A
__in_p_u_t----i V CC = MAX. VI = 2.7 V 40 40 j.LA
input current
B input 80 80
Any reset -0.4 -0.4
Low·level
A input VCC = MAX. VI = 0.4 V -2.4 -2.4 mA
output current /---------j
B input -3.2 -3.2
lOS Short·circuit output current§ VCC = MAX -20 -100 -20 -100 mA

Supply current Vcc = MAX, See Note 3

I 'LS90 9 15 9 15
mA
ICC
I 'LS92 9 15 9 15
tFor conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions,
tAil typical values are at V CC =5 V. T A = 25°C,
§ Not more than one output should be shorted at a time. and duration of the short-circuit should not exceed one second.
~ Outputs are tested at specified IOl plus the limit value of II l for the B input, This permits driving the B input while maintaining full fan·out
capability,
NOTE 3: ICC is measured with all outputs open. both RO inputs grounded following momentary connection to 4.5 V. and all other inputs
grounded.

107E

7-78 TEXAS I ....INSTRUMENTS

CORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54LS90, SN54LS92, SN54LS93,
SN74LS90, SN74LS92, SN74LS93
DECADE, DIVIDE-BY-TWELVE, AND BINARY COUNTERS
REVISED OCTOBER 1976

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS93 SN74LS93
PARAMETER TEST CONDITIONSt UNIT
MIN TYP:j: MAX MIN TYP:j: MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
VIK Input clamp voltage Vee; MIN, II ;-18mA -1.5 -1.5 V
VCC; MIN, VIH; 2 V,
VOH High-level output voltage 2.5 3.4 2.7 3.4 V
VIL; VIL max, IOH; -400 pA
Vee; MIN, VIH;2V, !IOl;4mA' 0.25 0.4 0.25 0.4
VOL low-level output voltage V
Vll; VIL max tlOl; 8 mA' 0.35 0.5
Input current
Any reset Vee; MAX, VI; 7V 0.1 0.1
II at maximum mA
A or B input Vee; MAX, VI; 5.5 V 0.2 0.2
input voltage
High-level Any reset 20 20
IIH Vee; MAX, V!;2.7V pA
input current A or ~ input 40 80
Any reset -0.4 -0.4
Low-level
IlL A input Vee; MAX, VI; 0.4 V -2.4 -2.4 mA

lIDS
Oui ~ut Curn3nt
-1.6 -1.61 iliA

lee Supply current Vee; MAX, See Note 3 9 15 9 15 mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at V CC = 5 V, T A; 25°C.
§ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
, QA outputs are tested at specified IOL plus the limit value for II L for the B input. This permits driving the B input while maintaining full
fan-out capability.
NOTE 3: ICC is measured with all outputs open, both RO inputs grounded following momentary connection to 4.5 V, and all other inputs
grounded.

switching characteristics, Vee =5 V, TA = 25°C

FROM TO 'LS90 'LS92 'LS93
PARAMETER'; TEST CONDITIONS UNIT

•
(INPUT) (OUTPUT) MIN TYP MAX MIN TYP MAX MIN TYP MAX
A QA 32 42 32 42 32 42
f max MHz
B QB 16 16 16
tPLH 10 16 10 16 10 16
A QA ns
tpHL 12 18 12 18 12 18
tpLH 32 48 32 48 46 70
A QO ns
tpHL 34 50 34 50 46 70
tPLH CL=15pF, 10 16 10 16 10 16
B QB ns
tpHL RL; 2 kn 14 21 14 21 14 21
tPLH See Figure 1 21 32 10 16 21 32
B Qe ns
tpHL 23 35 14 21 23 35
tPLH 21 32 21 32 34 51
B QO ns
tpHL 23 35 23 35 34 51
tPHL Set-to-O Any 26 40 26 40 26 40 ns
tpLH QA,QO 20 30
Set-to-9 ns
tpHL QB,QC 26 40

41 f max == maximum count frequency

tpLH == propagation delay time, low·to·high·level output
tpH L == propagation delay time, high·to·low·level output

1076

TEXAS INCORPORATED
INSTRUMENTS 7-79
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN5490A, SN5492A, SN5493A, SN54L90, SN54L93,
SN54LS90, SN54LS92, SN54LS93, SN7490A, SN7492A, SN7493A,
SN74L90, SN74L93, SN74LS90, SN74LS92, SN74LS93
DECADE, DIVIDE-BY-TWELVE, AND BINARY COUNTERS
PARAMETER MEASUREMENT INFORMATION

TEST
POINT

FROM OUTPUT
UNDER TEST - ...---tI.-.-I.........,.;........,

eLI
(See Note B)-=-
LOAD CIRCUIT

•
VOLTAGE WAVEFORMS

NOTES: A. Input pulses are supplied by a generator having the following characteristics:
for '90A, '92A, '93A, tr';; 5 ns, tf .;; 5 ns, PRR = 1 MHz, duty cycle = 50%, Zout "" 50 ohms;
for 'L90, 'L93, tr';; 15 ns, tf';; 15 ns, PRR = 500 kHz, duty cycle = 50%, Zout "" 50 ohms;
for 'LS90, 'LS92, 'LS93, tr .;; 15 ns, tf .;; 5 ns, PRR = 1 MHz, duty cycle = 50%, Zout "" 50 ohms.
B. CL includes probe and jig capacitance.
C. C1 (30 pF) is applicable for testing 'L90 and 'L93.
D. All diodes are 1N916 or 1N3064.
E. Each reset input is tested separately with the other reset at 4.5 V.
F. Reference waveforms are shown with dashed lines.
G. For '90A, '92A, and '93A; Vref = 1.5 V. For 'L90, 'L93, 'LS90, 'LS92, and 'LS93; Vref = 1.3 V.

FIGURE 1

1076
TEXAS INSTRUMENTS
INCORPORATED
7·80 POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TTL TYPES SN5491A, SN54L91, SN54LS91, SN7491A, SN74L91, SN74LS91
MSI 8-BIT SHIFT REGISTERS
BULLETIN NO. DL-S 7611854, MARCH 1974-REVISED OCTOBER 1976

MSI TTL 1FT REGISTERS

for applications in
• Digital Computer Systems • Data-Handling Systems • Control Systems

SN5491A, SN54LS91 ... J PACKAGE SN5491A, SN54LS91 •.. W PACKAGE

SN54L91, SN7491A,SN74L91, SN74LS91 ••• J OR N PACKAGE SN54L91, SN74L91 ..• T PACKAGE
DUAL·!N-LiNE PACKAGE (TOP VIEW) FLAT PACKAGE (TOP VIEW)

FUNCTION TABLE
INPUTS OUTPUTS
ATtn AT tn+8
A B QH OH
H H H L
L X L H
X L L H
H = high, L = low,
X = irre!ev.::!!'1t NC NC NC Vee NC NC NC
tn = Reference bit time,
clock low
t n +8 = Bit time after 8 positive logic: see function table
low-to-high
clock transitions. NC-No internal connection

TYPICAL schematics of inputs and outputs

TYPICAL
MAXIMUM '91A, 'L91 'LS91
TYPE POWER
CLOCK EQUIVALENT OF EACH INPUT EQUIVALENT OF EACH INPUT
DISSIPA TlON
FREQUENCY
'91A
'L91
18 MHz
6.5 MHz
175mW
17.5mW
vce~_- Req

'LS91 18 MHz 60mW INPUT __

description

These monolithic serial-in, serial-out, 8-bit shift regis-

ters utilize transistor-transistor logic (TTL) circuits
and are composed of eight R-S master-slave flip-flops,
input gating, and a clock driver. Single-rail data and
input control are gated through inputs A and Band
an internal inverter to form the complementary
inputs to the first bit of the shift register. Drive for
the internal common clock line is provided by an
'91AoReq = 4 kn NOM
'L91, Req = 40 kn NOM

'91A, 'L91
TYPICAL OF BOTH OUTPUTS

Vee
'LS91
TYPICAL OF BOTH OUTPUTS
Vee
•
inverting clock driver. This clock pulse inverter/driver
causes these circuits to sh"ift information one bit on OUTPUT
the positive edge of an input clock pulse.

'91A' R = 130 n NOM

'L91, R = 500 n NO.'VI
functional block diagram
(DUAL·IN·lINEI [FLAT PACKAGE]
A ......:..:11~21:....:[..:..:10:.;.1J
(131 [131
1111 [121 Q QH

eK
Q 1141 [141 QH

CLOCK

1076

TEXAS INSTRUMENTS 7-81

INCORPORATED
POST OFFICE B~X 5012 • DALLAS, TEXAS 75222
 TYPES SN5491A, SN7491A
8-BIT SH 1FT REGISTERS

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) 7V
Input voltage (see Note 2) 5.5V
Operating free-air temperature range: SN5491A -55°C to 125°C
SN7491A O°C to 70°C
Storage temperature range -65°C to 150°C
NOTES: 1. Voltage values are with respect to network ground terminal.
2. Input signals must be zero or positive with respect to network ground terminal.

recommended operating conditions

SN5491A SN7491A
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -400 -400 p.A
Low-level output current, 10L 16 16 mA
Width of clock input pulse, tw 25 25 ns
Setup time, tsu (see Figure 1) 25 25 ns
Hold time, th (see Figure 1) 0 0 ns
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN5491 A SN7491A
PARAMETER TEST CONDITIONSt UNIT
MIN NOM MAX MIN NOM MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
Vee- MIN, VIH-2V,
VOH High-level output voltage 2.4 3.5 2.4 3.5 V
VIL = 0.8 V, 10H = -400p.A
Vee= MIN, VIH=2V,
VOL Low-level output voltage 0.2 0.4 0.2 0.4 V
VIL = 0.8 V, 10L = 16mA
II Input current at maximum input voltage Vee= MAX, VI = 5.5 V 1 1 mA

•
IIH High-level input current Vee - MAX, VI- 2.4 V 40 40 p.A
IlL Low-level input current Vee = MAX, VI = 0.4 V -1.6 -1.6 mA
lOS Short-circuit output currentS Vee= MAX -20 -57 -18 -57 mA
lee Supply current Vee = MAX, See Note 3 35 50 35 58 mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
t All typical values are at V CC = 5
V, T A = 25° C.
§ Notmore than one output should be shorted at a time.
NOTE 3: ICC is measured after the eighth clock pulse with the output open and A and B inputs grounded.

switching characteristics, Vee = 5 V, TA = 25°e

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f max Maximum clock frequency CL = 15pF, 10 18 MHz
tpLH Propagation delay time, low-to-high-Ievel output RL=4oon, 24 40 ns
tpHL Propagation delay time, high-to-Iow-Ievel output See Figure 1 27 40 ns

1076

7-82 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54L91, SN74L91
8-BIT SHIFT REGISTERS

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . 8V
Input voltage (see Note 2) . . . . . 5.5V
-55°C to 125 e
G
Operating free-air temperature range: SN54L91
SN74L91 oOe to 70°C
Storage temperature range -65°C to 150°C
NOTES: 1. Voltage values are with respect to network ground terminal.
2. I nput signals must be zero or positive with respect to network ground terminal.

recommended operating conditions

SN54L91 SN74L91
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -100 -200 /.LA
Low-level output current, 10L 2 3.6 mA
! High logic level 100 100 ns
Width of clock input pulse, tw(clock)
I Low logic level 150 150 ns
::;etup time, tsu (~ee Figure 1 j 120 120 ns
Hold time. th (see Figure 1) 0 0 ns
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54L91 SN74L91
PARAMETER TEST CONDITIONSt UNIT
MIN TYP:j: MAX MIN TYP+ MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.7 V
Vee- MIN, VIH-2V,
VOH High-level output voltage 2.4 3.3 2.4 3.2 V
VIL = 0.7 V, 10H = MAX

•
Vee- MIN, VIH - 2V
VOL Low-level output voltage 0.15 0.3 0.2 0.4 V
VIL = 0.7 V, 10L = MAX
II Input current at maximum input voltage Vee - MAX, V,- 5.5 V 100 100 /.LA
IIH High-level input current Vce = MAX, VI = 2.4 V 10 10 /.LA
IlL Low-level input current Vee- MAX, VI- 0.3 V -0.18 -0.18 mA
lOS Short-circuit output current Vee = MAX -3 -15 -3 -15 mA
ICC Supply current Vce- MAX, See Note 3 3.5 6.6 3.5 6.6 mA

tFor conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions.
+AII typical values are at Vee = 5 V. TA = 25°C.
NOTE 3: ICC is measured after the eighth clock pulse with the outputs open and A and B inputs grounded.

switching characteristics, Vee = 5 V, TA = 25°e

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f max Maximum clock frequency 3 6.5 MHz
Propagation delay time,
tpLH eL=50pF, RL =4 kn, 55 100 ns
low-to-high-Ievel output
See Figure 1
Propagation delay time,
tPHL 100 150 ns
high-to-Iow-Ievel output

076

TEXAS INCORPORATED
INSTRUMENTS 7-83
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54LS91, SN74LS91
8-BIT SHIFT REGISTERS
REVISED OCTOBER 1976

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) 7V
Input voltage . . . . . . . 7V
Operating free-air temperature range: SN54LS91 -55°C to 125°C
SN74LS91 oOe to 70°C
Storage temperature range -65°C to 150°C
NOTES: 1. Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54LS91 SN74LS91
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, IOH -400 -400 /J A
low-level output current. IOl 4 8 mA
Width of clock input pulse, tw 25 25 ns
Setup time, tsu (see Figure 1) 25 25 ns
Hold time, th (see Figure 1) 0 0 ns
Operating free-air temperature. T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS91 SN74LS91
PARAMETER TEST CONDITIONSt UNIT
MIN TYP:j: MAX MIN TYP:j: MAX
VIH High-level input voltage 2 2 V
Vil low-level input voltage 0.7 0.8 V
VIK I nput clamp voltage Vee = MIN, 11=-18mA -1.5 -1.5 V
Vee = MIN, VIH = 2 V,
VOH High-level output voltage 2.5 3.5 2.7 3.5 V
VI l = VI l max, IOH = -400 /JA
Vee = MIN, VIH - 2 V, IIOl - 4 mA 0.25 0.4 0.25 0.4
V

•
VOL low-level output voltage
Vil = Vil max IIOl = 8mA 0.35 0.5
Input current at
II Vee = MAX, VI = 7 V 0.1 0.1 mA
maximum input voltage
IIH High-level input current Vee = MAX, VI=2.7V 20 20 /J A
III low-level input current Vee = MAX, VI = 0.4 V -0.4 -0.4 mA
i lOS Short·c:rcu:t output current § , Vee= MAX 1-20 -100 1-20 -100, rnA
ICC Supply current Vee = MAX, See Note 3 12 20 12 20 mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
= 5 V, T A = 25" C.
:j: All typical values are at V CC
§ Not more than one output should be shorted at a time, and du ration of the short-circuit should not exceed one second.
NOTE 3: ICC is measured after the eighth clock pulse with the output open and A and B inputs grounded.

switching characteristics, Vee = 5 V, TA = 25°e

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f max Maximum clock frequency el = 15pF, 10 18 MHz
tplH Propagation delay time, low-to-high-Ievel output Rl=2kn, 24 40 ns
tpHl Propagation delay time, high-to-Iow-Ievel output See Figure 1 27 40 ns

107

7-84
TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 • OALLAS, TEXAS 75222
 TYPES SN5491A. SN54L91, SN54LS91, SN7491A. SN74L91, SN74LS91
8-BIT SHIFT REGISTERS

PARAMETER MEASUREMENT INFORMATION

VCC =5 V OUTPUT
- LOADCIRCuIT1 - - -,
VCC =5 V I
I
r---------, I
I I I
I I
PULSE I C I
GENERATOR r--------r-~~-~~
(See Note A)
INPUT A IL _
Note B
se;T
-=
~_Note
I
I
____ _D_ _ _ __ ~
2.4 V

r-- --LO;:D~!;:U~;--- - - ,
~L
--- -- -
SAME AS LOAD CIRCUIT 1
---- - - ....JI
TCC"T
.lI-o.lIIl .....
_ IO •• 1 .....
_I _I I'T
.

1 2 thru 7 8 9 thru 15 16 17 18 19 thru 23 24 25 26 27

CLOCK-PULSE
INPUT
n n---n n n----n n n n n---JlJlJlJlJl
I U L__ J U U L__ J U U U U L__

INPUTA L____ ____ ~ ____________

OUTPUTQH _ _ _ _ _ _ _ Sl____ ____ s - L
TYPICAL INPUT/OUTPUT WAVEFORMS

•
J""'!'_ _--3V
CLOCK
INPUT
INPUT
I
-1-- - -OV
I
I ~-------3V
I
I INPUT
I 1 AOR B
1
I
tpH L ---t--J -I - - - - - - - - 0V

tp LH --t---I - - : - th
-1- - -- - ---3V
INPUT
AOR 13
~-------OV

PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS SWITCHING TIMES VOLTAGE WAVEFORMS

NOTES: A. The generator has the following characteristics: tw(clock) = 500 ns, PRR ,,;; 1 MHz, Zout'" 50 For SN5491A/SN7491A, n.
tr";; 10 ns and tf ,,;; 10 ns; for SN54L91/SN74L91, tr";; 15 ns and tf ,,;; 15 ns; and for SN54LS91/SN74LS91, tr = 15 ns, and

B. CL includes probe and jig capacitance.

C. All diodes are 1N3064or 1N916.
D. C1 = 30 pF and is used for SN54L91/SN74L91 only.
E. For SN5491A/SN7491A, Vref = 1.5 V; for SN54L91/SN74L91 and SN54LS91/SN74LS91, Vref = 1.3 V.
FIGURE l-SWITCHING TIMES

1076

TEXAS INCORPORATED
INSTRUMENTS 7-85
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TTL TYPES SN5494, SN7494
MSI 4-81T SHIFT REGISTERS
BULLETIN NO. DL-S 7211812, DECEMBER 1972

TTL MSI PARALLEL-IN SERIAL-OUT REGISTERS

for application as
• Dual-Source, Parallel-To-Serial Converter • Serial-In Serial-Out Register
description
SN5494 •.• J OR W PACKAGE
These monolithic shift registers which utilize tran- SN7494 •.• J OR N PACKAGE
sistor-transistor logic (TTL) circuits in the familiar (TOP VIEW)
Series 54/74 configuration, are composed of four R-S
master-slave flip-flops, four AND-DR-INVERT gates,
and four inverter-drivers. Internal interconnections of P2A PE2 P2B P2C GND P2D CLEAR OUTPUT

these functions provide a versatile register which

performs right-shift operations as a serial-in, serial-out
register or as a dual-source, parallel-to-serial convert-
er. A number of these registers may be connected in
series to form an n-bit register.
All flip-flops are simultaneously set to a low output
level by applying a high-level voltage to the clear
input while the internal presets are inactive (high).
See the preset function table below. Clearing is
independent of the level of the clock input.
The register may be parallel loaded by using the clear P1A P1B P1C P1D VCC PE1 CLOCK

input in conjunction with the preset inputs. After

clearing all stages to low output levels, data to be
loaded is applied to either the P1 or P2 inputs of each positive logic: see function tables
register stage (A, B, C, and D) with the corresponding
preset enable input, PE1 or PE2, high. Presetting,like
clearing, is independent of the level of the clock
input.
Transfer of information to the outputs occurs on the positive-going edge of the clock pulse. The proper information
must be setup at the R-S inputs of each flip-flop prior to the rising edge of the clock input waveform. The serial input

•
provides this information for the first flip-flop, while the outputs of the subsequent flip-flops provide information for
the remaining R-S inputs. The clear input must be at a low level and the internal presets must be inactive (high) when
clocking occurs.
PRESET FUNCTION TABLE
REGISTER FUNCTION TABLE
(BIT A, TYPICAL OF ALL)
PRESET iNPUTS iNTERNAL INTERNAL ~RESETS !NPUTS ' INTERNAL OUTPUTS OUTPUT
PE1 P1A PE2 P2A PRESET A A B C 0 CLEAR CLOCK SERIAL QA QB QC Qo
L X L X H (inactive) H H H H H X X L L L L
L X X L H (inactive) L L L L L X X H H H H
X L L X H (inactive) H H H H L L X GAO GBO Geo GOO
X L X L H (inactive) L H L H L L X H GBO H QOO
H H X X L (active) H H H H L t H H QAn QBn Qen
X X H H L (active) H H H H L t L I L GAn GBn QCn

H = high
level (steady state), L = low level (steady state), X = irrelevant, t = transition from low to high level
0AO, 0BO, 0CO, 0DO = the level of 0A, 0B, 0C, or 0D, respectively, before the indicated steadY'state input conditions were established.
0An, 0Bn' 0Cn = the level of 0A, 0B, or 0C, respectively, before the most-recent t transition of the clock.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) ....... . 7V
Input voltage (see Note 2) . . . . . . . . 5.5 V
Operating free-air temperature range: SN5494 Circuits -55°C to 125°C
SN7494 Circuits . O°C to 70°C
Storage temperature range -65°C to 150°C
NOTES: 1. Voltage values are with respect to network ground terminal.
2. Input voltage must be zero or positive with respect to network ground terminal.

1076

7·86 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN5494, SN7494
4-BIT SHIFT REGISTERS

functional block diagram

PRESETS
1\
/ \
P1A P2A P1B P2B P1C P2C P1D P2D
(1) (16) (2) (14) (3) (13) (4) (11)

PRESET {PE2 (15)

ENABLE (6)
INPUTS PE1~~----+__--~-+------+-~---+-+----~~~-+-+------~

...--------1 S S OB S S aD (9) OUTPUT

CK CK CK

;0---.....----+--1 R R R

CLEAR CLEAR CLEAR CLEAR

(8)
CLOCK

-+ ...
I

I
dynamic input activated by transition from a high level to a low level

schematics of inputs and output

EQUIVALENT OF EACH INPUT OUTPUT
•
Vee
------....------- Vee

INPUT

. . .- - - - - OUTPUT

PE1 and PE2: Req = 1 kn NOM

All others: Req = 4 kn NOM

1272

TEXAS INCORPORATED
INSTRUMENTS 7-87
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN5494, SN1494
4-811 SHIFT REGISTERS

recommended operating conditions

SN5494 SN7494
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, IOH -400 -400 folA
Low-level output current, IOL 16 16 mA
Width of clock pulse, tw(clock) 35 35 ns
Width of clear pulse, tw(clearl 30 30 ns
Width of preset pulse, tw(preset) 30 30 ns

Setup time, tsu

I High-level data 35 35
ns
I Low-level data 25 25
Hold time, th 0 0 ns
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN5494 SN7494
PARAMETER TEST CONDITIONSt UNIT
MIN TYP:j: MAX MIN TYp:j: MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
Vee= MIN, VIH =2V,
VOH High-level output voltage 2.4 3.5 2.4 3.5 V
VIL = 0.8 V, IOH = -400folA
Vee= MIN, VIH=2V,
VOL Low-level output voltage 0.2 0.4 0.2 0.4 V
VIL = 0.8 V, IOL = 16mA
II Input current at maximum input voltage Vee = MAX, VI = 5.5 V 1 1 mA
Presets 1 and 2 160 160
IIH High-level input current Vee= MAX, VI = 2.4 V folA
Other inputs 40 40
Presets 1 and 2 -6.4 -6.4
IlL Low-level input current Vee = MAX, VI = 0.4 V mA
Other inputs -1.6 -1.6

•
lOS Short·circuit output current § Vee = MAX -20 -57 -18 -57 mA
lee Supply current Vee = MAX, See Note 3 35 50 35 58 mA

:For co~ditions shown as MIN or MAX, use t~e appropriate value specified under recommended operating conditions.
+AII tYPical values are at Vee = 5 V, T A = 25 e.
§Not more than one output should be shorted at a time.
NOTE 3: iCC is measured with the outputs ooero. clear grounded following momentary application of 4.5 V, both preset-enable inputs
grounded, and all other inputs at 4.5 V.

switching characteristics, Vee = 5 V, TA = 25°e

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f max Maximum clock frequency 10 MHz
Propagation delay time, low-to-high-Ievel
tpLH
output from clock I 25 40 ns
I
Propgaation delay time, high-to-Iow-Ievel
tpHL eL=15pF, RL = 400 n, 25 40 ns
output.from clock
See Note 4
Propagation delay time, low-to-high-Ievel
tpLH 35 ns
output from preset
Propagation delay time, high-to-Iow-Ievel
tpHL 40 ns
output from clear

NOTE 4: Load circuit and voltage waveforms are shown on page 3-10.

1076

7-88 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN5495A, SN54L95, SN54LS95B,
TTL
SN7495A, SN74L95, SN74LS95B
MSI 4-BIT PARALLEL-ACCESS SHIFT REGISTERS
BULLETIN NO. DL-S 7611872. MARCH 1974-REVISEDOCTOBER 1976

TYPICAL MAXIMUM TYPICAL

TYPE SN5495A, SN54LS95B .•• J OR W PACKAGE
CLOCK FREQUENCY POWER DISSIPATION
SN7495A, SN74LS95B .•. J OR N PACKAGE
'95A 36 MHz 195mW (TOP VIEW)
'L95 5MHz 19mW
'LS95B 36 MHz 65mW OUTPUTS CLOCK 2

Vee ~ ~;~~i ~~~~J

description 12 n
These 4-bit registers feature parallel and serial inputs,
parallel outputs, mode control, and two clock input.s.
The registers have three modes of operation:
Parallel (broadside) load
Shift right (the direction aA toward aD)
Shift left (the direction aD toward aA)
Parallel loading is accomplished by applying the four
bits of data and taking the mode control input high.
The data is loaded into the associated flip-flops and
positive logic: see function table
appears at the outputs after the high-to-Iow transition
of the clock-2 input. During loading, the entry of SN54L95 ••• J OR T PACKAGE
serial data is inhibited. SN74L95 ••• J OR N PACKAGE
(TOP VIEW)
Shift right is accomplished on the high-to-Iow transi-
OUTPUTS CLOCK 2
tion of clock 1 when the mode control is low; shift INPUT
A ~7~H~~i
left is accomplished on the high-to-Iow transition of
clock 2 when the mode control is high by connecting
the output of each flip-flop to the parallel input of
the previous flip-flop (aD to input C, etc.) and serial
data is entered at input O. The clock input may be
applied commonly to clock 1 and clock 2 if both
modes can be clocked from the same source. Changes
at the mode control input shou Id normally be made

•
while both clock inputs are low; however, conditions
described in the last three lines of the function table
will also ensure that register contents are protected. positive logic: see function table

FUNCTION TABLE
INPUTS OUTPUTS
MODE CLOCKS PARALLEL
SERIAL QA QB Qc QD
CONTROL 21L) 1.IR) A B C D
H H X X X X X X QAO QBO Qeo QDO
H ~ X X a b c d a b c d
H ~ X X QBt Qe t Qot d QBn Qen QO n d
L L H X X X X X QAO QBO Qeo QOO
L X -I- H X X X X H QAn QBn Oen
L X -I- L X X X X L QAn QBn Qen
t L L X X X X X QAO QBO Qeo QOO
+ L L X X X X X QAO QBO Oeo QOO
-I- L H X X X X X QAO QBO Qeo QOO
t H L X X X X X QAO QBO Qeo QOO
t H H X X X X X QAO QBO Qeo QOO
tShifting left requires external connection of QB to A, QC to B, and QD to C. Senal data IS entered at input D.
H = high level (steady state), L = low level (steady state), X = irrelevant (any input, including transitions)
~ = transition from high to low level, t = transition from low to high level
a. b, c, d = the level of steady-state input at inputs A, B. C, or D, respectively.
QAO, QBO, QCO, QDO = the level of QA. QB. QC. or QD. respectively. before the indicated steady-state input conditions were established.
QAn. QBn. QCn. QDn = the level of QA •.Q B• QC. or QD. respectively. before the most-recent ~ transition of the clock.

1076

TEXAS INSTRUMENTS 7-89

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN5495A, SN54L95, SN54LS95B, SN7495A, SN74L95, SN74LS95B
4-BI1 PARALLEL-ACCESS SHIFT REGISTERS
REVISED OCTOBER 1976

functional block diagram (,95A,'LS95B) !'L95J

CLOCK 1 ,91[7]
RIGHT -5HI FT---r---;......./

ClOCK2 (8)[8!
LEFT-SH1FT-----L-./

(10119}

schematics of inputs and outputs

'95A 'L95 '95A, 'L95

EQUIVALENT OF EACH INPUT EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS

VCC1 3--
Req VCC~-- Req

INPUT -- INPUT --

Mode control: Req = 3 kn NOM Mode control: Req = 20 kn NOM

Clock inputs: Req = 4 kn NOM '95A: R = 100 n
All other inputs: Req = 40 kn NOM
All other inputs: Req = 6 kn NOM 'L95: R = 500 n

'LS95B 'LS95B 'LS95B

•
EQUIVALENT OF CLOCK EQUIVALENT OF DATA TYPICAL OF ALL OUTPUTS
AND MODE CONTROL INPUTS AND SERIAL INPUTS
----'P--VCC
VCC:E-- VCC~-­
17 n NOM
__ ~15 kn NOM

u 'N'UTO--
INPUT --
L------""---OUTPUT

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
SN54' SN54L' SN54LS' SN74' SN74L' SN74LS' UNIT
Supply voltage, V CC (see Note 1) 7 8 7 7 8 7 V
Input voltage (see Note 2) 5.5 5,5 7 5,5 5.5 7 V
I nteremitter voltage (see Note 3) 5.5 5.5 5:5 5.5 V
Operating free-air temperature range -55 to 125 o to 70 °c
Storage temperature range -65 to 150 -65 to 150 °c
NOTES: 1. Voltage values, except interemitter voltage, are with respect to network ground terminal.
2. For the 'L95, input voltages must be zero or positive with respect to network ground terminal.
3. This is the voltage between two emitters of a multiple-emitter input transistor. This rating applies between the clock-2 input and
the mode control input of the '95A and 'L95.

1076

7-90 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN5495A. SN7495A
4-81T PARALLEL-ACCESS SHIFT REGISTERS
REVISED MARCH 1974

recommended operating conditions

SN5495A SN7495A
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, VCC 4.5 5 5.5 4.75 5 5.25 V
High-level output current, IOH -800 -800 J.i.A
Low-level output current, IOL 16 16 mA
Clock frequency, fclock 0 25 0 25 MHz
Width of clock pulse, tw(clock) (see Figure 1) 20 20 ns
Setup time, high-level or low-level data, tsu (see Figure 1) 15 15 ns
Hold time, high-level or .Iow-Ievel data, th (see Figure 1) 0 0 ns
Time to enable clock 1, tenable 1 (see Figure 2) 15 15 ns
Time to enable clock 2, tenable 2 (see Figure 2) 15 15 ns
Time to inhibit clock 1, tinhibit 1 (see Figure 2) 5 5 ns
Time to inhibit clock 2, tinhibit 2 (see Figure 2) 5 5 ns
.. +i ........ -I= .. .. ~ .,. + ...... I.
- 55 ." n ~n

IV I
0,..
'-' I

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN5495A SN7495A
PARAMETER TEST COND!T!ONSt UN!T
MIN TYP+ MAX MIN TYP+ MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
VIK Input clamp voltage VCC - MIN, II = -12 mA -1.5 -1.5 V
VCC= MIN, VIH=2V,
VOH High-level output voltage 2.4 3.4 2.4 3.4 V
VIL = 0.8 V, 10H = -800J.i.A
I
VCC= MIN, VIH = 2 V,
VOL Low-level output voltage 0.2 0.4 0.2 0.4 V
VIL = 0.8 V, 10L = 16mA
Input current at
II
maximum input voltage
Vec= MAX, VI = 5.5V 1 i 1 mA I
Serial, A, B, C, D,

•
High-level 40 40
IIH Clock 1 or 2 Vec = MAX, VI = 2.4 V J.i.A
input current
Mode control 80 80
Serial, A, B, C, D,
Low-level -1.6 -1.6
IlL Clock 1 or 2 Vee= MAX, VI=0.4V mA
input current
Mode control -3.2 -3.2
lOS Short-circuit output current§ VCC = MAX -18 -57 -18 -57 mA
ICC Supply current VCC - MAX, See Note 4 39 63 39 63 mA

t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
0
+AII typical values are at V CC =5 V, T A = 25 C.
§ Not more than one output should be shorted at a time.
NOTE 4: ICC is measured with all outputs and serial input open; A, B, C, and D inputs grounded; mode control at 4.5 V; and a momentary
3 V, then ground, applied to both clock inputs.

switching characteristics, Vee = 5 V, TA = 25°e

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f max Maximum clock frequency 25 36 MHz
eL = 15 pF, RL =400 n,
tpLH Propagation delay time, low-to-high-Ievel output from clock 18 27 ns
See Figure 1
tpHL Propagation delay time, high-to-Iow-Ievel output from clock 21 32 ns

1076

TEXAS INCORPORATED
INSTRUMENTS 7-91
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54L95, SN74L95
4-81T PARALLEL-ACCESS SHIFT REGISTERS

recommended operating conditions

SN54L95 SN74L95
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, V CC 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -100 -200 IlA
Low-level output current, 10L 2 3.6 mA
Clock frequency, fclock 0 3 0 3 MHz
Width of clock pulse, tw(clock) (see Figure 1) 200 200 ns
Setup time, high-level data, tsu (see Figure 1) 100 100 ns
Setup time, low-level data, tsu (see Figure 1) 120 120 ns
Hold time, high-level or low-level data, th (see Figure 1 ) 0 0 ns
Time to enable clock 1, tenable 1 (see Figure 2) 225 225 ns
Time to enable clock 2, tenable 2 (see Figure 2) 200 200 ns
Time to inhibit clock 1, tinhibit 1 (see Figure 2) 100 100 ns
Time to inhibit clock 2, tinhibit 2 (see Figure 2) 0 0 ns
Operating free-air temperature, T A -55 125 0 70 °c

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54L95 SN74L95
PARAMETER TEST CONDITIONSt UNIT
MIN TYP+ MAX MIN TYP+ MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.7 V
VCC = MIN, VIH = 2 V,
VOH High-level output voltage 2.4 3.3 2.4 3.2 V
VIL = 0.7 V, 10H = MAX
VCC = MIN, VIH=2V,
VOL Low-level output voltage 0.15 0.3 0.2 0.4 V
VIL = 0.7 V, 10L = MAX
I nput current Serial, A, B, C, 0,
100 100
II at maximum Clock lor 2 VCC = MAX, VI = 5.5V IlA
input voltage Mode control 200 200

•
Serial, A, B, C, 0,
High-level 10 10
IIH Clock 1 or 2 VCC = MAX, VI = 2.4 V IlA
input current
Mode control 20 20
Serial, A, B, C, 0,
Low-level -0.18 -0.18
IlL clock 1 or 2 VCC = MAX, VI = 0.3 V mA
Input current
l Mode control i i -0.36 -0.361 1
lOS Short-circuit output current § VCC = MAX -3 -15 -3 -15 mA

ICC Supply current VCC = MAX, See Note 4 3.8 9 3.8 9 mA I

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAli typical values are at Vee = 5 V, T A = 25°C.
§Not more than one output should be shorted at a time.
NOTE 4: Ice is measured with all outputs and serial input open; A, S, e,. and D inputs grounded; mode control at 4.5 V; and a momentary
3 V, then ground, applied to both clock inputs.

switching characteristics, Vee = 5 V, TA = 25°e

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f max Maximum clock frequency 3 5 MHz
CL = 5OpF, RL =4 kil,
tpLH Propagation delay time, low-to-high-Ievel output from clock 115 200 ns
See Figure 1
tpHL Propagation delay time, high-to-Iow-Ievel output from clock 125 200 ns

1076

7-92 TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54LS95B, SN74LS95B
4-BIT PARALLEL-ACCESS SHIFT REGISTERS
REVISED OCTOBER 1976

recommended operating conditions

SN54LS95B SN74LS95B
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -400 -400 /LA
Low-level output current, 10L 4 8 mA
Clock frequency, fclock 0 25 0 25 MHz
Width of clock pulse, tw(clock) (see Figure 1) 25 25 ns
Setup time, high-level or low-level data, tsu (see Figure 1) 20 20 ns
Hold time, high-level or low·level data, th (see Figure 1) 20 10 ns
Time to enable clock 1, tenable 1 (see Figure 2) 20 20 ns
Time to enable clock 2, tenable 2 (see Figure 2) 20 20 ns
Time to inhibit clock 1, tjnhibit 1 (see Figure 2) 20 20 ns
Time to inhibit clock 2, tinhibit 2 (see Figure 2) 20 20 ns
--,.., ...
! Op",,,ung
~ o. - ..... - TA
Ir"" air L"mp"ratur", _.r:;
5 ... , .. 5
'''1 n ..,,0 Or-
" !

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS95B SN74LS95B
PARAMETER TEST eONDITIONSt
MIN TYP:j: MAX MIN TYP:j: MAX UNIT
VI H High-level input voltage 2 2 V
VI L Low-level input voltage 0.7 0.8 V
V IK I nput clamp voltage Vee- MIN, 11'= -18 mA -1.5 -1.5 V
Vee= MIN,
VOH High-level output voltage 2.5 3.4 2.7 3.4 V
VIL = VIL max, 10H = -400/LA

Vee = MIN, IIOL = 4 mA 0.25 0.4 0.25 0.4

I VOL Lovl.J-!eve! output vo!tage V;H = 2 V, 11-------+----------1--------1 V
VIL = VIL max 10L = 8 mA 0.35 0.5 I
Input current at

•
Vee = MAX, 0.1 0.1 mA
maximum input voltage
High-level
IIH Vee= MAX, VI = 2.7 V 20 20 /LA
input cu rrent
Low-level
IlL Vee = MAX, VI = 0.4 V -0.4 -0.4 mA
input current
lOS Short-circuit output current§ Vee= MAX -20 -100 -20 -100 mA
ICC Supply current Vee - MAX, See Note 4 13 21 13 21 mA

:For conditions shown as MIN or MAX, use othe appropriate value specified under recommended operating conditions.
+AII typical values are at V CC = 5 V, T A = 25 C.
§ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
NOTE 4: ICC is measured with all outputs and serial input open; A, B, C, and D inputs grounded; mode control at 4.5 V; and a momentary
3 V, then ground, applied to both clock inputs.

switch ing characteristics, Vee = 5 V, TA = 25° C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f max Maximum clock frequency 25 36 MHz
eL = 15 pF, RL=2kn,
tpLH Propagation delay time, low-to-high-Ievel output from clock 18 27 ns
See Figure 1
tpHL Propagation delay time, high-to-Iow·level output from clock 21 32 ns

1076
TEXAS INCORPORATED
INSTRUMENTS 7-93
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN5495A, SN54L95, SN54LS95B, SN7495A, SN74L95, SN74LS95B
4-BIT PARALLEL-ACCESS SHIFT REGISTERS

PARAMETER MEASUREMENT INFORMATION

TEST
POINT VCC

RL

____ __ (See Note D)

~~~~~~;:~T

(See Note CL
B) T
~~~~

':' r
;
-I~~"~
~ C1
(See Note C)

LOAD CIRCUIT

!- tw(data) ....eoJ
tr - , I-- --I I-- tf I I
DATA
INPUT
J"10%-9O'J(,---~-r-ef"110% l"V-re-f---""'f= - - --::
I- tsu -I I- t i tsu
thT I th

I I
CLOCK 1 OR 2
INPUT
Vref
I I OV
1---4--- tw(clock)

I VOH

! ~,-v_re_f_...:..!_.JI.~re~ n _ Voc
tPHL ~ I----t- tPLH

NOTES: A. Input pulses are supplied by a generator having the following characteristics: tr <;;; 10 ns, tf <;;; 10 ns, and Zout '" 50 For the n.
data pulse generator, PRR = 500 kHz; for the clock pulse generator, PRR = 1 MHz. When testing f max , vary PRR. For '95A,
tw(data);;' 20 ns; tw(clock);;' 15 ns. For 'L95, tw(data);;' 150 ns; tw(clock) ;;'200 ns. For 'LS95B, tw(data);;' 20 ns,

•
tw(clock) ;;. 15 ns.
B. CL includes probe and jig capacitance.
C. C1 (30 pF) is applicable for testing' L95.
D. All diodes are 1N916 or 1N3064.
E. For '95A, V ref = 1.5 V; for 'L95 and 'LS95B, V ref = 1.3 V.

VOLTAGE WAVEFORMS
FIGURE 1-SWITCHING TIMES

- - - - - - - - - - VIH
SERIAL
INPUT _ _ _ _ _- - - VIL

_--_ ,._ _ _ _ _ VIH

\\.-_--J1 - - - VIL

INPUT ' -_ _ _ _ _ _ _ VIL

'-------..j~ :::
CLOCK 2 tinhibit 2
INPUT

QA OUTPUT
_ _ _ _ _ _ _J 1- - \ ~ _ _ _ _J 1 L VOH
VOL

NOTES: A. Input A is at a low level.

B. For '95A, Vref = 1.5 V; for 'L95 and 'LS95B, Vref = 1.3 V.

VOLTAGE WAVEFORMS
FIGURE 2-CLOCK ENABLE/INHIBIT TIMES

1076

7·94 TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN5496. SN54L96. SN54LS96.
TTL SN7496. SN74L96, SN74LS96
MSI 5-81T SHIFT REGISTERS
BULLETIN NO. DL-S 7611821, MARCH 1974-REVISED OCTOBER 1976

SN5496, SN54LS96 ••. J OR W PACKAGE

• N-Bit Serial-To-Parallel Converter SN54L96 .•• J PACKAGE
SN7496, SN74L96, SN74LS96 ... J OR N PACKAGE
• N-Bit Parallel-To-Serial Converter (TOP VIEW)

• N-Bit Storage Register

TYPICAL
TYPE PROPAGATION TYPICAL
DELAY TIME POWER DISSIPAT!ON
'96 25 ns 240mW
'L96 50 ns 120mW
'LS96 25 ns 60mW
description
These shift registers consist of five R-S master-slave
flip-flops connected to perform parallel-to-serial or
serial-to-parallel conversion of binary data. Since both
inputs and outputs for all flip-flops are accessible,
parallel-in/parallel-out or serial-in/serial-out operation
CLOCK • ABC , VCC • D E . !,_R~~EI
may b~ p~rformed. ~ '--------y---J ~NP,~L.t:

PRESET PRESET

All flip-flops are simultaneously set to a low output

positive logic: see function table
level by applying a low-level voltage to the clear input
while the preset is inactive (low). Clearing is independent of the level of the clock input.

The register may be parallel loaded by using the clear input in conjunction with the preset inputs. After clearing all
stages to low output levels, data to be loaded is applied to the individual preset inputs (A, B, C, D, and E) and a
high-level load pulse is applied to the preset enable input. Presetting like clearing is independent of the level of the clock
input.

Transfer of information to the outputs occurs on the positive-going edge of the clock pulse. The proper information

•
must be set up at the R-S inputs of each flip-flop prior to the rising edge of the clock input waveform. The serial input
provides this information to the first flip-flop, while the outputs of the subsequent flip-flops provide information for
the remaining R-S inputs. The clear input must be high and the preset or preset enable inputs must be low when
clocking occurs.

FUNCTION TABLE
INPUTS OUTPUTS
PRESET PRESET
CLEAR CLOCK SERIAL QA QB QC QD QE
ENABLE A B C D E
L L X X X X X X X L L L L L
L X L L L L L X X L L L L L
H H H H H H H X X H H H H H
H H L L L L L L X QAO QBO QCO QOO QEO
H H H L H L H L X H QBO H QOO H
H L X X X X X L X QAO QBO Oeo QOO QEO
H L X X X X X t H H QAn QBn QCn QDn
H L X X X X X t L L QAn QBn QCn QDn

H = high level (steady state), L = low level (steady state)

X = irrelevant (any input, including transitions)
t = transition from low to high level
QAO, QBO, etc = the level of QA, QB, etc, respectively before the indicated steady-state input conditions were established.
QAn, QBn, etc = the level of QA, QB, etc, respectively before the most-recent t transition of the clocl<.

1076

TEXAS INSTRUMENTS 7-9S

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN5496. SN54L96. SN54LS96.
SN7496. SN74L96. SN74LS96
5-81T SHIFT REGISTERS
typical clear, shift, preset, and shift sequences

CLOCK

CLEAR -U 1
I 1
SERIAL I rt--lL._________________________________________________________
INPUT _--+-1-----'. I .
PRESET: 1
ENABLE ---TI------+-------------------------~i
n 1.. ______________
A : ri;l~___________________
1 1
B
:
I
~~--------------------
1
PRESETS c I l L
1 :
D
: : ~~-------------
I : 1 L

---,
I 1
.----,IL.___________________________ I I11..__________________
:
OA __ ~I ____ ~I ~,

__ ~.----, ; - 1_ _. . . . . ,

OB ___ I I I I '--_________
--~ .----, :I
OUTPUTS Oc _ I I I
-- -1
00 ___ I
.----,
I I
I----,L--..JI
I L-
--~ r--1 1 ~.
H ~
J
L

•
OE ___ I I I I I H H

I 1--------
.. SHIFT 1
- - - - - - - - - - - -.. 1 - SHIFT-
CLEAR PRESET

functional block diagram

~. dynamic input activated by transition from a high level to a low level.

1076

7·96 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN549S, SN54L9S, SN54LS9S,
SN749S, SN74L9S, SN74LS9S
5-81T SHIFT REGISTERS
REVISED OCTOBER 1976

schematics of inputs and outputs

'96 '96

EQUIVALENT OF TYPICAL OF
EACH INPUT ALL OUTPUTS

Vcc -----4~--

INPUT

INPUT Req NOM

Preset enable 800 n
All others 4 kn

'L96 'L96

EQUIVALENT OF TYPICAL OF
EACH INPUT ALL OUTPUTS

V CC -----4~--
---s
--~VCC

2600 NOM

iNPUT
_t(oUTeUT
INPUT
Preset enable
Req NOM
1.6 kn
II
All others 8 kn

'LS96 'LS96

EQUIVALENT OF TYPICAL OF-

EACH INPUT ALL OUTPUTS
V C C - - -....- - -----~~-VCC

Req

INPUT ---4H.... - - - . -

' - - -....- OUTPUT

INPUT Req NOM

Serial 25 kn
Clock, Clear 17 kn
Preset enable 3.4 kn

1076

TEXAS INCORPORATED
INSTRUMENTS 7-97
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN5496. SN7496
5-BIT SHIFT REGISTERS

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) 7V
Input voltage (see Note 2). . . .'. . . . . 5.5 V
Operating free-air temper"ture range: SN5496 -55°C to 125°C
SN7496 aOe to 7aoe
Storage temperature range -65°C to 15aoe
NOTES: 1, Voltage values are with respect to network ground terminal.
2. Input voltages must be zero or positive with respect to network ground terminal.

recommended operating conditions

SN5496 SN7496
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -400 -400 !J.A
Low-level output current, 10L 16 16 mA
Clock frequency, fclock 0 10 0 10 MHz
Width of clock input pulse, tw(clock) 35 35 ns
Width of preset and clear input pulse, tw 30 30 ns
Serial input setup time, tsu (see Figure 1) 30 30 ns
Serial input hold time, th (see Figure 1) 0 0 ns
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN5496 SN7496
PARAMETER TEST CONDITIONSt UNIT
MIN TYPt MAX MIN TYP:j: MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
Vee - MIN, VIH-2V,
VOH High-level output voltage 2.4 3.4 2.4 3.4 V
VIL = 0.8 V, 10H = -4oo!J.A

II VOL

II
Low-level output voltage

Input current at maximum input voltage

Vee- MIN,
VIL = 0.8 V,
Vee = MAX,
VIH - 2 V,
10L = 16mA
VI = 5.5 V
0.2 0.4

1
0.2 0.4

1
V

mA
any input except
40 40
, IIH High-level input current preset enable I Vee= MAX, Vi = 2.4 V !l.A. I

preset enable 200 200

any input except
-1.6 -1.6
IlL Low-level input current preset enable Vee = MAX, VI = 0.4 V mA
preset enable -8 -8
lOS Short-circuit output current§ Vee = MAX -20 -57 -18 -57 mA
ICC Supply current Vee- MAX, See Note 3 48 68 48 79 mA

tFor conditions shown at MIN or MAX, use the appropriate value specified under recommended operating conditions.
0
tAli typical values are at V CC = 5 V, T A = 25 C.
§ Not more than one output should be shorted at a time.
NOTE 3: ICC is measured with the clear input grounded and all other inputs and outputs open.

switching characteristics, Vee = 5 V, TA = 25°e

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay time, low-to-high-Ievel output from clock 25 40 ns
eL=15pF,
tpHL Propagation delay time, high-to-Iow-Ievel output from clock 25 40 ns
RL=4oon,
tPLH Propagation delay time, low-to-high-Ievel output from preset or preset enable 28 35 ns
See Figure 1
tpHL Propagation delay time, high-to-Iow-Ievel output from clear 55 ns

7-98 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54L96. SN74L96
5-811 SHIFT REGISTERS

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . 7V
Input voltage (see Note 2) . . . . . 5.5V
Operating free·air temperature range: SN54L96 -55°C to 125°C
SN74L96 oOe to 70°C
Storage temperature range -65°C to 150°C
NOTES: 1. Voltage values are witR respect to net'l\Iork ground terminal.
2. Input voltage must be zero or positive with respect to network ground terminal.

recommended operating conditions

SN54L96
SN74L96
1-------+----------1
MIN
UNIT
NOM MAX MIN NOM MAX
Supply voltage, V CC 4.5 5 5.5 4.75 5 5.25 V
High·level output current, 10H -200 -200 /lA
Low-level output current, 10L 8 8 mA
Clock frequency, fclock o 5 o 5 MHz
Width of clock, preset, or clear input pulse, tw 100 100 ns
Serial input setup t!me, tsu (~ee Figure 1) • tv.
IVV ioa ns
Serial input hold time, th (see Figure 1) o o ns
Operating free-air temperature, T A -55 125 o

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54L96 SN74L96
PARAMETER TEST CONDITIONSt UNIT
MIN TYP:j: MAX MIN TYP:j: MAX
VIH High·level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
Vee = MIN, VIH = 2 V, I
VOH High-level output voltage 2.4 3.2 2.4 3.2 V
VIL = 0.8 V, 10H = -200 IJ.A I
Vce= MIN, VIH=2V,
Low-level output voltage 0.2 0.4 0.2 0.4 V

•
VOL
VIL = 0.8 V, 10L = 8 mA
II Input current at maximum input voltage Vce = MAX, VI = 5.5 V 1 1 mA
any input except
20 20
IIH High-level input current preset enable VCC= MAX, VI = 2.4 V IJ.A
preset enable 100 100
any input except
-0.8 -0.8
IlL Low-level input current preset enable Vec = MAX, VI = 0.4 V mA
preset enable -4 -4
lOS Short-circuit output current§ Vee= MAX -10 -29 -9 -29 mA
lee Supply current Vce= MAX, See Note 3 24 34 24 40 mA

{For co~ditions shown at M IN or MAX, use t~e appropriate value specified under recommended operating conditions.
All typical values are at V CC = 5 V, T A = 25 C.
§Not more than one output should be shorted at a time.
NOTE 3: ICC is measured with the clear input grounded and all other inputs and outputs open.

switching characteristics, Vee = 5 V, TA = 25°e

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tpLH Propagation delay time, low-to-high-Ievel output from clock 50 80 ns
CL = 15pF,
tpHL Propagation delay time, high-to-Iow-Ievel output from clock 50 80 ns
RL = 800 n,
tPLH Propagation delay time, low-to-high-Ievel output from preset or preset enable 56 70 ns
See Figure 1
tpHL Propagation delay time, high-to-Iow-Ievel output from clear 110 ns

1076

TEXAS INCORPORATED
INSTRUMENTS 7-99
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54LS96. SN74LS96
5-81T SHIFT REGISTERS
REVISED OCTOBER 1976

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) 7V
Input voltage . . . . . . . 7V
Operating free-air temperature range: SN54LS96. -55°C to 125°C
SN74LS96. aOe to 7aoe
Storage temperature range -65°C to 15aoe
NOTE1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54LS96 SN74LS96
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage. VCC 4.5 5 5.5 4.75 5 5.25 V
High·level output current, 10H -400 -400 IJA
Low·level output current, 10L 4 C rnA
Clock frequency, fclock 0 25 0 25 MHz
Width of clock input pulse, tw(clock) 35 35 ns
Width of preset and clear input pulse, tw 30 30 ns
Serial input setup time, tsetup (see Figure 1) 30 30 ns
Serial input hold time, thold (see Figure 1) 0 0 ns
Operating free-air temperature, T A -55 125 0 70 °c

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS96 SN74LS96
PARAMETER TEST CONDITIONSt UNIT
MIN TYP:!: MAX MIN TYP:!: MAX
VIH High.level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
VIK I nput clamp voltage Vee: MIN, 11:-18mA -1.5 -1.5 V

•
Vee: MIN, VIH: 2V,
VOH High-level output voltage 2.5 3.5 2.7 3.5 V
VIL: VIL max, 10H: -400 IJA
Vee: MIN, VIH:2V, IIOL :4mA 0.25 0.4 0.25 0.4
VOL Low-level output voltage V
VIL: VIL max IIOL :8mA 0.35 0.5
I nput current 0.5
Preset enable 0.5 I
Vee: MAX, VI :7V
il at maximum rnA ,
input voltage I All others 0.1 0.1 :

High-level Preset enable 100 100

IIH input current Vee: MAX, VI =2.7 V IJA
All others 20 20
Low-level Preset enable -2 -2.
IlL input cu rrent Vee = MAX, VI = 0.4 V rnA
All others -0.4 -0.4
lOS Short-circuit output current§ Vee: MAX -20 -100 -20 -100 mA
lee Supply current Vee: MAX, See Note 3 12 20 12 20 mA

IFor conditions shown at MIN or MAX. use t~e appropriate value specified under recommended operating conditions.
All typical values are at V CC : 5 V, T A: 25 C.
§ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
NOTE 3: ICC is measured with the clear input grounded and all other inputs and outputs open.

switching characteristics, Vee = 5 V, TA = 25°e

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tpLH Propagation delay time, low-to-high-Ievel output from clock 25 40 ns
eL: 15 pF,
tpHL Propagation delay time, high-to-Iow-Ievel output from clock 25 40 ns
Propagation delay time, low-to-high-Ievel output from preset or preset enable
i'lL = 2 kn,
tPLH 28 35 ns
See Figure 1
tPHL Propagation delay time, high·to-Iow-Ievel output from clear 55 ns

1076

7-100 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN5496, SN54L96, SN54LS96,
SN7496, SN74L96, SN74LS96
5-81T SHIFT REGISTERS
PARAMETER MEASUREMENT INFORMATION

OUTPUT Vee

FROM OUTPUT (See Note e)

UNDER TEST

T
eL~15PF
':' (See Note B)

LOAD CIRCU!T

f-- tw(dear) ---t

CLEARINPU~ V
PRR';;; 1 MHz 1\ ref
,I
r---------~S ~S-----------------------3V
Vref
--------------------------OV
I
I

PRESET INPUT
PRR';;; 1 MHz
(See Note D)
I
I
I

---+I-----------------'i5 .,.S_ _ _ _ _ _ _ _ _ _ _ _ J.
iI Vref
~ 3V
I Vref
I 0V
I ~tw(preset)-l
I t--tw l clockj--4f _tw(clockl--! !
I I Ir---~5~ I I 3V
CLOCK INPUT
PRR';; 1 MHz ! \V<Of I:V"f 'V~f 4~~u-~---_uov
r-
I 11...1
SERIALINPU~I
I
PRR .;;; 1 MHz
'-J
I

I V ref
-I

I
j+- th

V ref,'
--1
-II
II
I V
th I
I
I
3V II
I I , ' ref I
I I-tsu ....I""" -----T------OV
t----------t-
tpH L
_ _ _ ___. : (See Note FI
!. 'I
I
tPL H
5
L-
~ 'I tpHL
I.----.r- tPLH
I r---- V
°AOUTPUT
(See Note E) I V,of I V"f '\V,of ! V,,-, n v::
VOLTAGE WAVEFORMS

NOTES: A. Input pulses are supplied by pulse generators having the following characteristics: duty cycle';; 50%, Zout "" 50 n; for '96 and
'L96, tr .;; IOns, tf .;; IOns, and for' LS96 tr = 15 ns, tf = 6 ns.
B. CL includes probe and jig capacitance.
C. All diodes are 1 N3064 or 1 N916,
D. Preset may be tested by applying a high-level voltage to the individual preset inputs and pulsing the preset enable or by applying a
high-level voltage to the preset enable and pulsing the individual preset inputs.
E. QA output is illustrated. Relationship of serial input to other 0 outputs is illustrated in the typical shift sequence.
F. Outputs are set to the high level prior to the measurement of tpH L from the clear input.
G. For '96 and' L96, V ref = 1.5 V; for' LS96 V ref = 1.3 V.

FIGURE 1-SWITCHING TIMES

1076

TEXAS INSTRUMENTS 7-101

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TIL TYPES SN5497, SN7497
MSI SYNCHRONOUS 6-BIT BINARY RATE MULTIPLIERS
BULLETIN NO. DL-S 7611 • DECEMBER 1972-REVISED OCTOBER 1976

SN5497 •.• J OR W PACKAGE

• Perform Fixed-Rate or Variable-Rate
Frequency Division
SN7497 .•• J OR N PACKAGE
(TOP VIEW)

• For Applications in Arithmetic, Radar,

Digital-to-Analog (0/ A), Analog-to-Digital Vee
RATE INPUTS

~
UNITY! ENABLE
CLEAR CASCADE INPUT

(A/D), and other Conversion Operations

• Typical Maximum Clock Frequency ... 32

Megahertz

description

These monolithic, fully synchronous, programmable

counters utilize Series 54/74 TTL circuitry to achieve
32-megahertz typical maximum operating frequen-
cies. These six-bit serial binary counters feature
buffered clock, clear, and enable inputs to control the
operation of the counter, and a strobe input to enable
or inhibit the rate input/decoding AND·OR-INVERT positive logic: see description
gates. The outputs have additional gating for
cascading and transferring unity-count rates.

The counter is enabled when the clear, strobe, and enable inputs are low. With the counter enabled, the output
frequency is equal to the input frequency multiplied by the rate input M and divided by 64, ie.:

M-f·1n
fout = 64

where: M = F-2 5 + E-2 4 + D-2 3 + C-2 2 + B-2 1 + A-2 0

When the rate input is binary a (all rate inputs lowl. Z remains high. In order to cascade devices to perform 12·bit rate
multiplication, the enable output is connected to the enable and strobe inputs of the next stage, the Z output of each

I stage is connected to the unity/cascade input of the other stage, and the sub·multiple frequency is taken from the Y
output.

The unity/cascade input, when connected to the clock input, may be utilized to pass the clock frequency (inverted) to
the Y output when the rate input/decoding gates are inhibited by the strobe. The unity/cascade input may also be used
as a control for the Y output.
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS

-----VCC
VCC------~.-------

OUTPUT

Ciock input: Req = 2 kn NOM

Other inputs: Req = 4 kn NOM

1076

7-102 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALL.AS. TEXAS 75222
 TYPES SN5497, SN7497
SYNCHRONOUS 6-BIT BINARY RATE MULTIPLIERS

description (continued)
STATE AND/OR RATE FUNCTION TABLE (See Note A)

INPUTS OUTPUTS
LOGIC LEVEL OR
BINARY RATE NUMBER OF PULSES
NUMBER OF UNITY/
CLEAR ENABLE STROBE F E D C B A CLOCK PULSES CASCADE Y Z ENABLE NOTES
H X H X X X X X X X H L H H B
L L L L L L L L L 64 H L H 1 C
L L L L L L L L H 64 H 1 1 1 C
L L L L L L L H L 64 H 2 2 1 C
L L • L L L L H L L 64 H 4 4 1 C
L L L L L H L L L 64 H 8 8 1 C
L L L L H L L L L 64 H 16 16 1 C
L L L H L L L L L 64 H 32 32 1 C
L L L H H H H H H 64 H 63 63 1 C
L L L H H H H H H 64 L H 63 1 D
L L L H L H L L L !
64 !
H !
40 !
40 !
1 !
E I
!

NOTES: A. H = high level, L'= low level, X = irrelevant. All remaining entries are numeric counts.
B. This is a simplified illustration of the clear function. The states of clock and strobe can affect the logic level of Y and Z. A low
unity/cascade will cause output Y to remain high.
C. Each rate illustrated assumes a constant value at rate inputs; however, these illustrations in no way prohibit variable-rate inputs.
D. Unity/cascade is used to inhibit output Y.
Mofin (8 + 32) fin 40 fin
E. f out = M = --6-4-- = ~ = 0.625 fin'

functional block diagram

II

1272

TEXAS INCORPORATED
INSTRUMENTS 7-103
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN5497, SN7497
SYNCHRONOUS 6-BIT BINARY RATE MULTIPLIERS

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ......... . 7V
Input voltage . . . . . . . ......... . 5.5 V
Operating free·air temperature range: SN5497 (see Note 2) -55°e to 125°e
SN7497 oOe to 700e
c 0
Storage temperature range -65 e to 150 e

recommended operating conditions

SN5497 SN7494
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, VCC 4.5 5 5.5 4.75 5 5.25 V
High-level output current, IOH -400 -400 /lA
Low-level output current, IOL 16 16 mA
Clock frequency, f clock 0 25 0 25 MHz
Width of clock pulse, tw(clock) 20 20 ns

Width of clear pulse, tw(clearl 15 15 ns

Enable setup time, tsu: (See Figure 1)
Before positive-going transition of clock pulse 25 25 ns
Before negative-going transition of previous clock pulse 0 t w (clock)-10 0 t W (clock)-10
Enable hold time, th: (See Figure 1)
After positive-going transition of clock pulse 0 tw(clock)-10 0 t w (clock)-10 ns
After negative-going transition of previous clock pulse 20 t cp -10 20 tcp-10
Operating free-air temperature, T A (See Note 2) -55 125 0 70 °c

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONSt MIN TYP+ MAX UNIT
V IH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V

II VIK

VOH
Input clamp voltage

High-level output voltage

Vcc; MIN,
Vcc; MIN,
II; -12 mA
VIH;2V,
2.4 3.4
-1.5 V

V
VIL; 0.8 V, IOH; -400 /lA
, Vee = MIN VIH; 2 V
v
VOL Low-level output voltage
IVIL;0.8~, IOL; 16mA
0.2 0.4

II Input current at maximum input voltage Vcc; MAX, VI; 5.5 V mA

clock input 80
High-level input current Vcc; MAX, VI; 2.4 V p.A
other inputs 40
clock input -3.2
Low-level input current Vee; MAX, VI; 0.4 V ~------------~ mA
other inputs --1.6
lOS Short circuit output current § Vee; MAX -18 -55 mA
IceH Supply current, outputs high Vcc; MAX, See Note 3 58 mA
ICCL Supply current, outputs low Vee; MAX, See Note 4 80 120 mA

tFor test conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at VCC; 5 V, T A; 25°C.
§ Not more than one output should be shorted at a time.
NOTES: 1. Voltage values are with respet to network ground terminal.
2. An. SN5497 in the W pack.age operating at free-air tem~eratures above 11SoC requires a heat sink that provides a thermal
resistance from case to free-air, ReCA, of not mOre than 55 C/W_
3. ICCH is measured with outputs open and all inputs grounded.
4. !CCL is measured with outputs open and all inputs at 4.5 V.

1076

7-104 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN5497, SN7497
SYNCHRONOUS 6-BIT BINARY RATE MULTIPLIERS
REVISED OCTOBER 1976

switching characteristics, VCC = 5 V, TA = 25°C, N = 10

FROM TO
PARAMETERS~ TEST CONDITIONS MIN TYP MAX UNIT
INPUT OUTPUT
f max 25 32 MHz
tPLH 13 20
Enable Enable ns
tPHL 14 21
tPLH 12 18
Strobe Z ns
tpHL 15 23
tpLH 26 39
Clock Y ns
tpHL 20 30
tPLH 12 18
Clock Z ns
tpHL 17 26
tpLH CL=15pF, 6 10
Rate Z ns
tpHL RL = 400 n, 9 14
See Figure 1
Unity/Cascade Y
tpHL
·rL,.n
Strobe Y I ." .:IV I
ns
I tpHL
tPLH
I I I 22
19
33
30
tpHL
Clock Enable
I 22 33 I ns

tpLH Y 24 36
Clear ns
tpHL Z 15 23
tpLH 15 23
Any Rate Input Y ns
tpHL 15 23 I

~ f max
== maximum clock frequency.
tpLH == propagation delay time, low·to·high·level output.
tpHL == propagation delay time, high-to-Iow-Ievel output.

TYPICAL APPLICATION DATA

•
This application demonstrates how the '97 can be cascaded to perform 18-bit rate multiplication. This scheme is
expandable to n-bits by extending the pattern illustrated.
18-BIT RATE INPUT

CLEAR
ENABLE (LOW)
DISABLE (HIGH)
ENABLE (LOW)
DISABLE (HIGH)

CLOCK
INPUT-J1------~.--+---+----------------~--+-------------~

INVERTED OUTPUT NONINVERTED OUTPUT

As illustrated, two of the 6-bit multipliers can be cascaded by connecting the Z output of unit A to the unity cascade
input of unit B, in which case, a two-input NOR gate is used to cascade the remaining multipliers. Alternatively, all three
Y outputs can b~ cascaded with a 3-input NOR gate. The three unused unity ~ascade inputs can be conveniently
terminated by connecting each to its Z output.

1076

TEXAS INCORPORATED
INSTRUMENTS 7-105
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN5497, SN7497
SYNCHRONOUS 6-BIT BINARY RATE MULTIPLIERS

PARAMETER MEASUREMENT INFORMATION

~
3V
VCC
ENABLE '.5 V 1.5 V
INPUT I ------OV
l............-.tpHL I
OUTPUT OF DEVICE ~ Ie---ej-tpLH
---4H111t+i...-t...-t,.,

~
UNDER TEST IVOH
ENABLE 1.5 V '.5 V
OUTPUT ___ VOL

All three outputs are loaded during testing Flip-flops are at the maximum count.
Other inputs are 'ow.
LOAD CIRCUIT
PROPAGATION DELAY TIMES,
ENABLE INPUT TO ENABLE OUTPUT
r---ENABLED~;---DISABLED--

:--'WlciOCkl~ ~'WlciOCkl"

~::
I I I I
3V CLOCK OR
I I I I
CLOCK STROBE

j.-.+-"'LH I.....-tpHL

I.- >10 ns ! 1c--ft.: ~- VOH

OUTPUT Z
~'SV i \::..
~tPHL i VOL
1.SV
I ,.......-..rtPLH

~ .... L VOH

~~~~
1\---------
OUTPUT Y
----VOL
VOH Unity/cascade and rate inputs are high, other inputs are low,
OUTPUT Y
and flip-flops are at any count other than maximum.
_ _ _ _ _ _ _ _---J. \"'.- - - - - VOL
PROPAGATION DELAY TIMES, CLOCK TO Z AND Y,
ENABLING FROM POSITIVE-GOING AND STROBE INPUT TO Z AND Y
TRANSITION OF CLOCK PULSE

-DISABLED, ;--ENABLED~r--DISABLED-­

"'wlcloCkr-l---tq>~ RATE INPUT ~3V

I I I
I I I I---t-'PHL I OV
I I

•
I I ~tPLH
CLOCK

I
OUTPUT Z
~
~~.~~
__ . r VOH

I~'h ---VOL
',u ---..4 t-- I
Flip-flops are at a count so that all other inputs to the gate
I I 3V

~N~~~L~~~
under test are high and all other inputs. including other rate
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ OV inputs, are low.

PROPAGATION DELAY TiMES,

RATE INPUT TO Z

OUTPUT Y

UNITY/CASCA::-\',5V ';:::-3 V

ENABLING FROM NEGATIVE-GOING INPUT ~~'~~---OV

TRANSITION OF PREVIOUS CLOCK PULSE to--.,- h 'PHL

~
1. Unity/Cascade and pin 2 (rate input) are high, other inputs -I---VO'"
are low. Clear the counter and apply clock and enable OUTPUTY '5V '5V

pulse as illustrated. VOL

2. Setup and hold times are illustrated for enabling a single Output Z is high.
clock pulse (count). Continued application of the enable
function will enable subsequent clock pulse (counts) until PROPAGATION DELAY TIMES,
disabling occurs (enable goes high). The total number of UNITY/CASCADE INPUT TO Y
counts will be determined by the total number of
positive-going clock transition enabled.

NOTES: A. The input pulse generator has the following characteristics: tw(clock) = 20 ns, tTLH .;;; 10 ns. tTHL .;;; 10 ns. PRR =1 MHz,
Zout '" 50 n.
B. CL includes probe and jig capacitance.
C. All diodes are 1 N3064.
FIGURE 1-SWITCHING TIMES

1076

7-106 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TTL TYPES SN54L98, SN14L98
MSI 4-81T DATA SELECTORS/STORAGE REGISTERS
BULLETIN NO. DL-S 72111322, DECEMBER 1972

SN54L98 ••• J PACKAGE

SN74L98 ••• J OR N PACKAGE
(TOP VIEW)

description

These monolithic data selectors/storage registers are

composed of four S-R master-slave flip-flops, four
CLOCK
AND-OR-!NVERT gates, one buffer, and six
WORD
inverter/drivers. SELECT

When the word select input is low, word 1 (A 1 , 81,

C1, 01) is applied to the flip-flops. A high input to
word select will cause the selection of word 2
(A2, 82, C2, D2). The selected word is shifted to the
QutPl)t terminals on the negative-going edge of the , A2 Ai 61 82 Ci C2 02 I GNIJ
clock pulse.

Typical power dissipation is 25 mW. The SN54L98 is positive logic: word select low for word 1,
characterized for operation over the full military word select high for word 2,
see descri ption
temperature range of -55°C to 125°C; the SN74L98
is characterized for operation from O°C to 70°C.

functional block diagram and schematics of inputs and outputs

EQUIVALENT OF EACH INPUT

V C C - - -.....- - -
CK

INPUT
I
(14)
OB OB

CK

Dc (131 Dc TYPICAL OF ALL OUTPUTS

CK

(111
00 00

CK

CLOCK~(~10~1------------------~C>~----------~

--<J> ... dynamic input activated by transition from a high level to a low level.
I

1076

TEXAS INSTRUMENTS 7-107

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54L98. SN74L98
4-81T DATA SELECTORS/STORAGE REGISTERS

absolute maximu m ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, Vee (see Note 1) ..... 8V

Input voltage (see Note 2) . . . . . 5.5 V
Operating free-air temperature range: SN54L98 -55°C to 125°C
SN74L98 aOe to 7aoe
Storage temperature range -65°C to 15aoe
NOTES: 1. Voltage values are with respect to network ground terminal.
2_ Input voltages must be zero or positive with respect to network ground terminal.

recommended operating conditions

SN54L98 SN74L98
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -100 -200 /l-A
Low-level output current, 10L 2 3.6 mA
Width of clock pulse, tw(clock) 200 200 ns
at A, B, e, or 0 100 100
Setup time for high-level data, tsu(H) ns
at word select 150 150
at A, B, e, or 0 120 120
Setup time for low-level data, tsu(L) ns
at word select 100 100
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54L98 SN74L98
PARAMETER TEST eONDITIONSt UNIT
MIN TVP+ MAX MIN TVP+ MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.7 V
Vee = MIN, VIH = 2V,
VOH High-level output voltage 2.4 3.3 2.4 3.2 V
VIL = 0.7 V, 10H = MAX

I VOL

II
Low-level output voltage

Input current at maximum input voltage

Vee
VIL
= MIN,
= 0.7 V,
Vee - MAX,
VIH = 2V
10L = MAX
VI- 5.5 V
0.15 0.3

100
0.2 0.4

100
V

/l-A
IIH High-level input current Vee - MAX, VI = 2.4 V 10 10 /l-A
ilL Low-ievei input current Vee - ~1AX, Vi - 0.3 V -0.18 -0.18 mA I
lOS Short-circuit output current§ Vee - MAX -3 -15 -3 -15 mA
lee Supply current Vee - MAX, See Note 3 5 9 5 9 mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at Vee = 5 V, TA = 25°e.
§ Not more than one output should be shorted at a time.
NOTE 3: I ee is measured with all inputs grounded and all outputs open.

switching characteristics, Vee = 5 V, T A = 25° C

PARAMETER TEST eONDITIONS MIN TVP MAX UNIT
f max Maximum clock frequency 3 5 MHz
Propagation delay time, low-to-
tPLH CL=50pF, RL = 4 k.l1., 115 200 ns
high-level output from clock input
See Note 4
Propagation delay time, high-to-
tpHL 125 200 ns
low-level output from clock input

NOTE 4: Load circuit and voltage waveforms are shown on page 3-11.

PRINTED IN USA 1076

1-108 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 TEXAS INSTRUMENTS RESERVES THE RIGHT TO MAKE CHANGES AT ANY TIME
IN ORDER TO IMPROVE DESIGN AND TO SUPPLY THE BEST PRODUCT POSSIBLE.
 TTL TYPES SN54L99, SN74L99
MSI 4-81T RIGHT-SHIFT LEFT-SHIFT REGISTERS
BULLETIN NO. DL-S 7211871. DECEMBER 1972

SN54L99 ••. J PACKAGE

• N-Bit Serial-to-Parallel Converter SN74L99 ••• J OR N PACKAGE
(TOP VIEW)
• N-Bit Parallel-to-Serial Converter
• N-Bit Storage Register
• J-K Serial Input
description
These 4-bit registers feature parallel inputs, parallel
outputs, J-K serial inputs, mode control, and two
clock inputs. The registers have three modes of
operation:
Parallel (Broadside) load
Shift right (the direction GA toward GO)
Shift left (the direction GO toward GAl
Parallel loading is accomplished by applying the four
bits of data and taking the mode control input high. e vee D
The data is loaded into the associated flip-flop and
appears at the outputs after the high-to-Iow transition
of the clock-2 input. During loading, the entry of positive logic: see function table
serial data is inhibited.
Shift right is accomplished on a high-to-Iow transition of clock 1 when the mode control is low. Serial data for the
right-shift mode is entered at the J-R inputs. These inputs permit the first stage to perform as a J-R, a Ootype, or T -type
flip-flop as shown in the function table. Shift left is accomplished on the high-to-Iow transition of clock 2 when the
mode control is high by connecting the output of each flip-flop to the parallel input of the previous flip-flop (GO to
input C, etc.). Serial data for this mode is entered at the 0 input. The clock input may be applied commonly to clock 1
and clock 2 if both modes can be clocked from the same source. Changes at the mode control input should normally be
made while both clock inputs are low; however, conditions described in the last three lines of the function table will
also ensure that register contents are protected.

FUNCTION TABLE
INPUTS OUTPUTS

•
MODE CLOCKS SERIAL PARALLEL
°A °B Oc OD OD
CONTROL 2 (L) 1 (R) J K A B C D
H H X X X X X X X QAO QSO QCO QDO QDO
H j, X X X a b c d a b c d d
H j, X X X Qst Qct QDt d QS n QCn QDn d d
L L H X X X X X X QAO QSO QCO QDO GOO
L X j, L H X X X X QAO QAO QS n QCn OCn
L X j, L L X X X X L QAn QS n QCn OCn
L X j, H H X X X X H QAn QS n QCn °Cn
L X j, H L X X X X °An QAn QS n QCn OCn
t L L X X X X X X QAO QSO QCO QDO °DO
j, L L X X X X X X OAO QSO QCO QDO 000
j, L H X X X X X X QAO QSO QCO QDO 000
t H L X X X X X X QAO QSO QCO QDO 000
t H H X X X X X X QAO QSO QCO QDO 000

tShifting left requires external connection of QB to A, QC to B, and QD to C. Serial data is

entered at input D.

H = high level (steady statel, L = low level (steady state)

X = irrelevant (any input, including transitions)
J, = transition from high to low level, t = transition from low to high level.
a. b. c. d = the level of steady·state input at inputs A. B. C. or D. respectively.
QAO. QBO. QCO. QDO = the level of QA' QB. QC. or QD. respectively. before the indicated steady-state input conditions were established.
QAn' QBn. QCn. QDn = the level of QA' QB. QC. or QD. respectively. before the most-recent .[ transition of the clock.

1076

TEXAS INSTRUMENTS 7-109

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54L99, SN74L99
4-81T RIGHT-SHIFT LEFT-SHIFT REGISTERS

functional block diagram

J 12)

SERIAL
INPUTS

{ CK
K 116)

114)
OB

B 13)

PARAllEL
INPUTS

112) Oc

C (4)

o 16)
(11) aD

M~OE 17)
CONTROL

RI~~~S~:FT·...!(8"')_+""""F----\'

II I
-<4>.
I
dynamic input activated by transition from a high level to a low level.

schematics of inputs and outputs

EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS

vcc--------~-------- ----+------v CC

INPUT

OUTPUT

Input A and M· Req = 20 kn NOM

All other: Req = 40 kn NOM

i272

7-11.0 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54L99. SN74L99
4-81T RIGHT-SHIFT LEFT-SHIFT REGISTERS

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1) ........ . 8V
Input voltage (see Note 2) . . . . . . . . . 5.5 V
Operating free-air temperature range: SN54L99 Circuits -55°C to 125°C
SN74L99 Circuits O°C to 70°C
Storage temperature range -65°C to 150°C
NOTES: 1. Voltage values are with respect to network ground terminal.
2. Input voltages must be zero or positive with respect to network ground terminal.

recommended operating conditions

SN54L99 SN74L99
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -100 -200 p.A
Low-level output current, IOL 2 3.6 rnA
Width of clock pulse, tw(clock) 200 200 ns
Setup time for high-level data at J, K, A, 8, C, or D inputs, tsu(H) 100 100 ns
Seiup tirnt:: for iuw~ievei data at J, K, A, 8, C, or D inputs, tsu\Lj i20 -i20 ns
Hold time at J, K, A, 8, C, or D inputs, th 0 0 ns
Time to enable clock 1, tenable 1 (see Figure 1) 225 225 ns
Time to enable clock 2, tenable 2 (see Figure 1) 200 200 ns
Time to inhibit clock 1, tinhibit 1 (see Figure 1) 100 100 I1S

Time to inhibit clock 2, tinhibit 2 (see Figure 1) 0 0 ns

Operating free-air temperature, T A -55 125 0 70 °c

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54L99 SN74L99
PARAMETER TEST CONDITIONSt UNIT
MIN TYP:j: MAX MIN TYP:j: MAX
VIH High-level input voltage 2 2 V

•
VIL Low-level input voltage 0.7 0.7 V
Vce = MIN, VIH =2V,
VOH High-level output voltage 2.4 3.3 2.4 3.2 V
VIL = 0.7 V, 10H = MAX
Vee= MIN, VIH = 2V
VOL Low-level output voltage 0.15 0.3 0.2 0.4 V
VIL = 0.7 V, 10L =MAX
Input current at J, K, 8, e, or D 100 100
II Vee = MAX, VI = 5.5V p.A
maximum input voltage MorA 200 200
High-level J, K, 8, C, or D 10 10
IIH Vee = MAX, VI = 2.4 V p.A
input current MorA 20 20
Low-level J, K, B, e, or D -0.18 -0.18
IlL Vee = MAX, VI = 0.3 V rnA
input current MorA -0.36 -0.36
lOS Short-circuit output current§ Vee = MAX -3 -15 -3 -15 rnA
lee Supply current Vee = MAX, See Note 3 3.8 9 3.8 9 rnA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
:j:AII typical values are at V CC = 5 V, T A = 25° C.
§ Not more than one output should be ~orted at a time_
NOTE 3: With all outputs and J and K inputs open, mode control at 4_5 V, inputs A through D grounded, ICC is measured after a momentary
3 V, then ground, is applied to both clock inputs_

switching characteristics, Vee = 5 V, TA = 25° e

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f max Maximum clock frequency 3 5 MHz
eL = 50 pF, RL =4 kn,
tPLH Propagation delay time, low-to-high-Ievel output from either clock 115 200 ns
See Figure 2
tpHL Propagation delay time, high-to-Iow-Ievel output from either clock 125 200 ns

1076

TEXAS INCORPORATED
INSTRUMENTS 7-111
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54L99, SN74L99
4-81T RIGHT-SHIFT LEFT-SHIFT REGISTERS

PARAMETER MEASUREMENT INFORMATION

OUTPUT VCC

FROM OUTPUT
UNDER TEST
CL = 50 pF
(See Note B) J
LOAD CIRCUIT

Jand K
INPUTS
\----- ----VIH

\ " . . - - - - - - - - V IL

~ fI I _______ IH
MINPUT \,.3V
I'--"""!""---
1.3V 1\ .
------
. VV
IL
teMilie 1 -i-----II
r--------
j. - - - - V
CLOCK 1 IH
INPUT

CLOCK 2
INPUT
tinhibit 2 -+------

'---------'.
n .-_-_-_- _
- - - - - - - - - - V IL

-
V

V IL
IH

QA OUTPUT
_ _ _ _ _ _ _ _J
;'-------"\"--------11 ---
\ --
'----
V
OH
VOL

NOTE: A input is at the low level.

VOLTAGE WAVEFORMS
FIGURE 1-CLOCK ENABLE/INHIBIT TIMES

•
';15 ns--+\ I+- :!l I- ~15 ns
DATA
INPUT ~~ 00%\
1.3 V I
f,1.3V
\:V------
3V

10% ~ 10%
OV
I I
~ Isu(L) -t I.- Isu(H) ..I I
I I ...-t th ~
-t th l- I
I

CLOCK
INPUT
I OV
~15 ns t.-~15 ns ~tW(clOCkl
I
I

__-
I
I V OH

t~'_n
I
OUTPUT
(See Note 0)
/ --I
I
I
I
I
\13V

j I
I
1

I-
VOL

tPHLI- -I tpLH

VOLTAGE WAVEFORMS
FIGURE 2-SWITCHING TIMES
NOTES: A. The input waveforms are supplied by pulse generators having the following characteristics: Zout '" 50 For data pulse n.
generator: tw ~ 150 ns, PRR';;; 500 kHz, lsetup(L) = 120 ns, and lsetup(H) = 100 ns. For clock pulse generator: tw ~ 200 ns and
PRR';;; 1 MHz. When testing f max ' vary PRR.
B. CL includes probe and jig capacitance.
C. All diodes are 1N916.
D. When data input is applied to J and K inputs, the output waveform applies only to output QA'

1076

7-112 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TTL TYPES SN54100, SN74100
MSI 8-BIT BISTABLE LATCHES
BULLETIN NO. DL-S 7211830, DECEMBER 1972

SN54100 ••• J OR W PACKAGE

logic SN54100 ••• J OR N PACKAGE
(TOP VIEW)

FUNCTION TABLE ENABLE

(Each Latch) Vee lG

INPUTS OUTPUTS
0 G a a
L H L H
H H H L
X L 00 00
H = high level, X = irrelevant
00 = the level of Q before the
high-to-Iow transition of G

description
These latches are ideally suited for use as temporary
storage for binary information between processing positive logic: see function table
units and input/output or indicator units. Informa- NC-No internal connection
tion present at a data (D) input is transferred to the Q
output 'vvhen the enable (G) is high and the a"Output functional block diagram (each latch)
will follow the data input as long as the enable
remains high. When the enable goes low, the informa-
tion (that was setup at the data input at the time
the transition occurred) is retained at the Q output
until the enable is permitted to go high.

These circuits are completely compatible with all ENABLE DATA

popular TTL or DTL families. All inputs are diode-
clamped to minimize transmission-line effects and
simplify system design. Typical power dissipation is schematic (each latch)
40 milliwatts per latch. The SN541 00 is characterized
for operation over the full military temperature range
of _55 to 125 e; the SN7 4100 is characterized for
0 0

operation from 0 e to 70° e.

0

•
Resistor values shown are nominal and in ohms.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) 7V
Input voltage . . . . . . . 5.5 V
Intermitter voltage (see Note 2) 5.5 V
Operating free-air temperature range: SN54100 -55°C to 125°C
SN74100 oOe to 70°C
Storage temperature range -65°C to 150°C
NOTES: 1. Voltage values, except interemitter voltage. are with respect to network ground terminal.
2. This is the voltage between two emitters of a multiple-emitter input transistor. For this circuit, this rating applies between the
enable and D inputs of any latch.

1076

TEXAS INSTRUMENTS 7-113

INCORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54100, SN74100
8-BIT BISTABLE LATCHES
REVISED OCTOBER 1976

recommended operating conditions

SN54100 SN74100
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -400 -400 /J A
Low-level output current, 10L 16 16 rnA
Width of enabling pulse, tw 20 20 ns
Setup time, tsu 20 20 ns
Hold time, th 5 5 ns
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONSt MIN TYP+ MAX UNIT
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
VIK Input clamp voltage Vee= MIN, 11=-12mA -1.5 V
Vee = MIN, VIH=2V,
VOH High-level output voltage 2.4 3.4 V
VIL = 0.8 V, 10H = -400/JA
Vee= MIN, VIH = 2 V,
VOL Low-level output voltage 0.2 0.4 V
VIL = 0.8 V, 10L = 16mA
II Input current at maximum input voltage Vee = MAX, VI = 5.5 V 1 rnA
D input 80
IIH High-level input current Vee = MAX, VI = 2.4 V /J A
G input 320
D input -3.2
IlL Low-level input current Vee= MAX, VI=O.4V rnA
G input -12.8
SN54100 -20 -57
lOS Short-circuit output current§ Vee = MAX rnA
SN74100 -18 -57

•
Vee = MAX, SN541 00 64 92
ICC Supply current rnA
See Note 3 SN74100 64 106

t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
0
+AII typical values are at V CC =5 V, T A = 25 C.
§ Not more than one output should be shorted at a time.
NOTE 3: ICC is tested with all inputs grounded and all outputs open.

switching characteristics, Vee = 5 V, TA = 25°e

FROM TO
PARAMETER~ TEST CONDITIONS MIN TYP MAX UNIT
(INPUT) (OUTPUT)
tPLH 16 30
D Q eL = 15 pF, ns
tpHL 14 25
RL=400n,
tpLH 16 30
G Q See Note 4 ns
tpHL 7 15

'\I tp LH '" propagation delay time, low-to-high-Ievel output

tpHL '" propagation delay time, high-to-Iow-Ievel output
NOTE 4: Test circuit and voltage waveforms are the same as those shown for the '75, '77, 'L 75, and' L 77 on page 7-40.

1076

7-114 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • OALLAS. TEXAS 75222
 TTL TYPES SN54116, SN74116
MSI DUAL 4-81T LATCHES WITH CLEAR
BULLETIN NO. DL·S 7211849, DECEMBER 1972

• Two Independent 4-Bit Latches in a

Single Package SN54116 ••• J OR W PACKAGE
SN74116 ••• J OR N PACKAGE
• Separate Clear Inputs Provide One-Step (TOP VIEW)
Clearing Operation
• Dual Gated Enable Inputs Simplify
Cascading and Register Implementations
• Compatible for Use with TTL and DTL
Circuits
• Input Clamping Diodes Simplify
System Design

description

These monolithic TTL circuits utilize O·type bistables positive logic: see function table
to implement two independent four·bit latches in a
singie package. Each four·bit iatch has an indepen·
dent asynchronous clear input and a gated two· input functional block diagram (each 4-bit latch)
enable circuit. When both enable inputs are low, the
output levels will follow the data input levels. When
either or both of the enable inputs are taken high, the
outputs remain at the last levels setup at the inputs
prior to the low·to-high-Ievel transition at the enable
input(s). After this, the data inputs are locked out.

The clear input is overriding and when taken low will

reset all four outputs low regardless of the levels of
the enable inputs.

•
The SN54116 is characterized for operation over the
full military temperature range of -55°C to 125°C;
the SN74116 is characterized for operation from O°C
to 70°C.
FUNCTION TABLE
(EACH LATCH)
INPUTS
OUTPUT
ENABLE
CLEAR DATA a
G1 G2
H L L L L
H L L H H
H X H X 00
H H X X 00
L X X X L
H = high level, L = low level, X = irrelevant
00 = the level of ° before these input conditions were established.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) ....... . 7V
I nput voltage " . . . ., ....... . 5.5 V
Operating free-air temperature range: SN54116 Circuits -55°C to 125°C
SN74116 Circuits O°C to 70°C
Storage temperature range -65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.

1076

TEXAS INSTRUMENTS 7-115

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54116, SN74116
DUAL 4-BIT LATCHES WITH CLEAR

recommended operating conditions

SN54116 SN74116
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -800 -800 p.A
Low-level output current, 10L 16 16 rnA
Enable 18 18
Input pulse width, tw ns
Clear 18 18
High logic level 8 8
Data setup time, tSIJ ns
Low logic level 14 14
Clear inactive-state setup time, tsu 8 8 ns
Data release time, high-level data, trelease 2 2
ns
Data hold time, low-level data, th 8 8
Operating free-air temperature, T A -55 125 0 70 °c

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONSt MIN TYpt MAX UNIT
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
VIK Input clamp voltage Vee= MIN, 11=-12mA -1.5 V
Vee= MIN, VIH=2V,
VOH High-level output voltage 2.4 3.4 V
VIL = 0.8 V, 10H = -SOOJJ.A
Vce= MIN, VIH = 2V,
VOL Low-level output voltage 0.2 0.4 V
VIL = 0.8 V, 10L = 16mA
'I Input current at maximum input voltage Vee = MAX, VI = 5.5V 1 rnA
Gl, G2, or clear 40
IIH High-level input current Vee = MAX, VI=2.4V JJ.A
Any D 60
Gl, G2, or clear -1.6

•
IlL Low-level input current Any D, initial peak Vee = MAX, VI = 0.4 V --2.4 rnA
Any D, steady-state -1.6
SN54116 -20 -57
lOS Short-circuit output current§ Vee= MAX rnA
SN74116 -18 -57
Vee = MAX, Condition A 60 100
ICC Supply current rnA
See Note 2 Condition B 40 70

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device
type.
tAli typical values are at Vee = 5 V, T A = 25°C.
§Not more than one output should be shorted at a time.
NOTE 2: With outputs open, ICC is measured for the following conditions:
A. All inputs grounded.
B. All 13 inputs are grounded and all other inputs are at 4.5 V.

switching characteristics, Vee =5 V, TA = 25°e

FROM TO
PARAMETER~ TEST CONDITIONS MIN TYP MAX UNIT
(INPUT) (OUTPUT)
tPLH 19 30
Enable AnyQ ns
tpHL eL = 15pF, 15 22
tpLH RL=400n, 10 15
Data Q ns
tpHL See Figure 1 12 18
tpHL Clear AnyQ 15 22 ns

~tpLH '" propagation delay time, low-to-high-Ievel output

tpHL'" propagation delay time, high-to-Iow-Ievel output

1076

7-116 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54116, SN74116
4-811 LATCHES WITH CLEAR

schematics of inputs and outputs

EQUIVALENT OF CLEAR, EQUIVALENT OF TYPICAL OF
G1, AND G2 INPUTS DATA INPUTS ALL OUTPUTS

VCC
VCC1 kn -
4 3 -
NOM V C CReq
3--

INPUT --
'N'UT .--

OUTPUT

Initial Req = 3 kn NOM

Steady-state Req = 6 kn NOM

PARAMETER MEASUREMENT INFORMATION

FROM OUTPUT
UNOER TEST

LOAD CIRCUIT

~
CLEAR
INPUT
15v
I'
1.5 V
.!.. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
r-- tw_
3V
ov
I ~tsu
OATA
INPUT \L-__---Jlr---_-_-_-::
,..-_ _ _ 14-- tw -----t ~ Iw -! 3V

,seeE~:.:~~ _ _...;...._ _ _ _. J11.5V ~1.5V P}.1.._5_V__..JEov

•
l.-'PHL'" 14- IPHL _ 14-- IPLH-+I

OUTPUT
_ _ _ _'""\ I
\1.5 V I .
_----_ I
\1.S V F I V

OH
VOL

SWITCHING TIMES FROM CLEAR AND ENABLE INPUTS

OATA 3V
INPUT loS V
(See Note E) I I I
I -.I!4-lrelease: ~ ..... Ih
ENABLE I Isu ..... _ - - _ 14- Isu ~ 3V

,see~~:.u~__...;!-----I=--------.J11.5V ~ OV
IPLH ~ I4-IPHL--l

OUTPUT _ _ _--J
1";-·S-V---\. .1_.S_V___ J
/

SWITCHING TIMES FROM DATA INPUTS

NOTES: A. Input pulses are supplied by generators having the following characteristics: tr';; 10 ns, tf';; 10 ns, PR R =1 MHz, duty cycle';; 50%,
Zout "" 50 n.
B. CL includes probe and jig capacitance.
C. All diodes are 1 N3064.
D. The other enable input is low.
E. Clear input is high.

FIGURE 1

1076

7-117
TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE SOX 5012 • DALLAS. TEXAS 75222
 TTL TYPES SN54120, SN74120
MSI DUAL PULSE SYNCHRONIZERS/DRIVERS
BULLETIN NO. DL-S 7211537, SEPTEMBER 1971-REVISED DECEMBER 1972

SN54120 ..• J OR W PACKAGE

• Generates Either a Single Pulse or Train of Pulses SN74120 •.• J OR N PACKAGE
Synchronized with Control Functions (TOP VIEW)

• Ideal for Implementing Sync-Control Circuits ~ ____

INPUTS
~A~ ______ ~

Similar to those Used in Oscilloscopes

• Latched Operation Ensures that Output Pulses
Are Not Clipped
• High-Fan-Out Complementary Outputs Drive
System Clock Lines Directly
• Internal Input Pull-Up Resistors Eliminate
Need for External Components
• Diode-Clamped Inputs Simplify System Design
• Typical Propagation Delays: ~----~v~----~
INPUTS

9 Nanoseconds through One Level

16 Nanoseconds through Two Levels logic: see description and function table

description

These monolithic pulse synchronizers are designed to synchronize an asynchronous or manual signal with a system
clock. Reliable response is ensured as the input signals are latched up; therefore duration of logic input is not critical
and the adverse effects of contact-bounce of a manual input are eliminated. The ability to pass output pulses is started
and stopped by the levels or pulses applied to the latch inputs S1, S2, or R in accordance with the function table.
High-speed circuitry is utilized throughout the clock paths to minimize skew with respect to the system dock.

FUNCTION TABLE
After initiation, the mode control (M) input deter-
mines whether a series of pulses or only one pulse is INPUTS
FUNCTION

•
passed. In the absence of a stop command, the clock R S1 S2
driver will continue to pass clock pulses as long as the X L X Pass Output Pulses
mode control input is low (see Figures 2 through 4). X X L Pass Output Pulses
If the mode control input is high only a single clock L H H Inhibit Output Pulses
pulse will be passed (see Figure 5). H ~ H Start Output Pulses
H H ~ Start Output Pulses

I~
When the mode control is set to pass a series of H H Stop Output Pulses
pulses, the last pulse out is determined by two general H H Continue t
rules:
H = high level (steady state)
L = low level (steady state)
a. When pulses are terminated by the S or R
~ = transition from H to L
inputs, conditions meeting the setup times
x = jrTe~evant
(specified under recommended operating
t Operation initiated by last ~ transition,continues.
conditions) will dominate.

b. Low-to-high-Ievel transitions at the mode control input should be avoided during the 20-nanosecond period
immediately following the negative transition of the input clock pulse as transitions during this time period
mayor may not allow the next pulse to pass (see Figures 4 and 5). When pulses are terminated by th~ mode
control input, a positive transition at the mode control input meeting the high·level setup time, tsu (H),
(specified under recommended operating conditions) will pass that positive clock pulse then inhibit remaining
clock pulses. The clock input (e) is latch-controlled ensuring that once initiated the output pulse will not be
terminated until the full pulse has been passed.

1076

7-118 TEXAS INCORPORATED

(NSTRUMENTS
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54120, SN74120
DUAL PULSE SYNCHRONIZERS/DRIVERS

desCription (continued)

This clock driver circuit is entirely compatible for use with either digital logic circuits or mechanical switches for input
controls since all inputs, except the clock, have internal pull-up resistors. This eliminates the requirement to supply an
external resistor to prevent the input from floating when the control switch is open. The internal resistor also means
that these inputs may be left disconnected if unused.

Typical propagation delay time is 9 nanoseconds to the Y output and 16 nanoseconds to the Y output from the clock
input. The outputs will drive 60 Series 54/74 loads at a high logic level and 30 loads at a low logic level. Typical power
dissipation is 127 milliwatts per driver. The SN54120 is characterized for operation from -55°C to 125°C; the
SN74120 is characterized for operation from O°C to 70°C.

functional block diagram (each driver)

INPUTS

JOU~~UTS
l
0 - -....- - - - -......- - -

: _ _ _ _ _ _ _L_ -~---Ir-I--:~J
-t_-_-_-_ ....

•
schematics of inputs and outputs
EQUIVALENT OF EQUIVALENT OF EACH TYPICAL OF
EACH C INPUT M. R. OR S INPUT ALL OUTPUTS

- - - - - - - - Vee
Vee ---+---- VeG~._-.....- -

NOM

INPUT INPUT

I...--~-- OUTPUT

1272

TEXAS INSTRUMENTS
INCORPORATED
7·119
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54120, SN74120
DUAL PULSE SYNCHRONIZERS/DRIVERS

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1) 7V
Input voltage . . . . . . . . . 5.5 V
Interemitter voltage (see Note 2) 5.5 V
Operating free-air temperature range: SN54120 Circuits -55°C to 125°C
SN74120 Circuits O°C to 70°C
Storage temperature range . . . . -65°C to 150°C
NOTES: 1. Voltage values, except interemitter voltage, are with respect to network ground terminal.
2. This is the voltage between two emitters of a multiple-emitter transistor. For this circuit, this rating applies between the S1 and S2
inputs.

recommended operating conditions

SN54120 SN74120
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -2.4 -2.4 mA
Low-level output current, 10L 48 48 mA
Any input except mode control,
12 12
tsu(H or Ll
Setup time (see Figures 2 thru 5) ns
Mode control II tsu(H)
tsu(Ll
0
12
0
12
Any input except mode control,
3 3
Hold time (see Figures 3 and 5) th(H or Ll ns
Mode control, th(H or Ll 20 20
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST eONDITIONSt MIN TYP:j: MAX UNIT
VIH High-level input voltage 2 V
VIL Low·level input voltage 0.8 V
VIK I nput clamp voltage Vee- MIN, 11--12mA -1.5 V

•
Vee; MIN, VIH; 2 V,
VOH H.igh-Ievel output voltage 2.4 3.4 V
VIL; 0.8 V, 10H; -2.4 mA
Vee; MIN, VIH; 2 V,
VOL Low-level output voltage 0.2 0.4 V
VIL;0.8V, 10L; 48 mA
II I nput current at max imum input voltage Vee; MAX, VI; 5.5 V 1 mA
Clock input 80, J.!A
IIH High-level input current Vee; MAX, VI;2.4V
Other inputs -0.12 -0.2 -0.36 mA
elock input -3.2
IlL Low-level input current Vee; MAX, VI; 0.4 V mA
Other inputs -2.1
lOS Short-circuit output current§ Vee; MAX -35 -90 mA
lee Supply current Vee; MAX, See Note 3 51 90 mA

t For conditions shown as M!N or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at Vee; 5 V, T A; 25°e.
§ Not more than one output should be shorted at a time.
NOTE 3: lee is measured with ground applied to all inputs except R which is at 4.5 V and all outputs open.

switching charC!cteristies, Vee = 5 V, T A = 25°e

FROM TO
PARAMETER~ TEST eONDITION~ MIN TYP MAX UNIT
(INPUT) (OUTPUT)
tPLH 14 22
e y eL ; 45 pF, ns
tpHL 17 25
RL;133.!1,
tpLH y 10 16
e See Figure 1 ns
tpHL 8 13
~ tPLH "" Propagation delay time, low-to-high-Ievel output
tpH L "" Propagation delay time, high-to-Iow-Ievel output

1076

7-120 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54120, SN74120
DUAL PULSE SYNCHRONIZERS/DRIVERS
PARAMETER MEASUREMENT INFORMATION

Vcc
OUTPUT
! RL '133"
NOTES: A. The clock input pulse in figures 2
supplied by a generator having the following char-
through 5 is

1
acteristics: tw(clock);;;' 15 ns, PRR';; 1 MHz, and
FROM OUTPUT± l..IIIII.--4Il_-tIlll..l
..._ il ....-tIlll..l
....-IIIIII..I
• .., Zout "" 50.n.
UNDER TEST ,...,. jiI'j jiI'j jiI'j
B. CL includes probe and jig capacitance.

l' CL =45pF
C. All diodes are 1 N3064.

FIGURE 1-LOAD CIRCUIT FOR SWITCHING TESTS

.1
tw(clock) ri .,'.. I
tw(clock)
--- 3 V

~"lL~UCTK I~1.5V ~ ~
-----J
;:::...L tsu(L)
1'---./
I
'---Ii
!4----M- tsu(Hl
'- 0 V
. I I I .

~
I I' I / , . - - - - 3V
S1 or S2 1.5 VI II 1.5 V
INPUT \.._~:_ _ _~:.-_ _ _ _ _ _ _~. 0V
(See Note)
tPHL--!
I
, - - - - - - - - - - - - - - VOH
YOUTPUT

Y OUTPUT

•
' -_ _ _ _ _ _ _ _ VOL

NOTE: Mode control and R inputs are low·unused S input is high.

FIGURE 2-INITIATING AND TERMINATING PULSE TRAIN FROM S INPUTS

CLOCK
INPUT
i----!I tsu(L) I
, OV
I ......... tn(L) ,
3V

~
II I
S1orS2 1.5V 1.5V
INPUT I
-----------------
-*---'1-----r
_______________________________
tsu(L) ~ I .J th(L)
OV

I 3V
RINPUT

_ - - - - - - - - - VOH
YOUTPUT

NOTE: Mode control input is low and unused S input is high.

FIGURE 3-INITIATING PULSE TRAIN FROM S AND TERMINATING WITH R INPUTS

1076

TEXAS INCORPORATED
INSTRUMENTS 7·121
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54120, SN74120
DUAL PULSE SYNCHRONIZERS/DRIVERS

PARAMETER MEASUREMENT INFORMATION

.1 tw(clock)

CLOCK
---I
INPUT
OV
.....~-.01- tsu(L)
1 I. . .~---+- tsu (H)
3V

~~~ROL .~~.5__V_____________________~~1.-5-~----_-_-_--_-_--_-_-_--_-_--_-_-_--_-_-
OV

VOH

YOUTPUT
'-_..J ___________ - - - - VOL

NOTE: At least one of the S inputs is low.

FIGURE 4-INITIATING AND TERMINATING PULSE TRAIN WITH MODE CONTROL INPUT

• CLOCK
INPUT I
I
I
th(L)~
\4- tsu{H)
OV

3V

MODE CONTROL
INPUT
-------+----t-h(-H-)---~ - - - ""t' -
fsv! - - - - -- -- - - - - - - - - - - - - OV
I~ __ ~_t~~) __________________ _
3V

S1 or S2
INPUT
~~5_V________________________________ OV

VOH

"'----~-----------
YOUTPUT
VOL

NOTE: Input R is low and the unused S input is high.

FIGURE 5-ENABLING SINGLE PULSE

1076

7·122 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TTL TYPES SN54LS124, SN54S124, SN74LS124, SN74S124
MSI DUAL VOLTAGE-CONTROLLED OSCILLATORS
BULLETIN NO. DL-S 7612025, MARCH 1974-REVISED OCTOBER 1976

SN54LS124, SN54S124 ••• J OR W PACKAGE

• Two Independent VCO's in a 16-Pin SN74LS124, SN74S124 .•. J OR N PACKAGE
Package (TOP VIEW)

• Output Frequency Set by Single External

Component:
Crystal for High-Stability Fixed-Frequency
Operation
Capacitor for Fixed- or Variable-Frequency
Operation
• Separate Supply Voltage Pins for Isolation
of Frequency Control Inputs and Oscillators
from Output Circuitry
• Highly Stable Operation over Specified .
Temperature and/or Supply Voltage Ranges

GUARANTEED TYPICAL
TYP!CAL
TYPE FREQUENCY POWER
f max
SPECTRUM DISSIPATION
logic: While the enable input is low, the
'LS124 1 Hz to 20 MHz 30 MHz 150mW
output is enabled. While the enable
'S124 1 Hz to 60 MHz 85 MHz 525mW input is high, the output is high.

description

The 'LS124 and 'S124 feature two independent voltage-controlled oscillators (VCOI in a single monolithic chip. The
output frequency of each VCO is established by a single external component, either a capacitor or a crystal, in
combination with two voltage-sensitive inputs, one for frequency range and one for frequency control. These inputs
can be used to vary the output frequency as shown under typical characteristics for the 'S124. The concept also applies
for the 'LS124. These highly stable oscillators can be set to operate at any frequency typically between 0.12 Hz and
30 MHz ('LS124) or 0.12 hertz and 85 megahertz (,S124). Under the conditions used in Figure 3, the output

•
frequency can be approximated as follows:

4 4
fo = 1 X 10- for 'LS124 fo = 5.X 10- for 'S124
Cext ' Cext

where: fo = output frequency in hertz

Cext = external capacitance in farads.

These devices can operate from a single 5-volt supply. However, one set of supply-voltage and ground pins (VCC and
GND) is provided for the enable, synchronization-gating, and output sections, and a separate set eVCC and8GND)
is provided for the oscillator and associated frequency-control circuits so that effective isolation can be accomplished in
the system.

The enable input of these devices starts or stops the output pulses when it is low or high, respectively. The internal
oscillator of the 'LS124 runs continuously even while the output is disabled, whereas the internal oscillator of the
'S124 is itself started and stopped by the enable input. The enable input is one standard load in each series. The enable
input and the buffered output operate at standard Schottky-clamped TTL levels.

The pulse synchronization-gating section ensures that the first output pulse is neither clipped nor extended. Duty cycle
of the square-wave output is fixed at approximately 50 percent. Simultaneous operation of both VCO's in the same
package is not recommended.

The SN54LS124 and SN54S124 are characterized for operation over the full military temperature range of _55°C to
125°C; the SN74LS124 and SN74S124 are characterized for operation from O°C to 70°C.

1076

TEXAS INSTRUMENTS 7-123

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54LS124, SN54S124, SN74LS124, SN74S124
DUAL VOLTAGE-CONTROLLED OSCILLATORS

schematics of inputs and outputs

'LS124

EQUIVALENT OF EACH EQUIVALENT OF EACH FREQUENCY TYPICAL OF BOTH OUTPUTS

ENABLE INPUT CONTROL OR RANGE INPUT
--------------~-----Vee

Vee----------_e--
50 n NOM
vCC------~------
R3
17 kn NOM

INPUT~~ __~---~- R1
I NPUT--'''''''''....----I '----.....- - - - OUTPUT

R2

NOMINAL VALUES
R1 R2 R3
Frequency control 79 kn 14 kn 27 kn
Range 85 kn 6 kn 24 kn

'S124

EQUIVALENT OF EACH EQUIVALENT OF EACH FREQUENCY TYPICAL OF BOTH OUTPUTS

ENABLE INPUT CONTROL OR RANGE INPUT
- - - - -....- - Vee
Vee--------~---- 114 n NOM
Vee---------.--------

INPUT

•
INPUT

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, Vee (see Notes 1 and 2) . 7V

Input voltage: 'LS124 Enable input . 7V
'LS124 Frequency control or range input Vee
'S124 . . . . . . . . . . . . . . 5.5V
Operating free-air temperature range: SN54LS124, SN54S124 -55°e to 125°e
SN74LS124,SN74S124 oOe to 700e
0
Storage temperature range -65°e to 150 e

NOTES: 1. Voltage values are with respect to the appropr'ate ground terminal.
2. Throughout this data sheet, the symbol Vee is used for the voltage applied to both the Vee and8vee terminals, unless other-
wise noted.

1076

7-124 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54LS124, SN74LS124
DUAL VOLTAGE-CONTROLLED OSCILLATORS

recommended operating conditions

SN54LS124 SN74LS124
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, VCC 4.5 5 5.5 4.75 5 5.25 V
Input voltage at frequency control or range input, Vl(freq) or Vl(rng) 0 5 0 5 V
High-level output current, 10H -1.2 -1.2 mA
Low-level output current, 10L 12 24 mA
1 1 Hz
Output frequency (enabled),lo
20 20 MHz
Operating free-air temperature, T A -55 125 0 70 °c

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS124 SN74LS124
PARAMETER TEST CONDITIONSt
MIN TYP:j: MAX MIN TYp:j: MAX UNIT
High-ievei input
2 2
voltage at enable
Low-level input
VIL 0.7 0.8 V
voltage at enable
VIK I nput clamp voltage at enable VCC= MIN, 11- -18 mA -1.5 -1.5 V
VCC- MIN, VIH-2V,
VOH High-level output voltage 2.5 3.4 2.7 3.4 V
IOH = -1.2 mA
VCC = MIN, 8vcc open IOL = 12mA 0.25 0.4 0.25 0.4
VOL Low-level output voltage V
Vil = Vilmax IOl = 24 mA 0.35 0.5
Freq control VI-5V 50 250 50 250
II I nput current VCC= MAX p.A
or range VI= 1 V 10 50 10 50 I
I nput current
II at maximum Enable VCC= MAX, VI =7V 0.1 0.1 mA

•
input voltage
High-level
IIH Enable VCC= MAX, VI = 2.7 V 20 20 p.A
input current
low-level
III Enable VCC = MAX, VI = 0.4 V -0.4 -0.4 mA
input current
lOS Short-circuit output current§ VCC= MAX -40 -225 -40 -225 mA
Supply current, total into
ICC VCC= MAX, See Note 2 30 50 30 50 mA
pins 15 and 16
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at Vee = 5 V, T A = 25°C.
§Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
NOTE 2: ICC is measured with the outputs disabled and open.

switching characteristics, Vee = 5 V (unless otherwise noted), RL = 667 n, e L = 45 pF, T A = 25°e

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
C = 2 pF IVl(freq) = 4 V, Vl(rng) = 1 V 20 30
fo Output frequency (capacitor controlled)- ext MHz
IVl(freq) = 1 V, VI (rng) = 5 V 11 20
fo Output frequency (crystal controlled) 8Vcc = 3 V, VI(freq) = Vl(rng) =0 V 10 20 MHz

Output duty cycle Cext = 8.3 pF to 500 p.F 50%

Propagation delay time,
tpHl fo'" 1 Hz 30+* ns
high-to-Iow-Ievel output from enable
9
'The delay will typically be 30 ns plus up to one period of one cycle (i.e. 30 ns to 30 ns + 1 X 10 ns) depending upon the timing of
the enable pulse with respect to the signal generated by the internal oscillator. fo(Hz)

1076

TEXAS INSTRUMENTS 7-125

INCORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54S124, SN14S124
DUAL VOLTAGE-CONTROLLED OSCILLATORS

recommended operating conditions

SN54S124 SN74S124
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee (see Note 1) 4.5 5 5.5 4.75 5 5.25 V
Input voltage at frequency control or range input, Vl(freq) or Vl(rng) 1 5 1 5 V
High-level output current, 10H -1 -1 rnA
Low-level output current, 10L 20 20 rnA
1 1 Hz
Output frequency (enabled), f 0
60 60 MHz
Operating free-air temperature, T A -55 125 0 70 °e

NOTE 1: Throughout this data sheet, the symbol Vee is used for the vOltage applied to both pins 15 and 16.

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITlONSt MIN TYP:j: MAX UNIT
VIH High-level input voltage at enable 2 V
VIL Low-level input voltage at enable 0.8 V
VIK Input clamp voltage at enable Vee; MIN, II; -18mA -1.2 V
Vee; MIN, VIH;2V, I SN54S' 2.5 3.4
VOH High-level output voltage V
10H; -1 rnA r SN74S' 2.7 3.4
Vee; MIN, VIL;0.8V,
VOL Low-level output voltage 0.5 V
10L; 20 rnA

II Input current
Freq control
Vee; MAX
I VI- 5V 10 50
JlA
or range I VI; 1 V 1 15
Input current at
II Enable Vee; MAX, VI; 5.5 V 1 rnA
maximum input voltage
IIH High-level input current Enable Vee; MAX, VI;2.7V 50 JlA
IlL Low-level input current Enable Vee; MAX, VI; 0.5 V -2 rnA
lOS Short-circuit output current § Vee; MAX -40 -100 rnA

•
Vee; MAX, See Note 2 105 150
ICC
Supply current, total into
pins 15 and 16
Vee; MAX, TA; 125°C, IW package
110
rnA
See Note 2 only
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at Vee; 5 V, T A = 25°C.
~Not more than O!1e output ~hou!d be shorted at a time ,a,nd duration of the short-circuit should not exceed one second.
NOTE 2: ICC is measured with the outputs disabled and open.

switching characteristics, Vee = 5 V, RL = 280 n, eL = 15 pF, TA = 25°e

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

fo Output frequency eext; 2 pF I VI(freq) ; 4 V, Vl(rng) ; 1V 60 85

MHz
I Vl(freq); 1 V, Vl(rng); 5 V 25 40
Output duty cycle eext - 8.3 pF to 500 JlF 50%
1.4
Propagation delay time, fo; 1 Hz to 20 MHz s
tPHL fo(Hz)
high-to-Iow-Ievel output from enable
fo > 20 MHz 70 ns

1076

7-126 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54LS124, SN54S124, SN74LS124, SN74S124
DUAL VOLTAGE-CONTROLLED OSCILLATORS

TYPICAL APP.LlCATION DATA

free-running oscillator

Free-running oscillators can be implemented for most systems by setting the output frequency of the veo with either a
capacitor or a crystal. If excitation is provided with a capacitor the frequency control and/or range inputs can be used
to vary the output frequency.

When the 'S124 is excited with a crystal, low-frequency response (.;;;; 1 MHz) can be improved if a relatively small
capacitor (5 to 15 pF) is paralleled with the crystal. When operated at the fundamental frequency of a crystal, the
frequency control input should be high (~ 5 V) and the range input should be low (grounded) for maximum stability
over temperature and supply voltage variations.

When the 'LS124 is excited with a crystal, a small capacitor (2 to 10 pF) should be placed in series with the crystal
and the e Vee supply should be lowered to approximately 3 V. A series-resonant, fundamental-mode crystal with
series resistance less than 200 ohms should be used. The frequency control and range inputs should be grounded. The
maximum recommended frequency for crystal-excited operation is 10 MHz.

phase-locked loops

A basic crystal-controlled phase-locked loop is illustrated in Figure 1. This application can be used for implementation
of:

a. A highly stable fixed-frequency clock generator.

b. A highly stable fixed- or variable-frequency synthesizer.
c. A highly efficient "slave-clock" system for synchronizing off-card, remote, or data-interfacing clock systems
N
With fixed division rates for both M and N, the output frequency (fo) will be stable at fo = M fl. Obviously, either
ivi or N, or both, couid be programmable counters in which case the output frequency (fol wiil be a variable frequency
dependent on the instantaneous value of ij-t,.
The crystal-controlled veo can be operated up to 60 MHz with an accuracy that is dependent on the crystal. At the
higher frequencies, response of the phase comparator can become a limiting factor and one of the following approaches
may be necessary to extend the operating frequency range.
a. FreqUencies{tand k can be divided equally by the same constant (K) also shown in Figure 1. The constant can
be any value greater than unity (K> 1), and should be selected to yield frequency ranges that can be handled
adequately by the phase-comparator and filter. The output frequency (fo) retains the same relationship as
previously explained because now:
•
KN N
KM fl = fl M
b. In another method, the comparison of it
and ~ can be performed with either an SN54LS85/SN74LS85 or
SN54S85/SN74S85. The resultant A> B and A < B outputs from the 'LS85 or 'S85 permit the detector to be
simplified to a charge-pump circuit. See Figure 2.

1076

TEXAS INCORPORATED
INSTRUMENTS 7-127
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54S124, SN74S124
DUAL VOLTAGE-CONTROLLED OSCILLATORS

TYPICAL APPLICATION DATA

RGURE 1-PHASE-LOCKED LOOP FIGURE 2-HIGH-FREQUENCY PHASE-LOCKED LOOP

TYPICAL CHARACTERISTICS ('S124 only)

BASE OUTPUT FREQUENCY NORMALIZED OUTPUT FREQUENCY

vs vs

•
EXTERNAL CAPACITANCE INPUT VOLTAGE

N
1G

100M I I Vee' 5
V
Vl(freq)o= VI (rng) = 2 V
1 1.2

~
i
:r: >-
u 1.1
I 10M i TA = 25 C -< c:
>-
I I :
Q}

~i iii i
u ::J
c: i 0-
Ql I I
:::J 1M ~
0-
Ql

U: 100 k i ",I I u..

......

e
:::J

~
...... ! !
:::J :::J
e 10 k
!
!
0
0
:::J
I !
';", I ! I
I
"C
Ql
1k .!:::!
~ co
co
a:l
100
i
I
'\
~
i i E
I (5
'\ z
~
:
10 I\. I
..c
'\ '\. ..=
:§
I I
'\
0.1
10- 12 10- 10 10- 8 10-6 10- 4 10- 2
VI (freq)-Input Voltage-V
Cext-External Capacitance-F

FIGURE 3 FIGURE 4

NOTE: fo = fn X fo(base).

1076

7-128 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TTL TYPES SN54S135, SN14S135
MSI QUADRUPLE EXCLUSIVE-OR/NOR GATES
BULLETIN NO. DL-S 7211826, DECEMBER 1972

SN54S135 •.. J OR W PACKAGE

• Fully Compatible with Most TTL and SN74S135 .•• J OR N PACKAGE
TTL MSI Circuits (TOP VIEW)

• Fully Schottky Clamping Reduces Vcc 4B 4A 4Y 3C,4C 3B 3A 3Y

Delay Times ... 8 ns Typical
• Can Operate as Exclusive-OR Gate (C Input
Low) or as Exclusive-NOR Gate (C Input High)

FUNCTION TABLE
INPUTS OUTPUT
A B C Y
L L L L
L H L H
H L L H

I~ ~I
H L
11;1 1Y 1C.2C 2A
L H

I~ ~
H L
L I L positive logic: Y;;; {A(±)B)(BC == ABC + ABC +-:ABC + A8C
IH H H I H
H = high level, L = low level

schematics of inputs and outputs

EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS

--------VCC
VCC------~------

INPUT
2.8 k.\1 NOM

OUTPUT •
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . 7V
Input voltage . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range: SN54S135 _55°C to 125°C
SI\I74S135 . . aOe to 7aoe
Storage temperature range . . . . . . . . . -65°C to 15aoe
NOTE1: Voltage values are with respect to network ground terminal.

1076

TEXAS INSTRUMENTS 7-129

INCORPORATED
POST OFFICE BOX 5012 • CALLAS. TEXAS 75222
 TYPES SN54S135, SN74S135
QUADRUPLE EXCLUSIVE-OR/NOR GATES

recommended operating conditions

SN54S135 SN74S135
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, V CC 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -1 -1 rnA
Low-level output current, 10L 20 20 rnA
Operating free-air temperature, T A -55 125 0 70 DC

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONSt MIN TYP+ MAX UNIT
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
VIK Input clamp voltage VCC= MIN, II = -18mA -1.2 V

High-level output voltage

VCC = MIN, VIH=2V, I SN54S' 2.5 3.4
V
VOH
VIL = 0.8 V, 10H = -1 rnA I SN74S' 2.7 3.4
VCC= MIN, VIH=2V,
VOL Low-level output voltage 0.5 V
VIL = 0.8 V, 10L = 20mA
II Input current at maximum input voltage VCC= MAX, VI = 5.5 V 1 rnA
IIH High-level input current VCC= MAX, VI=2.7V 50 /.LA
IlL Low-level input current VCC= MAX, VI=0.5V -2 rnA
lOS Short-circuit output current§ VCC= MAX -40 -100 rnA
ICC Supply current VCC= MAX, See Note 2 65 99 rnA

t For conditions shown as MI N Or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
D
+AII typical values are at Vee = 5 V, TA = 25 e.
§ Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second.
NOTE 2: ICC is measured with the inputs grounded and the outputs open.

switching characteristics, Vee = 5 V, TA = 25°e

•
FROM
PARAMETER. TEST CONDITIONS MIN TYP MAX UNIT
(INPUT)
tpLH 8.5 13
AorB B or A = L, C = L ns
tpHL 11 15
tpLH
tpHL
i A orB B or A ~ H. C = L ! 8
9
12
13.5
ns

tpLH 10 15 I
AorB B or A = L, C= H CL=15pF, ns
tpHL 6.5 10
RL = 280 n,
tpLH 8.5 12
AorB B or A = H, C = H See Note 3 ns
tpHL 7 11
tpLH 8 12
C A=B ns
tpHL I 9.5 14.5
tpLH 7.5 11.5
C A*B ns
tpHL 8 12

• tpLH =' propagation delay time, low-to-high-Ievel output

tpH L =' propagation delay time, high-to-Iow-Ievel output
NOTE 3: Load circuit and voltage waveforms are shown on page 3-10.

1076

7·130 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TTL TYPES SN54136, SN54LS136, SN74136, SN74LS136
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
MSI WITH OPEN-COLLECTOR OUTPUTS
BULLETIN NO, DL-S 7611827, DECEMBER 1972-REVISED OCTOBER 1976

SN54136, SN54LS136", J OR W PACKAGE

SN74136, SN74LS136 , , ,J OR N PACKAGE
(TOP VIEW)
Vce 4B 4A 4Y 3B 3A 3Y

FUNCTION TABLE
INPUTS OUTPUT
A B Y
L L L
L H H
H L H
H H L
H = high level, L = low level

1A 1B 1Y 2A 2B 2Y GND

positive logic: Y = A<±)B = AB + AS

schematics of inputs and outputs

EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS

OF '136 OF '136

VCC----..--

__ ~OUTeUT
INPUT

EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS

•
OF'LS136 OF'LS136

VCC

12.5 kn NOM

_ _ ~OUTeUT
INPUT ..,....
0.
-

~~ ~~
~,

,,'7

l076

TEXAS INSTRUMENTS 7-131

INCORPORATED
POST OFFICE BOX 5012 • OALLAS, TEXAS 75222
 TYPES SN54136, SN74136
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
WITH OPEN-COLLECTOR OUTPUTS

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, Vee (see Note 1) 7V

Input voltage . . . . . . . . 5.5 V
Operating free-air temperature range: SN54136 -55°C to 125°C
SN74136 oOe to 70°C
Storage temperature range -65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54136 SN74136
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output voltage, VOH 5.5 5.5 V
Low-level output current, IOL 16 16 mA
Operating free-air temperature, T A -55 125 0 70 e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITlONS·t MIN TVP+ MAX UNIT
VIH High-level input voltage 2 V
VIL LOW-level input voltage 0.8 V
VIK Input clamp voltage Vee= MIN, II =-8mA -1.5 V
Vee= MIN, VIH=2V,
IOH High-level output current 250 j.lA
VIL = 0.8 V, VOH = 5.5 V
Vee = MIN, VIH = 2V,
VOL Low-level output voltage 0.2 0.4 V
VIL = 0.8 V, IOL = 16 mA
II Input current at maximum input voltage Vee= MAX, VI=5.5V 1 mA

•
IIH High-level input current Vee = MAX, VI = 2.4 V 40 j.lA
IlL Low-level input current Vee = MAX, VI = 0.4 V -1.6 mA
ISN54136 30 43
ICC Supply current, high-level output Vee = MAX, See Note 2 mA
JSN74136 30 50

t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device
type.
= 5 V, T A = 25°C.
+AII typical values are at Vee
NOTE 2: ICC is measured with one input of each gate at 4.5 V, the other inputs grounded, and the outputs open.

switching characteristics, Vee = 5 V, TA = 25° C

FROM
PARAMETER~ TEST CONDITIONS MIN TVP MAX UNIT
(INPUT)
tpLH 12 18
A or B Other input low eL=15pF, ns
tpHL 39 50
RL =400 n,
tpLH 14 22
AorB Other input high See Note 3 ns
tpHL 42 55

11 tp LH == propagation delay time, low-to-h igh-Ievel output

tpH L == propagation delay time, high-to-Iow-Ievel output
NOTE 3: Load circuit and voltage waveforms are shown on page 3-10•.

1076

7-132 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54LS136, SN74LS136
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
WITH OPEN-COLLECTOR OUTPUTS
REVISED OCTOBER 1976

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, Vee (see Note 1) ..... . 7V

Input voltage . . . . . . . . . . . . . . 7V
Operating free-air temperature range: SN54LS136 -55°e to 125°e
SN74LS136 aOe to 7aoe
Storage temperature range -65°e to 15aoe
NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54LS136 SN74LS136
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output voltage, VOH 5.5 5.5 V
Low-level output current, IOL 4 8 mA
Operating free-air temperature, T A -55 125 0 70 °e

eiectricai characteristics over recommended operating free-air temperature range (uniess otherwise noted;
SN54LS136 SN74LS136
PARAMETER TEST eONDITIONst UNIT
MIN TYP:j: MAX MIN TYP:j: MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
VIK Input clamp voltage Vee = MIN, 11=-18mA -1.5 -1.5 V
Vce- MIN, VIH-2V,
IOH High-level output current 100 100 /LA
VIL = VIL max, VOH = 5.5 V

Vee= MIN, IIOL = 4 mA 0.25 0.4 0.25 0.4

VOL Low-level output voltage VIH=2V, V
I I I
VIL=VILmaxi IOL=8mA 0.35 0.5 I
II Input current at maximum input voltage Vce= MAX, VI = 7V 0.2 0.2 mA

•
IIH High-level input current Vce = MAX, VI=2.7V 40 40 /LA
IlL Low-level input current Vce- MAX, VI- 0.4 V -0.8 -0.8 mA
lee Supply current Vee- MAX, See Note 2 6.1 10 6.1 10 mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
:j:AII typical values are at V CC = 5 V, T A = 25°C.
NOTE 2: ICC is measured with one input of each gate at 4.5 V, the other inputs grounded, and the outputs open.

switching characteristics, Vee =5 V, TA = 25° C

FROM
PARAMETER~ TEST CONDITIONS MIN TYP MAX UNIT
(INPUT)

tPLH 18 30
AorB Other input low eL=15pF, ns
tpHL 18 30
RL=2kn,
tpLH 18 30
A orB Other input high See Note 4 ns
tpHL 18 30

~ tpLH == propagation delay time, low-to-high-Ievel output

tpH L == propagation delay time, high-to-Iow-Ievel output
NOTE 4: Load circuit and voltage waveforms are shown on page 3-11.

1076

TEXASINCORPORATED
INSTRUMENTS 7-133
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TIL TYPES SN54LS138, SN54LS139. SN54S138, SN54S139,
SN74LS138. SN74LS139. SN74S138. SN74S139
MSI DECODERS/DEMULTIPLEXERS
BULLETIN NO. DL-S 7611 DECEMBER 1972-REVISED OCTOBER 1976

• Designed Specifically for High-Speed:

SN54LS138, SN54S138 ••• J OR W PACKAGE
Memory Decoders
SN74LS138, SN74S138 ••• J OR N PACKAGE
Data Transmission Systems (TOP VIEW)

• 'S138 and 'LS138 3-to-8-Line Decoders

Incorporate 3 Enable Inputs to Simplify DATA OUTPUTS
r -________ ________
~A~ ~

Cascading and/or Data Reception

• 'S139 and 'LS139 Contain Two Fully
Independent 2-to-4-Line Decoders/
Demultiplexers
• Schottky Clamped for High Performance

TYPICAL
TYPICAL
TYPE PROPAGATION DELAY
POWER DISSIPATION
(3 LEVELS OF LOGIC)
'LS138 22 ns 32mW
'S138 8 ns 245mW
'LS139 22 ns 34mW
'S139 7.5 ns 300mW positive logic: see function table

description
These Schottky-clamped TTL MSI circuits are SN54LS139, SN54S139 •.• J OR W PACKAGE
designed to be used in high-performance memory- SN74LS139, SN74S139 ••• J OR N PACKAGE
decoding or data-routing applications requiring very (TOP VIEW)
short propagation delay times. In high-performance
memory systems these decoders can be used to SELECT DATA OUTPUTS

minimize the effects of system decoding. When Vee EN~~LE~~

employed with high-speed memories utilizing a fast-

•
enable circuit the delay times of these decoders and
the enable time of the memory are usually less than
the typical access time of the memory. This means
that the effective system delay introduced by the

~
Schottky-clamped system decoder is negligible.

The 'LS138 and 'S138 decode one-of-eight lines

12345618
dependent on the conditions at the three binary 1G 1A 16 lYO lY1 1Y2 lY3 GND
select inputs and the three enable inputs. Two ENA6LE'-v--' ~
SELECT DATA OUTPUTS
active-low and one active-high enable inputs reduce
the need for external gates or inverters when
expanding. A 24-line decoder can be implemented
without external inverters and a 32-line decoder positive logic: see function table
requires only one inverter. An enable input can be
used as a data input for demultiplexing applications.

The 'LS139 and 'S139 comprise two individual two-line-to-four-line decoders in a single package. The active-low enable
input can be used as a data line in demultiplexing applications.

All of these decoders/demultiplexers feature fully buffered inputs each of which represents only one normalized Series
54LS/74LS load ('LS138, 'LS139) or one normalized Series 54S/74S load ('S138, 'S139) to its driving circuit. All
inputs are clamped with high-performance Schottky diodes to suppress line-ringing and simplify system design. Series
54LS and 54S devices are characterized for operation over the full military temperature range of -55°C to 125°C;
Series 74LS and 74S devices are characterized for oOe to 70°C industrial systems.

1076

7-134 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54LS138, SN54S138, SN54LS139, SN54S139
SN74LS138, SN74S138, SN74LS139, SN74S139
DECODERS/DEMULTIPLEXERS
functional block diagrams and logic

'LS138, 'S138
FUNCTION TABLE
'LS138, 'S138

INPUTS
OUTPUTS
ENABLE SELECT
G1 G2* C B A YO Y1 Y2 Y3 Y4 Y5 Y6 Y7
X H X X X H H H H H H H H
L X X X X H H H H H H H H
H L L L L I, H H H H H H H
H L L L H H L H H H H H H
DATA
OUTPUTS H L L H L H H L H H H H H
H L L H H H H H L H H H H

jr I
A H L H L L H H H H L H H H

I I~ ~I
H L L H H H H L H
SELECT 8 H H
INPUTS H L H L H H H H H H L
_ 131 "'- . "'- . H L H H H H H H H H H
l'-~
'G2 = G2A + G2B
H = high level, L = low level, X = irrelevant

'LS139, '5139

'LS139, '5139
(EACH DECODER/DEMUL TIPLEXER)
FUNCTION TABLE

INPUTS
OUTPUTS
ENABLE SELECT

•
DATA G B A YO Y1 Y2 Y3
OUTPUTS H X X H ,H H H
L L L L H H H
L L H H L H H
L H ,L H H L H
L H H H H H L

H = high level, L = low level, X = irrelevant

-
schematics of inputs and outputs
EQUIVALENT OF EACH EQUIVALENT OF EACH TYPICAL OF OUTPUTS TYPICAL OF OUTPUTS
INPUT OF 'LS138, 'LS139 INPUT OF 'S138, 'S139 OF 'LS138, 'LS139 OF 'S138, 'S139

---~~-vcc -----vcc
vcc--.......- - v cc

c
20 kn NOM 2.8 kn NOM

INPUT_.,........~~ INPUT -- L..--+__ OUTPUT OUTPUT

1272

TEXAS INSTRUMENTS
INCORPORATED
7-135
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54LS138, SN54LS139, SN74LS138, SN74LS139,
DEC 0 DERS/ DEMU LTI PLEXERS
REVISED OCTOBER 1976

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1) 7V
Input voltage 7V
Operating free-air temperature range: SN54LS138, SN54LS139 Circuits -55°C to 125°C
SN74LS138, SN74LS139 Circuits O°C to 70°C
Storage temperature range -65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54LS138 SN74LSl38
SN54LSl39 SN74LSl39 UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, IOH -400 -400 J.lA
Low-level output current, IOL 4 8 rnA
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LSl38 SN74LS138
PARAMETER TEST CONDITIONSt SN54LSl39 SN74LS139 UNIT
MIN TYP:j: MAX MIN TYP:j: MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
VIK I nput clamp voltage Vee; MIN, II ;-18mA -1.5 -1.5 V
Vee = MIN, VIH = 2 V,
VOH High-level output voltage 2.5 3.4 2.7 3.4 V
VIL = VIL max, IOH = -400 IlA
Vee= MIN, VIH = 2 V, IIOL = 4 mA 0.25 0.4 0.25 0.4
VOL Low-level output voltage V
VIL = VIL max IIOL = 8mA 0.35 0.5
Input current at

•
II Vee= MAX, VI = 7V 0.1 0.1 mA
maximum input voltage
IIH High-level input current Vee; MAX, VI = 2.7 V 20 20 Il A
IlL Low-level input current Vee - MAX, VI - 0.4 V -0.4 -0.4 mA
lOS Short-circuit output current ~ Vee; MAX -6 -40 -5 -42 rnA
Vee; MAX, I'LS138 6.3 10 6.3 10
, lee Supply current mA
I I Outputs en<lbled and open I'LS139 , 6.8 11, 5.8 111 I
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device
type.
fAil typical values are at V CC ; 5 V, T A = 25°C.
~Not more than one output should be shorted at a time.
switching characteristics, Vee = 5 V, T A = 25° C
! II
PARAMETER~ I FROM TO LEVELS
I TEST CONDITIONS
SN54LSl38
SN74LSl38 I SN54LS139
SN74LS139
IIUNIT I
(INPUT) (OUTPUT) OF DELAY
MIN TYP MAX MIN TYP MAX
tPLH 13 20 13 20 ns
2
tPHL Binary 27 41 22 33 ns
Any
tpLH Select 18 27 18 29 ns
3 eL=15pF,
tpHL 26 39 25 38 ns
RL=2kP.,
tPLH 12 18 16 24 ns
2 See Note 2
tPHL 21 32 21 32 ns
Enable Any
tPLH 17 26 ns
3
tPHL 25 38 ns

~ tp LH ==
propagation delay time, low-to-high-Ievel output; tPH L == propagation delay time, high·to-Iow-Ievel output.
NOTE 2: Load circuits and waveforms are shown on page 3-11.

1076

7-136 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54S138, SN54S139, SN74S138, SN74S139
DECODERS/DEMULTIPLEXERS

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1) 7V
Input voltage . . . . . . . 5.5 V
Operating free-air temperature range: SN54S138, SN54S139 Circuits -55°C to 125°C
SN74S138, SN74S139 Circuits aOc to 7aoC
Storage temperature range -65°C to 15aoC
NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54S138 SN74S138
SN74S139 SN74S139 UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, IOH -1 -1 mA
Low-level output current, 10L 20 20 mA
Operating free-air temperature, T A -55 125 0 70 °e

eiectricai characteristics over recommended operating free-air temperature range (unless otherwise noted)
i i
SN54S138 SN54S139
PARAMETER TEST eONDITIONst SN74S138 SN74S139 UNIT
MIN TYP:j: MAX MIN TYp:j: MAX
V,H High-level input voltage 2 2 V
V,L Low-level input voltage 0.8 0.8 V
V,K I nput clamp voltage Vee = MIN, I, = -18mA -1.2 -1.2 V

VOH High-level output voltage

Vee = MIN, VIH = 2 V,I SN54S' 2.5 3.4 2.5 3.4
V
VIL = 0.8 V, IOH=-1 mA I SN74S' 2.7 3.4 2.7 3.4
Vee = MIN, V,H = 2V,
VOL Low-level output voltage
I VIL = 0.8 V, 'OL = 20 mA
0.5 i 0.5l V i
I
II Input current at maximum input voltage Vee= MAX, VI = 5.5 V 1 1 mA

•
IIH High-level input current Vee = MAX, V, = 2.7 V 50 50 p.A
',L Low-level input current Vee= MAX, V,=0.5V -2 -2 mA
lOS Short-circuit output current§ Vee = MAX -40 -100 -40 -100 mA
ICC Supply current Vee = MAX, Outputs enabled and open 49 74 60 90 mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device
type.
+AII tYpical values are at Vee = 5 V, T A = 25°C.
~ Not more than one output should be shorted at a time, and duration of the short·circuit test should not exceed one second.

switching characteristics, Vee = 5 V, TA = 25°e

SN54S138, SN54S139
FROM TO LEVELS TEST
PARAMETER~ SN74S138 SN74S139 UNIT
(INPUT) (OUTPUT) OF DELAY CONDITIONS
MIN TYP MAX MIN TYP MAX
tPLH 4.5 7 5 7.5
2 ns
tpHL Binary 7 10.5 6.5 10
Any
tPLH select 7.5 12 7 12
3 eL=15pF, ns
tPHL 8 12 8 12
RL = 280 .11,
tPLH 5 8 5 8
2 See Note 3 ns
tPHL 7 11 6.5 10
Enable Any
tPLH i 7 11
3 ns
tpHL I
7 11 1 i
~ tpLH == propagation delay time, low·to·high·level output
tpHL == propagation delay time, high·to·low·level output
NOTE 3: Load circuits and waveforms are shown on page 3-10.

1076

TEXAS INSTRUMENTS 7-137

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TTL TYPE SN74141
MSI BCD-TO-DECIMAL DECODER/DRIVER
BULLETIN NO. DL-S 7211801, DECEMBER 1972

• Drives gas-filled cold-cathode indicator tubes directly

• Fully decoded inputs ensure all outputs are off for invalid codes
• Input clamping diodes minimize transmission-line effects

J OR N PACKAGE
FUNCTION TABLE (TOP VIEW)
OUTPUTS OUTPUTS
INPUT OUTPUT
~GND~
O!C B A ONt
L L L L 0
L L L H 1
L L H L 2
L L H H 3
L H L LI 4
L H L H 5
L H H L 6
L,HiH H 7
H LiLi L 8
H L L H 9
H L H L NONE
positive logic: see truth table
H L H H NONE
H H L L NONE
H H L H NONE
H H H L NONE
H H H H NONE functional block diagram

H = high level, L = low level A (3)

t All other outputs are off

•
description
The SN74141 is a second-generation BCD-to-decimal
decoder designed specifically to drive cold-cathode
indicator tubes. This decoder demonstrates an B (6)
improved capability to minimize switching transients
in order to maintain a stable display.

Full decoding is provided for all possible input states.

For binary inputs 10 through 15, all the outputs are 4
off. Therefore the SN74141, combined with a mini-
mum of external circuitry, can use these invalid codes II
in blanking leading- and/or trailing-edge zeros in a II
display. The ten high-performance, n-p-n output tran- c~1 II
sistors have a maximum reverse current of 50 micro-
amperes at 55 volts.

Low-forward-impedance diodes are also provided for

each input to clamp negative-voltage transitions in
order to minimize transmission-line effects. Power
dissipation is typically 80 milliwatts. The SN74141
is characterized for operation over the temperature D (4)
range of DoC to 70°C.

1076

7-138 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPE SN74141
BCD-TO-DECIMAL DECODER/DRIVER

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1) 7V
Input voltage . . . . . . . 5.5V
Current into any output (off-state) 2mA
Operating free-air temperature range O°C to 70°C
Storage temperature range -65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

MIN NOM MAX UNIT

Supply voltage, VCC . . . . . . 4.75 5 5.25 V
Off· state output voltage 60 V
Operating free-air temperature, T A o 70°C

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
- -
PARAMETER TEST CONDITIONSt MIN TYP:j: MAX UNIT
V!H High-level input voltage 2 \I

VIL Low-level input voltage 0.8 V

VIK Input clamp voltage Vee = MIN, 11= -5 mA -1.5 V
VO(on) On-state output voltage Vee - MIN, 10 -7 mA 2.5 V
Off-state output voltage
VO(off) Vee = MAX, 10 = 0.5mA 60 V
for input counts 0 thru 9
10(0ff) Off-state reverse cu rrent Vee= MAX, Vo = 55 V 50 p.A
Off-state reverse current Vee = MAX, ITA = 55° e 5
10 (off) 0 /lA
for input counts 10 thru 15 Vo = 30 V ITA =70 e 15

'I Input current at maximum input voltage

A input
I Vee = MAX, Vi =5.5V
40
1 mA

IIH High-level input current Vee = MAX, VI = 2.4 V /lA

•
B, e, or D input 80
A input -1.6
IlL Low-level input current Vee = MAX, VI = 0.4 V mA
B, e, or D input -3.2
lee Supply current Vee = MAX, See Note 2 16 25 mA

t For conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions.
:j:This typical value is at V CC = 5 V, T A = 25° C.
NOTE 2: ICC is measured with all inputs grounded and outputs open.

schematics of inputs and outputs

EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS

Vcc------e~-----

'---",-OUTPUT

INPUT-. .~. .-e~M-~~e--

, - - -. .- OUTPUT

Input A: Req = 6 kn NOM

Inputs S, C, D: Req = 2 kn NOM

1076

7-139
TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TTL TYPE SN14142
MSI BCD COUNTER/4-BIT LATCH/BCD DECODER/DRIVER
BULLETIN NO. DL·S 7211719, MAY 1972-REVISED DECEMBER 1972

JOR N
DUAL-IN-LINE PACKAGE (TOP VIEW)
FUNCTION TABLE
CLOCK/ LATCH DRIVER OUTPUTS
INPUTS OUTPUTS COUNT GD STROBE ~
COUNT PULSE LATCH VCC INPUT OUTPUT INPUT 9 8 0 1
CLEAR ONt CD
(CLOCK) STROBE
X L L 0 H
1 H L 1 H
2 H L 2 H
3 H L 3 H
4 H L 4 H
5 H L 5 H
6 H L 6 H
7 H L 7 H
8 H L 8 L
9 H L 9 L
10 H L 0 H
11 H H 0 H
~--~--~~v~~--~--~
t All other outputs are off. DRIVER OUTPUTS
H = hi9h level, L = low level, X = irrelevant
positive logic: see function table and description
description

The SN74142 contains a divide-by-ten (BCD) counter, a four·bit latch, and a decoder/Nixie:!: tube driver on a
monolithic chip and is packaged in popular 16-pin packages. This single MSI function can replace the equivalent of
three separately packaged MSI circuits to reduce printed-circuit board area and the number of system interconnections,
resulting in reduced costs and improved reliability.

Four master-slave flip-flops are fully decoded to provide a divide-by-ten counter. A direct clear input will, when taken
low, reset and hold the counter at zero (all Q outputs low, GO output high). While the clear input is inactive (high),

•
each positive-going transition of the clock will increment the counter. The GO output is made available externally for
cascading to n-bit counters.

The Q outputs of the counter are routed to the data inputs of the four-bit latch. While the latch strobe input is low, the
internal latch outputs will follow the respective Q outputs of the counter. When the latch strobe input is taken high, the
latch stores the data Which has been setup by the counter outputs prior to the low·to·high level transition of the latch
strobe input. The DO output from the counter is not stored by the latch since it is intended for clocking the next
counter stage. This means that the system counter can continuously acquire new data. Since all outputs of the latch and
Q outputs of the counter drive low-capacitance on-chip loads, the circuitry is considerably simplified with respect to
the number of components required. This results in a highly efficient function which typically reduces power
requirements 15% when compared to systems using the three separate packages.

The SN74142 counter/latch/driver features fully buffered inputs to reduce drive requirements to one normalized Series
74 load per input, and diode-clamping of all inputs to minimize transmission line effects. The counter will accept input
clock frequencies up to 20 MHz and is entirely compatible for use with all popular TTL and DTL logic circuits. The
high-performance n·p-n driver outputs are identical to the SN74141 and have a maximum off-state reverse current of 50
microamperes at 55 volts.

*Nixie is a registered trademark of the Burroughs Corporation.

572

7-140 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPE SN74142
BCD COUNTER/4-BIT LATCH/BCD DECODER/DRIVER

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, Vee (see Note 1) 7V

I nput voltage . . . . . . . 5.5 V
Off-state current into outputs 0 thru 9 1 mA
Operating free·air temperature range oOe to 70°C
Storage temperature range -65°C to 150°C
NOTE 1: All voltage values are with respect to the network ground terminal.

recommended operating conditions

MIN "'OM MAX UNIT
Supply voltage, Vee 4.75 5 5.25 V
High-level output current from QO, 10H -400 J.LA
Low·level output current from QO, 10L 8 mA
Input clock frequency, fclock 0 20 MHz

elock pulse width, tw(c1ock) (see Figure 1)

I High logic level 15
ns
I Low logic level 35
elear pulse width, tw(c!earl (see Figure 1) 25 .. -
Strobe pulse width, tw(strobe) (see Figure 1) 20 ns
Clear inactive-state setup time, tsu (see I-igure 1) 25 ns
t w (c1ock)·
Strobe time, tstrobe (see Figure 1) 45 ns
+10
Operating free-air temperature, T A 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONSt MIN TYP:j: MAX UNIT
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
VIK Input clamp voltage Vee= MIN, II = -12mA -1.5 V
VOH High-level QO output voltage Vce= MIN, 10H = -400J.LA 2.4 3.4 V

•
VOL Low-level QO output voltage Vee = MIN, 10L = 8 mA 0.2 0.4 V
VO(on) On-state voltage, outputs 0 thru 9 Vce= MIN, 10 = 7 mA 2.5 V
VO(off) Off-state voltage, outputs 0 thru 9 Vee= MAX, 10= 0.5mA 60 V
a
I (oft) Off-state current, outputs 0 thru 9 Vce= MAX, VO= 55V 50 J.LA
II Input current at maximum input voltage Vee= MAX, VI = 5.5 V 1 mA
IIH High-level input current Vee = MAX, VI = 2.4 V 40 J.LA
IlL Low-level input current Vee = MAX, VI = 0.4 V -1.6 mA
lOS Short-circuit QO output current Vee= MAX -18 -55 mA
lee Supply current Vee= MAX, All outputs open 68 102 mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at VCC = 5 V, T A = 25°C.

switching characteristics, Vee =·5 V, TA = 25° C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Propagation delay time, low-to-high-Ievel
tpLH 35 55
50 output from clock
eL=15pF, ns
Propagation delay time, high-to-Iow-Ievel
tpHL RL = 800 n, 30 45
Co output from clock
See Figure 1
Propagation delay time, low-to-high-Ievel
tpLH 30 45 ns
Co output from clear

1076

TEXAS INCORPORATED
INSTRUMENTS 7-141
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPE SN14142
BCD COUNTER/4-BIT LATCH/BCD DECODER/DRIVER

schematics of inputs and outputs

EQUIVALENT OF EACH INPUT OUTPUT Q TYPICAL OF OUTPUTS 0 THRU 9
-~~-VCC

VCC-----.------ OUTPUT

INPUT
OUTPUT

PARAMETER MEASUREMENT INFORMATION

OUTPUT Vee

FROM
OUTPUT - -. .--~~~-t~~~~~
QD

LOAD CIRCUIT

tA ts

tw(clear) I- .1
~tsu :
I
CLEAR
~~~ ______ ~ ____s~ ______s~ _______ ::
•
INPUT

I I I
I I 1
CLOCK -----:"""\ I I 1.S V ..r-:\. 1.S V .r::'\ - -- 3V
INPUT

_...1...-1._---91;.,----:-.....!1 -twiciock;H ~i
I1
- YH-
I
'-----ov
I . I
twtclockl L
1 : I- -I tw(strobe) 1 I 3V
LATCH ----~I----------~I~~ J( I
STROBE I 11.S V "'----'l_l.S V 1
(See NoteS) I.----.t-tPLH I \---------:------ -l------OV
I I-(se;%:~s)-I tPHL~ I----it
PLH

OUTPUT
00 _____..""v l~s___E=:::
VOLTAGE WAVEFORMS

NOTES: A. This typical abbreviated sequence illustrates clearing from count 8 or 9 and counting through ten clock pulses. Clock pulses 3
through 7 and 9 are omitted for brevity.
B. Strobe input can go low at any time; however, the positive transition to store data from any given clock transition (tAl must
occur a minimum of 45 ns after tA and prior to 10 ns after the next positive-going clock transition (tB + 10 nsl.
C. Input pulses are supplied by generators having the following characteristics: tr';; 7 ns, tf .;; 7 ns, PRR = 1 MHz, and Zout '" 50 n.
D. CL includes probe and jig capacitance.
E. All diodes are 1 N3064.

FIGURE 1

1076

7·142 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TTL TYPES SN54143, SN54144, SN74143, SN74144
MSI 4-81T COUNTER/LATCH, SEVEN-SEGMENT LED/LAMP DRIVERS
BULLETIN NO. DL·S 7211538, NOVEMBER .1971-REVISED DECEMBER 1972

SN54143,SN54144 ••• J OR W PACKAGE

SN74143, SN74144 ••• J OR N PACKAGE
(TOP VIEW)
LATCH ~
LATCH OUTPUTS
______ ____A~
LED/LAMP
________DRIVER
~ ~
OUTPUTS
________
JI'~ ~

MAX STROBE
VCC COUNT INPUT 0c 0B 0A \ I \
22

e /
NODE --------.v
LED/LAMP DRIVER OUTPUTS

logic: see description

• Choice of Driver Outputs:

SN54143 and SN74143 have 15-mA Constant-Current Outputs for Driving Common-Anode LED's such as TI L302 or
TI L303 without Series Resistors

SN54144 and SN74144 Drive High-Current Lamps, Numitrons t, or LED's from Saturated Open-Collector Outputs

•
• Universal Logic Capabilities
Ripple Blanking of Extraneous Zeros
Latch Outputs Can Drive Logic Processors Simultaneously
Decimal Point Driver Is Included

• Synchronous BCD Counter Capability Includes:

Cascadable to N-Bits
Look-Ahead-Enable Techniques Minimize Speed Degradation When Cascaded for Large-Word Display
Direct Clear Input
description
These TTL MSI circuits contain the equivalent of 86 gates on a single chip. Logic inputs and outputs are completely
TTL/DTL compatible. The buffered inputs are implemented with relatively large resistors in series with the bases of the
input transistors to lower drive-current requirements to one-half of that required for a standard Series 54/74 TTL input.
The serial-count-enable, actually two internal emitters, is rated as one standard series 54/74 load. The logic outputs,
except RBO, have active pull-ups.
The SN54143 and SN74143 driver outputs are designed specifically to maintain a relatively constant on-level sink
current of approximately 15 milliamperes from outputs "a" through "g" and seven milliamperes from output "dp"
over a voltage range from one to five volts. Any number of LED's in series may be driven as long as the output voltage
rating is not exceeded.

tTrademark of RCA

1076

TEXAS INSTRUMENTS 7-143

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54143, SN54144, SN74143, SN74144
4-81T COUNTER/LATCH, SEVEN-SEGMENT LED/LAMP DRIVERS
description (continued)

The SN54144 and SN74144 drivers have high-sink-current saturated outputs for driving indicators having voltage
ratings up to 15 volts or requiring up to 25 milliamperes drive. The SN54144 sinks 20 milliamperes and the SN74144
sinks 25 milliamperes at an on-level voltage of 0.6 volts across their respective operating temperature ranges.

All inputs are diode-clamped to minimize transmission-line effects, thereby simplifying system design. Maximum clock
frequency is typically 18 megahertz and power dissipation is typically 280 milliwatts. The SN54143 and SN54144 are
characterized for operation over the full military temperature range of -55°C to 125°C; the SN74143 and SN74144
are characterized for operation from 0° C to 70° C.

Functions of the inputs and outputs of these devices are as follows:

FUNCTION PIN NO. DESCRIPTION
CLEAR INPUT 3 When low, resets and holds counter at O. Must be high for normal
counting.
CLOCK INPUT 2 Each positive-going transition will increment the counter provided that the
circuit is in the normal counting mode (serial and parallel count enable
inputs low, clear input high).
PARALLEL COUNT 23 Must be low for normal counting mode. When high, counter will be
ENABLE INPUT (PCEI) inhibited. Logic level must not be changed when the clock is low.
SERIAL COUNT Must be low for normal counting mode, also must be low to enable
ENABLE INPUT (SCEI) maximum count output to go low. When high, counter will be inhibited
and maximum count output will be driven high. Logic level must not be
changed when the clock is low.
MAXIMUM COUNT 22 Will go low when the counter is at 9 and serial count enable input is low.
OUTPUT Will return high when the counter changes to 0 and will remain high during
counts 1 through 8. Will remain high (inhibited) as long as serial count
enable input is high.
LATCH STROBE 21 When low, data in latches follow the data in the counter. When high, the
INPUT data in the latches are held constant, and the counter may be operated
independently.

• LATCH OUTPUTS
(OA, OB, OC, 0D)

DECIMAL POINT
!NPUT
BLANKING INPUT
(BI)
17,18,19,20

5
The BCD data that drives the decoder can be stored in the 4-bit latch and
is available at these outputs for driving other logic and/or processors. The
binary weights of the outputs are: OA = 1, OB = 2, Oc = 4, OD = 8.
Must be high to display decimal point. The decimal point is not displayed
when this input is low or when the display is blanked.
When high, will blank (turn off) the entire display and force RBO low.
Must be low for normal display. May be pulsed to implement intensity
control of the display.
RIPPLE-BLANKING 4 When the data in the latches is BCD 0, a low input will blank the entire
INPUT (RBI) display and force the RBO low. This input has no effect if the data in the
latches is other than O.
RIPPLE-BLANKING 6 Supplies ripple blanking information for the ripple blanking input of the
OUTPUT (RBO) next decade. Provides a low if BI is high, or if RBI is low and the data in
the latches in BCD 0; otherwise, this output is high. This pin has a resistive
pull-up circuit suitable for performing a wire-AND function with any
open-collector output. Whenever this pin is low the entire display will be
blanked; therefore, this pin may be used as an active-low blanking input.
LED/LAMP DRIVER 15,16,14,9 Outputs for driving seven-segment LED's or lamps and their decimal
OUTPUTS 11,10,13,8 points. See segment identification and resultant displays on following
(a, b, c, d, e, f, g, dp) page.

1171

7-144 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54143, SN54144, SN74143, SN74144
4-81T COUNTER/LATCH, SEVEN-SEGMENT LED/LAMP DRIVERS

o 2 3 4 5 6 7 8 9
SEGMENT
NUMERICAL DESIGNATIONS-RESULTANT DISPLAYS
IDENTIFICATION

schematics of inputs and outputs

'143, '144 '143, '144 '143 '144

EQUIVALENT OF EQUIVALENT OF TYPICAL OF ALL TYPICAL OF

EACH INPUT SI/RBO OUTPUTS EXCEPT SI/RSO ALL OUTPUTS
EXCEPT SI/RBO EXCEPT SI/RBO

Vee

A
I - -

"'llA:
NOM
X;C
OUTPUT/INPUT
, I •
NOM
-
__ ~OUTPUT

* i " ~ I ( ~20 "Y I

I INPUT --
I _ OUTPUT

i f
seEI: Req
Other
inputs: Req
= 4 kn
=8
Ih
NOM

kn NOM
I
II - ---r-(
t 1 I ~
11 .. ILJ ------'lNOM
n

~----~------~~--------------------~~-------------------------
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . 7V
Input voltage . . . . . . . . . . . . . . . . . 5.5 V
Off-state voltage at outputs "a" thru "g" and "dp", '144 . 15 V
Off-state current at outputs "a" thru "g" and "dp", '143 250f.lA

•
Continuous total power dissipation at (or below) 70°C free-air temperature (see Note 2) 1.4 W
Operating free-air temperature range: SN54' Circuits -55°C to 125°C
SN74' Circuits . . O°C to 70°C
Storage temperature range . . . . . . . . . . . -65°C to 150°C
NOTES: 1. Voltage values are with respect to network ground terminal.
2. For t~e SN54143 .and SN54144 in the N. and W packages, this rating ap~lies at (or below) 80°C free-air tem~erature. For
operation above this temperature, derate linearly at the rate of 11.7 mW/ e for the W package and 14.7 mW/ e for the N
package. No derating is required for these devices in the J package.
recommended operating conditions
SN54143, SN54144 SN74143, SN74144
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, VCC 4.5 5 5.5 4.75 5 5.25 V
On-state voltage at outputs a thru g and dp ('143 only) 1 5 1 5 V
QA, aS, 0c, 00 -240 -240
High-level output current, IOH Maximum count -560 -560 p.A
RBO -120 -120
°A,OB,OC,OO,RBO 4.8 4.8
Low-level output current, IOL rnA
Maximum count 11.2 11.2
High logic level 25 25
Clock pulse width, tw(clock) ns
Low logic level 55 55
Clear pulse width, tw(clear) 25 25 ns
Serial and parallel carry 30t 30t
Setup time, tsu ns
Clear inactive state 60t 60t
Operating free-air temperature, T A -55 125 0 70 °c
tThe arrow indicates that the rising edge of the clock pulse is used for reference.

1076

TEXASINCORPORATED
INSTRUMENTS 7·145
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54143, SN54144, SN74143, SN74144
4-81T COUNTER/LATCH, SEVEN-SEGMENT LED/LAMP DRIVERS

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54143, SN74143 SN54144, SN74144
PARAMETER TEST eONDITIONst UNIT
MIN TYP:j: MAX MIN TYP:j: MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0_8 0.8 V
VIK I nput clamp voltage Vee= MIN, II = -12 mA -1.5 -1.5 V
RBO
High-level output Vee = MIN, VIH = 2 V,
VOH QA, QB, Qe, QD 2.4 2.4 V
voltage VIL=0.8V, 10H = MAX
Maximum count
Low-level output QA, QB, Qe, QD, RBO Vee = MIN, VIH = 2 V,
VOL 0.4 0.4 V
voltage Maximum count VIL = 0.8 V, 10L = MAX
Off-state
VO(off) Outputs a thru g, dp Vee = MAX, 10H = 250 IJ.A 7 15 V
output voltage
On-State
VO{on) Outputs a thru g, dp Vee= MIN, See Note 3 0.6 V
output voltage
Vee = MIN, VO= 1 V 9 15
Outputs a thru 9 Vee = 5 V, Vo = 2V 15
On-state Vee = MAX, Vo = 5V 15 22
10(on) mA
output current Vee - MIN, Vo -1 V 4.5 7
Output dp Vee = 5 V, Vo = 2V 7
Vee - MAX, Vo - 5V 7 12
II Input current at maximum input voltage Vee = MAX, VI = 5.5 V 1 1 mA
Serial carry 40 40 IJ.A
High-level
IIH RBO node Vee = MAX, VI = 2.4 V -0.12 -0.5 -0.12 -0.5 mA
input current
Other inputs 20 20 IJ.A
Serial carry -1.6 -1.6
Low-level Vee = MAX, VI=O.4V,
IlL RBO node -1.5 -2.4 -1.5 -2.4 mA
input current See Note 4
Other inputs -0.8 -0.8
Short-circuit QA, QB, Qe, QD -9 -27.5 -9 -27.5
lOS Vee = MAX mA
output current Maximum count -15 -55 -15 -55

•
ICC Supply current Vee = MAX, See Note 5 56 93 56 93 mA

t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
:j:AII typical values are at VCC = 5 V, T A = 25°C.
NOTES: 3. For SN54144, IOL = 20 mA; for SN74144, IOL = 25 mAo
4. II L at RBO node is tested with BI grounded and RBI at 4.5 V.
5. !CC is measlJred after the following conditiuns are established:
a) Strobe = RBI = DP = 4.5 V
b) Parallel count enable = serial count enable = BI = GND
c) U::)
Clear ("'1...r) then clock until all outputs are on
d) For '143, outputs "a" through "g" and "dp" = 2.5 V, all other outputs open. For '144, all outputs are open.

switching characteristics, Vee = 5 V, TA = 25°e

PARAMETERs I FROM
(INPUT)
TO
(OUTPUT) i TEST CONDITIONS I MIN TYP MAX I I
UNIT

f max 12 18 MHz
tpLH 12 20
tpHL
Serial look-ahead Maximum count
eL = 15 pF, RL = 560 n, 23 35
ns I
tPLH See Note 6 26 40
Clock Maximum count ns
tpHL 29 45

tPLH 28 45
Clock QA, QB, Qe, QD eL = 15 pF, RL = 1.2 kn, ns
tpHL 38 60
See Note 6
tpHL Clear QA, QB, QC, QO 57 90 ns

§fmax "" Maximum clock frequency, tpLH "" Propagation delay time, low-to-high-Ievel output,
tpH L "" Propagation delay time, high-to-Iow-Ievel output
NOTE 6: Load circuit and voltage waveforms are shown on page 3-10.

1076

7·146 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54143, SN54144, SN74143, SN74144
4-81T COUNTER/LATCH, SEVEN-SEGMENT LED/LAMP DRIVERS

functional block diagram

OUTPUTS

dp

l>---..------ . ~ I I I
~ I
RIPPLE 8L4.NK!NG
I I
D!;C!~..A.L
BLANKING INPUT

I
I
--<:t> ... Dynamic input activated by a transition from a high level to a low level.
I
I

TYPICAL APPLICATION DATA

This application demonstrates how the drivers may be cascaded for N-bit display applications. It features:

Synchronous, look-ahead counting

Ripple blanking of leading zeros; blanking of trailing zeros (not illustrated) can also be implemented

•
Overriding blanking -for total suppression or intensity modulation of display
Direct parallel clear
Latch strobe permits counter to acquire next display while viewing current display

MOST-SIGNIFICANT LED/LAMP DRIVER OUTPUTS LEAST-SIGNI FICANT

RIPPLE BLANK ING - DIGIT
DIGIT
INPUT 1\
CLOCK INPUT 111111111 1111 iii I II I II I I I I I I I I 11\
LATCH STROBE
INPUT
t~ ~~~~: :~,,~ U L ~~ 7;:~;~ U l ~~:;:7;~ U L ~~~" H~A
STROBE CK

p-----------<:
STROBE CK

p----------c
STROBE CK

p-----------<:
STROBE CK
J
p- 0 PEN

nr "' ""'"' ' ' -

TO NEXT l........(: RBI RBO RBI RBO RBI RBO RBI RBO
MORE
----< ~;~NT p-----------<: ~;~NT P----------< ~~NT h ~;~NT ht
=if "' "'''''''''''''~ r"' "'' ' ' ' ' ' ~ r"' ",, , , , , ,",
SIGNIFICANT SCEI SCEI SCEI SCEI
DIGIT
CLEAR PCEI CLEAR PCEI CLEAR PCEI - CLEAR PCEI f>"i
OVERRIDING
BLANKING INPU T l
H
J
CLEAR INPUT

I
DECIMAL POINT
INPUTS {
v
LATCH LOGIC OUTPUTS

tThe serial count-enable input of the least-significant digit is normally grounded; however, it may be used as a count-enable control for the
entire counter (high to disable, low to count) provided the logic level on this pin is not changed while the clock line is low or false counting
may result.

1076

TEXAS INSTRUMENTS INCORPORATED

7-147
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TTL TYPES SN54145, SN54LS145, SN74145, SN74LS145
MSI BCD-lO-DECIMAL DECODERS/DRIVERS
BULLETIN NO. DL-S 7611815. MARCH 1974-REVISED OCTOBER 1976

FOR USE AS LAMP, RELAY, OR MOS DRIVERS

SN54145, SN54LS145, . ,J OR W PACKAGE
• Full Decoding of Input Logic SN74145, SN74LS145 . , ,J OR N PACKAGE
(TOP VIEW)
• SN54145, SN74145, and SN74LS145 Have
SO-rnA Sink-Current Capability
• All Outputs Are Off for Invalid
BCD Input Conditions
• Low Power Dissipation of 'LS145 ...
35 mW Typical
logic
FUNCTION TABLE
INPUTS OUTPUTS
NO:
D C B A 0 1 2 3 4 5 6 7 8 9
0 L L L L L H H H H H H H H H
l' L L L H H L H H H H H H H H
2 L L H L H H L H H H H H H H
3 L L H H H H H L H H H H H H
4 L H L L H H H H L H H H H H
.
5 L H L H H H H H H L H H H H OuTPUTS
6 L H H L H H H H H H L H H H
7 L H H H H H H H H H H L H H positive logic: see function table
8 H L L L H H H H H H H H L H
9 H L L H H H H H H H H H H L
H L H L H H H H H H H H H H
Q H L H H H H H H H H H H H H
:J H H L L H H H H H H H H H H functional block diagram
«
> H H L H H H H H H H H H H H
~ H H H L H H H H H H H H H R
H H H H H H H H H H H H H H

= high = low level

I
H level (oft), L (on)

description

These monilithic BCD-to-decimal decoder/drivers

consist of eight inverters and ten four-input NAND
gates. The inverters are connected in pairs to make
BCD input data available for decoding by the NAND
gates. Full decoding of valid BCD input logic ensures
that all outputs remain off for all invalid binary input
conditions. These decoders feature high-performance,
n-p-n output transistors designed for use as indicator/
relay drivers or as open-collector logic-circuit drivers.
Each of the high-breakdown output transistors
(15 volts) of the SN54145, SN74145, or SN74LS145
will sink up to 80 milliamperes of current. Each input
is one Series 54/74 or Series 54LS/74LS standard
load, respectively. Inputs and outputs are entirely
compatible for use with TTL or DTL logic circuits,
and the outputs are compatible for interfacing with
most MOS integrated circuits. Power dissipation is
typically 215 milliwatts for the '145 and 35 milliwatts
for the 'LS145.

1076

7-148 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 lYPES SN54145, SN74145
BCD-lO-DECIMAL DECODERS/DRIVERS

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, Vee (see Note 1) 7V

Input voltage . . . . . . . . 5.5 V
Maximum current into any output (off-state) 1 mA
Operating free-air temperature range: SN54145 -55°C to 125°C
SN74145 aOe to 7aoe
Storage temperature range -65°C to 15aoe
NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54145 SN74145
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
Off-state output voltage, VO(off) 15 15 V
Operating free-air temperature, T A -55 125 0 70 °e
_.-

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONSt MIN TYPt MAX UNIT
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
VIK Input clamp voltage Vee= MIN, II = -12 rnA -1.5 V
Vee = MIN, VIH=2V,
10(off) Off-state output current 250 /JA
VIL = 0.8 V, VO(off) = 15 V
Vee= MIN, VIH=2V, 110(on) = 80 rnA 0.5 0.9
VO(on) On-state output voltage V
VIL = 0.8 V 110(on) = 20 rnA 0.4
!; Input current at maximum input voltage Vee = MAX, Vi = 5.5 V i rnA
IIH High-level input current Vee = MAX, VI=2.4V 40 /JA
IlL Low-level input current Vee= MAX, VI=OAV -1.6 rnA
ISN54145 43 62
lee Supply current Vee = MAX, See Note 2 rnA
ISN74145

tFor conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions.
tAil typical values are at VCC = 5 V. T A = 25°C.
43 70

II
NOTE 2: ICC is measured with all inputs grounded and outputs open.

switching characteristics, Vee = 5 V, TA = 25°e

PARAMETER 1 TEST CONDITIONS I MIN MAX I UNIT
Propagation delay time, low-to-high-Ievel output 1
RL = 100 n, See Note 3 1 50 I ns
Propagation delay time, high-to-Iow-Ievel output I eL = 15 pF,
I 50 I ns

NOTE 3: Load circuit and waveforms are shown on page 3-10.

schematics of inputs and outputs

EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS
Vcc _ _ _ _- -

OUTPUT

INPUT

1076

TEXAS INCORPORATED
INSTRUMENTS 7-149
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54LS145, SN74LS145
BCD-lO-QECIMAL DECODERS/DRIVERS
REVISED OCTOBER 1976

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, Vee (see Note 1) 7V

Input voltage . . . . . . . . . . . . . . 7V
Operating free-air temperature range: SN54LS145 -55°C to 125°C
SN74LS145 aOe to 7aoe
Storage temperature range -65°C to 15aoe
NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54LS145 SN74LS145
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
Off-state output voltage, VO(off) 15 15 V
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS145 SN74LS145
PARAMETER TEST CONDITIONSt UNIT
MIN TYP:j: MAX MIN TYP:j: MAX
VIH High-level input voltage 2 2 V
VIL Low·level input voltage 0.7 0.8 V
VIK Input clamp voltage Vee= MIN, II = -18 mA -1.5 -1.5 V
Vee = MIN, VIH = 2 V,
10(off) Off-state output current 250 250 p.A
VIL = VIL max, VOH = 15 V
Vee = MIN, IIOL = 12 mA 0.25 0.4 0.25 0.4
VO(on) On-state output voltage VIH = 2 V, tlOL = 24 mA 0.35 0.5 V
Vil = Vil max II0l = 80 mA 2.3 3
II Input current at maximum input voltage Vee = MAX, VI = 7V 0.1 0.1 mA

•
IIH High-level input current Vee= MAX, VI=2.7V 20 20 p.A
III low-level input current Vee= MAX, VI = 0.4 V -0.4 -0.4 mA
lee Supply current Vee= MAX, See Note 2 7 13 7 13 mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at VCC = 5 V. T A = 25°C.
NOTE 2: ICC is measurod with a!! inputs grounded and ovtputs ope~.

switching characteristics, Vee = 5 V, TA = 25°e

PARAMETER TEST CONDITIONS MIN MAX
J--:tP...:;l::.;H..:......_P_r_op:...a...;;g_at_io_n_d_e_la_y_t_im_e,_I_ow..,--to_-_h...:;ig_h_-le_v_e_1o_u_t,;..pu_t-l el = 45 pF, 50
See Note 4
tpHl Propagation delay time, high-to-Iow.level output 50

NOTE 4: Load circuit and waveforms are shown on page 3-11.

schematic of inputs and outputs

INPUT
VCC

q -
EQUIVALENT OF EACH INPUT

17 kfl NOM
--
TYPICAL OF ALL OUTPUTS

1076

7-150 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TTL TYPES SN54147, SN54148, SN54LS147, SN54LS148,
SN74147, SN74148 {TIM9907),SN74LS147, SN74LS148
MSI 10-UNE-TO-4-UNE AND 8-UNE-TO-3-UNE PRIORITY ENCODERS
BULLETIN NO. o LoS 7611727, OCTOBER-1S-76

'147, 'LS147
SN54147, SN54LS147 ••• J OR W PACKAGE
• Encodes 10-Line Decimal to 4-Line BCD SN74147, SN74LS147 ••• J OR N PACKAGE
(TOP VIEW)
• Applications Include: INPUTS
NC OU-g'UT~OU-ZUT
Keyboard Encoding
Range Selection
'148, 'LS148
• Encodes 8 Data Lines to 3-Line Binary (Octal)
• Applications Include:
N-Bit Encoding
Code Converters and Generators

TYPICAL TYPICAL
TYPE DATA POWER
DElAY DlSS!PAT!QN
'147 10 ns 225mW positive logic: see function table
'148 10 ns 190mW
NC-No internal connection
'LS147 15 ns 60mW
'LS148 15 ns 60mW SN54148, SN54LS148 • ,. J OR W PACKAGE
SN74148, SN74LS148 ••• J OR N PACKAGE
(TOP VIEW)
description
These TTL encoders feature priority decoding of the
inputs to ensure that only the highest-order data line
is encoded. The '147 and 'LS147 encode nine data
lines to four-line (8-4-2-1) BCD. The implied decimal
zero condition requires no input condition as zero is
encoded when all nine data lines are at a high logic

•
level. The '148 and 'LS148 encode eight data lines to
three-line (4-2-1) binary (octal). Cascading circuitry
(enable input EI and enable output EO) has been
provided to allow octal expansion without the need
for external circuitry. For all types, data inputs and
outputs are active at the low logic level. All inputs are
buffered to represent one normalized Series 54/74 or
54LS/74LS load, resp-ectively.
positive logic: see function table

'147, 'LS147 '148, 'LS148

FUNCTION TABLE FUNCTION TABLE
INPUTS OUTPUTS INPUTS OUTPUTS
1 2 3 4 5 6 7 8 9 0 C B A EI 0 1 2 3 4 5 6 7 A2 Al AO GS EO
H H H H H H H H H H H H H H X X X X X X X X H H H H H
X X X X X X X X L L H H L L H H H H H H H H H H H H L
X X X X X X X L H L H H H L X X X X X X X L L L L L H
X X X X X X L H H H L L L L X X X X X X L H L L H L H
X X X X X L H H H H L L H L X X X X X L H H L H L L H
X X X X L H H H H H L H L L X X X X L H H H L H H L H
X X X L H H H H H H L H H L X X X L H H H H H L L L H
X X L H H H H H H H H L L L X X L H H H H H H L H L H
X L H H H H H H H H H L H L X L H H H H H H H H L L H
L H H H H H H H H H H H L L L H H H H H H H H H H L H

H = ~igh logic level, L = low logic level, X = irrelevant

1076
TEXAS INSTRUMENTS 7-151
INCORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54147, SN54148, SN54LS147, S-N54LS148.
SN74141. _ SN74148 (TIM9907), S-N74L8141, SN74L8148
10-LlNE-TO-4-LlNE AND 8-LlNE-TO-3-LlNE PRIORITY ENCODERS
functional block, diagrams

1076

7-152 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES S~54147, S1\(54148, SN54LS147, SN54LS148,
SN74147, SN74148 (TIM9907) SN74LS147, SN14LS148
10-LlNE-TO-4-LlN~ AND 8-LlNE-TO-3-LlNE PRIORITY ENCODERS

schematics of inputs and outputs

'147, '148

EaUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS

Vee ---~.....- - - -----1.....- - V e e

INPUT

OUTPUT

o input ('148): Req = 2 kn NOM

All other inputs: Req = 4 kn NOM

'LS147, 'LS148
EaUiVALENT OF ALL iNPUTS TYPICAL OF ALL OUTPUTS

----~~-Vee
Vee------1.....- -

INPUT-...,..........,.....-..-.

OUTPUT

--tz}
'LS148 inputs 1 thru 7: Req = 9 kn NOM

Input voltage: '147, '148

All other inputs: Req = 18 kn NOM

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1)

'LS147, 'LS148
. 7V
5.5 V
. 7V
•
I nteremitter voltage: '148 only (see Note 2) 5.5 V
Operating free-air temperature range: SN54', SN54LS Circuits -55°C to 125°C
SN74', SN74LS Circuits aOc to 7aoC
Storage temperature range -65°C to 15aoC
NOTES: 1. Voltage values, except intermitter voltage, are with respect to network ground terminal.
2. This is the voltage between two emitters of a multiple-emitter transistor. For '148 circuits, this rating applies between any two of
the eight data lines, 0 through 7.

recommended operating conditions

SN54' SN74' SN54LS' SN74LS'
UNIT
MIN NOM MAX MIN NOM MAX MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 4.5 5 5.5 4.75 5 5.25 V
High-level output current, IOH -800 -800 -400 -400 p.A
Low-level output current, IOL 16 16 4 8 rnA
Operating free-air temperature, T A -55 125 0 70 -55 125 0 70 °e

1076

TEXASINCORPORATED
INSTRUMENTS 7-153
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54147. SN54148. SN74147. SN74148(TIM9907)1
10-UNE-TO-4-UNE AND 8-UNE-TO-3-UNE PRIORITY ENCODERS

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

'147 '148
PARAMETER TEST CONDITIONSt UNIT
MIN TVP:j: MAX MIN TVP:j: MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
VIK I nput clamp voltage Vee= MIN, II = -12 mA -1.5 -1.5 V
Vee= MIN, VIH=2V,
VOH High-level output voltage 2.4 3.3 2.4 3.3 V
VIL = 0.8 V, 10H = -SOOIlA
Vee- MIN, VIH - 2 V,
VOL Low-level output voltage 0.2 0.4 0.2 0.4 V
VIL = 0.8 V, 10L = 16mA
II I nput current at maximum input voltage Vee= MAX, VI = 5.5 V 1 1 mA
o input 40
IIH High-level input current Vee = MAX, VI = 2.4 V IlA
Any input except 0 40 80

Low-level input current

o input -1.6
IlL Vee = MAX, VI = 0.4 V mA
Any input except 0 -1.6 -3.2
lOS Short-circuit OUtput current § Vce= MAX -35 -85 -35 -85 mA
Vee = MAX, ICondition 1 50 70 40 60 mA
ICC Supply current
See Note 3 ICondition 2 42 62 35 55 mA
NOTE 3: For '147, ICC (condition 1) is measured with input 7 grounded, other inputs and outputs open; ICC (condition 2) is measured with
all inputs and outputs open. For '148, ICC (condition 1) is measured with inputs 7 and EI grounded, other inputs and outputs open;
ICC (condition 2) is measured with all inputs and outputs open.
t For conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions.
tAli typical values are at Vee = 5 V. T A = 25°c.
;iNot more than one output should be shorted at a time.

SN54147, SN74147 switching characteristics, Vee = 5 V, T A = 25°e

FROM TO
PARAMETER~ WAVEFORM TEST CONDITIONS MIN TVP MAX UNIT
(INPUT) (OUTPUT)
tPLH In-phase 9 14

•
Any Any CL=15pF, ns
tpHL output 7 11
RL = 400 n,
tpLH Out-of-phase 13 19
Any Any See Note 4 ns
tPHL output 12 19

SN54148, SN74148 switching characteristics, Vee = 5 V, T A = 25°e

FROM TO
PARAMETER~ WAVEFORM TEST CONDITIONS MIN TVP MAX UNIT
(INPUT) (OUTPUT)
tPLH In-phase 10 15
o thru 7 AO, Al, or A2 ns
tpHL output 9 14
tpLH Out-of-phase 13 19
o thru 7 AO, Al, or A2 ns
tPHL output 12 19
I I
I
I
I I Out-of-phase
I
tpLH ! 6 10 I ns
o thru 7 i EO
tpHL output 14 25
eL = 15pF,
tpLH In-phase 18 30
o thru 7 GS RL=400n, ns
tpHL output 14 25
See Note 4
tpLH In-phase 10 15
EI AO, A1, or A2 ns
tpHL output 10 15
tpLH In-phase 8 12
EI GS ns
tPHL output 10 15
tPLH In-phase 10 15
EI EO ns
tpHL output 17 30
~tPLH == propagation delay tim·e. low·to·high·level output
tPH L == propagation delay time, high·tO·low·level output
NOTE 4: Load circuits and waveforms are shown on page 3-10.

1076

7-154 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54LS147, SN54LS148, SN74LS147, SN74LS148
10-UNE-TO-4-UNE AND 8-UNE-TO-3-UNE PRIORITY ENCODERS

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS' SN74LS'
PARAMETER TEST CONDITIONSt UNIT
MIN TYP:j: MAX MIN TYP:j: MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
VIK Input clamp voltage VCC= MIN, 11- -18 mA -1.5 -1.5 V
VCC = MIN, VIH = 2 V
VOH High-level output voltage 3.4 2.5 3.4 2.7 V
VIL = 0.8 V, 10H =-400!LA
VCC = MIN, 0.25 0.4 0.25 0.4
110L =4 mA
VOL Low-level output voltage VIH =2V, V
VIL = VILmaxllOL =8 mA 0.35 0.5
Input current at 'LS148 inputs 1 thru 7 0.2 0.2
II VCC = MAX, VI_=7V mA
maximum input voltage All other inputs 0.1 0.1
'LS148 inputs 1 thru 7 40 40
IIH High-level input current VCC= MAX, VI = 2.7 V !LA
All other inputs 20 20
'LS148 inputs 1 thru 7 -0.8 -0.8
IlL Low-level input current Vee = MAX VI = Q,4V ml. .~
All other inputs -0.4 -0.4
lOS Short-circuit output current§ Vcr. = MAX -20 -100 -20 -100 mA

ICC Supply current

VCC = MAX, ICondition 1 12 20 12 20 mA
See Note 5 ICondition 2 10 17 10 17 mA

NOTE 5: For 'LS147, ICC (condition 1) is measured with input 7 grounded, other inputs and outputs open; ICC (condition 2) is measured
with all inputs and outputs open. For 'LS148, ICC (condition 1) is measured with inputs 7 and EI grounded, other inputs and
outputs open, ICC (condition 2) is measured with all inputs and outputS open.
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAli tYpical values are at V CC = 5 V, T A = 25°C.
~ Not more than one output should be shorted at a time.

SN54LS147, SN74LS147 switching characteristics, Vee = 5 V, TA = 25°e

FROM TO
PARAMETER'! WAVEFORM TEST CONDITIONS MIN TYP MAX UNIT
!INPUT) (OUTPUT)
tPLH In-phase 12 18
Any Any

II
CL=15pF, ns
tpHL output 17 25
RL=2kn,
tPLH Out-of-phase 24 36
Any Any See Note 4 ns
tPHL output 19 29

SN54LS148, SN74LS148 switching characteristics, Vee = 5 V, TA = 25°e

FROM TO
PARAMETER~ WAVEFORM TEST CONDITIONS MIN TYP MAX UNIT
!INPUT) (OUTPUT)
tPLH In-phase 12 18
Othru 7 AO,A1,orA2 ns
tPHL output 17 25
tPLH Out-of-phase 24 36
Othru 7 AO,A1,orA2 ns
tPHL output 19 29
tPLH Out-of-phase 12 18
Othru 7 EO ns
tpHL output 6 15
CL=15pF,
tPLH In-phase 15 23
o thru 7 GS RL = 2 kn, ns
tPHL output 14 21
See Note 6
tPLH In-phase 12 18
EI AO, A1, or A2 ns
tPHL output 17 25
tPLH In-phase 11 17
EI GS ns
tPHL output 24 36 I

tPLH In-phase 14 21 '

EI I EO ns
tPHL j output 17 25 I
'li tPLH == propagation delay time, low-to-high-Ievel output
tPHL:: propagation delay time, high-to-Iow-Ievel output
NOTE 6: Load circuits and waveforms are shown on page 3-11.

1076 DESIGN GOAL

This page provides tentative information on a
product in the developmental stage. Texas
TEXAS INCORPORATED
INSTRUMENTS 7-155
I nstruments reserves the right to change or dis- POST OFFICE BOX 5012 • CALLAS. TEXAS 75222
continue this product without notice.
 TYPES SN54147, SN54148 (TIM9907)' SN54LS147, SN54LS148,
SN74147, SN74148, SN74LS147, SN74LS148 -----
10-LlNE-TO-4-LlNE AND 8-LI
-----
NE-TO-3-LlNE PRIORITY ENCODERS
TYPICAL APPLICATION DATA

16-LlNE DATA
~ ________________________ ______________________
--JA~ ~

/ ENABLE

o 2 3 4 5 6 7 EI o 2 3 4 5 6 7 EI

SN54148/SN74148, SN54148/SN74148,
SN54LS148/SN74LS148 SN54LS148/SN74LS148

EO GS EO GS

SN5400/SN7400
SN54LSOO/SN74LSOO

• PRIORITY
FLAG

Full 4-bit binary 16-line-to-4-line encoding can be implemented as shown above. The enable input must be low to
enable the function. Decoding with 2·input NAND gates produces true (active-high) data for the 4-line binary outputs.
If active-low data is required, the SN5408/SN7408 or SN54LS08/SN74LS08 AND gate may be used, respectively.

1076

7-156 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54150, SN54151A, SN54152A. SN54LS151, SN54LS152, SN54S151,
. SN74150, SN74151A, SN74LS151, SN74S151
DATA SELECTORS/MULTIPLEXERS
BULLETIN NO. DL-S 7611819, DECEMBER 1972-REVISED OCTOBER 1976

SN54150 _ •. J OR W PACKAGE
SN74150 •• _J OR N PACKAGE
(TOP VIEW)

• '150 Selects One-of-Sixteen Data Sources

• Others Select One-of-Eight Data SourCes
• Performs Parallel-to-Serial Conversion
• Permits Multiplexing from N Lines to
One Line
• Also For Use as Boolean Function
Generator
• Input-Clamping Diodes Simplify System
Design
• Fully Compatible with Most TTL and DTL
Circuits
positive logic: see function table
TYPICAL AVERAGE TYPICAL
TYPE PROPAGATION DELAY TIME POWER SN54151A,SNJ=.ALS151, S~':54S151 ••• J OR 'l'J PACKAGE
DATA INPUT TO W OUTPUT DISSIPATION SN74151A SN74LS151,SN74S151 ••• J OR N PACKAGE
'150 11 ns 200mW (TOP VIEW)
'151A 8 ns 145mW
'152A 8 ns 130mW
'L8151 11 nst 30mW
'L8152 11 nst 28mW
'8151 4.5ns 225mW

t Tentative data

description
STROBE

These monolithic data selectors/multiplexers contain

full on-chip binary decoding to select the desired data
source. The '150 selects one-of-sixteen data sources;
DATA INPUTS OUTPUTS

positive logic: see function table

II
the '151A, '152A, 'LS151, 'LS152, and 'S151 select
one~9f~eight data sources. The '150, '151A,'LS151,
and" 'S151 have a strobe input which must be at a low SN54152A, SN54LS152 __ • W PACKAGE
(Top VIEW)
logic level to enable these devices. A high level at the
strobe forces the W output high, and the Y output (as
applicable) low.

The '151A, 'LS151, and 'S151 feature complemen-

tary Wand Y outputs whereas the '150, '152A, imd
'LS152 have an inverted (W) output only.

The '151A and '152A incorporate address buffers

which have symmetrical propagation delay times
through the complementary paths. Th is reduces the ~2~W
-v---- OUTPUT
possibility of transients occurring at the output(s)
due to changes made at the select inputs, even
when the '151A outputs are enabled (i.e., strobe low). positive logic: see function table

1076

TEXAS INSTRUMENTS 7-157

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54150, SN54151A, SN54152A, SN54LS151, SN54LS152, SN54S151,
SN74150, SN74151A SN74LS151, SN74S151
DATA SELECTORS/MUtTIPLEXERS
REVISED OCTOBER 1976

logic
'150 '151A, 'LS151, 'S151 '152A, 'LS152
FUNCTION TABLE FUNCTION TABLE FUNCTION TABLE
INPUTS INPUTS OUTPUTS SELECT
OUTPUT OUTPUT
SELECT STROBE SELECT STROBE INPUTS
W Y W W
C B A S C B A
D C B A S
X H H
X X X H. L H L L L DO
X X X
L L L L 09 Do -
L L L L L Eo L L H 01
L L L H L IT L L H L 01 51 L H L 52
L L H L L E2 L H L L 02 52 L H H 53
L L H H L E3 L H H L 03 53 H L L 54
H L L L 04 54 -
l H L L L E4 H L H 05
L H L H L E5 H L H L 05 Os H H L 00
L H H L L Es H H L L 06 56 H H H i57
-
H H H L 07 07
L H H H L E7
H L L L L Es ~= ~gh le~L = low
level, X = irrelevant
H L L H L E9 EO, E 1 ... E 15 = the complement of the level of the respective E input
DO, D1 ... D7 = the level of the D respective input
H L H L L El0
-
H L H H L Ell
H H L L L E12 '151A, 'LS151, 'S151
H H L H L E13
DO.!!!.I"_ _ _ _-==rq;;[)---,=~i
H H H L L E14
- 131
H H H H L E15 01

functional block diagrams o,.£L"'------F=='===l~::rl

D3 m
'150
IN"'" "'=""----l=r=i=l=E=;:::fl

.... os.

08(131
not)

" m

" I. 07(121

I El ~I

'1S2A, 'L5152
00 ~I

0,(11)

",Ill

03Q1
£'10 (21.

_m

l ::~:
oe{1!

osn31

08 112'1

e1i1 1t7} D7(111

£15 (161

se~~i;{:~:::: ADDRESS BUFFERS FOR '151A, '152A ADDRESS BUFFERS FOR 'LS151, 'S151, 'LS152

'''''''',--''''-{''''~~
D~

1076

7-158 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54150, SN54151A, SN54152A, SN74150, SN74151A
DATA SELECTORS/MULTIPLEXERS
REVISED OCTOBER 1976

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, VCC (see Note 1) 7V

Input voltage (see Note 2). . . 5.5 V
Operating free-air temperature range: SN54' Circuits -55°C to 125°C
SN74' Circuits O°C to 70°C
Storage temperature range: . . . . . . . . . . . -65°C to 150°C
NOTES: 1. Voltage values a/with respect to network ground terminal.
2. For the '150, input voltages must be zero or positive with respect to network ground terminal.

recommended operating conditions

SN54' SN74'
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, IOH -800 -800 /.LA
Low-level output current, 10L 16 16 rnA
Operating free-air temperature, T A -55 125 0 70 °e
---

electrical characteristics over recommended operating free-air temperature range (un!ess other.'Vise noted)
'150 '151A, '152A
PARAMETER TEST eONDITloNst UNIT
MIN TYP:j: MAX MIN TYP:j: MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
VIK Input clamp voltage Vee = MIN, 11- -8 rnA -1.5 V
Vee = MIN, VIH = 2 V,
VOH High-level output volt~ 2.4 3.4 2.4 3.4 V
VIL ~0.8V, 10H =-SOOJ,LA
Vee = MIN, VIH =2V,
1VOL Low-level output voltage 0.2 0.4 0.2 0.4 V
VIL = 0.8 V, 10L = 16mA
II Input current at maximum input voltage Vee - MAX, VI- 5.5V 1 1 rnA

•
IIH High-level input current Vee - MAX, VI- 2.4 V 40 40 /.LA
IlL Low-level input current Vee = MAX, VI - 0.4 V -1.6 -1.6 rnA
SN54' -20 -55 -20 -55
lOS Short-circuit output current§ Vee= MAX rnA
SN74' -18 -55 -18 -55
'150 40 68
Vee = MAX, 48 rnA
lee Supply current '151A 29
See Note 3
'152A 26 43

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device
type.
tAli typical values at VCC = 5 V, T A = 25°C.
§ Not more than one output of the' 151 A should be shorted at a time.
NOTE 3: ICC is measured with the strobe and data select inputs at 4.5 V, all other inputs and outputs open.

1076

TEXAS INSTRUMENTS 7-159

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54150, SN54151A, SN54152A, SN74150, SN74151A
DATA SELECTORS/MULTIPLEXERS

switching characteristics, Vee = 5 V, TA =25°e

FROM TO TEST '150 . '151A, '152A
PARAMETER~ UNIT
(INPUT! (OUTPUT! CONDITIONS MIN TYP MAX MIN TYP MAX
tPLH A, B,orC 25 38
Y ns
tpHL (4 levels! 25 38
tpLH A, B,C, or D 23 35 17 26
W ns
tpHL (3 levels! 22 33 19 30
tPLH 21 33
Strobe Y CL = 15pF, ns
tpHL 22 33
RL=400n,
tpLH 15.5 24 14 21
Strobe W See Note 4 ns
tpHL 21 30 15 23
tpLH 13 20
DO thru D7 Y ns
tpHL 18 27
tpLH EO thru E 15, or 13 20 8 14
W ns
tpHL DO thru D7 8.5 14 8 14

~tpLH '" propagation delay time, low·to·high·level output

tpH L '" propagation delay time, high·to·low·level output
NOTE 4: Load circuit and voltage waveforms are shown on page 3-10.

schematics of inputs and outputs

EQUIVALENT OF EACH INPUT EQUIVALENT OF EACH INPUT
OF '150 OF '151A, '152A

Vee---~......- - Vee - - - - 4......- -

•
INPUT INPUT

~--------~I ~I______~
TYPICAL OF ALL OUTPUTS
OF '150, '151A, '152A

1076

7·160 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • CAL.LAS. TEXAS 75222
 TYPES SN54LS151, SN54LS152, SN74LS151
DATA SELECTORS/MULTIPLEXERS

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, Vcc (see Note 1) . . . . . . . . 7V

Input voltage . . . . . . . . . . . . . . . . 7V
Operating free-air temperature range: SN54LS' Circuits -55°C to 125°C
SN74LS' Circuits aOc to 7aoC
Storage temperature range -65°C to 15aoC
NOTE 1: Vo.ltage values are with respect to network ground terminal.

recommended operating conditions

I SN54LS' SN74LS'
UNIT
IMIN NOM MAX MIN NOM MAX
Supply voltage, Vee ! 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H I -400 -400 /-I A
Low-level output current, 10L I 4 8 rnA
~ .'
I uperatlng nee-air temperature, -A
I 1-::>0-- ---
ILO I -
U --
IU I l.;

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS' SN74LS'
PARAMETER TEST CONDITIONSt UNIT
MI!'I TYP:j: MAX MIN TYP:j: MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
VIK Input clamp voltage Vee= MIN, 11=-18mA -1.5 -1.5 V
Vee= MIN, VIH = 2V,
VOH High-Ieve: output voltage 2.5 3.4 2.7 3.4 V
VIL = VIL max, 10H = -400 /-IA
Vee= MIN, VIH = 2V, lIOL=4mA 0.25 004 0.25 004
VOL Low-level output voltage V
VIL = VIL max IIOL=8mA 0.35 0.5

•
Input current at
II Vee = MAX, VJ =7 V 0.1 0.1 rnA
maximum input voltage
IIH High-level input current Vee= MAX, VI = 2.7 V 20 20 /-IA
IlL Low-level input current Vee- MAX, VI-OAV -0.4 -004 rnA
lOS Short-circuit output currentll Vee= MAX -20 -100 -20 -100 rnA
Vee = MAX, Outputs open, I 'LS151 6.0 10 6.0 10
lee Supply current rnA
All inputs at 4.5 V I 'LS152 5.6 9

t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device
type.
0
:j:AII typical values are at V CC = 5 V, T A = 25 C.
§ Not more than one output should be shorted at a time and duration of short-circuit should not exceed one second.

1076

TEXAS INCORPORATED
INSTRUMENTS 7-161
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54LS151, SN54LS152, SN74LS151
DATA SELECTORS/MULTIPLEXERS

switching characteristics, Vee =5 V, TA = 25°e

PARAMETER~ I FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
SN54LS·. SN74LS'
MIN TVP MAX
UNIT

tPLH A. B. orC 27 43
y ns
tPHL (4 levels) 18 30
tpLH A. B. orC 14 23
W ns
tPHL (3 levels) 20 32
tPLH y 26 42
Strobe CL = 15pF. ns
tPHL 20 32
RL = 2 kn.
tPLH 15 24
Strobe W See Note 5 ns
tPHL 18 30
tpLH 20 32
Any D Y ns
tPHL 16 26
tPLH 13 21
Any D W ns
tPHL 12 20

~ tPLH := Propagation delay time, low-to-high-Ievel output

tpHL:= Propagation delay time, high-to-Iow-Ievel output
NOTE 5: See load circuits and waveforms on page 3-11.

schematics of inputs and outputs

EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS

OF ·LS151. 'LS152 OF 'LS151. 'LS152
---'--VCC

n NOM
VCC ------41.....---- --- 120

•
Req

tNPUT-.~ """I---4I~_'-- -
Ll"1W
..

OUTPUT

n'7
Data select and strobe: Req = 20 kn NOM
Data inputs: Req = 17 kn NOM

1076

1-162 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54S151, SN74S151
DATA SELECTORS/MULTIPLEXERS

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, VCC (see Note 1) . . . . . . . . . 7V

Input voltage . . . . . . ' ........ . 5.5V
Operating free-air temperature range: SN54S151 Circuits -55°C to 125°C
SN74S151 Circuits aOc to 7aoC
Storage temperature range -65°C to 15aoC
NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54S151 SN74S151
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, IOH -1 -1 rnA
low-level output current, 10l 20 20 mA
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (uniess otherwise noted;
PARAMETER TEST eONDITloNst MIN TYP+ MAX UNIT
VIH High-level input voltage 2 V
Vil low-level input voltage 0.8 V
VIK Input clamp voltage Vee = MIN, II =-18mA -1.2 V

High-level output voltage

Vee= MIN, VIH - 2 V, I SN54S' 2.5 3.4
V
VOH
Vil = 0.8 V, IOH=-1 mA I SN74S' 2.7 3.4
Vee = MIN, VIH - 2V,
VOL low-level. output voltage 0.5 V I
VIL = 0.8 V, iOl = 20 mA I I I
II Input current at maximum input voltage Vee = MAX, VI = 5.5 V 11 mA

•
IIH High-level input current Vee = MAX, VI-2.7V 50 J.LA
III low-level input current Vee- MAX, VI = 0.5 V -2 mA
lOS Short-circuit output current!i Vee - MAX -40 -100 mA
Vee= MAX, All inputs at 4.5 V,
ICC Supply current 45 70 mA
All outputs open

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device
type.
+AII typical values are at V CC = 5 V, T A = 25°C.
§Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.

1076

TEXAS INCORPORATED
INSTRUMENTS 7-163
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN64S161, SN74S161
DATA SELECTORS/MULTIPLEXERS

switching characteristics, Vee = 5 V, TA =25°e

PARAMETER~
FROM
(INPUT)
I TO
(OUTPUT)
TEST CONDITIONS
SN54S151, SN74S151
MIN TYP MAX
UNIT

tpLH A, B,orC 12 18
Y ns
tPHL (4 levels) 12 18
tpLH A, B,orC 10 15
W ns
tpHL (3 levels) 9 13.5
tpLH 8 12
Any 0 Y CL = 15pF, ns
tpHL 8 12
tpLH
RL = 280 f!" 4.5 7
Any D W See Note 4 ns
tpHL 4.5 7
tPLH 11 16.5
Strobe Y I'js
tpHL 12 18
tpLH 9 13
Strobe W ns
tPHL 8.5 12

~ tp LH == Propagation delay time, low-to·high·level output

tpH L == Propagation delay time, high·to·low·level output
NOTE 4: See load circuits and waveforms on page 3-10.

schematics of inputs and outputs

EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS

OF 'S151 OF'S151

- - - - -.....- - vee
v e e - - -....- - - 50 n NOM

• INPUT
OUTPUT

1272

7-164 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TTL TYPES SN54153, SN54L153, SN54LS153, SN54S153,
SN74153, SN74L153, SN74LS153, SN74S153
MSI DUAL 4-UNE-TO-1-UNE DATA SELECTORS/MULTIPLEXERS
BULLETIN NO. DL-S 7611 DECEMBER 1972' -:- REVISE,? ER 1976

SN54153, SN64LS153, SN54S153 ••• J OR W PACKAGE

SN64L 153 ••• J PACKAGE
SN74153, SN74L153,SN74LS153,SN74S153 ••• J OR N PACKAGE
, (TOP VIEW)

• Permits MultiplexiJ'lg from N lines to 1 line

• Performs Parallel-to-Serial Conversion
• Strobe (Enable) Line Provided for Cascading
(N lines to n lines)
• High-Fan-Out, Low-Impedance, Totem-Pole
Outputs
• Fully Compatible with most TTL and DTL
Circuits
positive logic: see function table

TYPICAL AVERAGE
TYPICAL
PROPAGATION DELAY TIMES
TYPE POWER
FROM FROM FROM
DISSIPATION
DATA STROBE SELECT
'153 14 ns 17 ns 22 ns 180mW FUNCTION TABLE

'L153 27 ns 34 ns 44 ns 90mW SELECT

DATA INPUTS STROBE OUTPUT
'LS153 14 ns 19 ns 22 ns 31 mW INPUTS
'S153 6 ns 9.5 ns 12 ns 225mW B A CO C1 C2 C3 G Y
X X X X X X H L
L L 1:- X X X L L
I L L H X X X L H,

•
'-
L H X L X X L L
description L H X H X X L H
,-
'I-i L X X L X L L

Each of these monolithic, data selectors/multiplexers H L X X H X L H

contains inverters and drivers to supply fully H H X X X L L L
complementary, on-chip, binary decoding data H H X X X H L H
selection to the AND-OR-invert gates. Separate strobe Select inputs A and B are common to both sections,
H = high level. L = low level. X = irrelevant
inputs are provided for each of the two four-line
sections.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . 7V
Input voltage: '153, 'L153, 'S153 . . . . . . . . . . . . . . . . . . 5.5 V
'LS153 . . . . . . . . . . . . . . . . . . . . . . . 7V
O1>erating free-air temperature range: SN54', SN54L', SN54LS', SN54S' Circuits -55°C to 125°C
SN74', SN74L', SN74LS', SN74S' Circuits aOc to 7aoC
Storage temperature range . . . . . . . . . . . . -65°C to 15aoC

NOTE 1: Voltage values are with respect to network ground terminal.

1076

TEXAS INSTRUMENTS 7-165

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54153, SN54L153, SN54LS153, SN54S153,
SN74153, SN74L15-3, SN74LS153, SN74S153
DU"AL 4-LlNE-TO-1-LlNE DATA SELECTORS/MULTIPLEXERS
REVISED OCTOBER 1976

functional block diagram

STROBE lG (1)
(ENABLE)
ICO --:-c-------++-+-1

(5)
lCl ------t-t-t--H..-.J
DATA 1
(4)
lC2 -----+-t-++-t-L..-/

lC3 (3)

2C0 (10)

2Cl (11)

OATA2
2C2 (12)

2C3 (13)

STROBE 2G
(ENABLE) (15)

schematics of inputs and outputs

EQUIVALENT OF INPUTS OF '153, 'L 153 EQUIVALENT OF INPUTS OF 'LS153 EQUIVALENT OF INPUTS OF 'S153

•
V C CReq
3-- VCC?1--
20 kn NOM VCCy r)
2.8 - NOM'
kn -

INPUT -- INPUT --
INPUT --

m
~ ~

'153: Req = 4 kn NOM

'L 153: Req = 8 kn NOM

TYPICAL OF OUTPUTS OF '153, 'L 153 TYPICAL OF OUTPUTS OF 'LS153, 'S153

------VCC
VCC

OUTPUT
OUTPUT

'153: R = 130 n NOM 'LS153: R = 120 n NOM

'L 153: R = 260 n NOM '5153: R = 50 n NOM

1076

7-166 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54153, SN74153
DUAL 4-UNE-TO-1-UNE DATA SELECTORS/MULTIPLEXERS

recommended operating conditions

SN54153 SN74153
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -800 -800 p.A
Low-!evel output current, 10L 16 16 rnA
Operating free-air temperature, T A -55 125 0 70 °c

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54153 SN74153
PARAMETER TEST CONDITIONSt UNiT
MIN TYP:j: MAX MIN TYp:j: MAX
VIH High-level input voltage 2 2 V
Vi L Lo;,v-Ievel input voltage 0.8 0.8 V
VIK Input clamp voltage Vee- MIN, 11- -12mA -1.5 -1.5 V

High-"!eve! ct!tput voltage

Vee- MIN, VIH -2V, ') .. ., A ') .. ., A

I VOH VIL = 0.8 V, 10H = -800p.A

v

V,..,..-MIN v- IH--?V
VOL Low-Ieveloutput'voltage
.,," - ..... _, - 0.2 0.4 0.2 0.4 V
VIL = 0_8 V, 10L = 16mA
II Input current at maximum input voltage Vee = MAX, VI=5.5V 1 1 rnA
IIH High-level input current Vee - MAX, VI = 2.4 V 40 40 p.A
I'lL Low-level input current Vee - MAX, VI- 0.4 V -1.6 -1.6 rnA
lOS Short-circuit output currentli Vee = MAX -20 -55 -18 -57 rnA
leel Supply current, output low Vee - MAX, See Note 2 36 52 36 60 rnA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at V CC = 5 V. T A = 25° C.
§Not more than one output should be shorted at a time.
NOTE 2: ICCl is measured with the outputs open and all inputs grounded.

switching characteristics, Vee = 5 V, TA = 25°e

PARAMETERlI

tPLH
tpHL
tpLH
FROM
(INPUT)
Data
Data
Select
TO
(OUTPUT)
Y
Y
Y
TEST CONDITIONS

eL = 30pF, RL=400n,
MIN TYP

12
15
22
MAX UNIT

18
23
34
ns
ns
ns
•
tpHL Select Y See Note 3 22 34 ns
tpLH Strobe Y 19 30 ns
tpHL Strobe Y 15 23 ns

11 tp lH == propagation delay time, low-to-high-Ievel output

tpHl == propagation delay time, high-to-Iow-Ievel output
NOTE 3: load circuit and voltage waveforms are shown on page 3-10.

1076

TEXAS INSTRUMENTS 7-167

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. T.FXAS 75222
 TYPES SN54L153. SN14L153
DUAL 4-UNE-TO-1-UNE DATA SELECTORS/MULTIPLEXERS

recommended operating conditions

SN54L153 SN74l153
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, VCC 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -400 -400 /.IA
low-level output current, 10l 8 8 rnA
Operating free-air temperature, T A -55 125 0 70 °c

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54'L153 SN74l153
PARAMETER TEST CONDITIONSt UNIT
MIN TYP+ MAX MIN TYP+ MAX
VIH High-level input voltage 2 2 V
Vil low-level input voltage 0.8 0.8 V
VIK Input clamp voltage Vee= MIN, 11=-12mA -1.5 -1.5 V
Vec- MIN, VIH - 2V,
VOH High-level output voltage 2.4 3.4 2.4 3.4 V
Vil = 0.8 V, 10H = -4oo/.lA
VCC= MIN, VIH = 2V,
VOL low-level output voltage 0.2 0.4 0.2 0.4 V
Vil = 0.8 V, 10l =8 rnA
II Input current at maximum input voltage Vec= MAX, VI" 5.5V 1 1 rnA
IIH High-level input current VCC" MAX, VI = 2.4 V 20 20 /.IA
III Low-level input current Vec = MAX, VI = 0.4 V -0.8 -0.8 rnA
lOS Short-circuit output currentS Vee - MAX -10 -28 -9 -30 rnA
'CCl Supply current, output low Vec=MAX, See Note 2 18 26 18 30 rnA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

+AII typical values are at VCC = 5 V, T A = 25°C.

§ Not more than one output should be shorted at a time.

•
NOTE 2: ICCL is measured with the outputs open and all inputs grounded.

switching characteristics, Vee = 5 V, TA = 25°e

PARAMETER~
FROM
iNPUT
TO
OUTPUT
TEST CONDITIONS TVP MAX IUNIT I
tPlH Data Y 24 36 n5
tpHL Data Y 30 46 ns
tPlH Select V Cl = 30 pF, Rl =4000, 44 68 n5
tpHl Select Y See Note 3 44 68 n5
tpLH Strobe Y 38 60 n5
tpHL Strobe y 30 • 46 n5

~tpLH == propagation delay time, low·to-high-Ievel output

tpHL == propagation delay time, high-to-Iow-Ievel output
NOTE 3: Load circuit and voltage waveforms are shown on page 3-10.

1076

7-168 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54LS153, SN74LS153
DUAL 4-UNE-TO-1-UNE DATA SELECTORS/MULTIPLEXERS
REVISED OCTOBER 1976

recommended operating conditions

SN54LS153 SN74LS153
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -400 -400 J.lA
Low-level output current, 10L 4 8 mA
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS153 SN74LS153
PARAMETER TEST CONDITIONSt UNIT
MIN TYP; MAX MIN TYP; MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
VIK Input clamp voltage Vee = MIN, 11=-18mA -1.5 -1.5 V
Vee = MiN, VIH = 2V,
VOH High-level output voltage 2.5 3.4 2.7 3.4 V
VIL = VIL max, 10H = -400 J.lA
"-,_. 1 ___ . 1 _ •• _1 _ ...... _ ........ _1 .... ___ Vee= MIN, VIH = 2V, IIOL -4 mA 0.25 0.4 0.25 0.4
VOL L..UVV'"ICVCI UULIJUL VU1Ld!::tt:: v
VIL = VIL max IIOL =8mA 0.35 0.5
I nput current at
II Vee= MAX, VI =7V 0.1 0.1 mA
maximum input voltage
IIH High-level input current Vee = MAX, VI=2.7V 20 20 J.lA
IlL Low-level input current Vee- MAX, VI = 0.4 V -0.4 -0,4 mA
lOS Short-circuit output current § Vee-MAX -20. -100 -20 -100 mA
leeL Supply current, output low Vee-MAX, See Note 2 6.2 10 6.2 10 mA

tFor conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions.

fAll typical Vah.ie5 are at Vee;:;; 5 V, T A;;;:;; 25°C.

§ Not more than one output should be shorted at a time and duration of short-circuit should not exceed one second.

•
NOTE 2: ICCL is measured with the outputs open and all inputs grounded.

switching characteristics, Vee =5 V, TA =25°e

FROM TO
PARAMETER~ TEST CONDITIONS MIN TYP MAX UNIT
(INPUT) (OUTPUT)
tpLH Data Y 10 15 ns
tpHL Data Y 17 26 ns
eL=15pF,
tpLH Select Y 19 29 ns
RL = 2 kn,
tpHL Select Y 25 38 ns
See Note 4
tPLH Strobe Y 16 24 ns
tPHL Strobe Y 21 32 ns

~ tpLH== propagation delay time, low-to·high-Ievel output

tpHL == propagation delay time, high·to-Iow-Ievel output
NOTE 4: Load circuits and voltage waveforms are shown on page 3-11.

1076

TEXAS INCORPORATED
INSTRUMENTS 1-169
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54S153, SN74S1_53
DUAL 4-UNE-TO-1-UNE DATA SELECTORS/MULTIPLEXERS

recommended operating conditions

SN54S153 SN74S153
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -1 -1 mA
Low-level output current, 10L 20 20 mA
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONSt MIN TYP+ MAX UNIT

VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
VIK Input clamp voltage Vee= MIN, II =-18mA -1.2 V

High-level output voltage

Vee=MIN, VIH=2V, ISeries 545 2.5 3.4
V
VOH
VIL = 0.8 V, I
10H = -1 mA Series 745 2.7 3.4
Vee = MIN, VIH = 2 V,
VOL Low-level output voltage 0.5 V
VIL = 0.8 V, 10L = 20mA
II I nput current at maximum input voltage Vee= MAX, VI = 5.5 V 1 mA
IIH High-level input current Vee = MAX, VI = 2.7 V 50 /loA
IlL Low-level input current Vee = MAX, VI = 0.5V -2 mA
lOS Short-circuit output current§ Vee = MAX -40 -100 mA
leeL Supply current, low-level output Vee = MAX, See Note 2 45 70 mA

T For conditions shown ~s MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at VCC =5 V, T A = 25°C.
§Not more than one output should be shorted at a time and duration of short-circuit should not exceed one second.
NOTE 2: ICCL is measured with the outputs open and all inputs grounded.

II
S'Nitching characteristics, Vee =5 V, TA =25°C
FROM TO
PARAMETER. TEST CONDITIONS MIN TYP MAX UNIT
(INPUT) (OUTPUT)
tPLH Data Y 6 9 ns
tPHL Data Y 6 9 ns
tPLH Select y eL=15pF, RL = 280 0.., 11.5 18 ns
tpHL Select y See Note 3 12 18 ns
tpLH Strobe y 10 15 ns
tpHL Strobe y 9 13.5 ns

~ tpLH ;;; propagation delay time, low-to-high-Ievel output

tpHL "" propagation delay time, high-to-Iow-Ievel output
NOTE 3: Load circuit and voltage waveforms are shown on page 3-10.

1076

TEXAS INSTRUMENTS
7-170 INCORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TTL TYPES SN54154, SN54L154, SN74154, SN74L154
MSI 4-UN E-TO-16-UN E DECO DERS/ DEMU LTIPLEXERS
BULLETIN NO. DL-S 7211805, DECEMBER 1972

SN54154 ••• J OR W PACKAGE

SN54L154 .•• J PACKAGE
• '154 is Ideal for High-Performance SN74154, SN74L154 ••• J OR N PACKAGE
(TOP VIEW)
Memory Decoding
INPUTS OUTPUTS
• 'L 154 is Designed for Power-Critical
Applications
• Decodes 4 Binary-Coded Inputs into One of
16 Mutually Exclusive Outputs
• Performs the Demultiplexing Function by

•
Distributing Data From One Input Line to
Any One of 16 Outputs
input Ciamping Diodes Simpiify System ILl
': 3 4 5 6 7 8 9 ::,
III Y I I I I I I 1 1 1
I I I I I I I I I I JI
II
i
I
Design I I H2H3H4HsH6H7H8H9HJOHlIHI2~
\L.....-! L-...J '--I '---..J L......J ~ L-....J '---..J L..J L.......J L....J/G~Q
• High Fan-Out, Low-Impedance, Totem-Pole OUTPUTS
Outputs
positive logic: see function table
• Fully Compatible with Most TTL, DTL, and
MSI Circuits

TYPiCAL AVERAGE
TYPICAL
TYPE PROPAGATION DELAY
POWER DISSIPATION

•
3 LEVELS OF LOGIC STROBE
'154 23 ns 19 ns 170mW
'L154 46 ns 38 ns 85mW

description

Each of these monolithic, 4-line-to-16-line decoders utilizes TTL circuitry to decode four binary-coded inputs into one
of sixteen mutually exclusive outputs when both the strobe inputs, Gland G2, are low. The demultiplexing function is
performed by using the 4 input lines to address the output line, passing data from one of the strobe inputs with the
other strobe input low. When either strobe input is high, all outputs are high. These demultiplexers are ideally suited for
implementing high-performance memory decoders. For ultra-high-speed systems, SN54S138/SN74S138 and SN54S139/
SN74S139 are recommended.

These circuits are fully compatible for use with most other TTL and DTL circuits. All inputs are buffered and input
clamping diodes are provided to minimize transmission-line effects and thereby simplify system design.

Series 54 and 54L devices are characterized for operation over the full military temperature range of -55°e to 125°e;
o
Series 74 and 74L devices are characterized for operation from oOe to 70 e.

1076

TEXAS INSTRUMENTS 7-171

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54154, SN54L154, SN74154, SN74L154
4-LlNE-TO-16-UNE DECODERS/DEMULTIPLEXERS

logic
FUNCTION TABLE

INPUTS OUTPUTS
G1 G2 0 C B A 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
L L L L L L L H H H H H H H H H H H H H H H
L L L L L H H L H H H H H H H H H H H H H H
L L L L H L H H L H H H H H H H H H H H H H
L L L L H H H H H L H H H H H H H H H H H H
L L L H L L H H H H L H H H H H H H H H H H
L L L H L H H H H H H L H H H H H H H H H H
L L L H H L H H H H H H L H H H H H H H H H
L L L H H H H H H H H H H L H H H H H H H H
L L H L L L H H H H H H H H L H H H H H H H
L L H L L H H H H H H H H H H L H H H H H H
L L H L H L H H H H H H H H H H L H H H H H
L L H L H H H H H H H H H H H H H L H H H H
L L H H L L H H H H H H H H H H H H L H H H
L L H H L H H H H H H H H H H H H H H L H H
L L H H H L H H H H H H H H H H H H H H L H
L L H H H H H H H H H H H H H H H H H H H ·L
L H X X X X H H H H H H H H H H H H H H H H
H L X X X X H H H H H H H H H H H H H H H H
H H X X X X H H H H H H H H H H H H H H H H
H ~ high level, L ~ low level, X ~ irrelevant

functional block diagram and schematics of inputs and outputs EQUIVALENT OF EACH INPUT

vcc:x--
• 'NeuT tj--
INPUTS '154: R ~ 4 k.n NOM
'L154: R~8k.nNOM

TYPICAL OF ALL OUTPUTS

Vee

OUTPUT

'154: R ~ 130.n NOM

'L154: R ~ 260.n NOM

1272

7·172 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54154. SN74154
4-UNE-TO-16-UNE DECODERS/ DEMULTIPLEXERS

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, Vcc (see Note 1) . . . . . . . . 7V

I nput voltage. . . . . . .- . . . . . . . . . . 5.5 V
Operating free-air temperature range: SN54154 Circuits -55°C to 125°C
SN74154 Circuits O°C to 70°C
Storage temperature range -65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54154 SN74154
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High·level output current, 10H -800 -800 J.LA
Low-level output current, IOL 16 16 rnA
Operating free-air temperature, T A -55 125 0 70 °c

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54154 SN74154
PAnAMETER TEST CONDiTiONS' UNIT
MIN TYP MAX MIN TYpt MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
VIK Input clamp voltage Vee= MIN, II = -12mA -1.5 -1.5 V
Vec - MIN, VIH - 2V,
VOH High-level output voltage 2.4 3.4 2.4 3.4 V
VIL = 0.8 V, 10H = -800J.LA
Vee = MIN, VIH = 2 V,
VOL Low-level output voltage 0.2 0.4 0.2 0.4 V
VIL = 0.8 V, IOL=16mA
II Input current at maximum input voltage I Vee = MAX, v! = 5.5 V I 1 I 11 mA
IIH High-level input current Vce = MAX, VI = 2.4 V 40 40 J.LA
I

•
IlL Low-level input current Vee = MAX, Vi = 0.4 V -1.6 -1.6 mA
lOS Short-circuit output current!i Vee = MAX -20 -55 -18 -57 mA
Ice Supply current Vec = MAX, See Note 2 34 49 34 56 mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
tAli typical values are at V CC = 5 V. T A = 25° C.
§Not more than one output should be shorted at a time.
NOTE 2: ICC is measured with all inputs grounded and all outputs open.

switching characteristics, Vee = 5 V, TA = 25°e

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Propagation delay time, low-to-high-Ievel output,
tpLH 24 36 ns
from A, B, e, or D inputs through 3 levels of logic
Propagation delay time, high-to-Iow-Ievel output,
tpHL 22 33 ns
from A, B, e, or D inputs through 3 levels of logic eL=15pF, RL = 400 .11,
Propagation delay time. low-to-high-Ievel output, See Note 3
tpLH 20 30 ns
from either strobe input
Propagation delay time, high-to-Iow·level output,
tpHL 18 27 ns
from either strobe input

NOTE 3: Load circuit and voltage waveforms are shown on page 3-10.

1076

TEXAS INCORPORATED
INSTRUMENTS 7-173
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54L154, SN74J154
4-UNE-TO-16-UNE DECODERS/ DEMULTIPLEXERS

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, VCC (see Note 1) ........ . 7V

Input voltage. . . . . . . . . . . . . . . . . . 5.5V
Operating free-air temperature range: SN54L 154 Circuits -55°C to 125°C
SN74L 154 Circuits O°C to 70°C
Storage temperature range -65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54L 154 SN74L154
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -400 -400 j.LA
Low-level output current, IOL 8 8 rnA
Operating free-air temperature, T A -55 125 0 70 °e

electrical c.haracteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONSt MIN TYP:j: MAX UNIT
VIH High·level input voltage 2 V
VIL Low-level input voltage 0.8 V
VIK Input clamp voltage Vee = MIN, II = -12mA -1.5 V
Vee- MIN, VIH-2V,
VOH High-level output voltage 2.4 3.4 V
VIL = 0.8 V, 10H = -4oo/LA
Vee - MIN, VIH-2V,
VOL Low·level output voltage 0.2 0.4 V
VIL = 0.8 V, 10L = 8mA
II Input current at maximum input voltage Vee - MAX, VI - 5.5 V 1 rnA
IIH High·level input current Vec = MAX, VI = 2.4 V 20 /LA

•
IlL Low·level input current Vee ';"MAX, VI = 0.4 V -0.8 rnA
lOS Short·circuit output current ~ Vec= MAX -9 -29 rnA
Vce = MAX,I SN54L 154 17 25
ICC Supply current mA
See Note 2 I SN74L 154 17 28

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
:j: All typical values are at V CC = 5 V, T A = 25" C.
§ Not more than one output should be shorted at a time.
NOTE 2: ICC is measured with all inputs grounded and all outputs open.

switching characteristics, Vee = 5 V, TA = 25°e

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Propagation delay time, low-to-high-Ievel output,
tpLH 48 72 ns
from A, B, C, or D inputs through 3 levels of logic
Propagation delay time, high·to-Iow-Ievel output,
tPHL 44 66 ns
from A, B. e, or D inputs through 3 levels of logic CL=15pF, RL = 800 n,
Propagation delay time, low·to-high·level output, See Note 3
tPLH 40 60 ns
from either strobe input
Propagation delay time, high-to-Iow-Ievel output,
tpHL 36 54 ns
from either strobe input

NOTE 3: Load circuit and voltage waveforms are shown on page 3-10.

1076

7-174 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • OALLAS. TEXAS 75222
 TTL TYPES SN54155, SN54156, SN54LS155, SN54LS156,
SN74155, SN74156, SN74LS155, SN74LS156
MSI DUAL 2-UNE-T0-4-UNE DECODERS/DEMULTIPLEXERS
BULLETIN NO. DL-S 7611850, MARCH 1974-REVISED OCTOBER 1976

• Applications: SN54155, SN54156, SN54LS155, SN54LS156 ••• J OR W PACKAGE

Dual 2-to-4-Line Decoder SN74155, SN74156, SN74LS155, SN74LS156 •.• J OR N PACKAGE
DuaI1-to-4-Line Demultiplexer (TOP VIEW)
3-to-S-Line Decoder
1-to-S-Line Demultiplexer
• Individual Strobes Simplify Cascading for
Decoding or Demultiplexing Larger Words
• Input Clamping Diodes Simplify System
Design
• Choice of Outputs:
Totem Pole ('155, 'LS155)
Open-Collector ('156, 'LS156)
TYPICAL AVERAGE TYPICAL
TYPES PROPAGATION DELAY POWER
3 GATE LEVELS DISSIFATION
'155, '156 21 ns 125mW
'LS155 18 ns 31 mW positive logic: see function table
'LS156 32 ns 31 mVtJ

descri ption
These monolithic transistor-transistor-Iogic (TTL) circuits feature dual 1-line·to-4·line demultiplexers with individual
strobes and common binary-address inputs in a single 16-pin package. When both,sections are enabled by the strobes,
the common binary-address inputs sequentially select and route associated input data to the appropriate output of each
section. The individual strobes permit activating or inhibiting each of the 4-bit sections as desired. Data applied to input
1C is inverted at its outputs and data applied at 2C is not inverted through its outputs. The inverter following the 1C
data input permits use as a 3-to-8-line decoder or 1-to-8-line demultiplexer without external gating. Input clamping
diodes are provided on all of these circuits to minimize transmission-line effects and simplify system design.
Series 54 and 54LS are characterized for operation over the full military temperature range of -55°C to 125°C; Series
74 and 74LS are characterized for operation from O°C to 70°C.
schematics of inputs and outputs

•
'155, '156 '155 '156
EaUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS TYPICAL OF ALL OUTPUTS
VCC

Vcca--
INPUT
4 kn NOM

--
OUTPUT

'LS155, 'LS156 'LS155 'LS156

EaUIVALENT OF EACH INPUT

V C C - -.......- -
TYPICAL OF ALL OUTPUTS
Vcc TYPICAL OF ALL OUTPUTS

20 kn NOM
_ _ ~OUTeUT
INPUT --e.-,lollf--+-_
l....-.......--OUTPUT

1076

TEXAS INSTRUMENTS 7-175

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54155, SN54156, SN54LS155, SN54LS156,
SN74155, SN74156, SN74LS155, SN74LS156
DUAL 2-UNE-TO-4-UNE DECODERS/DEMULTIPLEXERS

functional block diagram and logic

FUNCTION TABLES
2-LlNE-T0-4-LlNE DECODER.
OR l-LiNE-TO-4-LINE DEMULTIPLEXER
INPUTS OUTPUTS
SELECT STROBE DATA
lYO lYl 1Y2 lY3
B A lG lC
X X H X H H H H
L L L H L H H H
STROBE
lG - - - - - - ,
L t-i L H H L H H
H L L H H H L H
H H L H H H H L
DATA
lC X X X L H H H H

INPUTS OUTPUTS
SELECT STROBE DATA
SELECT 2YO 2Yl 2Y2 2Y3
B B A 2G 2C
X X H X H H H H
L L L L L H H H
L H L L H L H H
H L L L H H L H
H H L L H H H L

SELECT X X X H H H H H
A

FUNCTION TABLE
3-LlNE-T0-8-LINE DECODER
OR l-LiNE-TO-8-LINE DEMULTIPLEXER

INPUTS OUTPUTS
STROBE
SELECT (01 (1\ (21 (31 (41 (51 (61 (71
OR DATA
ct B A G+ 2YO 2Yl 2Y2 2Y3 1YO lYl 1Y2 lY3

I
X X X H H H H H H H H H
L L L L L H H H H H H H
L L H L H L H H H H H H
L H L L H H L H H H H H
L H H L H H H L H H H H
H H H H .. H H ,
H H H H H L H H
H H H H H H L H
H H H H H H H

tC = inputs 1 C and 2C connected together

+G = inputs 1 G and 2G connected together
H = high level, L = low level, X = irrelevant

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, VCC (see Note 1) 7V

Input voltage: '155, '156 5_5V
'LS155, 'LS156 7V
Off-state output voltage: '155 5.5V
'LS155 7V
Operating free-air temperature range: SN54', SN54LS' Circuits -55°C to 125°C
SN74', SN74LS' Circuits aOe to 7aoe
Storage temperature range -65°C to 15aoe
NOTE 1: Voltage values are with respect to network ground terminal.

374

1-176 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54155, SN74155
DUAL 2-LlNE-TO-4-LlNE DECODERS/DEMULTIPLEXERS

recommended operating conditions

SN54155 SN74155
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -800 -800 p.A
Low-level output current, 10L 16 16 mA
Operating free-air temperature, T A -55 125 0 70 °c

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54155
PARAMETER· TEST CONDITIONSt SN74155 UNIT
MIN TYP+ MAX
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
VIK Input clamp voltage VCc~ MIN, II ~ -12 mA -1.5 V
VCC~ MIN, VIH ~ 2 V,
Vnl-l High-level output voltage 2.4 3.4 V
VIL ~ 0.8 V, 10H ~ -800 p.A
V CC ~ MIN V IH ~ 2V
VOL Low-ievei output voitage 0.2 0.4 V
VIL ~ 0.8 V, 10L ~ 16mA
II Input current at maximum input voltage VCc~ MAX, VI ~ 5.5 V 1 mA
IIH High-level input current VCC ~ MAX, VI ~ 2.4 V 40 p.A
IlL Low-level input current VCc~ MAX, VI ~ 0.4 V -1.6 mA
SN54155 -20 -55
lOS Short-circuit output current§ VCC ~ MAX mA
SN74155 -18 -57
VCC ~ MAX, SN54155 25 35
ICC Supply current mA
See Note 2 SN74155 25 40

t For conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values ·are at V CC ~ 5 V, T A ~ 25°C.
§ Not more than one output should be shorted at ~ time.

•
NOTE 2: ICC is measured with outputs open, A, B, and 1 C inputs at 4.5 V, and 2C, 1 G, and 2G inputs grounded.

switching characteristics, Vee = 5 V, TA = 25°e

FROM TO LEVELS
PARAMETERll TEST CONDITIONS MIN TYP MAX UNIT
(INPUT) (OUTPUT) OF LOGIC
A, B, 2C,
tPLH Y 2 13 20 ns
1G,or2G
A, B, 2C,
tpHL y 2 CL~15pF, 18 27 ns
1G,or2G
RL~400n,
tPLH AorB y 3 21 32 ns
See Note 3
tpHL AorB Y 3 21 32 ns
tpLH 1C y 3 16 24 ns
tpHL 1C y 3 20 30 ns

ll tPLH == propagation delay time, low-to-high·level output

tpH L == propagation delay time, high·to-Iow-Ievel output
NOTE 3: Load circuit and voltage waveforms are shown on page 3-10.

1076

TEXAS INSTRUMENTS 7-117

INCORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54LS155, SN74LS155
DUAL 2-UNE-T0-4-UNE DECODERS/DEMULTIPLEXERS
REVISED OCTOBER 1976

recommended operating conditions

SN54LS155 SN74LS155
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -400 -400 IJA
Low-level output current, 10L 4 8 mA
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS155 SN74LS155
PARAMETER TEST CONDITIONSt UNIT
MIN TYPt MAX MIN TYPt MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
VIK Input clamp voltage Vee= MIN, II = -18mA -1.5 -1.5 V
VCC- MIN, VIH - 2V,
VOH High-level output voltage 2.5 3.4 2.7 3.4 V
VIL = VIL max, 10H = -400 IJA
VCC- MIN, VIH - 2V, IIOL -4mA 0.25 0.4 0.25 0.4
VOL Low-level output voltage V
VIL = VIL max I'OL=8mA 0.35 0.5
Input current at
II Vec=MAX, VI =7V 0.1 0.1 mA
maximum input voltage
IIH High-level input current VCC= MAX, VI = 2.7 V 20 20 IJA
IlL Low-level input current Vce = MAX, VI = 0.4 V -0.4 -0.4 mA
lOS Short-circuit output current S VCC= MAX -6 -40 -5 -42 mA
ICC Supply current Vee = MAX, See Note 2 6.1 10 6.1 10 mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAil typical values are at VCC = 5 V. T A = 25°C.
§ Not mOre than one output should be shorted at a time.
NOTE 2: ICC is measured with outputs open, A, B, and 1C inputs at 4.5 V, and 2C, 1G, and 2G inputs grounded .

• I
,
switching characteristics, Vee

PARAMETER~

tpLH
I
,
II
FROM
(INPUT)

A, B,2C,
lG,or2G
=5 V, TA = 25° e
TO
(OUTPUT)

Y
I, LEVELS
OF LOGIC

2
I TEST CONDITIONS
SN54LS155
SN74LS155
MIN TYP

10
MAX

15
IUNITI

ns

A, B, 2C,
tpHL y 2 CL = 15 pF, 19 30 ns
lG,or2G
RL =2 kn,
tpLH AorB Y 3 17 26 ns
See Note 4
tpHL AorB Y 3 19 30 ns
tpLH le y 3 18 27 ns
tpHL le y 3 18 27 ns

~ tPLH "" propagation delay time, low-to-high-Ievel output

tpH L "" propagation delay time, high-to-Iow-Ievel output
NOTE 4: Load circuit and voltage waveforms are shown on page 3-11.

1076

7-178 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54156, SN74156
DUAL 2-LlNE-T0-4-LlNE DECODERS/DEMULTIPLEXERS

recommended operating conditions

SN54156 SN74156
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output voltage, VOH 5.5 5.5 V
Low-level output current, IOL 16 16 mA
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54156
PARAMETER TEST CONDITIONSt SN74156 UNIT
MIN TYp:j: MAX
ViH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
VIK Input clamp voltage Vee= MIN, II = -12 mA -1.5 V
Vee = MIN, VIH = 2 V,
IIOH High-level output current
.-
VII - 08 V ..
Vou = 5 5 V 250 I !lA I
Vee = MIN, VIH =2 V,
VOL Low-level output voltage 0.2 0.4 V
VIL = 0.8 V, IOL = 16mA
II Input current at maximum input voltage Vee = MAX, VI = 5.5 V 1 mA
IIH High-level input current Vee= MAX, VI = 2.4 V 40 JJ.A
IlL Low-level input current Vee = MAX, VI = 0.4 V -1.6 mA

Supply current
Vee = MAX, I SN54156 25 35
mA
lee
See Note 2 I SN74156 25 40

tFor conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at V CC = 5 V, T A = 25° C.
NOTE 2: ICC is measured with outputs open, A, S, and 1 C inputs at 4.5 V, and 2C, 1 G, and 2G inputs grounded.

switching characteristics, Vee

PARAMETER~

tPLH

tpHL
FROM
!INPUT)
A, B,2e,
1G,or2G
A, B, 2e,
1G,or2G
=5 V, TA = 25°e
TO
(OUTPUT)

Y
LEVELS
OF LOGIC

2
TEST CONDITIONS

eL = 15 pF,
MIN TYP

15

20
MAX

23

30
UNIT

ns

ns
•
RL =400 n,
tpLH A or B Y 3 23 34 ns
See Note 3
tpHL AorB Y 3 23 34 ns
tpLH 1e Y 3 18 27 ns
tpHL 1e Y 3 22 3~ ns

~ tp LH == propagation delay time, low-to-high-Ievel output

tpH L == propagation delay time, high-to-Iow-Ievel output
NOTE 3: Load circuit and voltage waveforms are shown on page 3-10.

1076

TEXAS INCORPORATED
INSTRUMENTS 7-179
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54LS156, SN74LS156
DUAL 2-UNE-T0-4-UNE DECODERS/DEMULTIPLEXERS

recommended operating conditions

SN54LSl56 SI'J74LS156
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output voltage, VOH 5.5 5.5 V
Low-level output current, IOL 4 8 rnA
Operating free-air temperature, T A -55 125 a 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LSl56 SN74LSl56
PARAMETER TEST eONDITIONSt UNIT
MIN TYP:j: MAX MIN TYP:j: MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
VIK Input clamp voltage Vee= MIN, II = -18mA -1.5 -1.5 V
Vee= MIN, VIH=2V,
IOH High-level output current 100 100 p.A
VIL = VIL max, VOH = 5.5 V
Vee= MIN, VIH=2V, IIOL = 4mA 0.25 0.4 0.25 0.4
VOL Low-level output voltage V
VIL = VIL max IIOL=8mA 0.35 0.5
I nput current at
II Vee = MAX, VI =7V 0.1 0.1 rnA
maximum input voltage
IIH High-level input current Vee= MAX, VI=2.7V 20 20 p.A
IlL Low-level input current Vee- MAX, VI = 0.4 V -0.4 -0.4 rnA
lee Supply current Vee= MAX, See Note 2 6.1 10 6.1 10 rnA

t For conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at V CC = 5 V, T A = 25° C.
NOTE 2: ICC is measured with outputs open, A, S, and 1 C inputs at 4.5 V, and 2C, 1G, and 2G inputs grounded.

switching characteristics, Vee = 5 V, TA = 25°e

• PARAMETER~

tPLH

tpHL
!
FROM
(INPUT)

A, B, 2e
1G,o,2G
A, B,2e,
1G,or2G
TO
(OUTPUT)

Y
LEVELS
OF LOGie

2
TEST CONDITIONS

eL = 15pF,
RL = 2 k.l1.,
MIN
SN54LSl56
SN74LSl56
TYP

25

34
MAX

40

51
UNIT

ns

ns

tpLH Aor B 3 31 46 ns
See Note 4
tpHL AorB Y 3 34 51 ns
tpLH le y 3 32 48 ns
tpHL 1e y 3 32 48 ns

~tpLH ;; propagation delay time, low-to-high-Ievel output

tpH L;; propagation delay time, high-to-Iow-Ievel output
NOTE 4: Load circuit and voltage waveforms are shown on page 3-11.

1076

7-180 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DAL.LAS, TEXAS 75222
 TYPES SN54157, SN54L157, SN54LS157, SN54LS158, SN54S157, SN54S158,
- SN74157. SN74L157, SN74LS157, SN74LS158. SN74S157. SN74S158
QUADRUPLE 2-UNE-TO-1-UNE DATA SELECTORS/MULTIPLEXERS
BULLETIN NO. DL-S 7611 MARCH 1974-REVISED OCTOBER 1976

features SN54157, SN54LS157, SN54S157 .•• J OR W PACKAGE

SN54L 157 ••. J PACKAGE
• Buffered Inputs and Outputs SN74157, SN74L157, SN74LS157, SN74S157 •.• J OR N PACKAGE
(TOP VIEW)
• Three Speed/Power Ranges Available
INPUTS OUTPUT INPUTS OUTPUT
TYPICAL ,.....-J'-.. r--"-..
TYPICAL VCC STROBE 4A 48 4Y 3A 38 3Y
AVERAGE
TYPES POWER
PROPAGATION
DISSIPATION
TIME
'157 9 ns 150mW
'L157 18 ns 75mW
'LS157 9 ns 49mW 3Y
'S157 5 ns 250mW
'LS158 7 ns 24mW 1A

'S158 4 ns 195mW

applications
• Expand Any Data Input Point SELECT 1A 18 1Y 2A 28 2Y GND
~~
INPUTS OUTPUT INPUTS OUTPUT
• Multiplex Dual Data Buses
positive logic:
• Generate Four Functions of Two Variables Low level at S selects A inputs
(One Variable Is Common) High level at S selects B inputs

• Source Programmable Counters SN54LS158, SN54S158 ... J OR W PACKAGE

SN74LS158, SN74S158 .•• J OR N PACKAGE
description (TOPVIEW)
These monolithic data selectors/multiplexers contain INPUTS OUTPUT INPUTS OUTPUT
inverters and drivers to supply full on-chip data ,.....-J'-.. r--"-..
selection to the four output gates. A separate strobe
input is provided. A 4-bit word is selected from one
of two sources and is routed to the four outputs. The

•
'157, 'L 157, 'LS157, and 'S157 present true data
whereas the 'LS 158 and'S 158 present inverted data
to minimize propagation delay time.
FUNCTION TABLE
INPUTS OUTPUTY
'157, 'L157, 'LS158
STROBE SELECT A B
'LS157, '8157 'S158
H X X X L H
SELECT~ 1Y ~ 2Y GND
L L L X L H
INPUTS OUTPUT INPUTS OUTPUT
L L H X H L
positive logic:
L H X L L H Low level at S selects A inputs
L H X H H L High level at S selects B inputs

H = high level, L = low level, X = irrelevant

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, VCC (see Note 1) 7V

Input voltage: '157, 'L157, 'S158 5.5V
'LS157, 'LS158 7V
Operating free-air temperature range: SN54', SN54L', SN54LS', SN54S' Circuits -55°C to 125°C
SN74', SN74L', SN74LS', SN74S' Circuits aOc to 7aoC
Storage temperature range -65°C to 15aoC
NOTE1: Voltage values are with respect to network ground terminal.

1076

TEXAS INSTRUMENTS 7-181

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54157, SN54L157, SN74157, SN74L157,
QUADRUPLE 2-UNE-TO-1-UNE DATA SELECTORS/MULTIPLEXERS

functional block diagram

'157, 'L157

1A

1B

2A

2B

3A

3B

4A

4B

SELECT

(15)
STROBE

• schematics of inputs and outputs

'157, 'L157 '157, 'L157

EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS

- .....--Vcc
Vcc---+--

INPUT
OUTPUT

'157: Req ~ 4 kn. NOM '157: R ~ 100 n. NOM

'L157: Req~8kn.NOM 'L157: R~200nNOM

374

7·182 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54LS157, SN54LS158, SN54S157, SN54S158,
SN74LS157, SN74LS158, SN74S157, SN74S158
QUADRUPLE 2-LlNE-TO-1-LlNE DATA SELECTORS/MULTIPLEXERS
functional block diagrams schematics of inputs and outputs
'LS157, 'S157 'LS157, 'LS158
(2) EQUIVALENT OF EACH INPUT
1A
..
Vcc---.--
(3)
1B
I N PUT ~if-+----<~

(5)
2A

(6)
2B

S or G inputs: Req = 8.5 kn NOM

(11)
3A A or B inputs: Req = 17 kn NOM

TYP!CAL OF ALL OUTPUTS

(10)
3B

(14)
4A

(13)
4B

(15)
STROBE G
(1)
SELECT S

'LS158, 'S158
(2) 'S157, 'S158
1A EQUIVALENT OF EACH INPUT

1B

2A
(3)

(5)
VCC3--
INPUT.
Req

--
II
(6)
2B

(11) S or G inputs: Req = 1.4 kn NOM

3A
A or B inputs: Req = 2.8 kn NOM
(10) TYPICAL OF ALL OUTPUTS
3B
VCC /

(14)
4A

(13) OUTPUT
4B

(15)
STROBE G
(1)
SELECT S

1076

TEXAS INSTRUMENTS 7-183

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54157. SN74157
QUADRUPLE 2-UNE-TO-1-UNE DATA SELECTORS/MULTIPLEXERS

recommended operating conditions

SN54157 SN74157
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -800 -800 !J.A
Low-level output current, 10L 16 16 mA
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54157 SN74157
PARAMETER TEST CONOITIONSt UNIT
MIN TYP+ MAX MIN TYP+ MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
VIK I nput clamp voltage Vee = MIN, 11=-12mA -1.5 -1.5 V
Vee = MIN, VIH = 2 V,
VOH High-level output voltage 2.4 3.4 2.4 3.4 V
VIL = 0.8 V. 10H = -800!J.A
Vee= MIN, VIH = 2 V,
VOL Low-level output voltage 0.2 0.4 0.2 0.4 V
VIL = 0.8 V, 10L = 16 mA
II Input current at maximum input voltage Vee - MAX, VI = 5.5 V 1 1 mA
IIH High-level input current Vee = MAX, VI=2.4V 40 40 !J.A
IlL Low-level input current Vee- MAX, VI = 0.4 V -1.6 -1.6 mA
lOS Short-circuit output current~ Vee = MAX -20 -55 -18 -55 mA
lee Supply current Vee= MAX, See Note 2 30 48 30 48 mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at Vee = 5 V, T A = 25°e.
§ Not more than one output should be shorted at a time and duration of short-circuit should not exceed One second.
NOTE 2: ICC is measured with 4.5 V applied to all inputs and all outputs open.

• switching characteristics, Vee::: 5 V, TA::: 25°e

PARAMETER~
tPLH
tPHL
tPLH
tpHL
tPLH
FROM (INPUT)

Data

Strobe

Select
TEST CONDITIONS

CL=15pF,
RL=400n,
See Note 3
MIN TYP
9
9
;3
14
15
MAX UNIT
14
14
20
21
23
ns

ns

ns
tpHL 18 27

~ tpLH :; propagation delay time, low-to-high-Ievel output

tpHL:; propagation delay time, high-to-Iow-Ievel output
NOTE 3: Load circuit and voltage waveforms are shown on page 3-10.

1076

7-184 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54L157, SN74L157
QUADRUPL~ 2-UNE-TO-1-UNE DATA SELECTORS/MULTIPLEXERS

recommended operating conditions

SN54L157 SN74L 157
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -400 -400 p,A
Low-level output current, 10L 8 8 mA
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST eONDlTlONSt MIN TYP+ MAX UNIT
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
VIK Input clamp voltage Vee= MIN, II = -12mA -1.5 V
Vee;;;; ~.4!!\!, ViH = 2V,
VOH High-level output voltage 2.4 3.4 V
VIL = 0.8 V, 10H = -400p,A
Vee= MIN, VIH = 2V,
VOL Low-level output voltage 0.2 0.4 V
VIL = 0.8 V, 10L = 8mA
II Input current at maximum input voltage Vee = MAX, VI=5.5V 1 mA
IIH High-level input current Vee = MAX, VI=2.4V 20 p,A
IlL Low-level input current Vee = MAX, VI = 0.4 V -0.8 mA
lOS Short-circuit output current § Vee = MAX -9 -28 mA
ICC Supply current Vee = MAX, See Note 2 15 24 mA

t For conditions shc\...... n as M! N or !\t1AX, use the appropriate value specified undar recommended operating conditions.
+AII typical values are at VCC = 5 V, T A = 25°C.
§Not more than one output should be shorted at a time.

•
NOTE 2: ICC is measured with 4.5 V applied to all inputs and all outputs open.

switching characteristics, Vee = 5 V, TA = 25°e

PARAMETER~ FROM (INPUT) TEST CONDITIONS MIN TYP MAX UNIT
tpLH 18 28
Data ns
tPHL 18 28
eL = 15 pF,
tPLH 26 40
Strobe RL=800n, ns
tPHL 28 42
See Note 3
tPLH 30 46
Select ns
tpHL 36 54

~ tp LH == propagation delay time, low-to-high·level output

tpHL == propagation delay time, high-to-Iow-Ievel output
NOTE 3: Load circuit and voltage waveforms are-shown on page 3-10.

1076

TEXAS INCORPORATED
INSTRUMENTS 7-185
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54LS157, SN54LS158, SN74LS157, SN74LS158
QUADRUPLE 2-UNE-TO-1-UNE DATA SELECTORS/MULTIPLEXERS

recommended operating conditions

SN54LS' SN74LS'
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -400 -400 /J A
Low-level output current, 10L 4 8 rnA
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS' SN74LS'
PARAMETER TEST CONDITIONSt UNIT
MIN TVP:j: MAX MIN TVP:j: MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
VIK Input clamp voltage Vee= MIN, 11=-18mA -1.5 -1.5 V
Vee= MIN, VIH = 2 V,
VOH High-level output voltage 2.5 3.4 2.7 3.4 V
VIL = MAX, 10H = -400/JA
Vee = MIN, VIH = 2 V, Ii0L = 4mA 0.25 0.4 0.25 0.4
VOL Low-level output voltage V
VIL = MAX Ii0L = 8mA 0.35 0.5
I nput current
S or G input 0.2 0.2
II at maximum Vee= MAX, VI = 7V rnA
A or B input 0.1 0.1
input voltage
High-level S or G input 40 40
IIH Vee = MAX, VI = 2.7 V /J A
input current A or B input 20 20
Low-level S or G input -0.8 -0.8
IlL Vee= MAX, VI = 0.4 V rnA
input current A or B input -0.4 -0.4
lOS Short-circuit output currend Vee = MAX -20 -100 -20 -100 rnA
l'LS157 9.7 16 9.7 16
ICC Supply current Vee= MAX, See Note 2 rnA
I'LS158 4.8 8 4.8 8

•
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at Vee = 5 V, T A = 25"e,
§ Not more than one output should be shorted at a time and duration of short-circuit should not exceed one second,
NOTE 2: ICC is measured with 4.5 V applied to all inputs and all outputs open.

switching characteristics, Vee = 5 V, T A = 25° C

FROM 'LS157 'LS158
PARAMETER~ TEST CONDITIONS UNIT
(INPUT) MIN TVP MAX MIN TVP MAX
tPLH 9 14 7 12
Data ns
tpHL 9 14 7 12
CL=15pF,
tPLH 13 20 11 17
Strobe RL=2kn, ns
tPHL 14 21 12 18
See Note 4
tPLH 15 23 13 20
Select ns
tPHL 18 27 16 24

~ tp LH "" propagation delay time, low-to-high-Ievel output

tpHL "" propagation delay time, high-to-Iow-Ievel output
NOTE 4: Load circuit and voltage waveforms are shown on page 3-11.

1076

7-186 TEXAS INSTRUMENTS

I~CORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54S157, SN54S158, SN74S157, SN74S158
QUADRUPLE 2-UNE-TO-1-UNE DATA SELECTORS/MULTIPLEXERS

recommended operating conditions

SN54S157 SN74S1'57
SN54S158 SN74S158 UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -1 -1 mA
Low-level output current, 10L 20 20 mA
Operating free·air temperature, T A -55 125 0 70 e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54S157 SN54S158
PARAMETER TEST eONDITIONSt SN74S157 SN74S158 UNIT
MIN TYP:j: MAX MIN TYP:j: MAX
VIH High·level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
v~K ~np!..!t damp vo!tage Vee;::: MIN, !i = -18mA _1') 1') \I

Vee= MIN, VIH = 2 V, ISeries 54S 2.5 3.4 2.5 3.4

VOH High·level output voltage V
VIL = 0.8 V, i
10H = -1 mA Series 74S 2.7 3.4 2.7 3.4
Vee= MIN, VIH = 2 V,
VOL Low-level output voltage 0.5 0.5 V
VIL = 0.8 V, 10L = 20 mA
II Input current at maximum input voltage Vee = MAX, VI = 5.5 V 1 1 mA
S or G input 100 100
IIH High·level input current Vee= MAX, VI=2.7V !J.A
A or B input 50 50
S or G input -4 -4
IlL Low-level input current Vee = MAX, VI=0.5V mA
A or B input -2 -2
lOS Short·circuit output current§ Vee= MAX -40 -100 -40 -100 mA
ICC Supply current Vee= MAX, See Note 2 50 78 39 61 mA

•
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at Vee = 5 V, T A = 25°e.
§ Not more than one output should be shorted at a time, and duration of the short·circuit should not exceed one second.
NOTE 2: lee is measured with 4.5 V applied to all inputs and outputs open.

switching characteristics, Vee = 5 V, TA = 25°e

SN54S157 SN54S158
FROM
PARAMETER~ TEST CONDITIONS SN74S157 SN74S158 UNIT
!INPUT)
MIN TYP MAX MIN TYP MAX
tPLH 5 7.5 4 6
Data ns
tPHL 4.5 6.5 4 6
eL = 15 pF,
tpLH 8.5 12.5 6.5 11.5
Strobe RL = 280 n, ns
tPHL 7.5 12 7 12
See Note 3
tpLH 9.5 15 8 12
Select ns
tPHL 9.5 15 8 12

~tpLH == propagation delay time, low·to·high·level ~utPut

tpH L == propagation delay time, high·to·low·level output
NOTE 3: Load circuit and voltage waveforms are shown on page 3-10.

1076
TEXAS INSTRUMENTS
INCORPORATED 1-181
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54159, SN74159
TTL 4-UNE-TO-16-UNE DECODERS/DEMULTIPLEXERS
MSI WITH OPEN-COLLECTOR _OUTPUTS
BULLETIN NO. DL-S 7211800, DECEMBER 1972

SN54159 ••• J OR W PACKAGE

• Open-Collector Outputs for Interfacing with SN74159 ••• J OR N PACKAGE
(TOP VIEW)
MOS or Memory Decoders/Drivers
• Decodes 4 Binary-Coded I nputs into One of
16 Mutually Exclusive Outputs
• Performs the Demultiplexing Function by
Distributing Data from One Input Line to
Any One of 16 Outputs
• Typical Average Propagation Delay Times:
24 ns through 3 Levels of Logic
19 ns from Strobe Input
• Output Off-State Current is Less Than 50 p.A ~----------~vr-----------~
OUTPUTS
• Fully Compatible with Most TTL, DTL, and
MSI Circuits positive logic: see function table

description

Each of these monolithic, 4-line-to-16-line decoders utilizes TTL circuitry to decode four binary-coded inputs into one
of sixteen mutually exclusive open-collector outputs when both the strobe inputs, G1 and G2, are low. The demulti-
plexing function is performed by using the 4 input lines to address the output line, passing data from one of the strobe
inputs with the other strobe input low. When either strobe input is high, all outputs are high. These demultiplexers are
ideally suited for implementing MOS memory decoding or for interfacing with discrete memory address drivers. For
ultra-high-speed applications, the SN54S138/SNi4S138 or SN54S139/SN74S139 is recommended.

These circuits are fully compatible for use with most other TTL and DTL circuits. Input clamping diodes are provided
to minimize transmission-line effects and thereby simplify system design. Input buffers are used to lower the fan-in
requirement to only one normalized Series 54/74 load. A fan-out to 10 normalized Series 54/74 loads in the low-level

• state is available from each of the sixteen outputs. Typical power dissipation is 170 mW .
The SN54159 is characterized for operation over the full military temperature range of -55°C to 125°C; the SN74159
is characterized for operation from O°C to 70°C.

function table
Same as SN54154, SN74154. See page 7-172.
functional block diagram
Same as SN54154, SN74154. See page 7-172.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, VCC (see Note 1) 7V

Input voltage . . . . . . . . 5.5 V
Off-state output voltage 5.5V
Operating free-air temperature range: SN54159 Circuits -55°C to 125°C
SN74159 Circuits aOc to 70°C
Storage temperature range -65°C to 150°C

NOTE1: Voltage values are with respect to network ground terminal

1076

7-188 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54159, SN74159
4-LlN E-TO-16-LlNE OECOOERS/OEMU LTIPLEXERS
WITH OPEN-COLLECTOR OUTPUTS
recommended operating conditions
SN54159 SN74159
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
Low-level output current, IOL 16 16 mA
Operating free-air temperature, T A 55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range {unless otherwise noted)
PARAMETER TEST CONDITIONSt MIN TYP:j: MAX UNIT
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
VIK Input clamp voltage Vec= MIN, II = -12 mA -1.5 V
Vee = MIN, VIH = 2 V,
IOH High-level output current 50 J.LA
V!L = 0.8 V, VOH = 5.5V
Vee= MIN, VIH=2V,
VOL Low-level output voltage 0.4 V
VIL = 0.8 V, IOL = 16mA
!i Input current 8t m~x:m:..:m input vo~tage Vee == fv1AX, VI- 5.5V mA
IIH High-level input current Vee = MAX, VI = 2.4 V 40 J.LA
IlL Low-level input current Vee = MAX, VI = 0.4 V -1.6 mA
lee Supply current Vee = MAX, All inputs grounded 34 56 mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
:j: All typical values are at V CC = 5 V, T A = 25° C.

switching characteristics, Vee = 5 V, TA = 25° C

PARAMETER TEST eONDITIONS MIN TYP MAX UNIT

tPLH
Propagation delay time, low-to-high-Ievel output,
I 23 36 oS
from A, B, e, or D inputs through 3 levels of logic
Propagation delay time, high-to-Iow-Ievel output,
24 ns

•
tpHL 36
from A, B, e, or D inputs through 3 levels of logic
eL=15pF, RL=400n, See Note 2
Propagation delay time, low-to-high-Ievel output,
tPLH 15 25 ns
from either strobe input
Propagation delay time, high-to-Iow-Ievel output,
tPHL 22 36 ns
from either strobe input

NOTE 2: See load circuit and waveforms shown on page 3-10.

schematics of inputs and outputs

EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS

Vcc - - - -. .- - - -

INPUT

1076

TEXAS INCORPORATED
INSTRUMENTS 7-189
POST OFFICE BOX 5012 • CALLAS. TEXAS 75222
 TYPES SN54160 THRU SN54163, SN54LS160A THRU SN54LS163A,
TTL SN54S162, SN54S163. SN74160 THRU SN74163,
MSI SN74LS16-0A THR-U S-N74LS163A, SN74S162, SN74S163
SYNCHRONOUS 4-81T ~OUNTERS
BULLETIN NO. DL-5 7611385 ER 1976

'160, '161,'LS160A, 'LS161A ... SYNCHRONOUS COUNTERS WITH DIRECT CLEAR

'162, '163, 'LS162A, 'LS163A, 'S162, 'S163 ... FULLY SYNCHRONOUS COUNTERS
SERIES 54', 54LS', 54S' .•. J OR W PACKAGE
• Internal Look-Ahead for Fast Counting SERIES 74', 74LS', 74S' ••• J OR N PACKAGE
(TOP VIEW)
• Carry Output for n-Bit Cascading
• Synchronous Counting
• Synchronously Programmable
• Load Control Line
• Diode-Clamped Inputs
TYPICAL
TYPICAL PROPAGATION TYPICAL
MAXIMUM
TYPE TIME, CLOCK TO POWER
CLOCK
QOUTPUT DISSIPATION
FREQUENCY
'160 thru '163 14 ns 32MHz 305mW
'LS160A thru 'LS163A 14 ns 32MHz 93mW CLEAR CLOCK ABC D ENABLE GND
~p
'5162 and 'S163 9 ns 70MHz 475mW DATA INPUTS

logic: see description

description
These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting
designs. The '160, '162, 'LS160A, 'LS162A, and 'S162 are decade counters and the '161, '163, 'LS161 A, 'LS163A, and
'S163 are 4-bit binary counters". Synchronous operation is provided by having all flip-flops clocked simultaneously so
that the outputs change coincident with each other when so instructed by the count-enable inputs and internal gating.
This mode of operation eliminates the output counting spikes that are normally associated with asynchronous (ripple
clock) counters. A buffered clock input triggers the four flip-flops on the rising (positive-going) edge of the clock input
waveform.
These counters are fully programmable; that is, the outputs may be preset to either level. As presetting is synchronous,
setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after
the next clock pulse regardless of the levels of the enable inputs. Low-to-high transitions at the load input of the '160

•
thru '163 or 'S163A or 'S162 should be avoided when the clock is low if the enable inputs are high at or before the
transistion. This restriction is not applicable to the 'LS160A thru 'LS163A. The clear function for the '160, '161,
'LS160A, and 'LS161A is -asynchronous and a low level at the clear input~ets all four of the flip-flop outputs low
regardless of the levels of clock,load, or enable inputs. The clear function for the '162, '163, 'LS162A, 'LS163A, 'S162,
and'S163 is synchronous and a low level at the clear input sets all four of the flip-flop outputs low after the next clock
pulse, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily
as decoding the maximum count desired can be accomplished with one external NAND gate. The gate output is
connected to the clear input to synchronously clear the counter to 0000 (LLLL). Low-to-high transitions at the clear
input of the '162 and '163 should be avoided when the clock is low if the enable and load inputs are high at or before
the transition.
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional
gating. Instrumental in accomplishing this function are two count-enable inputs and a ripple carry output. Both
count-enable inputs (P and T) must be high to count, and input T is fed forward to enable the ripple carry output. The
ripple carry output thus enabled will produce a high-level output pulse with a duration approximately equal to the
high-level portion of the QA output. This high-level overflow ripple carry pulse can be used to enable successive
cascaded stages. High-to-Iow-Ievel transitions at the enable P or T inputs of the '160 thru '163 should occur only when
the clock input is high. Transitions at the enable P or T inputs of the 'LS160A thru 'LS163A or 'S162 and 'S163 are
allowed regardless of the level of the clock input.
'LS160A toru 'LS163A, 'S162 and 'S163 feature a fully independent c!ock circuit. Changes at control inputs (enable
P or T, or clear) that will modify the operating mode have no effect until clocking occurs. The function of the
counter (whether enabled, disabled, loading, or counting) will be dictated solely by the conditions meeting the stable
setup and hold times.
The 'LS160A thru 'LS163A are completely new designs. Compared to the original 'LS160 thru 'LS163, they feature
O-nanosecond minimum hold time and reduced input currents II H and II L.

1076
7-190 TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 ~
~

-n
I:
:::I
SN54160, SN74160 SYNCHRONOUS DECADE COUNTERS SN54163, SN74163 SYNCHRONOUS BINARY COUNTERS ~
O·
:::I
SN54162, SN74162 synchronous decade counters are similar; SN54161, SN74f161 synchronous binary counters are similar; ~
however the clear is synchronous as shown for the SN54163, however, the clear is asynchronous as shown for the SN54160, C"
SN74163 binary counters at right. SN74160 decade counters at left. g
"iii'
0-
ce
iil
LOAD (91
LOAD (91 g
(14) DA
(141

....
OA

D~TA 13) i ~I
DATA
A
(3)
<
"'CI
m
£"oo-oi
[T]
en
. . >< (13) DB en
~
(131 DB
> 2
f,l
ID -
o
~8z
Z_

~~(J)
'0"""'1
(J)
DABTA (41 I I I r--"~I CLEAR I
DATA (4J
B --

CLOCK (2)
-....=
U"I
-a::.
CD

g~~ (121 Dc
(12) Dc :c
E~c::
:::a
C
~03:: D~TA_15_1_. I I I I I r--"~
OATA~)

\:1 [T]
C
en en
~ Z <2
2U"1
~ -i n-a::.
~ (J) (11) DO :cO:;
(11) DO
:::a W
0"
OATA~~
0 2 en
2
0
CLEAR (1) C ......
en:!::

=========[~ "" ; :;.~:

-a::. CD
ENABLE
p (71
.=
~DUTPUT
T (101
(15) 6::~e !:!!! ....
OUTPUT .= .... :c
n:::a
OC
Cen
22
..........
m-a::.
:::a-
';'-I
en~

•
~
-'...,
~1~[­
~ o~-g
Ql 8.. m
n 'fil
-i
:> ::TC-o
~~ ~ ~ ~
~
CD
N
~ --t

SN54LS160A. SN74LS160A SYNCv~"''''f}US

DECADE COUNTERS
• SN54LS163A. SN74LS163A SYNCHRONOUS
BINARY COUNTERS
....
r::
::s
~
o·::s
!E-
en~
-<-<
Z"'tJ
n
:een
::a
m

§,: ;l g: ~
SN54LS161A. SN74LS161A synchronous binary
O'"
0"
een
ZZ
g~ ~: :(m SN54LS162A. SN74LS162A synchronous decade n
eel'
s ~_~Q;' 0
counters are similar; however the clear is synchronous counters are similar; however, the clear is ~
Co C~
::J n::J
s0' ~.;t~, ~ as shown for the SN54LS163A. SN74LS163A binary asynchronous as shown for the SN54LS160A. Di·
ce
enr-en
0 C CD l> SN74LS160A decade counters at left.
!" a ~ 5'
counters at right.
CIl
@
3 ~-
,en
Q~Q ~ m=
5-;;; ~ ~
(ii' ~ :::!.
::::;>
n~
-0:2 0

8.~~ e:e
~~~ c::a
ZC
,,-1 ~
~ ["l"I men
-< >< ::aZ
~ > DATAA~
enc.n
~ OATAA~ ~

.,.-
(J1 ------~---~
~ z.......
r,
r-
en
~8z en
~~(J1 w
o~
~~ DATABill~-+------l DATAB~f-+I-+I-+I---+---..J
~c: en
o~ Z
......
["l"I ~

-
Z r-
~
en
(J1 en
=
>
DATAC~ J I I I I I r--- I L...J DATAC~I-+I--III-+I-il~---+-- ~
:e
::a
C
en
i2
......
~

DATAO~

--------(1-5Ig~mT
OATAO~ II I t-t_----l
~
_______ ---!

1'5Ig~~~jT
-
r-
en
en
w
>

S
m
 '8
Cl'l

2' JJ
m
::::I <
~ iii
0" m
SN54S162, SN74S162 SYNCHRONOUS DECADE COUNTERS SN54S163, SIN74S163 SYNCHRONOUS BINARY COUNTERS ::::I
0

-0-
Q) 0
0
-I
0
0" to
0 m
CLOCK CLOCK ~-------------- '"c..iii" JJ
U;
-.J

:::~"~
LOAD
~ Cl'l

a
Q)

CLEAR

DATAA '"I I I'

.. ----J
g ["l'1
-I
-I >< -<
~ > "tJ
~ (JJ DATAB \4, I III~ m
aIII -z _ tn
~8Z en
~~Cf) 2
.0'"""1 U'I
g~iC
~~C
~03:
~ tT'J
DATAC (51 II
tn-
-
~
tn
en
N

~ Z -<en
;;l '"""I Zz
~ Cf) n U'I
::C~
:::a en
oS;
Z w
0-
C tn
tn Z
~~
Itn
0:1_
')0 \151~:;~~ - en
-IN
ENABLE{~ OUTPUT

n
otn
c2
Z ......
-I~
mtn
:::a-
tn~
~

•
co
w
 TYPES SN54160, SN54162, SN54LS160A, SN54LS162A, SN54S162,
SN74160, SN74162,. SN74LS160A, SN74LS162A, SN74S162
SYNCHRONOUS 4-81t COUNTERS
'160, :162, 'LS160A, 'LS162A, 'S162 DECADE COUNTERS

typical clear, preset, count, and inhibit sequences

Illustrated below is the following sequence:

1. Clear outputs to zero ('160 and '-LS160A areasynchronous;:162, 'LS162A,and 'S162 are synchronous)
2. Preset to BCD seven
3. Count to eight, nine, zero, one, two, and three
4. Inhibit

CLEAR-U

LOAD u
c=
DATA c=
INPUTS

D ____~------~,
c=
1--
__

CLOCK

ENABLE P
,

• ENABLET ____~__~--'~I~I--~I------------~------~-----------:

OUTPUTS {
( QA_

OB
---,.
--! _,

= ~--fl
i
: I I
________

- --, ---i'----.Jr--1I
QC
- I I
- - --I I~-----------------------------------------
- -, --lI
QD __ ----1
': I

Ii- ----,

I I , I

RIPPLE-CARRY ----~I
: __ I __-+I' __ :__
~I ~I ~I
r----1I~____________~____________________
OUTPUT i i !7 ;8 9 0 2 3:
I I . . .>-----COUNT---__I-·- - - I N H I B I T - - - -
I SYNC PRESET
ASYNCCLEAR
CLEAR

1076

7-194 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54161, SN54163, SN54LS161A, SN54LS163A, SN54S163,
SN74161, SN74163, SN74LS161A, SN74LS163A, SN74S163
SYNCHRONOUS 4-81T COUNTERS
'161, 'LS161A, '163, 'lS163A, 'S163 BINARY COUNTERS

typical clear, preset, count, and inhibit sequences

Illustrated below is the following sequence:

1. Clear outputs to zero ('161 and 'LS161A are asynchronous; '163, 'LS163A, and 'S163 are synchronous)
2. Preset to binary twelve
3. Count to thirteen, fourteen fifteen, zero, one, and two
4. Inhibit

CLEAR~

LOAD LJ
A
,--
----~------~,
I
--
B ,--
DATA ----~------~I __
INPUTS
C ...J,...---i-------.,' -
'--
D 1,...--:-------." -
---.J L __

CLOCK

•
ENABLE P
I
I
ENABLE T I
I
OA - - - , --,
- ---! -,----.;----.j
-
OB _ _ _,
-,-,,_---.;_ _ _ _ ~

OUTPUTS

OD=-' ;~
I I I
I I .---,
RIPPLE-CARRY I I I I~ _ _ _......:-_ _ _ _ _ _ _ _ __
OUTPUT :: :12 13 14 15 0 2
I ..I·---COUNT---"'I~'- - - I N H I B I T - - -
I
I
SYNC PRESET
CLEAR

ASYNC
CLEAR

1076

INSTRUMENTS
TEXAS INCORPORATED 7-195
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54160 THRU SN54163. SN74160 THRU SN74163
SYNCHRONOUS 4-81T COUNTERS

schematics of inputs and outputs

EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS

VCC--------~--------

INPUT

Clock: Req = 2.8 H2 NOM

Enable T: Req = 2 kn NOM
Clear, Enable P: Req = 4 kn NOM
A, B, C, D: Req = 6 kn NOM

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) 1V
Input voltage . . . . . . . . 5.5 V
Interemitter voltage (see Note 2) 5.5V
Operating free-air temperature range: SN54' Circuits -55°C to 125°C

•
SN14' Circuits O°C to 10°C
Storage temperature range -65°C to 150°C
NOTES: 1. Voltage values, except interemitter voltage, are with respect to network ground terminal.
2. This is the voltage between two emitters of a multiple·emitter transistor. For these circuits, this rating applies between the count
enable inputs P and T.

recommended operating conditions

SN54160, SN54161 SN74160, SN74161 i
SN54162, SN54163 SN74162, SN74163i UNIT
I MIN NOM MAX MIN NOM MAX
Supply voltage, VCC 4.5 5 5.5 4.75 5 5.25 V
High-level output current, IOH -800 -800 I J.lA I
Low-level output current, IOL 16 16 I rnA !
Clock frequency, fclock 0 25 0 25 MHz
Width of clock pulse, tw(clock) 25 25 ns
Width of clear pulse, tw(clearl 20 20 ns
Data inputs A, B, C, D 20 20
Enable P 20 20 I
Setup time, tsu isee Figures 1 and 2) ns
Load 25 25
Clearo 20 20
Hold time at any input, th 0 0 ns
Operating free-air temperature, T A
.- ...
-55 125 0 70 °c
~his applies only for '162 and '163, which have synchronous clear inputs .

1076

7-196 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54160 THRU SN54163, SN74160 THRU SN74163
SYNCHRONOUS 4-811 COUNTERS

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

SN54160, SN54161 SN74160, SN74161

PARAMETER TEST CONDITIONSt SN54162, SN54163 SN74162, SN74163 UNIT
MIN TYP:j: MAX MIN TYP:j: MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0_8 OB V
VIK Input clamp voltage Vee= MIN, II =-12mA -1-5 -1-5 V
Vee = MIN, VIH = 2 V,
VOH High-level output voltage 2A 3.4 2.4 3A V
VIL = 0_8 V, 10H = -800J.l.A
Vee = MIN, VIH =2 V,
VOL Low-level output voltage 0_2 0.4 0.2 0.4 V
VIL=0.8V, IOL=16mA
II Input current at maximum input voltage Vec = MAX, VI = 5.5 V 1 1 rnA
High-!eve! Clock or enable T 80 I 80
IIH VCC = MAX, VI = 2.4 V J.l.A
input current Other inputs 40 40 I
Low-level Clock or enable T -3.2 -3.2 !
III Vee:= MAX, V; = 0.4 V rnA
input 'current Other inputs -1-6 -1-6
lOS Short-circuit output current § Vee = MAX -20 -57 -18 -57 rnA
ICCH Supply current, all outputs high VCC = MAX, See Note 3 59 85 59 94 rnA
ICCL Supply current, all outputs low VCC = MAX, See Note 4 63 91 63 101 rnA
~For conditions shown as MIN or MAX, use t~e appropriate value specified under recommended operating conditions.
+AII typical values are at VCC = 5 V, T A = 25 C.
§Not more than one output should be shorted at a time.
NOTES: 3. ICCH is measured with the load input high, then again with the load input low, with all other inputs high and all outputs open.
4. iCCL is measured with the clock ;'nput high, then again with the clock input low, with alt' other inputs low and all outputs open.

switching characteristics, Vee =S V, TA = 2Soe

•
FROM TO
PARAMETER~ TEST CONDITIONS MIN TYP MAX UNIT
(INPUT) (OUTPUT)
f max 25 32 ns
tpLH Ripple 23 35
Clock ns
tpHL carry 23 35
tPLH Clock Any CL = 15 pF, 13 20
ns
tpHL (load input highl Q RL = 400 n, 15 23
tpLH Clock Any See Figures 1 and 2 17 25
ns
tpHL (load input lowl Q and Notes 5 and 6 19 29
tPLH Ripple 11 16
Enable T ns
tPHL carry 11 16
tpHL Clear AnyQ 26 38 ns

~fmax == Maximum clock frequency

tpLH == propagation delay time, low-to-high-Ievel output
tpHL == propagation delay time, high-to-Iow-Ievel output
NOTES: 5. Load circuit is shown on page 3-10_
6. Propagation delay for clearing is measured from the clear input for the '160 and '161 or from the clock input transition for the
'162 and '163.

1076

TEXAS INCORPORATED
INSTRUMENTS 7-197
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54LS160A, THRU SN54LS163A, SN74LS160A, THRU SN74LS163A,
SYNCHRONOUS 4-811 COUNTERS

schematics of inputs and outputs

EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS

- - - - - -....- Vcc
VCC -----11..---- 120 n NOM

I NPUT - ...-41"-4~"--

L...-----4.-- OUTPUT

Data: Req = 2.5 kn NOM

Enable T, Load: Req = 10 kn NOM
Clock, Enable P: Req = 20 kn NOM
Clear ('LS160A. 'LS161A): Req = 20 kn NOM
Clear ('LS162A. 'LS163A): Req = 10 kn NOM

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, VCC (see Note 7) .. - . . - . . 7V

Input voltage . . . . . . . . . . - . . - . . 7V
Operating free-air tempEirature range: SN54LS' Circuits -55°C to 125°C
SN74LS' Circuits O°C to 70°C
Storage temperature range -65°C to 150°C

•
NOTE 7: Voltage values are with respect to network ground terminal.

recommended operating ~nditions

SN54LS' SN74LS'
:
i MIN NOM MAX MIN NOM MAX
Supply voltage, VCC 4.5 5 5.5 4.75 5 5.25 V
High-level output current, IOH -400 -400 /lA
low-level output current, IOl 4 8 mA
Clock frequency, fclock 0 25 0 25 MHz
Width of clock pulse, tw(clock) 25 25 ns
Width of clear pulse, tw(clearl 20 20 ns
Data inputs A, B, C, D 20 20
Enable P or T 20 20
Setup time, tsu (see Figures 1 and 2) ns
load 20 20
Clear O 20 20
Hold time at any input, th 0 0 ns
Operating free-air temperature, T A -55 125 0 70 "c
o This applies only for 'LS162 and 'LS1 63, which have synchronous clear inputs.

TENTATIVE DATA 1076

This page provides tentative information on a
7-198 new product. Texas Instruments reserves the TEXAS INSTRUMENTS
right to change specifications for this product INCORPORATED
POST OFFICE BOX 5012 • DA.LLAS. TEXAS 75222
in any manner without notice.
 TYPES SN54LS160A THRU SN54LS163A, SN74LS160A THRU SN74LS163A
SYNCHRONOUS 4-81T COUNTERS

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS' SN74LS'
PARAMETER TEST eONDITIONst UNIT
MIN TYP+ MAX MIN TYP:j: MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
VIK Input clamp voltage Vee= MIN, II =-18mA -1.5 -1.5 V
Vec= MIN, VIH=2V,
VOH High-level output voltage 2.5 3.4 2.7 3.4 V
VIL = VIL max, 10H = -400 p,A
VCC= MIN,
[IOL=4mA 0.25 0.4 0.25 0.4
VOL Low-level output voltage VIH = 2 V, V
VIL=VILmax IIOL=8mA 0.35 0.5

Data or enable P 0.1 0.1

Input current
Load, clock, or enable T 0.2 0.2
II at maximum VCC= MAX, VI = 7V rnA
Clear ('LS160A, 'LS161A) 0.1 0.1
input voltage
Clear ('LS 162A, 'LS 163A) 0.2 0.2
Data or enable P 20 20
High-level Load, clock, or enable T 40 40
VCC = MAX, VI = 2.7V !J.A
IIH
inpui Curreni Cit:ar\ 'LS i oGA, 'LSi oi Ai 20
I 20 I I
Clear('LS162A, 'LS163A) I 40 40
Data or enable P -0.4 -0.4
Low-level Load, clock, or enable T -0.8 -0.8
IlL VCC= MAX, VI = 0.4 V rnA
input current Clear ('LS160A, 'LS161A) -0.4 -0.4
Clear('LS162A, 'LS163A) -0.8 -0.8

lOS Short-circuit output current§ VCC= MAX -20 -100 -20 -100 mA
ICCH Supply current, all outputs high VCC= MAX, See Note 3 18 31 18 31 mA
ICCL Supply current, all outputs low VCC- MAX, See Note 4 19 32 19 32 rnA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at VCC = 5 V, T A = 25°C.
§Not more than one output should be shorted at a time, and duration of the short-eircuit should not exceed one second.
NOTES: 3. ICCH is measured with the load input high, then again with the load input low, with all other inputs high and all outputs open.

•
4. ICCL is measured with the clock input high, then again with the clock input low, with all other inputs low and all outputs open .

switching characteristics, Vee = 5 V, T A = 25°e

FROM TO
PARAMETER~ TEST CONDITIONS MIN TYP MAX UNIT
(INPUT) (OUTPUT)
f max 25 32 MHz
tPLH Ripple 20 35
Clock ns
tPHL carry 18 35
CL=15pF,
tPLH Clock Any 1:3 24
RL = 2 kn, ns
tpHL (load input high) Q 18 27
See Figures
tPLH Clock Any 13 24
1 and 2 and ns
tPHL (load input low) Q 18 27
Notes 8 and 9
tPLH Ripple 9 14
Enable T ns
carry 14'
tPHL
tpHL Clear AnyQ
- - 209 28 ns

~ f max == Maximum clock frequency

tpLH == propagation delay time, low-to-high-Ievel output.
tpHL == propagation delay time, high-to-Iow-Ievel output.
NOTES: 8, Load circuit is shown on page 3-11.
9. Propagation delay for clearing is measured from the clear input for the 'LS160A and 'LS161 A or from the clock transition
for the 'LS162A and 'LS163A.

1076 TENTATIVE DATA

This page provides tentative information on a
new product, Texas Instruments reserves the TEXAS INSTRUMENTS
INCORPORATED
7-199
right to change specifications for this product
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
in any manner without notice.
 TYPES SN54S162, SN54S163, SN74S162, SN74S163
SYNCHRONOUS 4-81T COUNTERS

schematics of inputs and outputs

EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS

-------------~-----VCC

VCc-------~e_-------
50 n NOM

INPUT
OUTPUT

Enable P or T inputs: Req = 1.4 kn NOM

Other inputs: Req = 2.8 kn NOM

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) 7V
Input voltage . . . . . . . . 5.5 V
Interemitter voltage (see Note 2) 5.5 V
Operating free-air temperature range: SN54S162, SN54S163 (see Note 10) -55°C to 125°C
SN74S162,SN74S163 oOe to 70°C
Storage temperature range -65°C to 150°C
recommended operating conditions

• Supply voltage, VCC

High-level output current, IOH
Low·level output current, IOL
Clock frequency, fclock'
Width of clock pulse, tw(clock) (high or low)
Width of clear pulse, twklearl
SN54S162, SN54S163
MIN
4.5

0
10
10
NOM
5
MAX
5.5
-1
20
40
i
i
SN74S162, SN74S163
MIN
4.75

-- 0
10
10
NOM
5
MAX
5.25
-1
20 I mA
40
UNIT

mA

i MHz
1

i
V

ns
ns
Dauinput~A,B,C,D 4 4
Enable P or T 12 12 i

I Setup time, tsu (see Figure 4)

i Load
I
14
I
14
i ns
Clear 14 14
Load inactive-state 12 12
Clear inactive-state 12 12
Release time, trelease (see Figure 4) Enable P or T 4 4 ns
Data inputs A, B, C, 0 3 3
Hold time, th (see Figure 4) Load 0 0 ns
Clear 0 0
Operating free-air temperature, T A .(see Note 10) -55 125 0 70 "c
NOTES: 1. Voltage values, except interemitter voltage, are with respect to network ground terminal.
2. This is the voltage between two emitters of a multiple-emitter transistor. For these circuits, this rating applies between th~e count
enable inputs P and T.
10, An SN54S162 or SN54S163 in the W package operating at free·air temperatures above 91°C requires a heat sink that provides a
thermal resistance from case to free-air, ReCA, of not more than 26°C/W.

1076

7-200 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54S162, SN54S163, SN14S162, SN14S163
SYNCHRONOUS 4-811 COUNTERS

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54S162 SN74S162
PARAMETER TEST CONDITIONSt SN54S163 SN74S163 UNIT
MIN TYP:j: MAX MIN TYP:j: MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
VIK Input clamp voltage Vee; MIN, II; -18mA -1.2 -1.2 V
Vee; MIN, VIH;2V,
VOH High-level output voltage 2.5 3.4 2.7 3.4 V
VIL; 0.8 V, 10H; -1 mA
Vec; MIN, VIH; 2 V,
VOL Low-level output voltage 0.5 0.5 V
VIL; 0.8 V, 10L; 20mA
II Input current at maximum input voltage Vee; MAX, VI; 5.5 V 1 1 mA
Enable T 100 100
IIH High-level input current Vee; MAX, VI; 2.7 V }lA
Othei inputs 50 50
Enable T -4 -4
IlL Low-level input current Vee; MAX, VI; 0.5 V mA
Other inputs -2 -2
lOS Short-circuit output current§ Vee; MAX -40 -100 -40 -100 mA
,
I,..,..
VV'
Iv N:lrrAnt
Su pp, --.. - .. - V,..,..; MAX 95 160 95 160 rnA
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAli typical values are at V CC = 5 V, T A = 25"C.
§ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.

switching characteristics, Vee = 5 V, T A = 25° C

FROM TO
PARAMETER~ TEST CONDITIONS MIN TYP MAX UNIT
(INPUT) (OUTPUT)
f max 40 70 MHz
tPLH Hippie 14 25
Clock ns
tpHL carry eL;15pF, 17 25

•
tPLH RL; 280 n, 8 15
Clock Any Q ns
tpHL See Figures 1, 3, and 4 and 10 15
tPLH Ripple Note 5 10 15
Enable T ns
tPHL carry 10 15

~fmax ==maximum clock frequency

tpLH ==propagation delay time, low·to·high·level output
tpH L == propagation delay time, high·to·low·level output
NOTE 5: Load circuit is shown on page 3-10.

1076

TEXAS INCORPORATED
INSTRUMENTS 7-201
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54160 THRU SN54163, SN54LS160A,THRU SN54LS163A
SN54S162, SN54S163, SN74160 THRU SN74163, ,
SN74LS160A THRU SN74LS163A, SN74S162, SN74S163
SYNCHRONOUS 4-81T COUNTERS
PARAMETER MEASUREMENT INFORMATION

I-tW(CIOCk) ...I
I I
I 3V
CLOCK
INPUT
- - - - - ov
I...-.....I-tPLH I.---..t- tpH L
I (measure at t n+1) I ,(measure at t n+2)

1
I

OUTPUT
°A ___ ';"",J Vref
I

~tPHL
~5""'----.J/ I
~tPLH
I I (measure at t n +4) I I (measure at t n +2)
I I

~,s. . __:........l~ref___ _
VOH
OUTPUT
Os
- - - VOL

I....---..L- tpHL II .1 tPLH

I : (measure at t n+8) I (measure at t n +4)

ou~uT-----------";"'--I.~s\-_ _.;...~lv~f ___ _ - - - VOL

I

•
1ooI1.f--_.....I-tPHL Ajl---+-I-tPLH
(measure at t n +10 (measure at t n +8)
I or t n+16) I
I

'~"S____--JlV~f ______
'\.. v(::e Note S) VOH
OUTPUT
°D VOL

~tPLH ~11~--t_I-tPHL
I I (measure at t n+10

I
I I or t n+16) (See Note S)
I

\S-\os---------------------------- ~:~
RIPPLE
CARRY_ _ _ _ _..J Vref
OUTPUT ,

VOLTAGE WAVEFORMS

NOTES: A. The input pulses are supplied by a generator having the following characteristics: PRR .;; 1 MHz, duty cycle';; 50%, Zout ,., 50 n;
for '160 thru '163, tr .;; 10 ns, tf .;; 10 ns; for' LS160A thru', LS163A,t r .;; 15 ns, tf .;; 6 ns; and for 'S162, 'S163, tr " 2.5 ns,
tf .;; 2.5 ns. Vary PRR to measure f max .
B. Outputs QD and carry are tested at t n +10 for'160,'162,'LS160A.'LS162A,and'S162, and at t n +16 for '161, '163,'LS161/\
'LS163A, and 'S163, where tn is the bit time when all outputs are low.
C. For '160'thru '163, 'S162, and 'S163, Vref = 1.5 V; for 'LS160A thru 'LS163A, Vref = 1.3 V.

FIGURE 1-SWITCHING TIMES

1076

7·202 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54160 THRU_ SN54163, SN54LS16QA THRU SN54LS163A,
SN74160 THRU SN74163, SN74LS160A TH-RU SN74LS163A
SYNCHRONOUS 4-81T COUNTERS

CLOCK INPUT ------------------------

'160, 'LS160A
'161, 'LS161A
PARAMETER MEASUREMENT INFORMATION
\
1 V ref
f ~-------------------------------
, Vref
3V

1 ----------------- OV
,-tW(CIOCk)-I
1
3V
CLEAR
INPUT
~v: ______ j _____________ __
__________________________
4-tw (clear).,.J ~I I
1 1_ t su -.I,
OV

3V
LOAD
INPUT
~~re~ ____________ __ OV
I I...- tsu - :

~:---------------
3V
DATA INPUTS
A, B, C, and D

-------~;-t-PH-L--~--------------~ _I tPLH j..::- v v

~~i:~~VTPVTS [ ~~v_re_f ~ ~i~J~~v-r~-f--_--_--_---

VOH

__________ ________ _--_---_--

_ __
--__- -__ --_--==
__
VOL
~ tpHL I...- ~ tPLH (measure at tn+2 or t n +4)

\vm : ,~~~~~~~--~-----~~~
VOH
QB and QC OUTPUTS
'160, 'LS160A

VOL
3V
ENABLE P or
ENABLE T
~~:----

•
OV
tPLH+---t .:--t--tPHL

RIPPLE ~-\~~-- VOH

______~--------_--------....:.--------------------_----_T ~
CARRY
OUTPUT
Vref
1
1- tsu -I 1 3V

~~~:~:f[\~_____Jf,vref \vm tl~': ___ h _ _ _ _ _ _ _ _ _ OV

-l tPH L I+-
I 1
'--
- , tPLH : - _ - - - - - - - - - - - - - - - - - - - - - - - - - - -
QOUTPUTS
'163, 'LS163A
QA and QD OUTPUTS
'162, 'LS162A
I ' \V
nIT

-l tpHL :-'--------~::-.~.I -
i lvref t-;L~(;;a;;;re-;;t~+~r~+~ - - - - VOL

QB and QC OUTPUTS
'162, 'LS162A
\vnn VOLTAGE WAVEFORMS
I~:-_-_-_-_-_ ~ ~ ===~ :::
NOTES: A. The input pulses are supplied by generators having the foik,~ing ch~racteristics: P R R .;; 1 M Hz, duty cycle';; 50%, Zout '" 50 n;
for '160 thru '163, tr';; 10 ns, tf';; 10 ns; and for 'LS160A thru 'LS163A, tr .;; 15 ns, tf .;; 6 ns.
B. Enable P and enable T setup times are meas~"'ed at tn+O'
C. For '160thru '163, Vref = 1.5 V; for 'LS160A thru 'LS163A, Vref = 1.3 V.

FIGURE 2-SWITCHING TIMES

1076

TEXAS INCORPORATED
INSTRUMENTS 7-203
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54S162, SN54S163, SN74S162, SN74S163
SYNCHRONOUS 4-81T COUNTERS

PARAMETER MEASUREMENT INFORMATION

~~:---------::
ENABLE T
INPUT

-i I
~
SV

t PLH ----:
I
I-- tpHL--I
I
I
\~---VOH
CARRY
OUTPUT ________________ J~SV \".---",;,,-VOL
VOL TAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: tr';;; 2.5 ns, tf';;; 2.5 ns, PRR ,;;; 1 MHz, duty
cycle';;; 50%, Zout '" 50 n.
B. tpLH and tpHL from enable T input to carry output assume that the counter is at the maximum count (QA and QD high for
'S162, all Q outputs high for 'S163).

FIGURE 3-PROPAGATION DELAY TIMES FROM ENABLE T INPUT TO CARRY OUTPUT

t-- tw(clock)
3V
I
I
CLOCK
INPUT
'--_ _....J: '--_ _ .....JI
r-- tsu -.! t--- tsu ~
I (active state) t.- th ~ (inactive state) I

CLEAR
INPUT
~,-1'_5V _____ ..J,t~v____ ~ ________ ~ ___ ::
• LOAD
INPUT
I-- tw(clear) ----+I :--
I
I

\'-.5_v___
t--
I
tsu
(active state)

tsu
~

--I
~
t-----:-
th ..I
I

l_....Jt~"- _____ J____

I.----I~th
...
tsu --:------l
(inactIve state)
I

I
I
3V

ov

I _______ J ____ 3V
-J~.SV
Dr'
DATAINPUTS_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
A, B, C, and \SV i ov
t---
I
tsu --1
~trelease
~5~--_3V
ENABLEPor
ENABLE T ____________________________________-J•

VOLTAGE WAVEFORMS
1: '.SV
_._______ 0 V

NOTE A: The input pulses are supplied by generators having the following characteristics: tr';; 2.5 ns, tf';; 2.5 ns, PRR ,;;; 1 MHz, duty
cycle';;; 50%, Zout '" 50 n.

FIGURE 4-PULSE WIDTHS, SETUP TIMES, HOLD TIMES, AND RELEASE TIME

1076

7·204 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 o
-..I
Ol

N-BIT SYNCHRONOUS COUNTERS

This application demonstrates how the look-ahead carry circuit can be used to implement a hi£lh-speed n-bit counter. The '160, '162,
'LS160A, 'LS162A, or 'S162 will count in BCD and the '161, '163, 'LS161A, 'LS163A or 'S163 will count in binary. Virtually any count
.....
-<
mode (modulo-N, Nl-to-N2, Nl-to-maximum) can be used with this fast look-ahead circuit. ."
m
U)
U)
iii!
U'I
U) ~
• 2
.....
~
-
en
c:::::t
~ INPUTS INPUTS INPUTS INPUTS
rr1 ~ ~ ~ r-~ -I
-<
~
_ .....
,:c
>< ""'C
enU):::a
> n c:::::t 2 :c
(J)
z_
»
r- :J>U'I
LD A B C D LD A B C D LD A B C D LD A B C D ~U)
8z H = COUNT
» ..... !!!2
~en
""C
L = DISABLE EN P EN P EN F' ""'C ::eenU'l
0o-i r- :::aN~
~;o
»
n c .. en
~c:: H = COUNT
RIPPLE RIPPLE RIPPLE RIPPLE -I
U)w
U)2,..
03: CARRY CARRY EN T CARRY EN T CARRY TO MORE- eZ 2 U'I'U)
OUTPUT OUTPUT OUTPUT OUTPUT
rr1
U)~t;2
SIGNIFICANT
Z STAGES 0 -<r--U'I
o-i
en CK CK CK CK ~ n-wr-
2U)en~
» ::een.. ,U)
CLR 0A 0B 0c 0D CLR 0A 0B 0c 0D CLR 0A 0B 0c 0D :::aW,"A-

r
[ __ CLR QA Qs Qc QD ':J> V" en
C!
2 .. 2c:::::t
..... _
C ~­
CLEAR c:2- .....
U) ..... en:c
~c:::::t

J__ ~ 1
'---v-----' ~ ~,U) :::a
'---v-----' I , _ I ..... C
OUTPUTS OUTPUTS OUTPUTS caen:c
CLOCK
=i N::::a U)
n" C2
U) U'I
C2U)~
C ..... 2r-
2~""'U)
~!!!~'m
:::aen enw
U)W;~'l>
.....

•
N
CI
U"I
 TTL TYPES SN54164. SN54L164. SN54LS164. SN74164. SN74L164. SN74LS164
MSI 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
BULLETIN NO. DL-S 7611835, MARCH 1974-REVISED OCTOBER 1976

• Gated (Enable/Disable) Serial Inputs SN54164, SN54LS164 .•. J OR W PACKAGE

• Fully Buffered Clock and Serial Inputs SN54L 164, SN74L 164 .•• J, N, OR T PACKAGE
SN74164, SN74LS164 .•• J OR N PACKAGE
• Asynchronous Clear (TOP VIEW)
OUTPUTS
TYPICAL
TYPICAL VCC ~CLEARCLOCK
TYPE MAXIMUM
POWER DISSIPATION
CLOCK FREQUENCY
'164 36MHz 21 mW per bit
CLEAR
'L164 18MHz 11 mW per bit
'LS164 36MHz 10 mW per bit A CK
description
These 8-bit shift registers feature gated serial. inputs
and an asynchronous clear. The gated serial inputs (A
and B) permit complete control over incoming data as
a low at either (or both) input(s) inhibits entry of the
new data and resets the first flip-flop to the low level
at the next clock pulse. A high-level input enables the positive logic: see function table
other input which will then determine the state of the
first flip-flop. Data at the serial inputs may be changed while the clock is high or low, but only information meeting the
setup requirements will be entered. Clocking occurs on the low-to-high-Ievel transition of the clock input. All inputs are
diode-clamped to minimize transmission-line effects.
Series 54, 54 L, and 54LS devices are characterized for operation over the full military temperature range of -55°C to
125°C; Series 74, 74L, and 74LS devices are characterized for operation from O°C to 70°C.

FUNCTION TABLE
INPUTS OUTPUTS
CLEAR CLOCK A B QA QB '" QH H = high level (steady state). L = low level (steady state)
L X X X L L L X = irrelevant (any input, including transitions)

•
H L X X t = transition from low to high level.
QAO QBO QHO
0AO. 0BO. 0HO = the level of 0A, 0B. or 0H, respectively, before the indicated
H t H H H QAn DGn steady-state input conditions were established.
H t L X L QAn DGn 0An. 0Gn = the level of OA or 0G before the most-recent t transition of the
clock; indicates a one-bit shift.
H t X L L QAn DGn

schematics of inputs and outputs

'164, 'L 164 'LS164

EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS

--+---Vcc VCC----- - - - -.......--VCC

Req
VCC1 3--
Req.

INPUT -- I NPUT-..,....-+-_

"----<~-OUTPUT
OUTPUT

'164: Req = 4 kn NOM

'L 164: Req = 8 kn NOM

'164: R = 200 n NOM Clear. clock: 17 kn NOM

'L 164: R = 400 n NOM Serial In: 25 kn NOM

1076

7-206 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54164, SN54L164, SN54LS164, SN74164, SN74L164, SN74LS164
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
REVISED OCTOBER 1976

typical clear, shift, and clear sequences

CLEAR'l..J
I
I
~
I

SERIAL {
INPUTS
A ~~------------~:------------
__':------...J
I
CLOCK I

QA===i ~~------~---------
---,
roc===-,-l
QB _ ~,~-------------~

-------1
~~----~---------
I
~
r--l ~I _ _~_ _ _- - - - -

J QD===.~J~ ________________________~ ~L...........:.._____________

OUTPUTS ~
QE ___ ---,
~'~ ___________________ ~
L...-....I
I
I n _ _ _ _ _ _ _ _ _ __
~I

I
QF ____ ---,I~ ______________________________ ~
I
I

QG __
---,~I~ _ _----------------------~ I

Q
H
---~l ___________________________~r_l~'_________

CLEAR
I
CLEAR

functional block diagram

CLEAR~----~ ~--~----~~-----.------~------.-----~~-----e------~
CLOCK~____~ ~~--~--~--+---e---~~~-4--~--~--~--+-~~~--,
•
(3) (4) 15) (61 110) 111) (12) (13)

OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT

°A Os Dc °D °E OF DG °H

1076

TEXAS INSTRUMENTS
INCORPORATED
7-207
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54164, SN74164
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, Vee (see Note 1) .... . 7V

Input voltage . . . . . . . . . . . . . 5.5V
Operating free-air temperature range: SN54164 -55°C to 125°C
SN74164 O°C to 70°C
Storage temperature range -65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54164 SN74164
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, VCC 4.5 5 5.5 4.75 5 5.25 V
High·level output current, 10H -400 -400 JlA
Low-level output current, 10L 8 8 mA
Clock frequency, fclock 0 25 0 25 MHz
Width of clock or clear input pulse, tw 20 20 ns
Data setup time, tsu (see Figure 1) 15 15 ns
Data hold time, th (see Figure 1) 5 5 ns
Operating free-air temperature, T A -55 125 0 70 °c

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54164 SN74164
PARAMETER TEST CONDITIONSt UNIT
MIN TYP:f: MAX MIN TYP:f: MAX
VIH High·level input voltage 2 2 V
VIL Low·level input voltage 0.8 0.8 V
VIK Input clamp voltage VCC= MIN, II = -12mA -1.5 -1.5 V
VCC- MIN, VIH=2V,
VOH High-level output voltage 2.4 3.2 2.4 3.2 V
VIL = 0.8 V, 10H = -400JlA

•
VCC- MIN, VIH - 2 V,
VOL Low-level output voltage 0.2 0.4 0.2 0.4 V
VIL = 0.8 V, 10L =8mA
II Input current at maximum input voltage VCC - MAX, VI-5.5V, 1 1 mA
IIH High-level input current VCC - MAX, VI = 2.4 V 40 40 JlA
IlL Low-level input current VCC - MAX, VI - 0.4 V -1.6 -1.6 mA
lOS Short-circuit output currentS VCC = MAX -10 -21.5 -9 -21.5 mA

Supply current
VCC - MAX, I Vl{clock) = 0.4 V 30 30
mA
ICC
See Note 2 IV I (clock) = 2.4 V 37 54 37 54

t For conditions shown at MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at Vee = 5 V, T A = 25°e.
§ Not more than two outputs should be shorted at a time.
NOTE 2: lee is measured with outputs open, serial inp,uts grounded, and a momentary ground, then 4.5 V, applied to clear.

switching characteristics, Vee = 5 V, TA = 25°e

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f max Maximum clock frequency CL = 15 pF 25 36 MHz
Propagation delay time, high-to-Iow-Ievel CL= 15pF 24 36
tpHL ns
Q outputs from clear input CL = 50 pF 28 42
RL=800n,
Propagation delay time, low-to-high-Ievel CL=15pF 8 11 21
tPLH See Figure 1 ns
Q outputs from clock input CL = 50 pF 10 20 30
Propagation delay time, high-to-Iow-Ievel CL= 15pF 10 21 32
tPHL ns
Q outputs from the clock input CL = 50 pF 10 25 37

1076

7-208 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54L164, SN74L164
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, Vee (see Note 1) ..... . 7V

Input voltage . . . . . . . . . . . . . . 5.5V
Operating free-air temperature range: SN54L 164 -55°C to 125°C
SN74L164 oOe to 70°C
Storage temperature range -65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54L164 SN74L164
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, V CC 4.5 5 5.5 4.75 5 5.25 V
Higi1-ievei output current, iOH -200 -200 ILA
Low-level output current, 10L 4 4 rnA
Clock frequency, fclock 0 12 0 12 MHz
Width of clock or clear input pulse, tw 40 40 ns
?n
Data setup tim2, tsu {see Figure 1} 30 iiS

Data hold time, th (see Figure 1) 10 10 ns

Operating free-air temperature, T A -55 125 0 70 °c

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54L164 SN74L164
PARAMETER TEST CONDITIONSt UNIT
MIN TYP:j: MAX MIN TYP:j: MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
V:K lop!,!! clamp voltage VCC- MIN, Ii --12mA -1.5 -1.5 V
VCC- MIN, VIH=2V,
VOH High-level output voltage 2.4 3.2 2.4 3.2 V
VIL = 0.8 V, 10H = -200 ILA,

•
VCC- MIN, VIH = 2V,
VOL Low-level output voltage 0.2 0.4 0.2 0.4 V
VIL = 0.8 V, 10L =4 rnA
II Input current at maximum input voltage VCC = MAX, VI = 5.5 V 1 1 rnA
IIH High-level input current VCC- MAX, VI-2.4 V 20 20 ILA
IlL Low-level input current VCC= MAX, VI = 0.4 V -0.8 -0.8 rnA
lOS Short-circuit output current§ VCC= MAX -5 -20 -4 -20 rnA
ICC Supply current VCC- MAX, See Note 3 19 27 19 27 rnA

tFor conditions shown at MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at Vee = 5 V, T A = 25°C
§Not more than two outputs should be shorted at a time.
NOTE 3: ICC is measured with outputs open, serial inputs grounded, the clock input at 2.4 V, and a momentary ground, then 4.5 V, applied to
clear.

switching characteristics, Vee = 5 V, T A = 25° C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f max Maximum clock frequency CL = 15pF 12 18 MHz
Propagation delay time, high-to-Iow-Ievel CL=15pF 48 72
ns
tpH L Q outputs fr~m clear input CL = 50 pF 56 84
RL=800n,
Propagation delay time, low-to-high-Ievel CL = 15pF 8 34 54
tPLH See Figure 1 ns
Q outputs from clock input CL - 50 pF 10 20 60
Propagation delay time, high-to-Iow-Ievel CL = 15 pF 10 42 64
ns
tpHL Q outputs from the clock input CL = 50 pF 10 50 74

1076

TEXAS INSTRUMENTS 7-209

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54LS164, SN74LS164
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
REVISED OCTOBER 1976

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, Vee (see Note 1) ..... . 7V

Input voltage . . . . . . . . . . . . . . 7V
Operating free-air temperature range: SN54LS164 -55°C to 125°C
SN74LS164 oOe to 70°C
Storag~ temperature range -65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54LSl64 SN74LS164
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, VCC 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -400 -400 p.A
Low-level output current, 10L 4 S mA
Clock frequency, fclock 0 25 0 25 MHz
Width of clock or clear input pulse, tw 20 20 ns
Data setup time, tsu (see Figure 1) 15 15 ns
Data hold time, th (see Figure 1) 5 5 ns
Operating free-air temperature, T A -55 125 0 70 °c

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS164 SN74LS164
PARAMETER TEST CONDITIONSt UNIT
MIN TYP+ MAX MIN TYP+ MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 O.S V
VIK Input clamp voltage VCC = MIN, 11=-lSmA -1.5 -1.5 V
VCC- MIN, VIH - 2 V,
VOH High-level output voltage 2.5 3.5 2.7 3.5 V

•
VIL = VIL max, 10H = -400 p.A
VCC - MIN, VIH = 2 V, IIOL - 4mA 0.25 0.4 0.25 0.4
VOL Low-level output voltage V
VIL = VIL max IIOL = SmA 0.35 0.5
Input current at
II VCC = MAX, VI = 7 V 0.1 0.1 mA
maximum input voltage
I!H High-level input current Vee = MAX, V! = 2.7 V 20, 20, p.A
IlL Low-level input current VCC - MAX, VI- 0.4 V -0.4 -0.4 mA
lOS Short-circuit output current § VCC = MAX -20 -100 -20 -100 mA
ICC Supply current VCC= MAX, See Note 3 16 27 16 27 mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at VCC = 5 V, T A = 25°C.
§ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
NOTE 3: ICC is measured with outputs open, serial inputs grounded, the clock input at 2.4 V, and a momentary ground, then 4.5 V applied
to clear.
switching characteristics, Vee = 5 V, T A = 25°e
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f max Maximum clock frequency 25 36 MHz
tpHL Propagation delay time, high-to-Iow-Ievel Q outputs from clear input CL=15pF, RL=2k!1, 24 36 ns
tPLH Propagation delay time, !ow-to-high-!evel Q outputs from clock input See Figure 1 17 27 ns
tpHL Propagation delay time, high-to-Iow-Ievel Q outputs from clock input 21 32 ns

1076
TEXAS INCORPORATED
INSTRUMENTS
7-210
POST OFFICE BOX 5012 • DAL.LAS. TEXAS 75222
 TYPES SN54164, SN54L164, SN54LS164, SN74164, SN74L164, SN74LS164
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS

PARAMETER MEASUREMENT INFORMATION

AANDB
VCC OUTPUT
PULSE
GENERATOR

A QA
B QB

CLOCK
Dc
QD
PULSE CLOCK QE
GENERATOR QF
DG
QH

CLEAR
PULSE
GENERATOR

TEST CIRCUIT

f
j..- tw(clear) ---I
PULSE
mAR
GENERATOR
~
(PRR .;; 1 MHz) I
V
ref
V
ref

------- ----------oV
i.--lw(Clock) -.I
I I
CLOCK
I I
PULSE
I I
Vref
GENERATOR
I

•
(PRR.;; 1 MHz) I
I '--___"'·_1 ____ ov

---~II
~rth --4 r- th
~I 3V
SERIAL INPUTS
AAND BPULSE II I I
Vref I
GENERATOR I
(PRR.;; MHz)

--t
1
'-___ .....,J~--_- 0 V

---eof tpLH ~tPHLI-­

r--~i:Jf------""""'~ VOH
QA OUTPUT
(See Note D)

VOL

VOLTAGE WAVEFORMS

NOTES: A. The pulse generators have the following characteristics: duty cycle';;; 50%, ZOtJt '" 50 n; for '164 and 'L164, tr';;; 10 ns,
tf .;;; 10 ns, and for' LS164, tr .;;; 15 ns, tf .;;; 6 ns.
B. CL includes probe and jig capacitance.
C. A"diodesare1N30640r1N916.
D. Q A output is illustrated. Relationship of serial input A and B data to other Q outputs is illustrated in the typical shift sequence.
E. Outputs are set to the high level prior to the measurement of tpH L from the clear input.
F. For '164 and 'L 164, Vref = 1.5 V; for 'LS164, Vref = 1.3 V.

FIGURE 1-SWITCHING TIMES

1076

TEXAS INCORPORATED
INSTRUMENTS 7-211
POST OFFICE SOX 5012 • DALLAS. TEXAS 75222
 TTL TYPES SN54165, SN54LS165, SN74165, SN74LS165
MSI PARALLEL-LOAD 8-BIT SHIFT REGISTERS
BULLETIN NO. DL-S 1375, OCTOBER 1976

SN54165, SN54LS165 .•. J OR W PACKAGE

• Complementary Outputs
SN74165, SN74LS165 ... J OR N PACKAGE
• Direct Overriding Load (Data) Inputs (TOP VIEW)
CLOCK A ALLEL INPUTS SERIALOUTPUT
• Gated Clock Inputs Vcc INHIBIT ~ INPUT ClH

• Parallel-to-Serial Data Conversion

TYPICAL MAXIMUM TYPICAL

TYPE CLOCK FREQUENCY POWER DISSIPATION

'165 26 MHz 210mW

'LS165 35MHz 105mW

description
The '165 and 'LS165 are 8-bit serial shift registers
that shift the data in the direction of QA toward positive logic: see description
QH when clocked. Parallel-in access to each stage is
made available by eight individual direct data inputs
that are enabled by a low level at the shift/load
input. These registers also feature gated clock inputs
and complementary outputs from the eighth bit. All
inputs a re diode-clamped to minimize
transmission-line effects, thereby simplifying system
design.

Clocking is accomplished through a 2-input positive-NOR gate, permitting one input to be used as a clock-inhibit
function. Holding either of the clock inputs high inhibits clocking and holding either clock input low with the
shift/load input high enables the other clock input. The clock-inhibit input should be changed to the high revel only
while the clock input is high. Parallel loading is inhibited as long as the shift/load input is high. Data at the parallel
inputs are loaded directly iilto the register on a high-to-Iow transition of the shift/load input independently of the levels
of the clock, clock inhibit, or serial inputs.

II FUNCTION TABLE
INPUTS

I SHIFT! !CLOCK! CLOCK! SERIAL PARALLEL

INTERNAL
OUTPUTS
OUTPUT I
LOAD INHIBIT GH '
A ..• H QA QB
L X X X a ... h a b h
H L L X X GAO QBO QHO
H L t H X H QAn QGn
H L t L X L QAn QGn
H H X X X GAO QBO QHO
See explanation of function tables on page 3-8.

schematic of inputs and output

'165
EQUIVALENT OF EACH INPUT TYPICAL OF BOTH OUTPl,ITS

-}VCC
VCC '- 'LS165
EQUIVALENT OF EACH INPUT TYPICAL OF BOTH OUTPUTS

VCC3--
Q
100 !l. Req
Req NOM INPUT --

INPUT --
OUTPUT

_ OUTPUT
Clock, clock inhibit: Req = 17 k!l. NOM
Parallel inputs,
Shiftiload: Req = 3 kn NOM serial input: Req = 24 kS1 NOM
Other inputs; Req "" 6 kn NOM
,J,
Shift/load: Req = 5.7 k!l. NOM

1076
7·212 TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54165, SN54LS165, SN74165, SN74LS165
PARALLEL-LOAD 8-BIT SHIFT REGISTERS

functional block diagram

________________________ INPUTS
________________________

~
~
A
~
~
(9) OUTPUT
OH

(7) OUTPUT
a..

C:IOCK 1151
INHIBIT ------L...-/

typical shift, load, and inhibit sequences

SHIFT/LOAD ~

r -------.IT:l
A

c
I
:
-----K:l
I
L ~----+----------------------------------

~----~-----------------------------------
L

•
,I
E ----.If:l~----~-----------------------------------
I L
I
I
G----.lf:l~ ____~____________________________
,
H~~_ _~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ _
I
OUTPUTO H

OUTPUTOH

I-
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, Vee (see Note 1) 7V

Input voltage: SN54165, SN74165 5.5 V
SN54LS165, SN74LS165 . 7V
Interemitter voltage (see Note 2) 5.5 V
Operating free-air temperature range: SN54165, SN54LS165 . -55°C to 125°e
SN74165,SN74LS165 aOe to 7aoe
Storage temperature range . -65°e to 15aoe
NOTES: 1. Voltage values, except interemitter voltage, are with respect to network ground terminal.
2. This is the voltage between two emitters of a multiple-emitter transistor. This rating applies tor the '165 to the shift/load inpu"[ ,n
conjunction with the clock-inhibit inputs.

1076

TEXAS INCORPORATED
INSTRUMENTS 7-213
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54165, SN74165
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
recommended operating conditions
SN54165 SN74165
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, VCC 4.5 5 5.5 4.75 5 5.25 V
High-level output current, IOH -800 -800 !J.A
Low-level output current, IOL 16 16 mA
Clock frequency, fclock 0 20 0 20 MHz
Width of clock input pulse, tw(clock) 25 25 ns
Width of load input pulse, tw(load) 15 15 ns
Clock-enable setup time, tsu (see Figure 1) 30 30 ns
Parallel input setup time, tsu (see Figure 1) 10 10 ns
Serial input setup time, tsu (see Figure 2) 20 20 ns
Shift setup time, tsu (see Figure 2) 45 45 ns
Hold time at any input, th 0 0 'ns
Operating free-air temperature, T A -55 125 0 70 °c

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54165 SN74165
PARAMETER TEST CONDITIONSt UNIT
MIN TYPj MAX MIN TYPt MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 I V
VIK Input clamp voltage VCC = MIN, 11=-12mA -1.5 -1.5 V
VCC = MIN, VIH - 2V,
VOH High-level output voltage 2.4 3.4 2.4 3.4 V
VIL = 0.8 V, 10H = -800!J. A
VCC - MIN, VIH - 2V,
VOL Low-level output voltage 0.2 0.4 0.2 0.4 V
VIL = 0.8 V, 10L = 16 mA
II Input current at maximum input voltage VCC - MAX, VI- 5.5 V 1 1 mA
Shift/load 80 80
IIH High-level input current VCC = MAX, VI = 2.4 V !J.A
Other inputs 40 40
Shift/load -3.2 -3.2

•
IlL Low-level input current VCC = MAX, VI = 0.4 V mA
Other inputs -1.6 -1.6
lOS Short-circuit output current ~ VCC = MAX -20 -55 -18 -55 mA
ICC Supply current VCC = MAX, See Note 3 42 63 42 63 mA
NOTE 3: With the outputs open, clock inhibit and clock at 4.5 V, and a clock pulse applied to the shift/load input, ICC is measured first
with the parallel inputs at 4.5 V, then with the parallel inputs grounded.
t Fer conditions shewn as M!N or I\/IA X, use the appropnate value specified under recommended operating conditions.
+AJI typical values are at Vee = 5 V, T A = 25°C.
§ Not more than one output should be shorted at a time.

switching characteristics, Vee = 5 V, T A = 25°e

PARAMETER~
FROM
(INPUT) I TO
(OUTPUT) i TEST CONDITIONS MIN TYP MAX! UNIT I
f max 20 26 MHz
tPLH 21 31
Load Any ns
tPHL 27 40
tPLH 16 24
Clock Any CL=15pF,RL=400n, ns
tpHL 21 31
See figures 1 thru 3
tpLH 11 17
H QH ns
tPHL 24 36
tPLH 18 27
H OH ns
tPHL 18 27

~fmax == maximum cioc"k frequency

tpLH "" propagation delay time, low-to-high-Ievel output
tp H L "" propagation delay time, h igh-to·low-Ievel output

1076

7-214 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54LS165, SN14LS165
PARALLEL-LOAD 8-BIT SHIFT REGISTERS

recommended operating conditions

SN54LS165 SN74LS165
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, VCC 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -400 -400 J.LA
Low-level output current, 10L 4 8 mA
Clock frequency, fclock 0 25 0 25 MHz
Width of clock input pulse, tw(clock) 25 25 ns
Width of load input pulse, tw(ioad) 15 15 ns
Clock-enable setup time, tsu .(see Figure 1 ) 30 30 ns
Parallel input setup time, tsu (see Figure 1) 10 10 ns
Serial input setup time, tsu (see Figure 2) 20 20 ns
Shift setup time, tsu (see Figure 2) 45 45 ns
Hold time at any input, th 0 0 ns
Operating free-air temperature, T A -55 125 0 70 °c

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
I PARAMETER
I TEST CONDITIONSt
I SN54LS165 I SN74LS165
II!,\!!T
MIN TYPt MAX MIN TYP+ MAX
V!H High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
VIK Input clamp voltage VCC: MIN, II :-18 mA -1.5 -1.5 V
VCC: MIN, VIH: 2 V,
VOH High-level output voltage 2.5 3.5 2.7 3.5 V
VIL : VI Lrnax, 10H :-400J.LA
Vcc: MIN,
VOL Low-level output voltage VIH: 2 V, I IOL:4mA 0.25 0.4 0.25 0.4 V

IOL:8 mA 0.35 0.5

VIL : VILmax,1
Input current at Shift/load 0.3 0.3
II Vee: MAX, VI =7 V mA
maximum input voltage Other inputs 0.1 0.1
Shift/load 60 60
IIH Low-level input current VCC: MAX, VI: 2.7 V J.LA
Other inputs 20 20

•
Shift/load -1.2 -12
IlL Low-level input current VCC = MAX, VI=O.4V rnA
Other inputs -0.4 -0.4
lOS Short-circuit output current§. Vce= MAX -20 -100 -20 -100 rnA
lee Supply current Vee: MAX, See Note 3 21 36 21 36 rnA

NOTE 3: With the outputs open, clock inhibit and clock at 4.5 V, and a clock pulse applied to the shift/load input, lee is measured first
with the parallel inputs at 4.5 V, then with the parallel inputs grounded.
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at Vee = 5 V, T A: 25°C.
§ Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.

switching characteristics, Vee = 5 V, T A = 25°e

FROM TO
PARAMETER~ TEST CONDITIONS MIN TYP MAX UNIT
(INPUT) (OUTPUT)
f max 25 35 MHz
tPLH 22 35
Load Any ns
tPHL 22 35
tPLH 27 40
Clock Any eL = 15 pF, RL : 2 kn, ns
tPHL 28 40
See figures 1 thru 3
tPLH 14 25
H QH ns
tPHL 21 30
tPLH 21 30
H OH ns
tPHL 16 25
~fmax == maximum clock frequency
tp LH == propagation delay time, low-to-high-Ievel output
tpH L == propagation delay time, high-to-Iow-Ievel output

1076

TEXAS INSTRUMENTS 7-215

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 ..... II
~
en
-a.-t

--------~
CLOCK INHIBIT :I>-C
INPUT
=-a
:l>m
r-
r-
en
3V
CLOCK men
INPUT Vref Vref r;-"Z
' - - _ _ _ _ _ _ _ _-.J, I I '--------'-I- -- - -- 0 V r-U'I
tsu ---+I ,.t W (CIOCk)"'1 I C)~
:1> _
I -I - - - - - - "I - - - -- 3 V
aen
1
_ _ _ _ _..:.I_ _ _-.-J
1
I
1
1 0 v co.?"
1 1 men
I
3V
=iz
SHIFT/
I V~ enU'l
LOAD 1
"
» =~
_ r-

"'""'i
[TI
><
OUTPUT
QH
"HL~
..,..-_ _ _ _..J

: - 1-
iJtH Vref
I
R,"HL
I \Vref
1
"LHrJt
I T Vref
---1----
:-r:'HL
I ,Vref
t----OV

"LH~VOH
: r Vref
:::0
»
S
m
-i
m
~~
=U'I
m ..
en
;l>
(J) tPLH~ ~tpHL tPLH--l.--.! ~tPHL tPLH-I.....t /4-+l--;-p::-- VOL
:::0
S
G')en
-z
~\1 I I 1 en .....
~Jvref ~V
z_ • ---VOH m
8z
OUTPUT
» -t~
m_
GlH - - - - . T V ref \Vref lVref en
~(J)
0"'; NOTES: A. The remaining six data inputs and the serial input are low. OL
C =en
en'U'I
:::0
~;o B. Prior to test, high-level data is load'~d into H input. m
S en
~c: C. The input pulse generators have tho following characteristics; PRR';; 1 MHz, duty cycle';; 50% Zout "" 50 fl.; for "165, tr';; 10 ns, tf';; 10 ns;
m z
03:: for 'LS165, tr';; 15 ns, tf';; 6 ns.
D. For '165, Vref = 1.5 V; for 'LS165, Vref = 1.3 V. FIGURE l-VOL TAGE WAVEFORMS
Z
-i
.....
~

-
[TI i r-
z
...; ~-----------------------.---------------------------- 3V
Z
"T1 en
(J)
SHIFT/
TEST
o en
LOAD :::0 U'I
POINT VCC
- - - -.---- ---- -OV S
»
-i
SERIAL
INPUT
RL
o
Z
0~~~RO~;:-iJT • III' . . . . ..

CLOCK
INPUT

NOTES:
\'----,
att n +7'
B. The input pulse generators have the following characteristics: PRR .;; 1 MHz, duty cycle';; 50%, NOTES: A. CL includes probe and jig capacitance.
Zout '" 50 fl.; for '165, tr';; 10 ns, tf';; 10 ns; for 'LS165, tr';; 15 ns, tf';; 6 ns. B. All diodes are IN3064.

C. For '165, Vref = 1.5 V; for 'LS165, Vref = 1.3 V. FIGURE 3-LOAD CIRCUIT FOR
FIGURE 2-VOLTAGE WAVEFORMS SWITCHING TESTS

e
0\
 TTL TYPES SN54166, SN54LS166, SN74166, SN74LS166
MSI 8-BIT SHIFT REGISTERS
BULLETIN NO. DL·S 7611808, OCTOBER 1976

SN54166, SN54LS166 ... J OR W PACKAGE

• Synchronous Load
SN74166, SN74LS166 ... J OR N PACKAGE
• Direct Overriding Clear (TOP VIEW)

• Parallel to Serial Conversion

PARALLEL PARALLEL INPUTS
TYPICAL SHIFT/ INPUT OUTPUT ~
TYPICAL MAXIMUM Vee LOAD H QH G F E CLEAR
TYPE CLOCK FREQUENCY POWER DISSIPATION

'166 35 MHz 360mW

'LS166 35 MHz 110mW

functional block diagram

SERiAL-A- --B- --e- [)ClOCK CLOCK '"G"N5'

INPUT - - . - . - - INHIBIT
?ARALLEL iNPUTS

positive logic: see description

description

The '166 and 'LS166 8-bit shift registers are

compatible with most other TTL and DTL logic
families. All '166 and 'LS166 inputs are buffered to
iower the drive requirements to one Series 54/74 or
Series 54LS/74LS standard load, respectively. Input
clamping diodes minimize switching transients and
simplify system design.

These parallel-in or serial-in, serial-out shift registers

have a complexity of 77 equivalent gates on a
I
monolithic chip. They feature gated clock inputs and
an overriding clear input. The parallel·in or serial-in
modes are established by the shift/load input. When
high, this input enables the serial data input and
couples the eight flip-flops for serial shifting with
each clock pulse. When low, the parallel (broadside)
data inputs are enabled and synchronous loading
occurs on the next clock pulse. During parallel
loading, serial data flow is inhibited. Clocking is
accomplished on the low·to-high-Ievel edge of the
clock pulse through a two-input positive NOR gate
permitting one input to be used as a clock-enable or
clock-inhibit function. Holding either of the clock
inputs high inhibits clocking; holding either low
enables the other clock input. This, of course, allows
the system clock to be free-running and the register
can be stopped on command with the other clock
input. The clock·inhibit input should be changed to
the high level only while the clock input is high. A
buffered, direct clear input overrides all other inputs,
~ . . . dynamic input activated by transition from a high level to a low level. including the clock, and sets all flip-flops to zero.

1076

TEXAS INSTRUMENTS 7-217

INCORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54166, SN54LS166, SN14166, SN14LS166
8-BIT SHIFT REGISTERS

typical clear, shift, load, inhibit, and shift sequences

CLOCK

CLOCKINHIBIT~~__~________________________~____~~L~__________________________
I I I
CLEAR~I
I I
SERIAL INPUT ~L-____________________~______~____~~__________________________
I I I
SHIFT/LOAD--~I--~------------------------~---.~r----------------------------------
,
A __~~________________________~__~~L______-7__________________________
,
L,
I
C __~~________________________~__~~L____~-7__________________________

PARALLEL
D__ ________________________ ______ ,________ _________________________
~~ ~ ~L~: ~

INPUTS
____~________________________~__~~L----~~--------------------------
I
L,

G____~________________________~__~~L----~~--------------------------
H __ ~~ ________________________ ~~ ___
I
OUTPUT QH ==:::'."_~________________________---'
1 - - - - - - - SE RIAL SH I FT ----------------1
CLEAR LOAD

FUNCTION TABLE

INPUTS INTERNAL
OUTPUT
SHIFTI CLOCK PARALLEL OUTPUTS
CLEAR CLOCK SERIAL QH
LOAD INHIBIT A ••• H QA QB
L X X X X X L L L

I H
H
H
X
L
H
L
L
L
L
t
t H
X
X
X
a ... h
X
QAO
a
H
QBO
b
QAn
QHO
h
QGn
H H L t L X L QAn, QGn
H X H X X

See explanation of function tables on page 3-8.

schematics of inputs and outputs

'166 'LS166

EQUIVALENT OF EACH INPUT OUTPUT EQUIVALENT OF EACH INPUT OUTPUT

Vee -----.---
Req

Parallel and
serial inputs: Req = 24 kn NOM
Others: Req = 17 kn NOM

1076

7-218 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54166, SN74166
8-BIT SHIFT REGISTERS

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, Vee (see Note 1) ..... 7V

Input voltage . .. . . . . . . . . . . . 5.5 V
Operating free-air temperature range: SN54166 -55°C to 125°C
SN74166 aOe to 7aoe
Storage temperature range -65°C to 15aoe
NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54166 SN74166
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, V CC 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -800 -soo JLA
Low-level output current, IOL 16 16 mA
Clock frequency, fclock 0 25 0 25 MHz
Width of clock or clear pulse, tw (see Figure 1) 20 20 ns
30 30 ns
uala sewp lime, ISU \see t"lgure II. 20 20
Hold time at any input, th (see Figure 1) o o
Operating free-air temperature, T A -55 125 o 70

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54166 SN74166
PARAMETER TEST CONDITIONSt UNIT
MIN TYP:j: MAX MIN TYP:j: MAX
VIH High-level input voltage 2 2 I V
VIL Low-level input voltage O.B O.B V
VIK I nput clamp voltage VCC= MIN, II =-12mA -1.5 -1.5 V
VCC- MIN, VIH - 2V,
VOH High-level output voltage 2.4 3.4 2.4 3.4 V
VIL = O.BV, 10H = -BOOjLA

VOL Low-level output voltage

VCC- MIN,
VIL = 0.8 V,
VIH - 2V,
10L = 16mA
0.2 0.4 0.2 0.4 V II
II Input current at maximum input voltage VCC- MAX, VI- 5.5V 1 1 mA
IIH High-level input current Vcc = MAX, VI = 2.4 V 40 40 JLA
IlL Low-level input current VCC= MAX, VI = 0.4 V -1.6 -1.6 mA
lOS Short-circuit output current Ii VCC - MAX -20 -57 -18 -57 mA
ICC Supply current VCC = MAX, See Note 2 72 104 72 116 mA

t For conditions shown as MI N or MAX. use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at Vec = 5 V, T A = 25°C.
§ Not more than one output should be shorted at a time.
NOTE 2: With all outputs open, 4.5 V applied to the serial input, all other inputs except the clock grounded, ICC is measured after a momentary
ground, then 4.5 V, is applied to clock.
switching characteristics, Vee = S V, T A = 2S"e
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f max Maximum clock frequency 25 35 MHz
Propagation delay time, high-to-
tPHL 23 35 ns
low-level output from clear
CL=15pF, RL = 400 fl,
Propagation delay time, high-to-
tpHL See Figure 1 20 30 ns
low-level output from clock
Propagation delay time, low-to-
tPLH 17 26 ns
~igh-Ievel output from clock

1076

TEXAS INSTRUMENTS 7-219

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SNS4LS166,SN74LS166
8·BIT SHIFT REGISTERS

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . 7V
Input voltage . . . . . . . . . . . . . . . . . . . 7V
Operating free-air temperature range: SN54LS166 _55°C to 125°C
SN74LS166 oOe to 70°C
Storage temperature range -65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54LS166 SN74LS166
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -400 -400 /.LA
Low-level output current, 10L 4 8 mA
Clock frequency, fclock 0 25 0 25 MHz
Width of clock or clear pulse, tw (see Figure 1) 20 20 ns
Mode-control setup time, tsu 30 30 ns
Data setup time, tsu (see Figure 1) 20 20 ns
Hold time at any input, 1h (see Figure 1) 0 0 ns
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS166 SN74LS166
PARAMETER TEST CONDlTlONSt UNIT
MIN TYP+ MAX MIN TYP+ MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
VIK Input clamp voltage Vee= MIN, 11=-18mA -1.5 -1.5 V
Vee = MIN, VIH = 2 V,
VOH High-level output voltage
VIL = VIL max, 10H = -400 /.LA i 2.5 3.4 2.7 3.4 I V

•
Vee = MIN, VIH=2V, IIOL =4 mA 0.25 0.4 0.25 0.4
VOL Low-level output voltage V
VIL = VIL max IIOL =8 mA 0.35 0.5
Input current at maximum
II Vee = MAX, VI = 7V 0.1 0.1 mA
input voltage
IIH High-level input current Vee = MAX, VI = 2.7 V 20 20 /.LA
I;L Lc....v-Ieve! input current Vee = MAX, Vi 0.4 V i -0.4 -0.4 mA I
lOS Short-circuit output current§ Vee= MAX -20 -100 -20 -100 mA
ICC Supply current Vee= MAX, See Note 2 22 38 22 38 mA

t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
fAil typical values are at Vee = 5 V. T A = 25°e.
§ Not more than one output should be shorted at a time, and duration of short-circuit should not exceed one second.
NOTE 2: With all outputs open. 4.5 V applied to the serial input and all other inputs except the clock grounded .. lee is measured a·fter a
momentary ground, then 4.5 V, is applied to clock.

switching characteristics, Vee = 5 V, TA = 25° C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f max Maximum clock frequency 25 35 MHz
Propagation delay time, high-to-
tPHL 19 30 ns
low-level output from clear
eL=15pF, RL =2 kn,
Propagation delay time, high-to-
tPHL See Figure 1 8 23 35 ns
low-level output from clock
Propagation delay time, low-to-
tpLH 8 24 35 ns
high-level output from clock

1076

7-220 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54166, SN54LS166, SN74166, SN74LS166
8-BIT SHIFT REGISTERS

PARAMETER MEASUREMENT INFORMATION

TEST
POINT

FROM TEST TABLE FOR SYNCHRONOUS INPUTS

~~~~~T __~-M__~"~~__~-'
DATA INPUT OUTPUT TESTED
TEST (See Note 0 SHIFT/LOAD
FOR TEST (SEE NOTE F)
/"f: CL = 15 pF H OV QH att n +1
....L(See Note C) Serial
4.5 V QH at tn+8
Input

LOAD FOR OUTPUT UNDER TEST

CLEIl.R!NPUT Vref
~
________ _
tw(clear) , , . . . . . - - - - - - - - - - - - - - - - - - - - - - 3 V

U~re~
tn+1
- - - - OV

tn r-- (See Note G)

tn ~
tn+1

I~--"" -~---3V
CLOCK INPUT

~ -~th Lov

DATA 9tsu~~3V
INPUT
(SEE TEST
Vref ~~ef_ _ _ _ ov
TABLE) I I
-.l --I tPHLj--
tpHL
(clear-Q) r- (CLK-Q)

' \::ef- - - - VOH

OUTPUT Q - - - - - " " " \ Vref

VOLTAGE WAVEFORMS
~----VOL
I
NOTE: A. All pulse generators have the following characteristics: Zout "" 50 n; for '166, tr .;; 7 ns and tf';; 7 ns; for 'LS166, tr';; 15 ns and
tf';; 6 ns_
B. The clock pulse has the following characteristics: tw(clock) .;; 20 ns and PRR = 1 MHz. The clear pulse has the following
characteristics: tw(clear) ;;, 20 ns and thold =0 ns. When testing f max , vary the clock PRR.
C. CL includes probe and jig capacitance.
D. All diodes are 1 N3064 or 1 N916.
E. A clear pulse is applied prior to each test.
F. Propagation delay times (tpLH and tpH L) are measured at t n +1' Proper shifting of data is verified at t n +8 with a functional test.
G. tn = bit time before clocking transition
tn+1 = bit time after one clocking transition
tn+8 = bit time after eight clocking transitions
H. For '166 Vref = 1.5 V; for 'LS166 Vref = 1.3 V.

FIGURE 1

1076 7·221
TEXAS INSTRUMENTSI~CORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TTL TYPES SN54161, SN14161
MSI SYNCHRONOUS DECADE RATE MULTIPLIERS
BULLETIN NO DL-S 7211813, DECEMBER 1972

SN54167 ••• J OR W PACKAGE

• Perform Fixed-Rate or Variable-Rate SN74167 ••. J OR N PACKAGE
Frequency Division (TOP VIEW)

• For Applications in Arithmetic, Radar,

Digital-to-Analog (D/A), Analog-to-Digital
RATE INPUTS

~
UNITY/ENABLE
CLEAR CASCADE INPUT STROBE

(AID), and other Conversion Operations

• Typical Maximum Clock Frequency ... 32

Megahertz

description

These monolithic, fully synchronous, programmable

counters utilize Series 54/74 TTL circuitry to achieve
32-megahertz typical maximum operating ~ ~
RATE INPUTS OUTPUTS
frequencies. These decade counters feature buffered
clock, clear, enable and set-to-nine inputs to control
the operation of the counter, and a strobe input to positive logic: see description
enable or inhibit the rate input/decoding AND-OR-
INVERT gates. The outputs have additional gating
for cascading and transferring unity-count rates. NC-No internal connection

The counter is enabled when the clear, strobe set-to-nine, and enable inputs are low. With the counter enabled, the
output frequency is equal to the input frequency mUltiplied by the rate input M and divided by 10, ie.:
Mofin
fout = ---;0
where: M = D023 + e02 2 + 8 02 1 + A02 0 for decimal zero through nine.

When the rate input is binary 0 (all rate inputs low), Z remains high. In order to cascade devices to perform two-decade

I rate multiplication (0-99), the enable output is connected to the enable and strobe inputs of the next stage, the Z
output of each stage is connected to the unity/cascade input of the other stage, and the SUb-multiple frequency is taken
from the Y output. For longer words, see typical application data, Figure 1.

The unity/cascade input, when connected to the clock input, may be utilized to pass the clock frequency (inverted) to
the Y output when the rate input/decoding gates are inhibited by the strobe. The unity/cascade input may also be used
as a control for the Y output.

All of the inputs of these counters are diode-clamped, and each input, except the clock input, represents one
normalized Series 54/74 load. The buffered clock input, used with the strobe gate, is only two Series 54/74 loads. Full
fan-out to 10 Series 54/74 loads is available from each of the output. These devices are completely compatible with
most TTL and DTL families. Typical dissipation is 270 milliwatts. The SN54167 is characterized for operation over the
full military temperature range ;f -55°C to 125°C, and the SN74167 is chara~terized for operation from oOe to 70°C.

1076

7-222 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 ° DALLAS. TEXAS 75222
 TYPES SN54161, SN14161
SYNCHRONOUS DECADE RATE MULTIPLIERS
STATE AND/OR RATE FUNCTION TABLE (See Note AI
INPUTS OUTPUTS
LOGIC LEVEL OR
NUMBER OF PULSES
BCD RATE NUMBER OF UNITY/
CLEAR ENABLE STROBE 0 C B A CLOCK PULSES CASCADE Y Z ENABLE NOTES
H X H X X X X X H L H H B
L L L L L L L 10 H L H 1 C
L L L L L L H 10 H 1 1 1 C
L L L L L H L 10 H 2 2 1 C
L L L L L H H 10 H 3 3 1 C
L L L L H L L 10 H 4 4 1 C
L L L L H L H 10 H 5 5 1 C
L L L L H H L 10 H 6 6 1 C
L L L L H H H 10 H 7 7 1 C
L L L H L L L 10 H 8 8 1 C
L L L H L L H 10 H 9 9 1 C
L L L H L H L 10 H 8 8 1 C,D
L L L 10 H 9 9 C,D
'- '- '- '- '- .u .. u u en
,~

L L L H H L H 10 H 9 9 1 C,D
L L L H H H L 10 H 8 8 1 C,D
L L L H H H H 10 H 9 9 1 I C,D
L L L H L L H 10 L H 9 1 I E
NOTES: A. H = high level, L = low level, X = irrelevant. All remaining entries are numeric counts.
B. This is a simplified illustration of the clear function. The states of clock and strobe' can affect the logic level of Y and Z. A low
unity/cascade will cause output Y to remain high.
C. Each rate illustrated assumes a constant value at rate inputs; however, these illustrations in no way prohibit variable-rate inputs.
D. These input conditions exceed the range of the decimal rate inputs.
E. Unity/cascade can be used to inhibit output Y.

functional block diagram and schematics of inputs and outputs

EQUIVALENT OF EACH INPUT

V CC--___4I----
I
INPUT

Clock: Req = 2 kn NOM

All others: Req = 4 kn NOM

TYPICAL OF ALL OUTPUTS

VCC

OUTPUT

1076

TEXAS INCORPORATED
INSTRUMENTS 7-223
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54167, SN74167
SYNCHRONOUS DECADE RATE MULTIPLIERS

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . 7V
Input voltage . . . . . . . . . . . . . 5.5V
Operating free·air temperature range: SN54167 -55°C to 125°C
SN74167 oOe to 70°C
Storage temperature range -65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54167 SN74167
MIN NOM MAX MIN NOM MAX UNIT
Supply voltage, V CC 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -400 -400 {LA
low-level outpu~ current, 'Ol 16 16 mA
Clock frequency, fclock 0 25 0 25 MHz
Width of clock pulse, tw(clock) 20 20 ns
Width of clear pulse, tw(clearl 15 15 ns
Width of set-ta-nine pulse tw(set-ta-91 15 15 ns
Enable setup time, tsu: (See Note 2)
From positive-going transition of clock pulse 25 25 ns
From negative-going transition of previous clock pulse 0 t w (clock)-10 0 t w (clock)-10 ns
Enable hold time, th: (See Note 2)
From positive-going transition of clock pulse 0 tw(clock)-10 0 t w (clock)-10 ns
From negative-going transition of previous clock pulse 20 tcp-10 20 tcp-10 ns
Operating free-air temperature, T A -55 125 0 70 °c
NOTE 2: tw(clock) is the interval in which the clock is high. tcp is the total clock cycle starting with a negative transition. See Figure 1
SN5497, SN7497 data sheet,
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONSt MIN TYP:j: MAX UNIT

I VIH
VI l
High-level input voltage
low-level input voltage
Input clamp voltage Vee- MIN, 11- -12 mA
2
0.8
-1.5
V

V
V

Vee = MIN, V,H = 2 V,

VOH Hlgh-!evel o.Jtput voltage 2.4 34 V
Vil = 0.8 V, 10H = -400 /.LA i
Vee= MIN, VIH=2V,
Val low-level output voltage 0.2 0.4 V
Vil = 0.8 V, 10l = 16 mA
I, Input current at maximum input voltage Vee = MAX, VI = 5.5V 1 mA
clock input 80
IIH High-level input current Vec= MAX, VI=2.4V JJ.A
other inputs 40
clock inputs -3.2
II l low-level input current Vec = MAX, VI = 0.4 V mA
other inputs -1.6
lOS Short circuit output current§ Vee = MAX -18 -55 mA
leCH Supply current, output high Vee- MAX, See Note 3 43 mA
ICCl Supply current, output low Vee = MAX,· See Note 4 65 99 mA

NOTES: 3. 'CCH is measured with outputs open and all inputs low.
4. ICCL is measured with outputs open and all inputs high except the set-to-nine input which is low.
tFor test conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable
device type.
:j: All typical values are at V CC =5 V, T A = 25° C.
§ Not more than one output should be shorted at a time.

1076

7-224 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54167, SN74167
SYNCHRONOUS DECADE RATE MULTIPLIERS

switching characteristics, VCC = 5 V, TA = 25°C

FROM TO
PARAMETERS1f TEST CONDITIONS MIN TYP MAX UNIT
INPUT OUTPUT
f max 25 32 MHz
tPLH 13 20
Enable Enable ns
tpHL 14 21
tpLH 12 18
Strobe Z ns
tpHL 15 23
tPLH 26 39
Clock y ns
tpHL 20 30
tpLH 12 18
Clock Z ns
tpHL 17 26
tPLH 9 14
Rate Z CL = 15 pF, ns
tPHL 6 10
RL=400n,
TPLH
Unity/Cascade Y See Note 5
tpHL
tpLH c+ ....... (..,. .... y
tpHL
----2::-:1~~=~~~1 ". I
-r n
Clock Enable
.- -- ns
tpHL 22 33
tPLH Y 24 36
Clear ns
tpHL Z 15 23
tpHL Set-t0-9 Enable 18 27 ns
tpLH 15 23
Any Rate Input y ns
tpHL 15 23
1ff max is maximum clock frequency.
tpLH is propagation delay time, low·to·high-Ievel output.
tpH L is propagation delay time, high-to-Iow-Ievel output.
NOTE 5: Load circuit, voltage waveforms, and input conditions for measuring switching characteristics are the same as those for the SN5497
and SN7497, page 7-106.

TYPICAL APPLICATION DATA

This application demonstrates how the decimal-rate multipliers may be cascaded for longer words. Three decades are
illustrated (0.999 to 999) although longer words can be implemented by using the pattern shown. The output is
II
decoded either from output Y with a NOR gate or from output Z with a NAND gate. Either method of decoding
produces the complement of the output used.

~ ______________________ INPUT______________________
RATE~A~ 1M) ~

IL-------.--~+_+_+_----_+----~--+_+_+_r_----_+----~

NC

OUTPUT1J" OUTPUT JL.

FIGURE 1

1076

TEXASINCORPORATED
INSTRUMENTS 7·225
POST OFFICE BOX 5012 • DALLAS. TeXAS 75222
 TYPES SN54LS168A, SN54LS169A, SN54S168, SN54S169,
TTL SN74LS168A, SN74LS169A, SN74S168, SN74S169-
MSI SYNCHRONOUS 4-81T UP UP/DOWN COUNTERS
BULLETIN NO. DL-S 7612068, OCTOBER 1976

'LS168A, 'S168 ... SYNCHRONOUS UP/DOWN DECADE COUNTERS

'LS169A, 'S169 ... SYNCHRONOUS UP/DOWN BINARY COUNTERS
SERIES SN54LS', SN54S' ..• J OR W PACKAGE
SERIES SN74LS', SN74S' .•• J OR N PACKAGE
Programmable Look-Ahead Up/Down (TOP VIEW)
Binary/Decade Counters
• Fully Synchronous Operation for Counting OUTPUTS
and Programming ~ ____-JA~____~

• Internal Look-Ahead for Fast Counting

• Carry Output for n-Bit Cascading
• Fully Independent Clock Circuit

TYPICAL MAXIMUM
TYPICAL
CLOCK FREQUENCY
TYPE POWER
COUNTING COUNTING
DISSIPATION
UP DOWN
'LSl68A. 'LSl69A 35MHz 35 MHz 100mW
V
'Sl68, 'S169 70 MHz 55 MHz 500mW DATA INPUTS

positive logic: see description

description

These synchronous presettable counters feature an internal carry look-ahead for cascading in high-speed counting
applications_ The 'lS168A and 'Sl68 are decade counters and the 'lS169A and 'S169 are 4-bit binary counters.
Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change

•
coincident with each other when so instructed by the count-enable inputs and internal gating. This mode of operation
helps eliminate the output counting spikes that are normally associated with asynchronous (ripple-clock) counters. A
buffered clock input triggers the four master-slave flip-flops on the rising (positive-going) edge of the clock waveform.

These counters are fully programmable; that is, the outputs may each be preset to either level. The load input circuitry
allows loading with the carry-enable output of cascaded counters. As loading is synchronous, setting up a low level at
the load input disables the counter and causes the outputs to agree with the data inputs after the next ciock pulse.

The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional
gating. Instrumental in accomplishing this function are two count-enable inputs and a carry output. Both count enable
inputs (P and T) must be low to count. The direction of the count is determined by the level of the up/down input.
When the input is high, the counter counts up; when low, it counts down. Input'F is fed forward to enable the carry
output. The carry output thus enabled will produce a low-level output pulse with a duration approximately equal to the
high portion of the QA output when counting up and approximately equal to the low portion of the QA output when
counting down. This low-level overflow carry pulse can be used to enable successive cascaded stages. Transitions at the
enable P or 'F inputs are allowed regardless of the level of the clock input. All inputs are diode-clamped to minimize
transmission-line effects, thereby simplifying system design.

These counters feature a fully independent clock circuit. Changes at control inputs (enable P, enable T, load, up/down)
that will modify the operating mode have no effect until clocking occurs. The function of the counter (whether
enabled, disabled,loading, or counting) will be dictated solely by the conditions meeting the stable setup and hold times.

The 'lS168A and 'LS169A are completely new designs. Compared to the original 'lS168 and 'lS169, they feature
O-nanosecond minimum hold time and reduced input currents IIH and Ill'

1076

7-226 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54LS168A, SN54LS169A, SN74LS168A, SN74LS169A
SYNCHRONOUS 4-81T UP/DOWN COUNTERS

functional block diagrams

en
a:

2
w
I-
:::>
oCJ
w
o
<t
CJ
•
w
o
<t"
eo
ttl
Vi
...J

""'"
2
en
<i
eo
ttl
Vi
...J

""2
In

en

1076

TEXAS INSTRUMENTS
I~CORPORATED
7-227
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54S168, SN54S169, SN74S168, SN74S169
SYNCHRONOUS 4-81T UP/DOWN COUNTERS

functional block diagrams

en
cc
w
I-
Z
::l
ot)
>cc
c:(
z
iii
~
en
,...
"3'
Z
en
Pi
ij
III
Z
en

......
y
0

~ "~ g ~

i
~~~
~~~
~ if /5 8 ~~o

• en
cc
W
I-
Z
::l
ot)
w
oc:(
t)
w
o
co
u:o
ij,...
Z
en
f8
ij
III
Z
en

- 12 § -
10
~ §:
u
" " 0
:5
~ ..." "'3
~ ~

374

7-228 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54LS168A, SN54S168, SN74LS168A, SN74S168
SYNCHRONOUS 4-81T UP/DOWN COUNTERS

'LS168A, 'S168 DECADE COUNTERS

typical load, count, and inhibit sequences

Illustrated below is the following sequence:

1. Load (presetl to BCD seven

2. Count up to eight, nine (maximum). zero, one, and two
3. Inhibit
4. Count down to one, zero (minimum). nine, eight, and seven

I
L

j
DATA
s-.J L.. _

INPUTS
c-.J j
L_

,
r-

CLOCK U"--W'--uLJ1J-U'--U-u'LJ-u'LJL.Jl.J-L
I I I :
-- I I
UfD __ J' , I 7
I I
--, , I
PANDT I~-+__~I_I~________________~

I:
,I
Os ----n, !------------.....
___ -J
l
I
:!
,I
°c ----;--11 I
~ __ -J 1 !-i--------------------------~--~----------------~·
°D -____
--, I!
L-.iJ L-
II
~:~~~ ----I
OUTPUT ___ ...J
I 1
"
I
'---J
I I ',I I
L-I
I
:7,,890 2 221109 8 7

U I----
.. COUNT UP --_II-INHIBIT -I I--- COUNT DOWN - - - -

LOAD

1076

TEXAS INCORPORATED
INSTRUMENTS 7-229
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54LS169A. SN54S169.SN14LS169A. SN14S169
SYNCHRONOUS 4-81T UP UP/DOWN COUNTERS

'LS169A, 'S169 BINARY COUNTERS

typical load, count, and inhibit sequences

Illustrated below is the following sequence:

1. Load (preset) to binary thirteen

2. Count up to fourteen, fifteen (maximum). zero, one, and two
3. Inhibit
4. Count down to one, zero (minimum). fifteen, fourteen, and thirteen

LOAD L---.J
A ,"----";-" - -
---l L..._

B _ _ _~.....I _ -
r-
DATA
INPUTS
C~
D
---.J
,r----..L---_
CLOCK

•
_--~i-+--~IHI~----------------------
UfO __ J I

PANDT--'~~______________________--,
!
___ i

Q - - I
D
- --.I
RIPPLE -
CARRY
- -r--...,;,..---u
• I
LJ
OUTPUT- - ~ I
I 13 14 15 0 2, 2 2 o 15 14 13

I I·---COUNT
.. UP --_·.I·_INHIBIT-I
. ~COUNTOOWN-----
~
LOAD

1076

7-230 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DAL.LAS, TEXAS 75222
 TYPES SN54LS168A, SN54LS169A'ISN74LS168A, SN74LS169A
SYNCHRONOUS 4-81T UP/DOWN COUNTERS

schematics of inputs and outputs

EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS

------'t-- Vcc
VCC?Reqf
INPUT

'-~~- OUTPUT
~
Load: Req = 10 k!2 NOM
Data: Req = 25 k!2 NOM

Clock, Enable P, T, UfO: Req = 20 k!2 NOM

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, Vee (see Note 1)

Input voltage . . . . . . .
............ .
............ .
Operating free-air temperature range: SN54LS168A, SN54LS169A.

Storage temperature range

SN74LS168A, SN74LS169A.

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

7V
7V
-55°C to 125°C
oOe to 70°C
-65°C to 150°C
•
SN54LS168A SN74LS168A
SN54LS169A SN74LS169A UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, VCC 4.5 5 5.5 4.75 5 5.25 V
High-level output current, IOH -400 -400 f.lA
Low-level output current, IOL 4 8 rnA
Clock frequency, f clock 0 25 0 25 MHz
Width of clock pulse, tw(clock) (high or low) (see Figure 1) 25 25 ns
Data inputs A, B, C, D 20 20
Enable PorT 20 20
Setup time, tsu (see Figure 1) ns
Load 25 25
Up/Down 30 30
Hold time at any input with respect to clock, th (see Figure 1) 0 0 ns
Operating free-air temperature, T A -55 125 0 70 DC

TENTATIVE DATA
1076
This page provides tentative information on a
new product. Texas Instruments reserves the TEXAS INCORPORATED
INSTRUMENTS 7-231
right to change specifications for th is product
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
in any manner without notice.
 TYPES SN54LS168A, SN54LS169A,SN74LS168A, SN74LS169A
SYNCHRONOUS 4-81T UP/DOWN COUNTERS

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS168A SN74LS168A
PARAMETER TEST CONDlTlONSt SN54LS169A SN74LS169A UNIT I
MIN TYP+ MAX MIN TYP+ MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
VIK Input clamp voltage VCC= MIN, II = -18 rnA -1.5 -1.5 V
VCC- MIN, VIH-2V,
VOH High-level output voltage 2.5 3.4 2.7 3.4 V
VIL = VIL max, 10H = -400 IJ.A
VCC = MIN, 0.25 0.4 0.25 0.4
IIOL =4 rnA
VOL Low-level output voltage VIH=2V, V
VIL=VILmax IIOL=8mA 0.35 0.5

In put cu rrent A, B, C, D, P, U/D 0.1 0.1

II at maximum Clock, T VCC= MAX, VI =7 V 0.1 0.1 I rnA
input voltage Load 0.2 0.2 I
A,B,C,D,P,U/D 20 20
High-level
IIH Clock, T VCC = MAX, VI=2.7V 20 20 IJ.A
input current
Load 40 40
A, B, C, D, P, U/D -0.4 -0.4
Low·level
IlL Clock, T Vce = MAX, VI = 0.4 V -0.4 -0.4 rnA
input current
Load -0.8 -0.8
lOS Short-circuit output current§ VCC= MAX -20 -100 -20 -100 rnA
ICC Supply current VCC= MAX, See Note 2 20 34 20 34 rnA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+ All typical values are at V CC = 5 V, T A = 25° C.
§ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
NOTE 2: ICC is measured after applying a momentary 4.5 V, then ground, to the clock input with all other inputs grounded and the outputs
open.

switching characteristics, Vee = 5 V, T A = 25°e

• PARAMETER.

f max
tPLH
tPHL
tpLH
tPHL
FROM
!INPUT)

Clock

Clock
TO
(OUTPUT)

Ripple
carry
Any
Q
TEST CONDITIONS

CL=15pF,
RL = 2 kn,
See Figures 2 and 3
MIN

25
TYP

32
23
23
13
15
MAX

35
35
20
23
UNIT

MHz

ns

ns

tpLH - Ripple 10 14
Enable T and Note 3 ns
tPHL carry 10 14
tPLHO Ripple 17 25
Up/Down ns
tpHLO carry 19 29

.f max =" Maximum clock frequency

tpLH =" propagation delay time, low-to-high-Ievel output.
tpHL =" propagation delay time, high-to-Iow-Ievel output.
°propagation delay time from up/down to ripple carry must be measured with the counter at either a minimum or a maximum count. As the
logic level of the up/down input is changed, the ripple carry output will follow. If the count is minimum (0), the ripple carry output
transition will be in phase. If the count is maximum (9 for 'LS168A or 15 for 'LS169A), the ripple carry output will be out of phase.
NOTE 3: Load circuit is shown on page 3-11.

TENTATIVE DATA 1076

This page provides tentative information on a
7-232 new product. Texas Instruments reserves the TEXAS INCORPORATED
INSTRUMENTS
right to change specifications for th is product
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
in any manner without notice.
 TYPES SN54S168, SN54S169, SN74S168, SN74S169
SYNCHRONOUS 4-81T UP/DOWN COUNTERS

schematics of inputs and outputs

EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS

- - - - - -...--VCC
VCC--------~-------
50 Q NOM

OUTPUT

Enable P or T inputs: Req = 1.4 kQ I II J'-.:a.___..__.~

_________________
NOM

~ _______ O_t~_.e_r;~_.p_utS_:_Re_q_=2_.8_k_Q_N_O~_A ____ ~1 ~I __________~

r.h
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, Vee (see Note 4) 7V

Input voltage . . . . . . . . 5.5 V
Interemitter voltage (see Note 5) 5.5V
Operating free-air temperature range: SN54Si68, SN54Si69 isee Note 6) -55°C to 125°C
SN74S168,SN74S169 oOe to 700 e
0

•
Storage temperature range -65°e to 150 e

recommended operating conditions

SN54S168 SN74S168
SN54S169 SN74S169 UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, VCC 4.5 5 5.5 4.75 5 5.25 V
High-level output current, IOH -1 -1 rnA
Low-level output current, IOL 20 20 rnA
Clock frequency, fclock 0 40 0 40 MHz
Width of clock pulse, tw(clock} (high or low} (see Figure 1) 10 10 ns
Data inputs A, B, C, D 4 4
Enable PorT 14 14
Setup time, tsu (see Figure 1) ns
Load 6 6
Up/Down 20 20
Hold time at any input with respect to clock, th (see Figure 1) 1 1 ns
Operating free-air temperature, T A (see Note 6) -55 125 0 70 °c

NOTES: 4. Voltage values, except interemitter voltage, are with respect to network ground terminal.
5. This is the voltage between two emitters of a multiple·emitter transistor. For these circuits, this rating applies between the count
enable inputs P and T . . . . 0 . . .
6. An SN54S~68 or SN54S169 In the,,:, package operating at free-al~ temperatures above 91 C requires a heat sink that provIdes a
thermal resIstance from case to free-air, ReCA' of not more than 26 C/W.

1076

TEXAS INCORPORATED
INSTRUMENTS 7-233
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54S168, SN54S169, SN74S168, SN74S169
SYNCHRONOUS 4-81T UP/DOWN COUNTERS

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54S168 SN74S168
SN54S169
PARAMETER
I TEST CONDITIONSt
MIN TYPt MAX MIN
SN74S169
TYPt MAX
UNIT\

VIH High-tevel input voltage 2 2 V

VIL Low-level input voltage 0.8 0.8 ! V
VIK Input clamp voltage Vee = MIN, II = -18mA -1.2 -1.2 V
Vee = MIN, VIH = 2 V,
VOH High-level output voltage I 2.5 3.4 2.7 3.4 V
VIL = 0.8 V, 10H = -1 mA
Vee= MIN, VIH = 2 V,
VOL Low-level output voltage 0.5 0.51 V
VIL = 0.8 V, 10L = 20mA
II Input current at maximum input voltage Vee = MAX, VI-5.5V 1 1 mA
Enable T 100 100
IIH High-level input current Vce = MAX, VI=2.7V !1A
Other inputs 50 50
Enable T -4 -4
IlL Low-level input current Vec = MAX, VI = 0.5 V mA
Other inputs -2 -2
lOS Short-circuit output current§ VCC = MAX -40 -100 -40 -100 mA
Ice Supply cureent VCC- MAX, See Note 2 100 160 100 160 mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
fAil typical values are at V CC = 5 V, T A = 25°C.
§ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
NOTE 2: ICC is measured after applying a momentary 4.5 V, then ground, to the clock input with all other inputs grounded and the outputs
open.

switching characteristics, Vee = 5 V, TA = 25°e

FROM TO UP/DOWN = HIGH UP /DOWN = LOW
PARAMETER~ TEST CONDITIONS UNIT
(lNPUTI (OUTPUT! MIN TYP MAX MIN TYP MAX
f max 40 70 40 55 MHz

•
tpLH Ripple 14 21 14 21
Clock ns
tPHL carry 20 28 20 28
CL=15pF,
tPLH 8 15 8 15
Clock Any Q RL = 280 n, ns
tpHL 11 15 11 15
See Figures 2 and 3
tPLH Ripple 7.5 11 6 12
Enable T and Note 7 ns
tpHL
tPLHO
i carry
Ripple
15
9
22
15
15
8
25
15
I
Up/Down ns
tpHLO carry 10 15 16 22

~fmax '" maximum clock frequency

tpLH '" propagation delay time, low-to-high-Ievel output
tPHL '" propagation delay time, high-to-Iow-Ievel output
°Propagation delay time from up/down to ripple carry must be measured with the counter at either a minimum or a maximum count. As the
logic level of the up/down input is changed, the ripple carry output will follow. If the count is minimum (0), the ripple carry output
transition will be in phase. If the count is maximum (9 for 'S168 or 15 for'S 169), the ripple carry output will be out of phase.
NOTE 7: Load circuit is shown on page 3-10_

1076

7-234 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54LS168A, SN54LS169A, SN54S168, SN54S169,
SN74LS168A, SN74LS169A, SN74S168, SN74S169
SYNCHRONOUS 4-81T UP UP/DOWN COUNTERS
PARAMETER MEASUREMENT INFORMATION
I-- tw(clock) ...-.j
I (4...-- tw(clock) ~
I I I 3V
CLOCK
I I
Vref
INPUT
I I
I T--- OV
f4- tsu --t j 4 - - tsu --.I I
I (active state) I.- th -.! (inactive state) I I

\v~ l~~~ ___ Ti - - -

3V

LOAD
INPUT
~----~I-----'
i ------f---OV
!
~ tsu --t-- th -I I I
J._
DATA INPUTS
A, B, C, and D
f I
Vref
I
\.Vref
____
-------l---3V
!

----./ \ i OV
! I
I
r- tsu -.I
I
th~

ENABLE P or
I

\v~f
I
I
:C OV

ENABLE f "-___+I ____________....j.:...IT _V:f_ 3 V

I I
I
'-
~th
tsu
I ~ th
I I I 3V

lv~
\.
UP/DOWN
INPUT
\ V ref

Fav
•
\...
VOLTAGE WAVEFORMS
NOTES: A. The input pulses are supplied by a generator having the following characteristics: PRR '" 1 MHz, duty cycle", 50%, Zout '" 50!2;
for 'LS168A and 'LS169A, tr '" 15 ns, tf '" 6 ns, and for 'S168 and 'S169. tr '" 2.5 ns, tf '" 2.5 ns.
B. For 'LS168A and 'LS169A, Vref ~ 1.3 V; for 'S168 and 'S169, Vref ~ 1.5 V.

FIGURE 1-PULSE WIDTHS, SETUP TIMES, HOLD TIMES

,.,4
\. , 3V
ENABLE
INPUT
f
f",V_re_f _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
vref _______ av
I
!+--tPHL ----eo!
I
!.-- tPLH--II
I I VOL

\V~ lv~ ---VaH

RIPPLE
CARRY
OUTPUT

VOLTAGE WAVEFORMS
NOTES: A. The input 'Pulse is supplied by a generator having the following characteristics: PRR '" 1 MHz, duty cycle", 50%, Zout '" 50 !2;
for 'LS168A and 'LS169A, tr '" 15 ns, tf '" 6 ns; and for 'S168 and 'S169, tr '" 2.5 ns. tf '" 2.5 ns.
B. tpLH and tpH L from enable T input to ripple carry output assume that the counter is at the maximum count (QA and QD high
for 'LS168A and 'S168, all Q outputs high for 'LS169A and 'S169).
C. For 'LS168A and 'LS169A, Vref ~ 1.3 V; for 'S168 and 'S169, Vref ~ 1.5 V.
D. Propagation delay time from up/down to ripple carry must be measured with the counter at either a minimum or a maximum
count. As the logic level of the up/down input is changed, the ripple carry output will follow. If the count is minimum (0) the
ripple carry output transition will be in phase. If the count is maximum (9 for 'LS168A and 'S168, or 15 for 'LS169A and
'5169) the ripple carry output will be out of phase.
FIGURE 2-PROPAGATION DELAY TIMES TO CARRY OUTPUT

1076

TEXAS INCORPORATED
INSTRUMENTS 7·235
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54LS168A, SN54LS169A, SN54S168, SN54S169,
SN74LS168A, SN74LS169A, SN74S168, SN74S169
SYNCHRONOUS 4-81T UP/OOWNCOUNTERS
PARAMETER MEASUREMENT INFORMATION

I..tW!cIOCk) ..I
I I
I 3V
CLOCK
INPUT

~tPLH ~tPHL
I (measure at t n+1) I I (measure at t n+2)
I I I

OUTPUT V "tv", /
Y~'r---~·
0A _ _ _ _..JrVref

I
~tPHL ~tPLH
I I (measure at t n +4) I I (measure at t n+2)
I I

~~s----:~)I~,- ---
VOH
OUTPUT
°B
- - - VOL

I...--...L- tpHL II .1 tPLH

I : (measure at tn+Sl I I (measure at tn+4l

VOH

OU6;UT-------------~s --......;.!-,..,lv~, ___ ... _

- - - VOL
I

•
""11~-.....
I-tPHL ""1"--·""I-tPLH
I (measure at t n +10 (measure at tn+Sl
I or tn+16l I
~ v~::e Note B) VOH

'~'Fs==_~lv: _____ _
OUTPUT I
°D
r----r- tPHL I"
.......-
I
I
...t--tpLH
(measure at t n +10
I : or tn+16 1 (See Note B)

pf
VOH
RIPPLE
CARRY
OUTPUT "V", "".- - - - - - - . - - - - - - - - - - - - - - - - - VOL

UP-COUNT VOLTAGE WAVEFORMS

NOTES: A. The input pulses are supplied by a generator having the following characteristics: PRR .;; 1 MHz, duty cycle';; 50%. Zout '" 50 n;
for 'LS168A and 'LS169A, tr';; 15 ns, tf';; 6 ns; and for 'S168 and 'S169,t r ';; 2.5 ns,tf';; 2.5 ns. Vary PRR to measuref max •
B. Outputs Q D and carry are tested at tn+1 0 for the 'LS168A and 'S168, and at t n +16 for the 'LS169A and 'S169, where tn is the
bit-time when all outputs··are low.
C. For 'LS168A and 'LS169A, Vref = 1.3 V; for 'S168 and 'S169, Vref = 1.5 V.

FIGURE 3-PROPAGATION DELAY TIMES FROM CLOCK

1076

1-236 TEXAS '''ICORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TTL TYPES SN54170, SN54LS170, SN74170, SN74LS170
MSI 4-8Y-4 REGISTER FILES WITH OPEN-COLLECTOR OUTPUTS
BULLETIN NO. DL-S 7611349, MARCH 1974-REVISED OCTOBER 1976

• Separate Read/Write Addressing Permits SN54170, SN54LS170 ... J OR W PACKAGE

Simultaneous Reading and Writing SN74170, SN74LS170 ... J OR N PACKAGE
(TOP VIEW)
• Fast Access Times ... Typically 20 ns WRITE SELECT ENABLE OUTPUTS
Vcc D~~A 'W';''W;'' WRITE READ "'Q'T"Ci2'
• Organized as 4 Words of 4 Bits
• Expandable to 1024 Words of n-Bits
• For Use as:
Scratch-Pad Memory
Buffer Storage between Processors D2 02
Bit Storage in Fast Multiplication Designs
• Open-Collector Outputs with Low
Maximum Off-State Current:
'170 ... 30 ~A
'LSi70 ... 20 p.A
• SN54LS670 and SN74LS670 Are
C!':_:I __ D .... u_ .... _ ., Cl.. _ .._ r\ .... _ ...._
~l1ll1lal CUL nave ~-~LaLe VULt-IUL:I positive iogic: see description

description
The '170 and 'LS170 MSI 16-bit TTL register files incorporate the equivalent of 98 gates. The register file is organized
as 4 words of 4 bits each and separate on-chip decoding is provided for addressing the four word locations to either
write-in or retrieve data. This permits simultaneous writing into one location and reading from another word location.

Four data inputs are available which are used to supply the 4-bit word to be stored. Location of the word is determined
by the write-address inputs A and 8 in conjunction with a write-enable signal. Data applied at the inputs should be in its
true form. That is, if a high-level signal is desired from the output, a high level is applied at the data input for that
particular bit location. The latch inputs are arranged so that new data will be accepted only if both internal address gate
inputs are high. When this condition exists, data at the D input is transferred to the latch output. When the write-enable
input, GW, is high, the data inputs are inhibited and their levels can cause no change in the information stored in the

•
internal latches. When the read-enable input, GR, is high, the data outputs are inhibited and remain high.

The individual address lines permit direct acquisition of data stored in any four of the latches. Four individual decoding
gates are used to complete the address for reading a word. When the read address is made in conjunction with the
read-enable signal, the word appears at the four outputs.

This arrangeinent-data-entry addressing separate from data-read addressing and individual sense line-eliminates recovery
times, permits simultaneous reading and writing, and is limited in speed only by the write time (30 nanoseconds
typical) and the read time (25 nanoseconds typical). The register file has a nondestructive readout in that data is not
lost when addressed.

All '170 inputs and all inputs except the read enable and write enable of the 'LS170 are buffered to lower the drive
requirements to one Series 54/74 or Series 54LS/74LS standard load, respectively. Input-clamping diodes minimize
switching transients to simplify system design. High-speed, double-ended AND-OR-INVERT gates are employed for the
read-address function and drive high-sink-current, open-collector outputs. Up to 256 of these outputs may be wire-AND
connected for increasing the capacity up to 1024 words. Any number of these registers may be paralleled to provide
n-bit word length.

The SN54170 and SN54LS170 are characterized for operation over the full military temperature range of -55°C to
125°C; the SN74170 and SN74LS170 are characterized for operation from oOe to 70°C.

1076

TEXAS INSTRUMENTS
INCORPORATED
7-m
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54170, SN54LS170, SN74170, SN74LS170
4-BY-4 REGISTER FILES WITH OPEN-COLLECTOR OUTPUTS

logic
WRITE FUNCTION TABLE (SEE NOTES A, B, AND CI READ FUNCTION TABLE (SEE NOTES A AND DI

WRITE INPUTS WORD READ INPUTS OUTPUTS

WB WA GW 0 1 2 3 RB RA GR 01 02 Q3 04
L L L 0=0 00 00 00 L L L WOB1 WOB2 WOB3 WOB4
L H L 00 O=D 00 00 L H L W1B1 W1B2 W1B3 W1B4
H L L 00 00 O=D 00 H L L W2B1 W2B2 W2B3 W2B4
H H L 00 00 00 0=0 H H L W3B1 W3B2 W3B3 W3B4
X X H 00 00 00 00 X X H H H H H

NOTES: A. H = high level, L = low level, X = irrelevant.

B. (Q = 0) = The four selected internal flip·flop outputs will assume the states applied to the four external data inputs.
C. Q O = the level of Q before the indicated input conditions were established.
O. WOB1 = The first bit of word 0, etc.

functional block diagram '170

OUTPUTS

• DATA
INPUTS

03

1",,,f
~ WRITE INPUT
(4) (5)

374

7·238 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54170, SN54LS170, SN74170, SN74LS170
4-BY-4 REGISTER FILES WITH OPEN-COLLECTOR OUTPUTS
REVISED OCTOBER 1976

functional block diagram

'LS170

DATA
INPUTS
JI
I
03

•
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) 7V
Input voltage: '170 5.5V
'LS170 7V
Off-state output voltage: '170 5.5 V
'LS170 . . .. 7V
Operating free-air temperature range: SN54170, SN54LS170 (see Note 2) -55°C to 125°C
SN74170,SN74LS170 . oOe to 70°C
Storage temperature range -65°C to 150°C
NOTES: 1. Voltage values are with respect to network ground terminal.
2. An SN54170 in the W package operating at free-air temperatures above 105°C requires a heat sink that provides a thermal
resistance from case to free-air, ReCA' of not more than 38°C/W

1076

TEXAS INSTRUMENTS
INCORPORATED
7-239
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54170, SN74170
4-8Y-4 REGISTER FILES WITH OPEN-COLLECTOR OUTPUTS

recommended operating conditions

MIN
SN54170
NOM MAX MIN
SN74170
NOM MAX
UNIT I
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output voltage, VOH 5.5 5.5 V
Low-level output current, IOL 16 16 mA
Width of write-enable or read-enable pulse, tw 25 25 ns
Data input with respect to
10 10 ns
Setup times, high- or low·level data write enable, tsu(O)
(see Figure 2) Write select with respect to
15 15 ns
write enable, tsu{W)
Data input with respect to
15 15 ns
Hold times, high- or low-level data write enable, th(D)
{see Note 3 and Figure 2} Write select with respect to
5 5 ns
write enable, th{W)
Latch time for new data, tlatch (see Note 4) 25 25 ns
Operating free-air temperature range, T A (see Note 2) -55 125 0 70 °e

NOTES: 2. An SN54170 in the W package operating at free·air temperatures above 105°C requires a heat sink that provides a thermal
resistance from case to free-air, ReCA' of not more than 38° C/W.
3. Write select setup time will protect the data written into the previous address. If protection of data in the previous address is not
required, !su(w) can be ignored as any address selection sustained for the final 30 ns of the write-enable pulse and during th(W)
will result in data being written into that location. Depending on the duration of the input conditions, one or a number of
previous addresses may have been written into.
4. Latch time is the time allowed for the internal output of the latch to assume the state of new data. See Figure 2. This is important
only when attempting to read from a location immediately after that location has received new data.

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONSt MIN TYP+ MAX UNIT
VIH High-level input voltage 2 V
Low·level input voltage 0.8 V

•
VIL
VIK Input clamp voltage Vee= MIN, II = -12 mA -1.5 V
Vee - MIN, VOH - 5.5 V,
IOH High-level output current 30 }.LA
VIH=2V, VIL=0.8V
Vee= MIN, VIH=2V,
VOL Low-level output voltage 0.2 0.4 V
VIL = 0.8 V, IOL = 16mA ! I
II Input current at maximum input voltage Vee - MAX, VI - 5.5 V 1 mA
IIH High-level input current Vee = MAX, VI=2.4V 40 }.LA
IlL Low-level input current Vee = MAX, VI = 0.4 V -1.6 mA
Vee = MAX, LSN54170 127§ 140
lee Supply current mA
See Note 5 ISN74170 127§ 150

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at VCC = 5 V, T A = 25°C.
§Typical supply current shown is an average for 50% duty cycle.
NOTE 5: Maximum ICC is guaranteed for the following worst·case conditions: 4.5 V is applied to all data inputs and both enable inputs, all
address inputs are grounded, and all outputs are open.

1076

7-240 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54170, SN74170
4-8Y-4 REGISTER FILES WITH OPEN-COLLECTOR OUTPUTS

switching characteristics, Vee = 5 V, TA = 25°e

FROM TO
PARAMETER~ TEST CONDITIONS MIN TYP MAX UNIT
(INPUT) (OUTPUT)
tPLH 10 15
Read enable AnyQ CL=15pF, ns
tpHL 20 30
RL=400n,
tPLH 23 35
Read Select AnyQ See Figures 1 and 2 ns
tpHL 30 40
tpLH 25 40
Write enable AnyQ CL=15pF, ns
tpHL 34 45
RL=400n,
tPLH 20 30
Data AnyQ See Figures 1 and 3 ns
tpHL 30 45

~tpLH == propagation delay time, low-to-high-Ievel output

tpH L == propagation delay time, high-to-Iow-Ievel output

schematics of inputs and outputs

'170 '170

EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS

vcc------~ __-------
OUTPUT

INPUT

374

TEXAS INCORPORATED
INSTRUMENTS 7-241
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54LS170, SN74LS170
4-BY-4 REGISTER FILES WITH OPEN-COLLECTOR OUTPUTS

recommended operating conditions

SN54LS170 SN74LS170
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output voltage, VOH 5.5 5.5 V
Low-level output current, IOL 4 8 rnA
Width of write-enable or read-enable pulse, tw 25 25 ns
Data input with respect to
10 10 ns
Setup times, high- or low-level data write enable, tsu(Q)
(see Figure 2) Write select with respect to
15 15 ns
write enable, tsu(W)
Data input with respect to
15 15 ns
Hold times, high- or low-level data write enable, th(D)
(see Note 3 and Figure 2) Write select with respect to
5 5 ns
write enable, th(W)
Latch time for new data, tlatch (see Note 4) 25 25 ns
Operating free-air temperature range, T A -55 125 0 70 °e

NOTES: 3. Write-select setup time will protect the data written into the previous address. If protection of data in the previous address is not
required, tsu(W) Can be ignored as any address selection sustained for the final 30 ns of the write·enable pulse and during th(W)
will result in data being written into that location. Depending on the duration of the input conditions, one or a number of
previous addresses may have been written into.
4. Latch time is the time allowed for the internal output of the latch to assume the state of new data. See Figure 2. This is important
only when attempting to read from a location immediately after that location has received new data.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS170 SN74LS170
PARAMETER TEST eONDITIONSt UNIT
MIN TYP:j: MAX MIN TYP:j: MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V

•
VIK Input clamp voltage Vee :MIN, II: -18 mA -1.5 -1.5 V
Vee: MIN, VOH = 5.5 V,
IOH High-level output current 20 20 /.IA
VIL = VIL max, VIH = 2 V
Vee = MIN, 0.25 0.4
1ioL = 4mA 0.4 0.25
VOL Low-level output voltage VIH=2V, V
VIL=VILmax IIOL=8mA 0.35 0.5

Input current at Any D, R, or W, 0.1 O·

.1 ,
II Vee = MAX, VI = 7V rnA
maximum input voltage GR orGw 0.2 0.2
Any D, R, orW 20 20
IIH High-level input current Vee = MAX, VI = 2.7 V /.IA
GRorGw 40 40
AnyD,R,orW -0.4 -0.4
IlL Low-level input current Vee = MAX, VI = 0.4 V rnA
GR or GW -0.8 -0.8
lee Supply current Vee= MAX, See Note 6 25 40 25 40 rnA

t For conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions.
:tA" typical values are at VCC = 5 V, T A = 25°C.
NOTE 6: ICC is measured under the following worst-case conditions: 4.5 V is applied to a" data inputs and both enable inputs, all address
inputs are grounded, and a" outputs are open.

1076

7-242 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54LS170. SN74LS170
4-8Y-4 REGISTER FILES WITH OPEN-COLLECTOR OUTPUTS

switching characteristics, Vee = 5 V, TA = 25°e

FROM TO
PARAMETER~ TEST CONDITIONS MIN TYP MAX UNIT
(INPUT) (OUTPUT)
tpLH 20 30
Read enable AnyQ CL=15pF, ns
tpHL 20 30
RL = 2 kn,
tPLH 25 40
Read select AnyQ See Figures 1 and 2 ns
tpHL 24 40
tPLH 30 45
Write enable AnyQ CL=15pF, ns
tpHL 26 40
RL = 2 kn,
tpLH 30 45
Data AnyQ See Figures 1 and 3 ns
tpHL 22 35

~ tp LH "" propagation delay time, low-to-high-Ievel output

tpHL "" propagation delay time, high-to-Iow-Ievel output

schematics of inputs and outputs

'LS170 'LS170

EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS

Vee ----+---

:NPUT - .....~i-....- ..........

__ ~OUTeuT

Any D, R, or W: Req = 20 kn NOM

•
GR or GW: Req =10 kn NOM

374

TEXAS INCORPORATED
INSTRUMENTS 7-243
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54170, SN54LS170, SN74170, SN74LS170
4-8Y-4 REGISTER FILES WITH OPEN-COLLECTOR OUTPUTS
REVISED MARCH 1974

PARAMETER MEASUREMENT INFORMATION

Vee

~
FROM OUTPUT
l TEST
UNDER TEST POINT

Tel
CL includes probe and jig capacitance
LOAD CIRCUIT

FIGURE 1

WFlITE.sELECT
INPUT WA or We
~
___________
Vref Vre!
3V DATAINPUTJ-
01,02.03 or 04 I Vref
\------------'3 V

lSee Note A.) I I OV I 0'01

''"'~ i.- "'WI

I

DATAINPIJT
~~~2~t~!tD4 I ~I
--I :-
~" .• I
Vre! 1
~
..L~,,:,rere~~ ________________
I t----+- '1"I(0!
3v

0'01 :~~:~ABl_E-.,;:___ ---'1 \V"~ - - -- - -::

I ~[,ufDl f.-----1 IPLH ~tpHl
----~IV
VOH

WR'TE'EN.BLe~tw OUTPUT i-----

INPUTGw ~~'r;'- _________ 3\1
ov Q1, Q2, OJ Of 0lIl

----
ref Vref

~
~ [tatch----,
_ _ _ _ _ _ 3V
~

VOLTAGE WAVEFORM 1
If
g~T;'~';,';U,~ ~,-",_,___---'1_____________ ::
INPUT RA or Ae V rt , \ . V rel

•
ISft'NofeBI _ _ _ _ _ _...J :~ _ _ _ ov
1

READ·ENABLE
INPUTGR
j'w----r-l
~Vre' i~
3V I
!
:
~~¥=-

~'PHL:~'PlH
___ ov
:~~~~:ABLE__ - ,-:___--JI
I

\~f- -----::
~
11IVOH
I r .. ; ~'PLH
OUTPUT
0'. 02. 00, o.(l' 1.----1-:.: - - ;.. 'PHl...i
V'I
"
V
vOL
OUTPUT ~v-.
"'Hl

~3V
al,Q2,03,O'C: _ _ _ _ ~~ _ _ _ OV
VOL TAGE WAVEFORMS VOLTAGE WAVEFORM 2

FIGURE 2 FIGURE 3

NOTES: A. High-level input pulses at the select and data inputs are illustrated in Figure 2; however, times associated with low-level pulses are
measured from the same reference points.
B. When measuring delay times from a read-select input, the read-enable input is low. When measuring delay times from the
read-enable input, both read-select inputs have been established at steady states.
C. In Figure 3, each select address is tested. Prior to the start of each of the above tests, both write and read address inputs are
stablized with WA = RA and WB = RB. During the test GR is low.
D. Input waveforms arE; supplied by generators having the following characteristics: PRR .;;; 1 MHz, Zout "" 50 n, duty cycle';;; 50%,
tr .;;; 10 ns and tf .;;; 10 ns for' 170, and tr .;;; 15 ns and tf .;;; 6 ns for' LS 170.
D. For '170, Vref = 1.5 V; for 'LS170, Vref = 1.3 V.

1076

7-244 TEXAS INSTRUMENTS INCORPORATED

POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TTL TYPE SN74172
LSI 16-81T MULTIPLE-PORT REGISTER FILE WITH 3-STATE OUTPUTS
BULLETIN NO. DL-S 7211744, MAY 1972 - REVISED DECEMBER 1972

• Independent Read/Write Addressing Permits J OR N DUAL-IN-LiNE

Simultaneous Reading and Writing PACKAGE (TOP VIEW)

• Organized as Eight Words of Two Bits Each DATA WRITE/READ READ

WRITE INPUTS WRITE ADDRESS ENABLE OUTPUTS
ADDRE~ENABLE~~~
Vee 1W2 lOA 20A 2GW 2W!R2 2W/Al 2W/RO 2GR 1GR lOA 2QA
• Fast Access Times:
From Read Enable ... 15 ns Typical
From Read Select ... 33 ns Typical

• Three-State Outputs Simplify Use in

Bus-Organized Systems

• Applications:
Stacked Data Registers
Scratch-Pad Memory
Buffer Storage Between Processors ~W';,~E~CLOCK~~GND
nniT~ t:NA~Lt:: uATA Ht-AU UUiPUTS
ADDRESS INPUTS ADDRESS
Fast Multiplication Schemes

description positive logic: see description

The SN74172, containing the equivalent of 201 gates

on a monolithic chip, is a high-performance 16-bit
register file organized as eight words of two bits each.

Multiple address decoding circuitry is used so that the

read and write operation can be performed indepen-
dently on two word locations. This provides a true

•
simultaneous read/write capability. Basically, the file
consists of two distinct sections (see Figure A).

Section 1 permits the writing of data into any two-bit I

I
I I
word location while reading two bits of data from I

.
1411 '1 101
10

----------~
another location simu Itaneously. To provide this I SWORD

flexibility, independent decoding is incorporated. ~-L----{=~=Hg-""~t""'-""-- -- 28IT

STORAGE

I
AEGISTE~ I
I I
I
I
I
Section 2 of the register file is similar to section I
I I
I I
with the exception that common read/write address I 8UN~i~Ll LINE I
MULTIPLEXER 113) lOA
circuitry is employed. This means that section 2 can I
I
be utilized in one of three modes: I
1111)20e

1) Writing new data into two bits

2) Reading from two bits
3) Writing into and simultaneously ~
ADDRESS
reading from the same two bits. WRITE/READ
2W1"

Regardless of the mode, the operation of section 2 is FIGURE A

entirely independent of section 1.

1272

TEXAS INSTRUMENTS 7-245

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPE SN74172
16-81T MULTIPLE-PORT REGISTER FILE WITH 3-STATE OUTPUTS

description (continued)

The three-state outputs of this register file permit connection of up to 129 compatible outputs and one Series 54/74
high-logic-level load to a common system bus. The outputs are controlled by the read-enable circuitry so that they
operate as standard TTL totem-pole outputs when the appropriate read-enable input is low or they are placed in a
high-impedance state when the associated read-enable input is at a high logic level. To minimize the possibility that two
outputs from separate register files will attempt to take a common bus to opposite logic levels, the read-enable circuitry
is designed such that disable times are shorter than enable times.

All inputs are buffered to lower the drive requirements of the clock, read/write address, and write-enable inputs to one
normalized Series 54/74 load, and of all other inputs to one-half of one normalized Series 54/74 load.

Functions of the inputs and outputs of the SN74172 are as shown in the following table.

FUNCTION SECTION 1 SECTION 2 DESCRIPTION

Binary write address selects one of eight two-bit
Write Address 1WO, 1W1, 1W2 2W/RO, 2WIR1, 2W/R2
word locations.

When low, permits the writing of new data into

Write Enable 1GW 2GW the selected word location on a positive transition
of the clock input.

Data at these inputs is entered on a positive

transition of the clock input into the location
selected by the write address inputs if the write
enable input is low. Since the two sections are
independent, it is possible for both write functions
Data Inputs lOA, lOB 2DA,2DB to be activated with both write addresses selecting
the same word location. If this occurs and the

•
information at the data inputs is not the same for
both sections (i.e., lOA 01= 2DA and/or
1DB 01= 2DB) the low-level data will predominate
in each bit and be stored.

Common with Binary write address selects one of eight two-bit

Read Address lRO, lRl, lR2
write address word locations.

When read enable is low, the outputs assume the

Read Enable lGR 2GR levels of the data stored in the location selected by
read address inputs. When read enable is high, the
associated outputs remain in the high-impedance
Data Outputs state and neither significantly load nor drive the
lOA, lOB 20A,20B
lines to which they are connected.

The positive-going transition of the clock input

will enter new data into the addressed location if
Clock CK
the write enable input is low_ The clock is
common to both sections.

572

7·246 TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPE SN74172
16-81T MULTIPLE-PORT REGISTER FILE WITH 3-STATE OUTPUTS

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage (see Note 1) 7V
Input voltage .. . . . 5.5V
Output voltage (see Note 2) 5.5V
Operating free-air temperature range O°C to 70°C
Storage temperature -65°C to 150°C
NOTES: 1. Voltage values are with respect to network ground terminal.
2. This is the maximum voltage which should be applied to any output when it is in the high·impedance state.

recommended operating conditions

MIN NOM MAX UNIT
Supply voltage, Vee 4.75 5 5.25 V
High-level output current, 10H -5.2 mA
Low-level output current, 10L 16 mA
Clock frequency, f clock 0 20 MHz
Width of clock pulse, tw(clock) 25 ns
I Write select t w (dock)+10

I
Setup time, tsu(see Figure 1)
~1~H~i9~h~-le~v~e~ld~a~ta~~____3~0~__________~1 ns I
Low-ievei data 45
Write enable 35
Write select 0
Hold time, th(see Figure 1) ns
Write enable 0
High-level data 10
Data release time, trelease (see Figure 1) ns
Low-level data 10
Operating free-air temperature, T A 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST eONDITIONSt MIN TYPt MAX UNIT

•
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
VIK Input clamp voltage Vee= MIN, II = -12 mA -1.5 V
Vee - MIN, VIH - 2 V,
VOH High-level output voltage 2.4 3 V
VIL = 0.8 V, 10H = -5.2 mA
Vee - MIN, VIH - 2 V,
VOL Low-level output voltage 0.2 0.4 V
VIL = 0.8 V, 10L = 16 mA
Vee = MAX, Va - 2.4 V 40
10(off) Off-state (high-impedance state) output current Il A
Vee = MAX, Va = 0.4 V -40
II Input current at maximum input voltage Vee - MAX, VI- 5.5V 1 mA
IIH High-level input current Vee = MAX, VI = 2.4 V 40 IlA
\2W/RO, 2W/Rl, 2W/R2,
-1.6
IlL LOW-level input current lGW, 2GW, or clock Vee = MAX, VI = 0.4 V mA
I Any other input -0.8
lOS Short-circuit output current § Vee = MAX -18 -55 mA
Vee - MAX, All inputs at 4.5 V,
ICC Supply current 112 170 mA
Outputs open

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAil typical values are at VCC = 5 V, TA = 25°C.
§Not more than one output should be shorted at a time.

1076

TEXASINCORPORATED
INSTRUMENTS 7-247
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPE SN74172
16-BIT MULTIPLE-PORT REGISTER FILE WITH 3-STATE OUTPUTS

switching characteristics, Vee = 5 V, TA = 25°e, RL = 400 n

TEST
PARAMETER MIN TYP MAX UNIT
CONDITIONS
f max Maximum clock frequency 20 MHz
tpLH Propagation delay time, low-to-high-Ievel output from read select 33 45
ns
tpHL Propagation delay time, high-to-Iow-Ievel output from read select 30 45
CL=50pF,
tpLH Propagation delay time, low-to-high-Ievel output from clock 35 50
See Figure 1 ns
tpHL Propagation delay time, high-to-Iow-Ievel output from clock 35 50
tZH Output enable time to high level 14 30
ns
tZL Output enable time to low level 16 30
tHZ Output disable time from high level CL = 5 pF, 6 20
ns
tLZ Output disable time from low level See Figure 1 11 20

PARAMETER MEASUREMENT INFORMATION

t---tw~
CLOCK~I 3V
~.5V ~::
READ
INPUT 1.5 V 1.5 V
1--.. ,0",- t.u -I--------Ov
ENABLE
INPUT
WRITE ____ ~ISeeNot.CI~----3V i---1ZL---I t-ILZ"""1

SELECT
INPUTS ' '1.5
-V __________ L , 1.5 V ov WAVEFORM'
I
: 51 closed.
t----~4.5V
~'.5V
1
~"".5V
:
: ~~:~
I----tsu-
(See Note BI ,520oon ~ ~==*--.VOL

DATA INPUT
i~'!!~----3V
Y. v 15 V'-i I
~ tZH------!
: ~ tHZ-: 0.5 v 0.5 v
-----.1;.::';---- VOH
(HIGH·LEVEL D A T A l - - . / ' 1.5
It
I
. ."'\. I 0V
tsu --------..
~ ...- 3V
WAVEFORM 2
(See Note B)
Slopen,
52 closed F 1.SV
:::;0 V
'~::::"1.5V
51 and
S2c1osed

DATA INPUT ~.5V 1.5~ : ENABLE AND DISABLE TIMES FROM READ ENABLE
(LOW·LEVEL DATAl .l-------OV
~th

WRITE

~~~i:
~
1.5V
tsu ":
:
)<
-~:.::'---OV
3V
NOTES: A. Input waveforms are supplied by pulse generators
having the following characteristics: tr';;; 7 ns,
tf';;; 7 ns, PRR = 1 MHz, Zout '" 50 f2.
____________________~r---~_LH~~--VOH
B. Waveform 1 is for an output with internal conditions
; 1.5"x such that the output is low except when disabled.
OUTPUT

•
I ""--VOL
Waveform 2 is for an output with internal conditions
I--~LH-t
:/:,,:"1 VOH such that the output is high except when disabled.
OUTPUT /,.5V C. Write select setup time, as specified, will protect data
------------------------~ -VOL
written into previous address.
D, Load circuit is shown on page 3-10,
SWITCHING TIMES FROM CLOCK INPUT

VOLTAGE WAVEFORMS
FiGURE i
schematics of inputs and outputs
EaUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS

----41~-- V CC

OUTPUT

2W/RO, 2W/R1, 2W/R2,

1GW, 2GW, or Clock: Req =4 kf2 NOM
Other inputs: Req =8 kf2 NOM

1076

7·248 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TTL TYPES SN54173, SN54LS173, SN74173, SN74LS173
MSI 4-81T O-TYPE REGISTERS WITH 3-STATE OUTPUTS
BULLETIN DL-S 7611721 OCTOBER 1976

• Three-State Outputs Interface Directly

with System Bus
SN54173, SN54LS173 ••• J OR W PACKAGE
• Gated Output-Control Lines for Enabling or SN74173, SN74LS173 ••• J OR N PACKAGE
Disabling the Outputs (TOP VIEW)

• Fully Independent Clock Virtually DATA ENABLE

DATA INPUTS INPUTS
Eliminates Restrictions for Operating in One
of Two Modes: VCCCLEAR~~
Parallel Load
Do Nothing (Hold)
• For Application as Bus Buffer Registers

TYPICAL MAXIMUM TYPICAL

TYPE PROPAGATION CLOCK POWER
DELAY TIME FREQUENCY DISSIPATION
'173 23 ns 35 MHz 250mW

L.!.Jt..!JL!JLiJ~L!JL.?JL.!J
'LS173 18 !1S 50 ~.l!Hz 85m\AJ

~ ,10 20 30 40, CLOCK GND

description OUTPUT CONTROL OUTPUTS

The '173 and 'LS173 four-bit registers include D-type

flip-flops featuring totem-pole t~ree-state out-puts positive logic: see function table
capable of driving highly capacitive or relatively
low-impedance loads. The high-impedance third state
and increased high-logic-level drive provide these
flip-flops with the capability of being connected FUNCTION TABLE
directly to and driving the bus lines in a bus-organized
system without need for interface or pull-up compo-
I~un
I-----r----.----=------.----I OUTPUT I I
DATA ENABLE DATA
CLEAR CLOCK Q
nents. Up to 128 of the SN74173 or SN74LS173 G1 G2 D

•
outputs may be connected to a common bus and still H X X X X L
drive two Series 54/74 or 54LS/74LS TTL normal- L L X X X 00
ized loads, respectively. Simi larly, up to 49 of the L t H X X QO
SN54173 or SN54LS173 outputs can be connected L t X H X QO
to a common bus and drive one additional Series L t L L L L
54/74 or 54LS/74LS TTL normalized load, respec- L t L L H H
tively. To minimize the possibility that two outputs
will attempt to take a common bus to opposite logic When either M or N (or both) is (are) high the output is
disabled to the high-impedance state; however sequential
levels, the output control circuitry is designed so that operation of the flip-flops is not affected.
the average output disable times are shorter than the
average output enable times.
Gated enable inputs are provided on the '173 and 'LS173 for controlling the entry of data into the flip-flops. When
both data-enable inputs are low, data at the D inputs are loaded into their respective flip-flops on the next positive
transition of the buffered clock input. Gate output control inputs are also provided. When both are low, the normal
logic states (high or low levels) of the four outputs are available for driving the loads or bus lines. The outputs are
disabled independently from the level of the clock by a high logic level at either output control input. The outputs then
present a high impedance and neither load nor drive the bus line. Detailed operation is given in the function table.
Higher density D-type registers, some with improved performance and including the new octal D-type registers,
are shown in the functional index/selection guide, see pages 1-11 and 1-12.

1076

TEXAS INSTRUMENTS 7-249

INCORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54173, SN54LS173, SN74173, SN74LS173
4-81T O-TYPE REGISTERS WITH 3-STATE OUTPUTS

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, Vee (see Note 1) . 7V

Input voltage: '173 . . 5.5 V
'LS173 . . . . . .7 V
Off·state output voltage 5.5 V
Operating free-air temperature range: SN54173, SN54LS173 -55°C to 125°C
SN74173,SN74LS173 aOe to 7aoe
Storage temperature range -65°C to 15aoe
NOTE 1: Voltage values are with respect to network ground terminals.

functional block diagram and schematics of inputs and outputs

(11 VCC - '173

EaUIVALENT OF EACH INPUT

Q
OUTPUT M

CONTROL N
4 kfl NOM
{

INPUT --

~
OATA '
ENABLE TYPICAL OF ALL OUTPUTS
G2

OAT A .:.:..::::'-----+----+--1
20

• 'LS173
EaUIVALENT OF EACH INPUT

vee---T--

IN'UTO--
~ 20 kfl NOM

TYPICAL OF ALL OUTPUTS

1'51 ,Vee

OUTPUT

-<t>....
1
dynamic input activated by a transition from a high level to a low level.
I

1076

7·250 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54173, SN74173
4-81T O-TYPE REGISTERS WITH 3-STATE OUTPUTS

recommended operating conditions

SN54173 SN74173
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High·level output current, 10H -2 -5.2 mA
Low-level output current, 10L 16 16 mA
Input clock frequency, fclock 0 25 0 25 MHz
Width of clock or clear pulse, tw 20 20 ns
Data enable 17 17
Setup time, tsu Data 10 10 ns
Clear inactive state 10 10
Data enable 2 2
Hold time, th ns
Data 10 10
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONSt I MIN TYP:j: MAX IUNITI
High-level input voltage
Loy".-Ievel input voltage I 2 o.J ~ I
V IK I nput clamp voltage Vee = MIN, 11- -12 mA -1.5 V
Vee = MIN, VIH=2V,
VOH High-level output voltage 2.4 V
VIL = 0.8 V, 10H = MAX
Vee= MIN, VIH~2V,
VOL Low-Ievei output voltage 0.4 V
VIL = 0.8 V, 10L = 16 mA

10(off) Off-state (high-impedance state) output current

Vee-MAX, I VO-2.4V 40
JJ-A
VIH = 2 V I V o=O.4V -40
I nput current at maximum input voltage I Vee = MAX, V I = 5.5 V 1 I mA
IH H'19h -level input current I V ee = MAX V 1-
- 24 V
IlL Low-level input current Vee - MAX, VI - 0.4 V -1.6 mA

•
lOS Short-circuit output currend Vee = MAX -30 -70 mA
ICC Supply current Vee= MAX, See Note 2 50 72 mA

tFor ~onditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions.
:j:AII tYpical values are at V CC = 5 V, T A = 25° C.
§ Not more than one output should be shorted at a time.
NOTE 2: ICC is measured with all outputs open; clear grounded following momentary connection to 4.5 V; N, G1, G2, and all data inputs
grounded; and the clock input and M at 4.5 V. '

'switching characteristics, Vee = 5 V, TA = 25°e, RL = 400 Q

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

f max Maximum clock frequency 25 35 MHz
tpHL Propagation delay time, high-to-Iow-Ievel output from clear input 18 27 ns
tPLH Propagation delay time, low-to·high-Ievel output from clock input eL = 50 pF, 28 43
ns
tpHL 'Propagation delay time, high-to-Iow-Ievel output from clock input See Note 3 19 31
tPZH Output enable time to high level 7 16 30
ns
tPZL Output enable time to low level 7 21 30
tPHZ Output disable time from high level eL=5pF, 3 5 14
ns
tPLZ Output disable time from low level See Note 3 3 11 20

NOTE 3: Load circuits and voltage waveforms are shown on page 3-10.

1076

TEXAS INCORPORATED
INSTRUMENTS 7-251
POST OFFICE B?X 5012 • DALLAS. TEXAS 75222
 TYPES SN54LSI73, SN74LS173
4-81T O-TYPE REGISTERS WITH 3-STATE OUTPUTS

recommended operating conditions

SN54LS173 SN74LS173
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, IOH -1 -2.6 mA
Low-level output current, IOL 12 24 mA
Input clock frequency, fclock 0 30 0 30 MHz
Width of clock or clear pulse, tw 20 20 ns
Data enable 17 17
Setup time, tsu Data 17 17 ns
Clear inactive state 10 10
Data enable 0 0
Hold time, th ns
Data 0 0
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS173 SN74LS173
PARAMETER TEST CONDITIONSt UNIT
MIN TYPt MAX MIN TYPt MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
VIK Input clamp voltage Vee = MIN, 11=-18mA -1.5 -1.5 V
Vee = MIN, VIH - 2 V,
VOH High-level output voltage 2.4 3.4 2.4 3.1 V
VIL = VILmax 10H = MAX
Vee = MIN, 10L = 12 mA 0.25 0.4 0.25 0.4
VOL Low-level output voltage V
VIL=0.8V 10L - 24 mA 0.35 0.5
Vee = MAX, VO=2.7V 20 20
10(off) Off-state (high-impedance state) output current IJA
VIH = 2 V Va = 0.4 V -20 -20
II Input current at maximum input voltage Vee = MAX, VI =7 V 0.1 0.1 mA
IIH High-level input current Vee = MAX, VI=2.7V 20 20 IJA

•
IlL Low-level input current Vee = MAX, VI = 0.4 V -0.4 -0.4 mA
lOS Short-circuit output current§ Vee = MAX -30 -130 -30 -130 mA
lee Supply current Vee = MAX, See Note 2 17 30 17 30 mA

t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAli typical values are at Vee = 5 V, T A = 25°C.
§ Not more than one output shouid be shorted at a time.
NOTE 2: ICC is measured with all outputs open; clear grounded following momentary connection to 4.5 V; N, G 1. G2, and all data inputs
grounded; and the clock input and Mat 4.5 V.

switching characteristics, Vee = 5 V, TA = 25°e, RL = 667 n

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f max Maximum clock frequency 30 50 MHz
tPHL Propagation delay time, high-to-Iow-Ievel output from clear input 20 30 ns
tPLH Propagation delay time, low-to-high-Ievel output from clock input eL=45pF, 16 29
ns
tPHL Propagation delay time, high-to-Iow-Ievel output from clock input See Note 4 20 30
tpZH Output enable time to high level 13 21
ns
tpZL Output enable time to low level 24 36
tPHZ Output disable time from high level eL=5pF, 11 17
ns
tPLZ Output disable time from low level See Note 4 15 23

NOTE 4: Load circuits and voltage waveforms are shown on page 3-11.

1076
DESIGN GOAL
7-252 This page provides tentative information on a TEXAS INSTRUMENTS
product in the developmental stage. Texas INCORPORATED
I nstruments reserves the right to change or dis- POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
continue this product without notice.
 TYPES SN54174, SN54175, SN54LS174, SN54LS175, SN54S174, SN54S175,
SN74174, SN74175, SN74LS174, SN74LS175, SN74S174, SN74S175
H-EX/QUADRUP~~D-TYPE FLIP-FLOPS WITH CLEAR
BULLETIN NO. DL·S 7611 DECEMBER 1972-REVISED OCTOBER 1976

'174, 'LS174, 'S174 ... HEX D-TYPE FLIP-FLOPS

'175, 'LS175, 'S175 ... QUADRUPLE D-TYPE FLIP-FLOPS
• '174, 'LS174, 'S174 Contain Six Flip-Flops SN54174, SN54LS174, SN54S174 ... J OR W PACKAGE
with Single-Rail Outputs SN74174, SN74LS174, SN74S174 ... J OR N PACKAGE
(TOP VIEW)
• '175, 'LS175, 'S175 Contain Four Flip-Flops
with Double-Rail Outputs Vee 6Q 60 50 50 40 4Q CLOCK

• Three Performance Ranges Offered: See

Table Lower Right
• Buffered Clock and Direct Clear Inputs
• Individual Data Input to Each Flip-Flop
• Applications include:
Buffer/Storage Registers
Shift Registers
Pattern Generators
IUL~,..,n IU iQ 2D 2Q 3D 30 GNU

description

These monolithic, positive-edge-triggered flip-flops

positive logic: see function table
utilize TTL circuitry to implement D-type flip-flop
logic. All have a direct clear input, and the '175,
'LS175, and 'S175 feature complementary outputs
from each flip-flops.
SN54175, SN54LS175, SN54S175 •. , J OR W PACKAGE
SN74175, SN74LS175, SN74S175 ... J OR N PACKAGE
Information at the D inputs meeting the setup time (TOP VIEW)
requirements is transferred to the Q outputs on the
positive-going edge of the clock pulse. Clock Vce 40 40 40 30 30 30 CLOCK
triggering occurs at a particular voltage level and is

•
not directly related to the transition time of the
positive-going pulse. When the clock input is at either
the high or low level, the D;input signal has no effect
at the output.

These circuits are fully compatible for use with most

TTL or DTL circuits.

FUNCTION TABLE
CLEAR 10 10 10 20 20 20 GNO
(EACH FLIP-FLOP)
INPUTS OUTPUTS
CLEAR CLOCK D Q Qt
L X X L H positive logic: see function table
H t H H L
H t L L H
H L X Qo 00
TYPICAL TYPICAL
H = high level (steady state) MAXIMUM POWER
TYPES
L = low level (steady state) CLOCK DISSIPATION
X = irrelevant FREQUENCY PER FLIP-FLOP
t = transition from low to high level
'174, '175 35MHz 38mW
Q
O = the level of Q before the indiCated steadY'state
input conditions were established. 'LS174, 'LS175 40MHz 14mW
t = '175, 'LS175, and 'S175 only 'S174, 'S175 110MHz 75mW

1076 .

TEXAS INSTRUMENTS 7-253

INCORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54174, SN54175, SN54LS174, SN54LS175, SN54S174, SN54S175,
SN74174, SN74175, SN74LS174, SN74LS175,SN74S174, SN74S175
HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

functional block diagrams

'174, 'LS174, 'S174

10..;.13;;;.l_ _ _ _ _ _-I

'175, 'LS175, 'S175

14l
10

20 ...;,14.;;..l_ _ _ _-+-+-I 20

15l
20 20

30 ...;,16;.;..l_ _ _ _ -+-+-I 30

(12) (10)
3D 30

111l
40 40

• 50 ..:..(1;;:;:3):..-._ _ _---+-I-~
50
40

CLEAR
(15)

(14)
40

40

60 ...;,1,;.;,14;..,.l_ _ _ _+--1-1
60

I
I
--¢> ... dynamic input activated by transition from a high level to a low level.

I
I

1272

7-254 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54174, SN54175, SN54LS174, SN54LS175, SN54S174, SN54S175,
SN74174, SN74175, SN74LS174, SN74LS175, SN74S174, SN74S175
HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
REVISED OCTOBER 1976

schematics of inputs and outputs

SN54174,SN54175,SN74174,SN74175
__----------------------------___
EQUIVALENT OF ALL INPUTS
r---~--------------------------~
TYPICAL OF ALL OUTPUTS

---VCC
VCC--e__-

INPUT

OUTPUT

~--~
Clock, D: Req
Clear: Req
=8
=4
k.\1 NOM
k.\1 NOM
II ------------"
rh

SN54LS174,SN54LS175,SN74LS174,SN74LS175
__------------------------------_
EQUIVALENT OF ALL INPUTS
r----~~----------------------__,
TYPICAL OF ALL OUTPUTS

VCC~-- --aVCC
120.\1
Req NOM

INPUT --

W '---+--OUTPUT

II
Clock: Req = 17 k.\1 NOM
Clear, D: Req = 20 k.\1 NOM

SN54S174, SN54S175, SN74S174, SN74S175,.

~-------E-Q-UI-V-AL-E-N-T~b-FA-L-L-IN-P-U-TS--------- r-----~--T~Y~P~IC-AL-O~F~A-L-L-O~UT~P~U~TS~-------,

- - - - - - : : - + - - V CC

V cc-----4..---

INPUT
'---+--OUTPUT

1076

TEXAS INSTRUMENTS 1-255

INCORPORATED
POSi OFFICE BOX 5012 • DAL.LAS. TEXAS 75222
 TYPES SN54174, SN54175, SN74174, SN74175
HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1) 7V
Input voltage 5.5 V
Operating free-air temperature range: SN54174, SN54175 Circuits -55°C to 125°C
SN74174, SN74175 Circuits O°C to 70°C
Storage temperature range -65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54174, SN54175 SN74174, SN74175
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
'High-Ievel output current, 10H -800 -SOO IlA
Low-level output current, 10L 16 16 mA
Clock frequency, fclock 0 25 0 25 MHz
Width of clock or clear pulse, tw 20 20 ns

Setup time, tsu

I Data input 20 20 ns
I Clear inactive-state 25 25 ns
Data hold time, th 5 5 ns
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONSt MIN TYP:f: MAX UNIT
VIH High-level input voltage 2 V
VIL Low-level input voltage O.S V
VIK Input clamp voltage Vee= MIN, 11=-12mA -1.5 V
Vee= MIN, VIH = 2V,
VOH High-level output voltage 2.4 3.4 V
VIL = O.S V, 10H = -SOOIlA
Vee = MIN, VIH = 2 V,

•
VOL Low-level output voltage 0.2 0.4 V
VIL = O.S V, 10L = 16 mA
II I nput current at maximum input voltage Vee = MAX, VI=5.5V 1 mA
IIH High-level input current Vee = MAX, VI = 2.4 V 40 Il A
IlL Low-level input current Vee = MAX, VI = 0.4 V -1.6 mA

lOS Short-circuit output currentS Vee = MAX

I SN54' -20 -57
rnA
I SN74' , -18 -57
45 65
lee Supply current Vee = MAX, See Note 2 I1'174
'175 30 45
rnA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device
type.
tAli typical values are at Vee =5 V, T A = 25° e.
§ Not more than one output should be shorted at a time.
NOTE 2: With all outputs open and 4.5 V applied to all data and clear inputs, lec is measured after a momentary ground, then 4.5 V, is
applied to clock.

switching characteristics, Vee = 5 V, TA = 25°e

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f max Maximum clock frequency 25 35 MHz
Propagation delay time, low-to-high-Ievei output from clear
tPLH eL=15pF, 16 25 ns
(SN54175, SN74175 only)
RL=400n,
tpHL Propagation delay time, high-to-Iow-Ievel output from clear 23 35 ns
See Note 3
tpLH Propagation delay time, low-to-high-Ievel output from clock 20 30 ns
tpHL Propagation delay time, high-to-Iow-Ievel output from clock 24 35 ns

NOTE 3: Load circuit and voltage waveforms are shown on page 3-10.

1076

7-256 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54LS174. SN54LS175, SN74LS174, SN74LS175
HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
REVISED OCTOBER 1976

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) .............. . 7V
Input voltage . . . . . . . .............. . 7V
Operating free-air temperature range: SN54LS174, SN54LS175 Circuits -55°C to 125°C
SN74LS174, SN74LS175 Circuits aOc to 7aoC
Storage temperature range -65°C to 15aoC
NOTE 1: Voltage values are with respect to network ground terminal.
recommended operating conditions
SN54LS174 SN74LS174
SN54LS175 SN74LS175 UNIT
Mll\I NOM MAX MIN NOM MAX
Supply voltage, VCC 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -400 -400 jl.A
Low-level output current, 10L 4 8 mA
Clock frequency, fclock 0 30 0 30 MHz
Width of clock or clear pulse, tw 20 20 ns

Setup time, tsu

I Data Input ")1'\ ")1'\
...
I Clear inactive-state 25 25 ns
Data hold time, th 5 5 ns
Operating free-air temperature, T A -55 125 0 70 DC

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS174 SN74LS174
PARAMETER TEST eONDITIONSt SN54LS175 SN74LS175 UNIT
MIN TYP:j: MAX MIN TYP:j: MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
VIK Input clamp voltage Vee; MIN, i l ; -18mA -1.5 -1.5 V
Vee; MIN, VIH;2V,
VOH High-level output voltage 2.5 3.5 2.7 3.5 V
VIL;VILmax,IOH;-400!LA

•
Vec; MIN, VIH;2V, IIOL;4 mA 0.25 0.4 0.25 0.4
VOL Low-level output voltage V
VIL; VIL max IIOL; 8mA 0.35 0.5
Input current at
II Vec; MAX, VI;7 V 0.1 0.1 mA
maximum input voltage
IIH High-level input current Vee; MAX, VI; 2.7 V 20 20 !LA
IlL Low-level input current Vee; MAX, VI; 0.4 V -0.4 -0.4 mA
lOS Short-circuit output current§ Vce; MAX -20 -100 -20 -100 mA
I'LS174 16 26 16 26
lee Supply current Vee; MAX, See Note 2 mA
I 'LS175 11 18 11 18

t For conditions shown as M IN or MAX, use the appropriate value specified under recommended operating conditions.
D
:j:AII typical values are at Vce; 5 V, T A = 25 e.
§ Not more than one output should be shorted at a time, and duration of the short·circuit should not exceed one second.
NOTE 2: With all outp'uts open and 4.5 V applied to all data and dear inputs, lee is measured after a momentary ground, then 4.5 V, is
applied to clock.

switching characteristics, Vee = 5 V, TA = 25°e

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f max Maximum clock frequency 30 40 MHz
Propagation delay time, low-to-high-Ievel output from clear
CL = 15pF, 16 25 ns
tPLH (SN54LS175, SN74LS175 only)
RL=2kn,
tPHL Propagation delay time, high-to-Iow-Ievel output from clear 23 35 ns
See Note 4
tPLH Propagation delay time, low-to-high-Ievel output from clock 20 30 ns
tpHL Propagation delay time, high-to-Iow-Ievel output from clock 21 30 ns
NOTE 4: Load circuit and voltage waveforms are shown on page 3-11.

1076

TEXAS INSTRUMENTS 7-257

INCORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54S174, SN54S175, SN74S174, SN74S175
HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

absolute maximum ratings over operating free-air temperature_range (unless otherwise noted)
Supply voltage, VCC (see Note 1) ............. . 7V
Input voltage . . . . . . . . . . . . . . . . . . . . . . 5.5V
Operating free-air temperature range: SN54S174, SN54S175 Circuits -55°C to 125°C
SN74S174, SN74S175 Circuits . aOc to 7aoC
Storage temperature range -65°C to 15aoC
NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54S174, SN54S175 SN74S174, SN74S175
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vec I 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -1 -1 mA
Low-level output current, 10L 20 20 mA
Clock frequency, fclock 0 75 0 75 MHz
Clock 7 7
Pulse width, tw ns
Clear 10 10
Data input 5 5
Setup time, tsu ns
Clear inactive-state 5 5
Data hold time, th 3 3 ns
Operating free-air temperature, T A -55 125 0 70 °c

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONSt MIN TYP+ MAX UNIT
VIH High-level input voltage 2 V
V 11.,- Low-level input voltage 0.8 V
VIK Input clamp voltage VCC; MIN, II; -18mA -1.2 V
VCC; MIN, VIH; 2 V, I SN54S' 2.5 3.4
V
VOH High-level output voltage
VIL; 0.8 V, 10H; -1 mA ISN74S' 2.7 3.4

• VOL

II
IIH
IlL
lOS

lee
Low-level output voltage

Input current at maximum input voltage

High-level input current
Low-level input current
Short-circuit output current§

Supply current
VCC; MIN,
VIL

VCC
= 0.8 V,

Vcc; MAX
VIH;2V,
10L; 20mA
VCC; MAX, VI; 5.5 V
Vce; MAX, VI;2.7V
= MAX, VI; 0.5 V

Vec; MAX, See Note 2

1'174
1'175
-40
90
60
0.5

50
-2
-100
144
96
1
V

mA
IJ.A
mA
mA

mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device
type.
+AII typical values are at Vee; 5 V, T A; 25°C.
§ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
NOTE 2: With all outputs open and 4.5 V applied to all data and clear inputs, ICC is measured after a momentary ground, then 4.5 V, is
applied to clock.

switching characteristics, Vee;:;:: 5 V, TA ;:;: 25°e

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f max Maximum clock frequency 75 110 MHz
Propagation delay time, low-to-high-Ievel Q output from clear
tpLH CL = 15pF, 10 15 ns
(SN54S175, SN74S175 only)
RL;280n,
tpHL Propagation delay time, high-to-Iow-Ievel Q output from clear 13 22 ns
See Note 3
tPLH Propagation delay time, low-to-high-Ievel output from clock 8 12 ns
tpHL Propagation time, high-to-Iow-Ievel output from clock 11.5 17 ns

NOTE 3: Load circuit and voltage waveforms are shown on page 3-10.

PR!NTED IN U.S A
1076

7-258 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54176, SN54m, SN74176, SN74177
TTL
35-MHz PRESETTABLE DECADE AND
MSI BINARY COUNTERS/LATCHES
BULLETIN NO. DL-S 7211478, MAY 1971-REVISED DECEMBER 1972

SN54176, SN54177 ••• J OR W PACKAGE

SN74176, SN74177 ••• J OR N PACKAGE
__ (TOP VI EW)

CLOCK
VCC CLEAR 0D Os 1
• Reduced-Power Versions of SN54196, SN54197,
SN74196, and SN74197 50-MHz Counters

• D-C Coupled Counters Designed to Replace Signetics

8280,8281,8290, and 8291 Counters in Most
Applications

• Performs BCD, Bi-Quinary, or Binary Counting

• Fully Programmable

• Fully Independent Clear Input

• Guaranteed to Count at Input Frequencies

from 0 to 35 MHz

• Input Clamping Diodes Simplify System Design

asynchronous input: Low input to clear sets 0A,
OS, 0C, and 0D low.

description

These high-speed monolithic counters consist of four d-c coupled m"lster-slave flip-flops which are internally
interconnected to provide either a divide-by-two and a divide-by-five counter (SN54176, SN74176) or a divide-by-two
and a divide-by-eight counter (SN54177, SN74177). These counters are fully programmable; that is, the outputs may
be preset to any state by placing a low on the count/load input and entering the desired data at the data inputs. The
outputs will change to agree with the data inputs independent of the state of the clocks.

These counters may also be used as 4-bit latches by using the count/load input as the strobe and entering data at the
data inputs. The outputs will directly follow the data inputs when the count/load is low, but will remain unchanged
when the count/load is high and the clock inputs are inactive.
•
These high-speed counters will accept count frequencies of a to 35 megahertz at the clock-1 input and a to 17.5
megahertz at the clock-2 input. During the count' operation, transfer of information to the outputs occurs on the
negative-going edge of the clock pulse. The counters feature a direct clear which when taken low sets all outputs low
regardless of the states of the clocks.

All inputs are diode-clamped to minimize transmission-line effects and simplify system design. The circuits are
compatible with most TTL and DTL logic families. Typical power dissipation is 150 milliwatts. The SN54176 and
SN54177 circuits are characterized for operation over the full military temperature range of -55°C to 125°C; the
SN74176 and SN74177 circuits are characterized for operation from aOe to 70°C.

1076

TEXAS INSTRUMENTS 7-259

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54176. SN54ID. SN74176. SN741n
35-MHz PRESETTABLE DECADE AND
BINARY COUNTERS/LATCHES

typical count configurations

SN54176 and SN74176 SN54176, SN74176

FUNCTION TABLES
The output of flip-flop A is not internally connected
DECADE (BCD) BI-aUINARY (5-2)
to the succeeding flip-flops; therefore, the count may
(See Note A) (See Note B) .
be operated in three independent modes:
OUTPUT OUTPUT
1. When used as a binary·coded·decimal decade COUNT COUNT
counter, the clock-2 input must be externally aD ac aB aA aA aD ac aB
0 L L L L 0 L L L L
connected to the ~ output. The clock-1 input
1 L L L H 1 L L L H
receives the incoming count, and a count
2 L L H L 2 L L H L
sequence is obtained in accordance with the
BCD count sequence function table shown at 3 L L H H 3 L L H H

right. 4 L H L L 4 L H L L
5 L H L H 5 H L L L
2. If a symmetrical divide-by-ten count is desired 6 L H H L 6 H L L H
for frequency synthesizers (or other appli- 7 L H H H 7 H L H L
cations requiring division of a binary count by 8 H L L L 8 H L H H
a power of ten), the OD output must be 9 H L L H 9 H H L L
externally connected to the clock-1 input. The
H = high level, L = low level
input count is then applied at the clock-2 input NOTES: A. Output QA connected to clock-2 input.
and a divide-by-ten square wave is obtained at B. Output QO connected to clock-1 input.
output OA in accordance with the bi-quinary
function· table.
3. For operation as a divide-by-two counter and a divide-by-five counter, no external interconnections are required.
Flip-flop A is used as a binary element for the divide-by-two function. The clock-2 input is used to obtain binary
divide-by-five operation at the OB, OC, and OD outputs. In this mode, the two counters operate independently;
however, all four flip-flops are loaded and cleared simultaneously.

•
SN54177, SN74177
SN54177 and SN74177 FUNCTION TABLE
(See Note A)
The output of flip-flop A is not internally connected to the succeeding flip-flops,
OUTPUT
therefore the counter may be operated in two independent modes: COUNT
aoacas aA
1. When used as a high-speed 4-bit ripple-through counter, output OA must be I
0 'L L L L
externally connected to the clock-2 input. The input count pulses are applied to 1 L L L H
the clock-1 input. Simu Itaneous divisions by 2, 4, 8, and 16 are performed at the 2 L L H L
OA, OB, Qc, and OD outputs as shown in the function table at right. 3 L L H H

2. When used as a 3-bit ripple-through counter, the input count pulses are applied 4 L H L L

to the clock-2 input. Simultaneous frequency divisions by 2, 4, and 8 are 5 L H L H

available at the OB, OC, and OD outputs. Independent use of flip-flop A is 6 L H H L

available if the load and clear functions coincide with those of the 3-bit 7 L H H H

ripple-through counter. 8 H L L L
9 H L L H
10 H L H L
11 H L H H
12 H H L L
13 H H L H
14 H H H L
15 H H H H
H = high level, L = low level
NOTE A: Output QA connected
to clock-2 input.

1272

1-260 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DAL.L.AS, TEXAS 75222
 TYPES SN54176, SN54m, SN74176, SN74177
35-MHz PRESETTABLE DECADE AND
BINARY COUNTERS/LATCHES
functional block diagrams

., Q
o "
o o
§ §
~

.....
.....
:;;:
.....
z
en
~.
:;;: I
~ 1~I+I--,+I---4~--~---+~------~~------~

. oRf.l
., u Q

•
o o o
§ § §
~ 1 ~
E
CD

« ., u Q Q
s
1
0 0 0 0 10
>-

rj ~~
~~
rj
a:

J~
~
~ ~~ .r::
"'" "'"
OJ
>- , /\ , :c
CD

J
Q c
0
E
.g
";;

"!
"" ("" J '" >
.0

e
m 11 1] m ~
~
:J

M.
C.
C

"~"
>
"0
~ ~ ~ § -

--+--
1272

TEXAS INCORPORATED
INSTRUMENTS 7-261
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54176, SN54m, SN74176, SN741n
35-MHz PRESETTABLE DECADE AND
BINARY COUNTERS/LATCHES
schematics of inputs and outputs
EQUIVALENT OF COUNT/LOAD, EQUIVALENT OF CLOCK INPUTS TYPICAL OF ALL OUTPUTS
CLEAR, AND DATA INPUTS

VCC----+------ --+-_VCC

OUTPUT

NOMINAL VALUES OF
R1, R2, and R3
INPUT '176 '177
Data, Count/load: Req =4 kn NOM Clock 1 4 kn 4 kn
Clear: Req =2 kn NOM Clock 2 4 kn 6 kn

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, VCC (see Note 1) 7V

Input voltage . . . . . . . 5.5 V
Interemitter voltage (see Note 2) 5.5 V
Operating free-air temperature range: SN54176, SN54177 Circuits -55°C to 125°C
SN74176, SN74177 Circuits O°C to 70°C
Storage temperature range -65°C to 150°C

NOTES: 1. Voltage values are with respect to network ground terminal.

2. This is the voltage between two emitters of a multiple-emitter transistor. For this circuit, this rating applies between the clear and

•
countlload inputs .

recommended operating conditions

MIN NOM MAX UNIT
SN54' 4.5 5 5.5
, Supplv voltage. Vee V
I SN74' . -
, 47r::.
- -.-
High-level output current, IOH -800 I /lA
low-level output current, IOl 16 mA
Clock-1 input 0 35
Count frequency (see Figure 1) MHz
Clock-2 input 0 17.5
Clock-1 input 14

Pulse width, tw (see Figure 1)

Clock-2 input 28 I ns
Clear 20
load 25
High-level data tw(load)
Input hold time, th (see Figure 1) ns
low-level data tw(load)
High-level data 15
Input setup time, tsu (see Figure 1) ns
low-level data 20
Count enable time, tenable (see Note 3 and Figure 1) 25 ns
SN54' -55 125
Operating free-air temperature, T A °c
SN74' 0 70

NOTE 3' Minimum count enable time is tl1e interval immediatelv preceding the negative-going edge of the clock oulse during which interval the
count/load and clear inputs must both be high to ensure counting,

1272

7-262 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 15222
 TYPES SN54176, SN54ffl, SN74176, SN74177
35-MHz PRESETTABLE DECADE AND
BINARY COUNTERS/LATCHES
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54176, SN74176 SN54117, SN74117
PARAMETER TEST CONDITIONSt UNIT
MIN TYP:j: MAX MIN TYP:j: MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
VIK I nput clamp voltage VCC- MIN, 11--12mA -1.5 -1.5 V
VCC = MIN, V!H=2V,
VOH High-level output voltage 2.4 3.4 2.4 3.4 V
VIL = 0.8 V, IOH = -800/lA
VCC= MIN, VIH = 2 V,
VOL Low-level output voltage 0.2 0.4 0.2 0.4 V
VIL = 0.8 V, IOL = 16 mA~
II Input current at maximum input voltage VCC- MAX, VI - 5.5 V 1 1 rnA
Data, count/load 40 40
IIH High-level input current Clear, clock 1 VCC= MAX, VI = 2.4 V 80 80 /lA
Clock 2 120 80
Data, count!!oad -11> -11>

IlL Low-level input current

Clear
Clock 1
VCC = MAX, VI = 0.4 V ~;
-4.8
1 -;;1
-4.8
rnA
1 I Glock 2
1 1
I
~.

-4.~
Short-circuit output currentS VCC = iviAX
I SN54,1-20 -57 -20
iOS
SN74' -18 -57 -18
ICC Supply current VCC = MAX, See Note 4 30 48 30

NOTE 4: I ee is measured with all inputs grounded and all outputs open.
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

:j:AII typical values are at Vee = 5 V, T A = 25°e.

~ QA outputs are tested at IOL = 16 mA plus the limit value of II L for the clock-2 input. This permits driving the clock-2 input while fanning
out to 10 Series 54/74 loads.
§ Not more than one output shou Id be shorted at a time.

switching characteristics, Vee = 5 V, RL = 400 il, eL = 15 pF, TA = 25°e, see figure 1

PARAMETERO

f max
FROM (INPUT)

Clock 1
TO (OUTPUT)

QA
SN54176, SN74176 SN54117, SN54117
MIN
35
TYP
50
MAX MIN
35
TYP
50
MAX
UNIT

MHz
I
tPLH 8 13 8 13
Clock 1 QA ns
tpHL 11 17 11 17
tPLH 11 17 11 17
Clock 2 QS ns
tpHL 17 26 17 26
tpLH 27 41 27 41
Clock 2 QC ns
tpHL 34 51 34 51
tpLH 13 20 44 66
Clock 2 QD ns
tPHL 17 26 50 75
tpLH 19 29 19 29
A,S,C,D QA, QS, QC, QD ns
tpHL 31 46 31 46
tpLH 29 43 29 43
Load Any ns
tpHL 32 48 32 48
tpHL Clear Any 32 48 32 48 ns

Of max "" maximum count frequency

tPLH == propagation delay time, low-to~high-Ievel output
tpH L == propagation delay time, high-to-Iow-Ievel output

1076

TEXAS INSTRUMENTS 7-263

INCORPORATED
POST OFFICE BOX 5012 • OALLAS. TEXAS 75222
 ......
N
iii
...
C)

~ tW(CIOCkl.., CI:IW~
-U"I-<
Zl~
~~ ~, -
3.5 V
VCC CLOCK-' OR - - - 3.5 V
:J:Iti: m
CLOCK_2INPUy-,·5V ~
COUNT/LOAD
OR CLEAR .I! .
../" 5 V
::D:ccn
-<N
I 0 V ----I--------OV cn
..... tPLH.-I n~Z
FROM OUTPUT I 1 I ------3.5V C::DU"I
UNDER TEST OUTPUT I
I
FVOH
'.5 V CLOCK~' 1,.5V cm~
Zcn~

i
0A, 0B, DC, or 00 I
__________~I----~ INPUT I
I 1 OV ~mcn
t.-----.f- tPHL - - VOL m~ ..
LOAD CIRCUIT OUTPUT ---------\j.~ - - -- VOH
-I "0,,,,10-- VOH ::D~cn
OUTPUT cn;;Z
°A --,...U"I
;:m~
0A, 0B. DC, or 00 ,.5 V "tI
- - - - - VOL VOL »
CLOCK-MODE VOLTAGE WAVEFORMS CLOCK ENABLE TIME VOLTAGE »
::xl
~a9
n ..
~
['1'1
WAVEFORMS sm :C m
ncn
>< -I m:J:lt'Z
> ,----------------------------------------------------------------------3.5V m
::xl
cn a .....
m~
"'ID -
(J) s: .~
o CLEAR
Z_
m :J:It
~8Z -- -- - - - - - - - - - - - - - - - - - - - - - - - - ------OV » Z ..cn
~~(J) t- tsu --1
Cf)
c acn
0""; 3.5 V
::xl
~;o DATA INPUTS : I m
Z
~c:: A, B, C, AND 0 I S ~
03: 1
I I~-----OV m
2 9
['1'1
I I -I
-1- - _.J. - - - - - -
z
....; COUNT/LOAD
I
1
I
I
3.5 V
2
"T1
(J) INPUT
I"---J:~ \ I I OV
o
::xl
-I tPHL"-- r
I I
toe-- ..... J-- t.--..j tpHL 14- S
----"'\1
--.... tPLH
I
tPHL
I
-..j tPLH
~I.
I
VOH »
T.'.v
-I
OUTPUTS
0A, 0B, DC, AND 00
"\L,.5
\
V '.5 V .
,
\L,.5 V '.5 V I I '.5 V
o
Z
- - - VOL

CLEAR AND LOAD VOLTAGE WAVEFORMS

FIGURE 1

NOTES: A. The input pulse is supplied by a genorator having the following characteristics: PRR .;; , MHz, duty cycle';; 50%, tr < 5 ns, and unless
specified, tf < 5 ns. When testing f max , vary PRR.
B. CL includes probe and jig capacitance.
C. All diodes are' N3064.
D. Unless otherwise specified, QA is connected to clock 2.

::lCI'>
 TTL TYPES SN54178, SN54179, SN74178, SN74179
MSI 4-81T PARALLEL-ACCESS SHIFT REGISTERS
BULLETIN NO. DL·S 7211846, DECEMBER 1972

• Typical Maximum Clock Frequency ... 39 MHz SN54178 ••• J OR W PACKAGE

SN74178 •.• J OR N PACKAGE
• Three Operating Modes: (TOP VIEW)
Synchronous Parallel Load INPUTS OUTPUT OUTPUT
Right Shift VCC ~ SHI FT QD LOAD Oc

Hold (Do Nothing) 8

• Negative-Edge-Triggered Clocking
• D-C Coupling Symplifies System Designs
description
These shift registers utilize fully d·c coupled storage
elements and feature synchronous parallel inputs and
parallel outputs. The SN54179/SN74179 has a direct
~ SERIAL QA CLOCK Qs GND
clear line and complementary output from the D INPUTS IN OUTPUT OUTPUT
flip-f!op, thereby differing from the SN54178/
positive logic: see fu nction table
SN74178.
Parallel loading is accomplished by taking the shift C'F\.II:.JI1 "7Q
o.I'.,...,roT1 I.J ~
I n
• • 0.1 '-".1 •• IDJ\""VA~~
D lAI __ I'_~""

input low, applying the four bits of data, and taking SN74179 •.• J OR N PACKAGE
the load input high. The data is loaded into the
associated flip·flop synchronously and appears at the INPUTS OUTPUTS
ou
~ ~
UT
outputs after a high·to-Iow transition of the clock. VCC SHIFT LOAD :
During loading, serial data flow is inhibited. 9
Shift right is also accomplished on the falling edge of
the clock pulse when the shift input is high regardless
of the level of the load input. Serial data for this
mode is entered at the serial data input.
When both the shift and load inputs are low, clocking
of the register can continue; however, data appearing
at each output is fed back to the flip·flop input
creating a mode in which the data is held unchanged.
Thus, the system clock may be left free·running

I
without changing the contents of the register. positive logic: see function table

'178, '179 t
FUNCTION TABLE
INPUTS OUTPUTS
PARALLEL
CLEARt SHIFT LOAO CLOCK SERIAL °A OB Oc 00 <lot
A B C 0
X L L L H
L
H
X
IX-X- -HX- -XX- X
-X
X X
- -
X X
X L
------::1
X QAO QBO QCO QDO I ~O
H I L L ~ X X X X X QAO QBO QCO QDO ~O I
H I L H ~ X a b c d a b C d I_d
I
H
I
H X ~ H X X X X H QAn QBn QCn I ~Cn
H I H X ~ L X X X X L QAn QBn QCn I QCn
tThe columns for clear, aD, and the top line of the table apply for the '179 only.

H = high level (steady state), L = low level (steady state)

X = irrelevant (any input, including transitions)
~ = transition from high to low level
a, b, c, d = the level of steady-state input at inputs A, B, C, or D, respectively.
QAO, QBO, QCO, QDO = the level of QA, QB, QC, or QD, respectively, before the indicated steady-state input conditions were established.
QAn, QBn, QCn = the level of QA, QB, or QC, respectively, before the most-recent t transition of the clock.

1076

TEXAS INSTRUMENTS 7-265

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54178, SN54179, SN74178, SN74179
4-81T PARALLEL-ACCESS SHIFT REGISTERS

functional block diagram (,178) ['179]

SERIAL _('-'3)....;['-'4]'--_ _ _ _ _ _ _---f-""""I

OATAA_(2_)~[3_]_ _ _ _ _ _~_r~ (4) [5] OA

LOAD (9) [10]

OATAB_(_1)_[2_]_ _ _ _ _ _-+~~~ as (6) [7] as

DATA C (13) [15] Oc (8) [9] Oc

(12) [14] 00 (10) [11] 00

OATAO-------------~~~~

SHI FT _(1_1_)[_13_]-I [12] aD

['179
ONLY]

I CLEAR
['179
ONLY]
[1]

I
I
ct> I
Denotes input activated by a transition from a high ;evs! to a ~o ...'V fevel.

I
schematics of inputs and outputs

EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS

---4___- - Vee

Vcc---......- - -

INPUT

OUTPUT

1272

7-266 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54178, SN54179, SN74178, SN74179
4-81T PARALLEL-ACCESS SHIFT REGISTERS

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1) ............ . 7V
Input voltage . . . . . . . ............ . 5.5 V
Operating free-air temperature range: SN54178, SN54179 Circuits -55°C to 125°C
SN74178, SN74179 Circuits . O°C to 70°C
Storage temperature range -65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54178, SN54179 SN74178, SN74179
UNIT
MIN NOM MAX M!N NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -800 -800 /LA
Low-level output current, 10L io i6 rnA
elock frequency. fc!ock 0 25 0 25 MHz
Width of clock or clear pulse, tw (see Figure 1) 20 20 ns
Shift (H or L) or load 35 35
Data 30 30
Setup time, tsu (see Figure 1) ns
elear-inactive-state
15 15
(SN54179 and SN74179)
Hold time at any input, th 5 5 ns
Operating free-air temperature, T A -55 125 0 70 °e

•
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54178. SN54179 SN74178. SN74179
PARAMETER TEST eONDITIONSt UNIT
MIN TYP:j: MAX MIN TYP:j: MAX
VIH High-level input voltage 2 2 V
VIL Low·level input voltage 0.8 0.8 V
VIK Input clamp voltage Vee; MIN, II; -12mA -1.5 -1.5 V
Vee; MIN, VIH; 2V,
VOH H igh·level output voltage 2.4 3.4 2.4 3.4 V
VIL; 0.8 V, 10H; -800/LA
Vee- MIN, VIH-2V,
VOL Low-level output voltage 0.2 0.4 0.2 0.4 V
VIL; 0.8 V, 10L; 16 rnA
II I nput current at maximum input voltage Vee; MAX, VI; 5.5 V 1 1 mA
IIH High-level input current Vee; MAX, VI; 2.4 V 40 40 /LA
IlL Low-level input current Vee; MAX, VI; 0.4 V -1.6 -1.6 rnA
lOS Short-circu it output current § Vee; MAX -20 -57 -18 -57 rnA
lee Supply current Vee; MAX, See Note 2 46 70 46 75 rnA

t For conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions for the applicable device
type.
tAli typical values are at Vee; 5 V, T A; 25°e.
§ Not more than one output should be shorted at a time.
NOTE 2: lee is measured as follows:
a) 4.5 V is applied to serial inputs, load, shift, and clear,
b) Parallel inputs A through Dare gounded,
c) 4.5 V is momentarily applied to clock which is then grounded.

1076

TEXAS INCORPORATED
INSTRUMENTS 7-267
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54178, SN54179, SN74178, SN74179
4-81T PARALLEL-ACCESS SHIFT REGISTERS

switching characteristics, Vee =5 V, TA =25°e

FROM TO
PARAMETER~ TEST CONDITIONS MIN TYP MAX UNIT
(lNPun (OUTPUT)
f max 25 39 MHz
tpLH °D 15 23
Clear CL=15pF, RL = 400 n, ns
tpHL 0A, 0B, 0C, 0D 24 36
See Figure 1
tPLH 17 26
Clock Any output ns
tpHL 23 35

~fmax'; Maximum clock frequency

tpHL'; Propagation delay time, high-to-Iow-Ievel output
tpLH ';Propagation delay time, low-to-high-Ievel output

PARAMETER MEASUREMENT INFORMATION

OUTPUT VCC

FROMOUTPUT __~___-M__~__~~~~~~~
UNDER TEST

CL = 15pF
l'
'::' (See Note C)

LOAD CI RCUIT

14- tw(clearl-J 3 V
CLEAR ~ 1.5 V j:'5 ~ _____________________ 0V

I ~tsu
SHIFT
~1.5V ! 4~~--------------:~
I LOAD
I.-- I
: %1.5 V
tsu . .....;
~ ~ ;-:-- -
I
- - - -- - - -- -- - 3V
--oooil~· 14-- tsu I I - I 0V
I -::: '-t h !
DATA : /,1.5V :~ ~;:----- -- - - - - - - - 3 V
(See Note B)
--"'1--" ~
I I
t
SU
-::I II
. . . th rI t
su ~
I 0V

CLOCK
I
I
I
1.5 V
T-------
1.5 V
3V

____-+_J I ----.--- 0 V

° OUTPUT
----------:-t---
1.5V~
!.-tPHL.....
VOH

(See Note B) . " - - VOL

VOLTAGE WAVEFORMS

NOTES: A. Input pulses are supplied by generators having the following characteristics: tTLH';;; 10 ns, tTHL';;; 10 ns, PRR';;; 1 MHz,
Zout '" 50 n.
B. Data input and Q output are any related pair. Serial and other data inputs are at GND. Serial data input is tested in conjunction
with QA output in the shift mode.
C. CL includes probe and jig capacitance.
D. All diodes are 1 N3064.

FIGURE 1-SWITCHING TIMES

1076

7·268 TEXAS INSTRUMENTSINCORPORATED

POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TTL TYPES SN54180, SN74180
MSI 9-81T ODD/EVEN PARITY GENERATORS/CHECKERS
BULLETIN NO. DL-S 7211814, DECEMBER 1972

SN54180 .•. J OR W PACKAGE

logic
SN74180 .•• J OR N PACKAGE
(TOP VIEW)
FUNCTION TABLE
INPUTS OUTPUTS
Z; OF H'sAT Z; ~
EVEN ODD
A THRU H EVEN ODD
EVEN H L H L
ODD H L L H
EVEN L H L H
ODD L H H L
X H H L L
X L L H H

H = high level, L = low level, X = irrelevant ~·EveN ~·ODD

'----"---~EVEN ODD
- . . r - INPUT INPUT OUTPUT OUTPUT
INPUTS

positive logic: see function table

description

These universal, monolithic, 9-bit (8 data bits plus 1 parity bit) parity generators/checkers, utilize familiar Series 54/74
TTL circuitry and feature odd/even outputs and control inputs to facilitate operation in either odd- or even-parity
applications. Depending on whether even or odd parity is being generated or checked, the even or odd inputs can be
utilized as the parity or 9th-bit input. The word-length capability is easily expanded by cascading.

The SN54180/SN74180 are fully compatible with other TTL or DTL circuits. Input buffers are provided so that each
data input represents only one normalized series 54/74 load. A full fan-out to 10 normalized series 54/74 loads is
available from each of the outputs at a low logic level. A fan-out to 20 normalized loads is provided at a high logic level
to facilitate the connection of unused inputs to used inputs. Typical power dissipation is i70 mW.

The SN54180 is characterized for operation over the full military temperature range of -55°C to 125°C; and the
SN74180 is characterized for operation from O°C to 70°C.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted) II
Supply voltage, V CC (see Note 1) ....... . 7V
Input voltage . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range: SN54180 Circuits -55°C to 125°C
SN74180 Circuits O°C to 70°C
Storage temperature range -65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54180 SN74180
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, IOH -800 -800 /lA
Low-level output current, IOL 16 16 mA
Operating free-air temperature, T A -55 125 a 70 °e

1076

TEXAS INSTRUMENTS 7·269

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54180, SN74180
9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54180 SN74180
PARAMETER TEST CONDITIONSt UNIT
MIN TYPt MAX MIN TYPt MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
VIK Input clamp voltage Vee= MIN, II = -12mA -1.5 -1.5 V
Vee - MIN, VIH - 2 V,
VOH High-level output voltage 2.4 3.3 2.4 3.3 V
VIL=0.8V, 10H = -800 IlA
Vee MIN, VIH - 2 V,
VOL Low-level output voltage 0.2 0.4 0.2 0.4 V
VIL = 0.8 V, 10L = 16 rnA
II Input current at maximum input voltage Vee- MAX, VI- 5.5V 1 1 rnA
Any data input 40 40
IIH High-level input current Vee=MAX, VI = 2.4 V IlA
Even or odd input 80 80
Any data input -1.6 -1.6
IlL Low-level input current Vee = MAX, VI = 0.4 V rnA
Even or odd input -3.2 -3.2
lOS Short-circuit output current§ Vee = MAX -20 -55 -18 -55 rnA

lee Supply current Vee = MAX, See Note 2 34 49 34 56 rnA

NOTE 2: ICC is measured with even and odd inputs at 4.5 V, all other inputs and outputs open.
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
tAli typical values are at VCC =5 V, T A = 25°C.
§ Not more than one output should be shorted at a time.

switching characteristics, Vee = 5 V, TA =25° C

FROM TO
PARAMETER 11 TEST CONDITIONS MIN TYP MAxi UNIT
(INPUT) IOUTPUT)
tpLH 40 60
Data ~ Even ns
tpHL eL = 15pF, RL = 400 n, 45 68
tpLH Odd input grounded, See Note 3 32 48
Data ~Odd ns
tPHL 25 38
tPLH 32 48
Data ~ Even ns
tpHL eL = 15pF, RL=400n, 25 38
tPLH Even input grounded, See Note 3 40 60

II tpHL
tpLH
tpHL
Data

Even or Odd ~
~

Even or
Odd

~ Odd
CL = 15 pF,
See Note 3
RL=4oon,
45
13
7
68
20
10
ns

ns

NOTE 3: Load circuits and wavefonns are shown on p~9a 3-10.

11 tp LH == Propagation delay time, low-to-high-Ievel output
tPH'L== Propagation delay time, high-to-Iow-Ievel output

functional block diagram and schematics of inputs and outputs

EQUIVALENT OF TYPICAL OF BOTH

EACH INPUT OUTPUTS

vcc3--
INPUT
Req

--

Data inputs: Req = 4 k.n

Even and odd: Req = 2 kn

1076

7-270 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TTL TYPES SN54181, SN54LS181, SN54S181,
SN74181, SN74LS181, SN74S181
MSI ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS
BULLETIN NO. DL-S 7611831, DECEMBER 1972 - REVISED OCTOBER 1976

SN54181, SN54LS181, SN54S181 ..• J OR W PACKAGE

• Full Look-Ahead for High-Speed SN74181, SN74LS181, SN74S181 •.. J OR N PACKAGE
Operations on Long Words (TOP VIEW}

• Input Clamping Diodes Minimize

Transmission-Line Effects
• Darlington Outputs Reduce 7urn-Off
Time
• Arithmetic Operating Modes:
Addition
Subtraction
Shift Operand A One Position
Magnitude Comparison
Plus Twelve Other Arithmetic
Operations
• Logic Function Modes:
iogic: see tabies "j and 2
Exclusive-OR
Comparator
AND, NAND, OR, NOR
Plus Ten Other Logic Operations

TYPICAL ADDITION TIMES

NUMBER ADDITION TIMES PACKAGE COUNT CARRY METHOD
OF USING '181 USING 'LS181 USING'S181 ARITHMETIC/ LOOK-AHEAD BETWEEN
BITS AND '182 AND '182 AND'S182 LOGIC UNITS CARRY GENERATORS ALU's
1 to4 24 ns 24 ns 11 ns 1 NONE
5to 8 36 ns 40ns 18 ns 2 RIPPLE
9 to 16 36 ns 44 ns 19 ns 30r4 1 FULL LOOK-AHEAD
17 to 64 60 ns 68 ns I 28 ns 5 to 16 2 to 5 FULL LOOK-AHEAD

description
I
The '181, 'LS181, and 'S181 are arithmetic logic units (ALU)/function generators that have a complexity of 75
equivalent gates on a monolithic chip. These circuits perform 16 binary arithmetic operations on two 4-bit words as
shown in Tables 1 and 2. These operations are selected by the four function-select lines (SO, S1, S2, S3) and include
addition, subtraction, decrement, and straight transfer. When performing arithmetic manipulations, the internal carries
must be enabled by applying a low-level voltage to the mode control input (M). A full carry look-ahead scheme is made
available in these devices for fast, simultaneous carry generation by means of two cascade-outputs (pins 15 and 17) for
the four bits in the package. When used in conjunction with the SN54182, SN54S182, SN74182, or SN74S182, full
carry look-ahead circuits, high-speed arithmetic operations can be performed. The typical addition times shown above
illustrate the little additional time required for addition of longer words when full carry look-ahead is employed. The
method of cascading '182 or 'S182 circuits with these ALU's to provide multi-level full carry look-ahead is illustrated
under typical applications data for the '182 and 'S182.

If high speed is not of importance, a ripple-carry input (C n ) and a ripple-carry output (C n+4) are available. However,
the ripple-carry delay has also been minimized so that arithmetic manipulations for small word lengths can be
performed without external circuitry.

1076

TEXAS INSTRUMENTS 7-271

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54181, SN54LS181, SN54S181,
SN74181, SN74LS181, SN74S181
ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS

description (continued)
The '181, 'LS181, and 'S181 will accommodate active-high or active-low data if the pin designations are interpreted as
follows:

PIN NUMBER 2 1 23 22 I 21 I 20 I 19 18 9 10 11 13 7 16 15 17
Active-low data (Table 1) AO 80 Al 81 I A2 1 8 2 I A3 83 Fa Fl F2 F3 Cn Cn+4 ]5 G
Active-high data (Table 2) AO 80 A1 I
81 A2 82 A3 I I 83 Fa Fl F2 F3 Cn Cn +4 X y

Subtraction is accomplished by 1's complement addition where the 1's complement of the subtrahend is generated
internally_ The resultant output is A-8-1, which requires an end-around or forced carry to provide A-8.

The '181, 'LS181, or 'S181 can also be utilized as a comparator. The A = 8 output is internally decoded from the
function outputs (Fa, F 1, F2, F3) so that when two words of equal magnitude are applied at the A and 8 inputs, it will
assume a high level to indicate equality (A = 8)_ The ALU should be in the subtract mode with Cn = H when
performing this comparison. The A = 8 output is open-collector so that is can be wire-AND connected to give a
comparison for more than four bits. The carry output (C n+4) can also be used to supply relative magnitude
information. Again, the ALU should be placed in the subtract mode by placing the function select inputs S3, S2, Sl,
SO at L, H, H, L, respectively.

ACTIVE-LOW DATA ACTIVE-HIGH DATA

INPUT Cn OUTPUT Cn +4
(FIGURE 1) (FIGURE 2)
H H A;;'S A<;;S
H L A<S A>S
L H A >S A<S
L L A<;;S A;;'S

These circuits have been designed to not only incorporate all of the designer's requirements for arithmetic operations,

I but also to provide 16 possible functions of two 800lean variables without the use of external circuitry. These logic
functions are selected by use of the four function-select inputs (SO,Sl,S2,S3) with the mode-control input (M) ata
high level to disable the internal carry. The 16 logic functions are detailed in Tables 1 and 2 and include exclusive-OR,
NAND, AND, NOR, and OR functions.

Series 54, 54LS, and 54S devices are characterized for operation over the full military temperature range of -55°C to
125°C; Series 74, 74LS, and 74S devices are characterized for operation from O°C to 70°C.

signal designations

The '181, 'LS181, and 'S181 together with the '182 and 'S182 can be used with the signal designations of either
Figure 1 or Figure 2 _The inversion indicators (0) and the bars over the terminal letter symbols (e.g., C) each indicate
that the associated input or output is active with respect to the selected function of the device when that input or
output is low. That is, a low at C means "do carry" while a high means "do not carry"_

The logic functions and arithmetic operations obtained with signal designations of Figure 1 are given in Table 1; those
obtained with signal designations of Figure 2 are given in Table 2.

1076

7-272 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TeXAS 75222
 TYPES SN54181, SN54LS181, SN54S181,
S"74181, SN74LS181, SN74S181
ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS
signal designations (continued)

AO FO
A1 F1
A2 F2
'181, A3 '181,
'LS181, 80 'LS181,
OR OR
'S181 81 'S181
82 Cn+4
83

Ph I
Y

i ~~n xh I
J I
I
Cn C n+x en
C n+y
GO YO
C n+z
G1 Y1
G2 '182 Y2 '182
OR OR
G3 'S182
Y3 'S182

G XO Y
X1

SELECTION
FIGURE 1
(Use with Table 1)

TABLE 1
1--_ _- - r_ _----==A::=C"'TI:..:.V.::.E-.:::LO::..:W::..;D::..:A:o.:T.::::A'--_ _ _ _ _--I SELECTION
X2
X3
FIGURE 2
(Use with Table 2)

TABLE 2
X

ACTIVE-HIGH DATA
•
M=H M = L; ARITHMETIC OPERATIONS M=H M = L; ARITHMETIC OPERATIONS
LOGIC Cn = L Cn = H LOGIC Cn =H Cn = L
S3 S2 S1 SO S3 S2 S1 SO FUNCTIONS
FUNCTIONS (no carry) (with carry) (no carry I Iwi1i1carryl
L L L F=A F = A MINUS 1 F=A L L L L F=A F=A F = A PLUS 1
L L H F=AB F = AB MINUS 1 F = AB L L L H F=A+B F = A+ B F = IA + B) PLUS 1
L L H L F=A+B F=ASMINUSl F=AS L L H L F = AB F= A +S F = IA + Sl PLUS 1
L L H H F=l F = MINUS 1 (2', COMP) F = ZERO L L H H F=Q F = MINUS 1 12', COMPL) F = ZERO
L H L L F=A+B F = A PLUS IA + S) F = A PLUS (A + S) PLUS 1 L H L F=AB F = A PLUS AS F = A PLUS AS PLUS 1
L H L H F=S F = AB PLUS IA + S) F = AB PLUS (A + S) PLUS 1 L H H F=8 F = IA + B) PLUS AS F = IA + B) PLUS AS PLUS 1
L H H LF=AG;lB F =AMINUS B MINUS 1 F =A MINUS B L H H L F = A G;l B F=AMINUSBMINUSl F=AMINUSB
L H H H F=A+B F=A+S F = (A + S) PLUS 1 L H H H F =AS F = AS MINUS 1 F =AB
H L L L F = AB F = A PLUS (A + B) F = A PLUS (A + B) PLUS 1 H L L L F=A +B F = A PLUS AB F = A PLUS AB PLUS 1

H L L H F = A G;l B F = A PLUS B F = A PLUS B PLUS 1 H L L H F = A G;l B F = A PLUS B F = A PLUS B PLUS 1

H L H L F=B F = AS PLUS IA + Bl F = AS PLUS (A + B) PLUS 1 H L H L F=B F = IA + S) PLUS AB F = IA + B) PLUS AB PLUS 1

H L H H F=A +B F = (A + Bl F = (A + B) PLUS 1 H L H H F = AB F = AB MINUS 1 F = AB
L L F=Q F = A PLUS A' F = A PLUS A PLUS 1 H H L L F= 1 F = A PLUS A* F = A PLUS A PLUS 1
L H F = AS F = AB PLUS A F = AB PLUS A PLUS 1 H H L H F=A+S F = IA + B) PLUS A F = IA + BI PLUS A PLUS 1
H H H L F = AB F = AS PLUS A F = ABPLUS A PLUS 1 H H H L F=A+B F = IA + S) PLUS A F = IA + S) PLUS A PLUS 1
H H H H F=A F=A F = A PLUS 1 H H H H F=A F=AMINUSl F=A

• Each bit is shifted to the next more significant position_

1076

TEXAS INSTRUMENTS
INCORPORATED
7-273
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54181, SN74181
ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) 7V
Input voltage . . . . . . . . 5.5 V
Interemitter voltage (see Note 2) 5.5V
Operating free-air temperature range: SN54181 -55°C to 125°C
SN74181 oOe to 70°C
Storage temperature range -65°C to i 50°C
NOTES: 1. Voltage values, except interemitter voltage, are with respect to network ground terminal.
2. This is the voltage between two emitters of a multiple-emitter transistor. For this circuit, this ratinij applies to each A input in
conjunction with inputs S2 or S3, and to each B input in conjunction with inputs SO or S3

recommended operating conditions

SN54181 SN74181
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, VCC 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H (All outputs except A = B) -800 -800 /l-A
Low-level output current, 10L 16 16 rnA
Operating free-air temperature, T A -55 125 0 70 °c

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54181 SN74181
PARAMETER TEST CONOITIONst
MIN TYP:j: MAX MIN TYP:j: MAX UNIT
VIH High-level input voltage 2 2 V
V IL Low-level input voltage 0.8 0.8 V
VIK Input clamp voltage Vec=MIN, 11=-12mA -1.5 -1.5 V
High-level output voltage, Vce = MIN, VIH = 2 V,
2.4 304 204 304 V
VOH any output except A = B VIL = 0.8 V, 10H = -800 /.IA
High-level output current, Vee = MIN, VIH = 2 V,
A = B output only I VIL=0.8V, VOH=5.5V
250 I 250 /l-A

•
VCC - MIN, VIH - 2 V,
Low-level output voltage
I
I VIL=0.8V, IOL=16mA
0.2 0.4 0.2 0.4 V

II
Input current at
maximum input voltage
I
I
VCC = MAX, VI = 5.5 V 1 rnA

I Mode input 40 40
High-,eve Any A or B input 120 120
Vcc = MAX, VI = 2.4 V
input current Any S input 160 160
Carry input 200 200
Mode input -1.6 -1.6
Low-level Any A or B input -4.8 -4.8
Vce = MAX, VI = 004 V ~------------~------------~ rnA
input current Any S input -6.4 -604
Carry input -8 -8 1
Short-circuit output current,
lOS Vcc= MAX -20 -55 -18 -57 rnA
any output except A = B §
Vcc - MAX,' Condition A 88 127 88 140 rnA
ICC Supply current
See Note 3 I Condition B 94 135 94 150 rnA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
fAil typical values are at Vee = 5 V, T A = 25°C.
§ Not more than one output should be shorted at a time.
NOTE 3: With outputs open, ICC is measured for the following conditions:
A. SO through S3, M, and A inputs are at 4.5 V. all other inputs are grounded.
B. SO through S3 and M are at 4.5 V. all other inputs are grounded.

1076

7-274 TEXAS 'I'.CORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54181, SN74181
ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS

switching characteristics, Vee = 5 V, TA = 25°e (eL = 15 pF, RL = 400 st, see note 4)
PARAMETERlI FROM (INPUT) TO (OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT
tPLH 12 18
Cn Cn+4 ns
tpHL 13 19
tPLH M; 0 v, SO; S3; 4.5 V, 28 43
Any A or B Cn+4 ns
tpHL S1 ; S2 ; 0 V (SUM mode) 27 41
tPLH M ; 0 V, so ; S3 ; 0 V, 35 50
Any A or B Cn+4 ns
tpHL S1 ; S2; 4.5 V (DIFF mode) 33 50
tPLH M;OV 13 19
Cn AnyF ns
tpHL (SUM or DIFF mode) 12 18
tpLH M; 0 V, so; S3; 4.5 V, 13 19
Any A orB G ns
tpHL S1 ; S2 ; 0 V (SUM mode) 13 19
tPlH M ; 0 V, SO; S3; 0 V, 17 25
Any A or B G ns
tPHl S1 ; S2 ; 4.5 V (DIFF mode) 17 25
tplH M ; 0 V, so ; S3 ; 4.5 V, 13 19
Any A orB P ns
tpHL S1; S2; 0 V (SUM mode) 17 25
tpLH M = 0 V, SO = S3 = 0 V, 17 '1<=

Any A or"E3 P ns
tpHl 51 ; 52; 4.5 V (DiFF mode) 17 25
tPlH M; 0 V, SO; S3; 4.5 V, 28 42
AiorSi Fi ns
tpHL S1 ; S2 ; 0 V (SUM mode) 21 32
tpLH M; 0 V, SO; S3; 0 V, 32 48
Ai orBj Fj ns
tpHl S1 ; S2 ; 4.5 V (DIFF mode) 23 34
tplH 32 48
AjorBj Fj M ; 4.5 V (logjc mode) ns
tPHl 23 34
tpLH M; 0 V, SO; S3; 0 V, 35 50
Any A orB A;B ns
tpHl S1 ; S2; 4.5 V (DIFF mode) 32 48
~ tpLH== propagation delay time, low-to-high-Ievel output
tpHL == propagation delay time, high-to-Iow-Ievel output
NOTE 4: Load circuit and voltage waveforms are shown on page 3-10.

•
schematics of inputs and outputs

EQUIVALENT OF EACH INPUT TYPICAL OF All OUTPUTS A;B OUTPUT

EXCEPT A; B

V C C - - -......- - - - - -.....- - V C C

INPUT

'---~~-OUTPUT

Mode control: Req; 4 k.ll. NOM

Any A or S: Req; 2 k.ll. NOM
Any S: Req; 1.3 k.ll. NOM
Cn: Req; 1 k.ll. NOM

1076

TEXAS INSTRUMENTS 7-275

I!,;CORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54LS181, SN74LS181
ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS

absolute maximum ratings over recommended operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) 7V
Input voltage . . . . . . . . . . . . 5.5 V
Interemitter voltage (see Note 2) . . . . 5.5 V
Operating free-air temperature range: SN54LS181 -55°C to 125°C
SN74LS181 oOe to 70°C
Storage temperature range . . . . . . -65°C to 150°C
NOTES: 1. Voltage values, except interemitter voltage, are with respect to network ground terminal.
2. This is the voltage between two emitters of a multiple-€mitter transistor. For this circuit, this rating applies to each A input in
conjunction with inputs S2 or S3, and to each B input in conjunction with inputs SO or S3.

recommended operating conditions

SN54LS181 SN74LS181
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, VCC 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H (All outputs except A = B) -400 -400 JJA
Low-level output current, 10L 4 8 mA

Operating free-air temperature, T A -55 125 0 70 °c

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS181 SN74LS181
PARAMETER TEST CONDITIONSt UNIT
MIN TYP:j: MAX MIN TYp:j: MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 OlB V
VIK Input clamp voltage Vec= MIN, II = -18mA -1.5 -1.5 V
High-level output voltage, VCC= MIN, VIH=2V,
VOH 2.5 3.4 2.7 3.4 V
any output except A = B VIL = VIL max, 10H = -400 JJA
High-level output current, Vce= MIN, VIH = 2 V,
10H 100 100 JJA
A = B output only VIL = VIL max, VOH=5.5V
10L = 4 mA 0.25 0.4 0.25 0.4

•
Low-level All outputs
VCC= MIN, VIH=2V, 10L = 8mA 0.35 0.5
VOL output V
Output G VIL = VIL max IOL=16mA 0.47 0.7 0.47 0.7
voltage
OutputP" 10L - 8mA 0.35 0.6 0.35 0.5
Input Mode input 0.1 0.1
current at, AflY A or B input I 0.3 0.3\
il . Vce= MAX, VI=5.5V rnA
max. input Any S mput 0.4 I 0.4
voltage Carry input 0.5 0.5
Mode input 20 20
High-level
Any A or B input 60 60
IIH input Vee = MAX, VI=2.7V JJA
Any S input 80 80
current
Carry input 100 100
Mode input -0.4 -0.4
Low-level
Any A or B input -1.2 -1.2
IlL input Vce = MAX, VI=O.4V mA
Any S input -1.6 -1.6
current
earry input -2 -2
Short-circuit output current,
lOS VCC = MAX -6 -40 -5 -42 mA
any output except A = B §
Condition A 20 32 20 34
Ice Supply current Vcc= MAX, See Note 3 mA
Condition B 21 35 21 37

t For conditions shown as M IN or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at Vee = 5 V, T A = 25°e.
§ Not more than one outout should be shorted at a time.
NOTE 3: With outputs open, lee is measured for the following conditions:
A. SO through S3, M, and A inputs are at 4.5 V, all other inputs are grounded.
B. SO through S3 and M are at 4.5 V, all other inputs are grounded.

1076

7-276 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS, "TEXAS 75222
 TYPES SN54LS181, SN74LS181
ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS
REVISED OCTOBER 1976

switching characteristics, VCC = 5 V, TA = 25°C, (CL = 15 pF, RL = 2 kQ, see note 4)

FROM TO
PARAMETER~ TEST CONDITIONS MIN TYP MAX UNIT
(INPUT) (OUTPUT)
18 27
ns
13 20
M = a v, so = S3 = 4.5 V. 25 38
Any Aor B S1 = S2 = a v (SUM mode) ns
25 38
M- a v. SO = S3 - a v 27 41
Any A or B Cn +4 ns
S1 = S2 = 4.5 V (DIFF mode) 27 41
M=OV 17 26
Any F ns
(SUM or DIFF mode) 13 20

1--_---=.tP.=L:.;..H:.....-_-1 Any A or B M= a v. so = S3 = 4.5 V. 19 29

ns
tPHL S1 = S2 = a v (SUM mode) 15 23

....-_----=-tP....::L:;.!-'.:...._~ Any A or B = 0 V. SO = S3 = 0 V.
M 21 32 I
ns
tPHL S1 = S2 = 4.5 V (DIFF mode) 21 32
M = a v. so = S3 = 4.5 V. 20 30
f--_---'tp..;:L=-H-'--_--i Any A or B
tpHL S1 = S2 = a v. (SUM mode) 20 30

f--_----=-tP....::I:;.~.:...._~1 AnyAorB
= a V, so = S3 = a v.
M 20 30
ns
tpHL Sl = S2 = 4.5 V (DIFF mode) 22 33
M = a v. so = S3 = 4.5 V, 21 32
ns
Sl = S2 = a V (SUM mode) 13 20
M = a v. so = S3 = a v. 21 32
ns
Sl = S2 = 4.5 V (DIFF mode) 21 32
22 33
M = 4.5 V (logic mode) ns
26 38
M- a v. so - S3 - a v. 33 50
Any A or B A = B
62 I ns I
, tPHL! , ! S1 = S2 = 4.5 V (DIFF mode) 41
~tPLH = propagation delay time. low-to-high-Ievel output
tPH L == propagation delay time, high-to-Iow-Ievel output

•
NOTE 4: Load circuit and voltage waveforms are shown on page 3-11.

schematics of inputs and outputs

EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS A= BOUTPUT

EXCEPT A= B

Vcc---.--- -----~-Vcc

Vcc

INPUT
OUTPUT
1-..---4t--O UTP UT

Mode control: Req = 17 kit NOM

Any A or S: Req = 5.67 kit NOM
Any S: Req = 4.25 kit NOM
cn: Req = 2.86 kit NOM

1076

TEXAS INSTRUMENTS
I~CORPORATED
7-277
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54S181, SN74S181
ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS
REVISED OCTOBER 1976

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) 7V
Input voltage . . . . . . . . 5.5V
Interemitter voltage (see Note 2) 5.5V
Operating free-air temperature: SN54S181 -55°C to 125°C
SN74S181 oOe to 70°C
Storage temperature range -65°C to 150°C
NOTES: 1. Voltage values, except interemitter voltage, are with respect to network ground terminal.
2. This is the voltage between two emitters of a multiple·emitter transistor. For this circuit, this rating applies to each A input in
conjunction with inputs S2 or S3, and to each B input in conjunction with inputs SO or S3.

recommended operating conditions

SN54S181 SN74S181
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H (All outputs except A; B) -1 -1 mA
Low-level output current, 10L 20 20 mA
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54S181 SN74S181
PARAMETER TEST eONDITIONSt
MIN TYPt MAX MIN TYPt MAX
I UNIT
VIH High-level input voltage 2 2 ! V
VIL Low-level input voltage 0.8 0.81 V
VIK Input clamp voltage Vee; MIN, 11--18mA -1.2 -1.21 V
High-level output voltage, Vee; MIN, VIH; 2V,
2.5 3.4
,
VOH 2.7 3.4 V
any output except A ; B
High-level output current,
VIL; 0.8 V, 10H; -1 mA
i
Vee; MIN, VIH; 2 V,
10H
A ; B output only VIL; 0.8 V, VOH;5.5V
250 I 2501 p.A

Vee; MIN, VIH;2V,

VOL Low-level output voltage 0.5 0.5 V

II
VIL; 0.8 V, 10L; 20mA
Input current at
II Vee; MAX, VI; 5.5 V 1 1 mA
maximum input voltage

, High-!eve!
Mode input I 50 50
Any A or B input 150 i50 '
IIH input Vee; MAX, VI; 2.5 V p.A
Any S input 200 200
current
Carry input 250 250
Mode input -2 -2
- Low-level
Any A or B input -6 -6
IlL input Vee; MAX, VI ;0.5 V mA
Any S input -8 -8
current
Carry input -10 -10 I
Short-circuit output current,
lOS Vee; MAX -40 -100 -40 -100 mA
any outpu t except A ; B §
Vee; MAX, TA; 125°e, , W package
195
lee Supply current See Note 3 only mA
Vee - MAX, See Note 3 I All packages 120 220 120 220

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAli typical values are at VCC; 5 V, TA; 25°C.
§ Not more than one output should be shorted at a time.
NOTE 3: ICC is measured for the following conditions (the typical and maximum values apply to both):
A. SO through S3, M, and A inputs are at 4.5 V, all other inputs are grounded, and all outputs are open.
B. SO through S3 and M are at 4.5 V, all other inputs grounded, and all outputs are open.

1076

7-278 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54S181, SN14S181
ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS

switching characteristics, VCC = 5 V, TA = 25°C (CL = 15 pF, RL = 280 n, see note 4)

PARAMETER~ FROM (INPUT) TO (OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT
tpLH 7 10.5
Cn Cn+4 ns
tpHL 7 10.5
tpLH M- a v, so - S3 - 4.5 V, 12.5 18.5
Any A or B C n+4 ns
tpHL Sl = S2 = a v (SUM mode) 12.5 18.5
tPLH M - a v, SO - S3 - a v, 15.5 23
Any A orB C n +4 ns
tpHL Sl = S2 = 4.5 V (DIFF mode) 15.5 23
tpLH - M-OV 7 12
Cn Any F ns
tpHL (SUM or DIFF mode) 7 12
tpLH M- a v, so - S3 = 4.5 V, 8 12
Any A or B G ns
tpHL Sl = S2 = a v (SUM mode) 7.5 12
tpLH M = a v, so = S3 = a v, 10.5 15
Any A orB G ns
tpHL Sl = S2 = 4.5 V (DIFF mode) 10.5 15
tPLH M= a v, so = S3 = 4.5 v, 7.5 12
Any A orB P ns
tPHL Sl = S2 = a v (SUM mode) 7.5 12
"rL.n
0. n \ 1 en
v
C"'> n\./
V , u V - U u - V v, IV.'" 15
Any AorS -p ns
tPHL Sl = S2 =,4.5 V (DIFF mode)
M= a v, so = S3 = 4.5 v,
10.5
11
15
16.5
I
tPLH
AjorBj Fj ns
I Sl = S2 = a v (SUM mode)
tpHL I 11 16.5
tPLH M = a v, so = S3 = a v, 14 20
AjorBj Fj ns
tpHL Sl = S2 = 4.5 V (DIFF mode) 14 22
tPLH 14 20
AjorBj Fj M = 4.5 V (logic mode) ns
tpHL I 14 22
tpLH M=OV,SO=S3=OV, 15 23
AnyAorB A=B ns
tpHL Sl = S2 = 4.5 V (DIFF mode) 20 30

~tpLH == propagation delay time, low-to-high-!evel output

tpHL == propagation delay time, high-to-Iow-Ievel output
NOTE 4: Load circuit and voltage waveforms are shown on page 3-10.

schematics of inputs and outputs

EQUIVALENT OF EACH INPUT

Vcc - - - - - - . - - - - -
TYPICAL OF ALL OUTPUTS
EXCEPT A = B

--~-------- VCC
A =BOUTPUT

Vcc
•
INPUT OUTPUT

1..---'-'--- 0 UTP UT

Mode control: Req = 2.8 kDo NOM

Any A or B: Req = 940 Do NOM
Any S: Req = 700 Do NOM
cn: Req = 560 Do NOM

1076

TEXAS INCORPORATED
INSTRUMENTS 7-279
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54181, SN54LS181, SN54S181, SN74181, SN74LS181, SN74S181
ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS

functional block diagram

53 (3)
52 (4) I
51 (5) I
50 (6) I
I (17)
GorY

(18) (16)
133 or B3 C n + 4 or
(;n+4
(15)
PorX

(19)
A3 or A3

(13) _
F3 or F3

(20)
132 or B2

(21)
A2 or A2

>---+--....:..:.(1.:..:...-1) F2 or F2

•
(22)

II ""
BlorBl

~A"
(23)
Al or Al---+-+-+-~-I
II
(10) _
>-+-+------'-- F 1 or F 1

(1)
BOor Bu

}----+-----.:(.:.;...9) 0 or FO

AO or AO_(2_)- - - " " " " * - - I

M _______________ .~

1076

7-280 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54181, SN54LS181, SN54S181, SN14181, SN14LS181, SN14S181
ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS

PARAMETER MEASUREMENT INFORMATION

SUM MODE TEST TABLE
FUNCTION INPUTS: SO =S3 =4.5 V. Sl =S2 = M =0 V
OTHER INPUT
INPUT OTHER DATA INPUTS OUTPUT OUTPUT
PARAMETER UNDER r-,.A-PP,.:~;:.;~:..::M.;:.E..::;~:.,:I~""L""y"---+-A-=-PP:-L-y:--r-A:--P-=-P-Ly---l UNDER WAVEFORM
TEST TEST (See Note 41
4.5 V GND 4.5 V GND
Remaining
Ai Bi None In-Phase
AandS
Remaining
Bi Ai None Fi In-Phase
AandS
Remaining
Ai Bi None None In-Phase
A and B. Cn
Remaining
Bi Ai None None In-Phase
AandS,C n
Remaining Remaining
Ai None Bi In-Phase
B A,C n
Remaining Remaining
None A; In-Phase
B A,C n
All All Any F
None None In-Phase
A B or Cn +4
tPLH
Ai None Bi I Out-ol-Phase
Bi None Ai I Out-ol-Phase
DIFF MODE TEST TABLE
FUNCTION INPUTS: Sl =S2 =4.5 V. SO =S3 = M =0 V
INPUT OTHER DATA INPUTS OUTPUT OUTPUT
PARAMETER UNDER
APPLY APPLY
TEST
4.5V GND
Remaining Remaining
None Si In-Phase
B,C n
Remaining I Remaining
I Out.al-Phase
Ai None
A B,C n

•
Remaining
Ai None Si None In·Phase
A andB, Cn
Remaining
None None Out-ol-Phase
A andB, Cn
Remaining
B; None None In-Phase
AandS, Cn
Remaining
B; None None Out·ol·Phase
A andB,C n
Remaining Remaining
Ai None
A S,C n
In-Phase

Remaining Remaining
None A=B Out-ol Phase
A
tpLH All C n +4
None None None In-Phase
A andS- or any F
Remaining
B; None None
A,B,C n
Out-ol·Phase

Remaining
B; None None In ·Phase
A,B,C n

LOGIC MODE TEST TABLE

FUNCTION INPUTS: Sl = S2 = M = 4.5 V. SO = S3 = 0 V
OTHE'R INPUT
INPUT OTHER DATA INPUTS OUTPUT OUTPUT
SAME BIT
PARAMETER UNDER f-A:-::P:::"P:-:Ly-'--':'-=A:-'P=P-:-Ly,,---'f--AP:-:::::"P"""Ly-'---'---AP--P"-L"-'y---1 UN DE R WAVE FORM
TEST
4.5 V GND 4.5 V GND TEST (See Note 41

Remaining
None None
A andB, Cn
Remaining
B; None None Out-ol·Phase
tpHL A andB, Cn
NOTE 4: Load circuit and voltage waveforms are shown on pages 3-10 and 3-11.

1076

TEXAS INSTRUMENTS INCORPORATED

7-281
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TTL TYPES SN54182, SN54S182, SN74182, SN74S182
MSI LOOK-AHEAD CARRY GENERATORS
BULLETIN NO. DL-S 7611823, DECEMBER 1972-REVISED OCTOBER 1976

• Directly Compatible for Use With: SN54182, SN54S182 ... J OR W PACKAGE

SN54181/SN74181, SN54LS181/SN74LS181, SN74182, SN74S182 ••• J OR N PACKAGE
(TOP VIEW)
SN54S281/SN74S281, SN54S381, SN74S381,
SN54S481/SN74S481

PIN DESIGNATIONS

ALTERNATIVE DESIGNA TlONSt PIN NOS. FUNCTION

GO, G1, G2, G3 GO, G1, G2, G3 3,1,14,5 CARRY GENERATE INPUTS
PO, P1, P2, P3 PO, P1, P2, P3 4,2,15,6 CARRY PROPAGATE INPUTS
Cn Cn 13 CARRY INPUT
C n +x , C n +y , C n +x , C n +y ,
12,11,9 CARRY OUTPUTS
C n+ z Cn+z
G Y 10 CARRY GENERATE OUTPUT
P X 7 CARRY PROPAGATE OUTPUT
VCC 16 SUPPLY VOLTAGE
GND 8 GROUND
logic: see description and function tables
t Interpretations are illustrated on page 7-273

description
The SN54182, SN54S182, SN74182, and SN74S182 are high·speed, look·ahead carry generators capable of anticipating
a carry across four binary adders or group of adders. They are cascadable to perform full look-ahead across n-bit adders.
Carry, generate-carry, and propagate-carry functions are provided as enumerated in the pin designation table above.
When used in conjunction with the '181, 'LS181, or 'S181 arithmetic logic unit (ALU), these generators provide
high-speed carry look-ahead capability for any word length. Each '182 or 'S182 generates the look-ahead (anticipated
carry) across a group of four ALU's and, in addition, other carry look-ahead circuits may be employed to anticipate
carry across sections of four look-ahead packages up to n-bits. The method of cascading '182 or 'S182 circuits to
perform multi-level look-ahead is illustrated under typical application data.

•
The carry functions (inputs, outputs, generate, and propagate) of the look-ahead generators are implemented in the
compatible forms for direct connection to the ALU. Reinterpretations of carry functions as explained on the '181,
'LS18l, and 'S181 data sheet are also applicable to and compatible with the look-ahead generator. Logic equations for
the '182 and 'S182 are:

Cn + x = GO + PO Cn Cn +x = YO (XO + Cnl
C n+y = Gl + Pl GO + Pl PO Cn Cn+y = Yl [Xl + YO (XO + Cn )]
Cn+z = G2 + P2 Gl + P2 P1 GO + P2 Pl PO Cn or Cn +z = Y2 {X2 + Yl [Xl + YO (XO + Cn )]}
G = G3 + P3 G2 + P3 P2 Gl + P3 P2 Pl GO Y = Y3 (X3 + Y2) (X3 + X2 + Yll (X3 + X2 + Xl + YO)
15= P3 P2 Pl PO X = X3 + X2 + Xl + XO

logic

FUNCTION TABLE FOR G OUTPUT FUNCTION TABLE

FORPOUTPUT
INPUTS OUTPUT
G3 G2 G1 GO P3 P2 P1 G INPUTS OUTPUT
L X X X X X X L P3 P2 P1 PO P
X L X X L X X L L L L L L
X X L X L L X L All other
H
X X X L L L L L combinations
All other combinations H

H = high level, L = low level, X = irrelevant

Any inputs not shown in a given table are irrelevant with respect to that output.

1076

7-282 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54182, SN54S182, SN14182, SN14S182
LOOK-AHEAD CARRY GENERATORS

logic functional block diagram

FUNCTION TABLE
FOR C n+x OUTPUT

INPUTS OUTPUT
GO PO Cn C n+x
L X X H
X L H H
All other
L
combinations

- (6)
~30r X3 (5)
FUNCTION TABLE G30rY3

FOR Cn+y OUTPUT

INPUTS
Gl GO Pl PO Cn
L X X X X
X L L X X H
or
X X L L H
Cn+z
All other
P2 or X2 (15)
combinations G2orY2 (14)

FUNCTION TABLE FOR Cn+z OUTPUT

INPUTS OUTPUT I
G2 Gl GO P2 Pl PO Cn Cn+z I
L
X
X
L
X
X
X
L
X
X
X
X
X
X
H
H
- (2)
~1 orXl (1)
GlorYl illOJ
•
X X L L L X X H
X X X L L L H H
All other combinations L
I

H = high level, L = low level, X = irrelevant

Any inputs not shown in a given table are irrelevant with respect to
that output.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) 7V
Input voltage . . . . . . . . 5.5 V
Interemitter voltage (see Note 2) . . . . 5.5 V
Operating free-air temperature range: SN54', SN54S' Circuits. -55°C to 125°C
SN74', SN74S' Circuits. . aOc to 7aoC
Storage temperature range -65°C to 15aoC
NOTES: 1. Voltage values. except interemitter voltage, are with respect to network ground terminal.
2. This is the voltage between two emitters of a multiple·emitter input transistor. For these circuits, this rating applies to each IT
input in conjunction with any other G input or in conjunction with any P input.

1076

TEXAS I"'CORPORATED
INSTRUMENTS 7-283
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54182. SN74182
LOOK-AHEAD CARRY GENERATORS

recommended operating conditions

SN54182 SN74182
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, VCC 4.5 5 5.5 4.75 5 5.25 V
High-level output current, IOH -BOO -BOO /lA
low-level output current, 10l 16 16 mA
Operating free-air temperature, T A -55 125 0 70 °c

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54182 SN74182
PARAMETER TEST CONDITIONSt UNIT
MIN TYP+ MAX MIN TYP+ MAX
VIH High-level input voltage 2 2 V
Vil low-level input voltage O.S O.S V
VIK Input clamp voltage VCC= MIN, 11--12mA -1.5 -1.5 V
VCC= MIN, VIH=2V,
VOH High-level output voltage 2.4 3.4 2.4 3.4 V
Vil = O.S V, 10H =-SOO/lA
VCC= MIN, VIH = 2 V,
VOL low-level output voltage 0.2 0.4 0.2 0.4 V
Vll=O.SV, IOl = 16mA
II Input current at maximum input voltage VCC = MAX, VI = 5.5V 1 1 mA
Cn input SO SO
~3 input 120 120
High-level P2 input 160 160
IIH VCC= MAX, VI = 2.4 V IlA
input current 15'0, P1, or G3 input 200 200
GO or G2 input 360 360
G1 input 400 400
Cn input -3.2 -3.2
P3 input -4.S -4.S
low-level P2 input -6.4 -6.4
III Vec= MAX, VI = 0.4 V mA
input current 150, P1, or G3 input -S -S

•
GO or G2 input -14.4 -14.4
G1 input -16 -16
lOS Short-circuit output current§ Vec= MAX -40 -100 -40 -100 mA
leCH Supply current, all outputs high Vec=5V, See Note 3 27 27 mA
ICCl Supply current, all outputs low Vec - MAX, See Note 4 45 65 45 72 mA

TFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at V CC = 5 V, T A = 25° C.
§Not more than one output should be shorted at a time and duration of the short-circuit test should not exceed one second.
NOTES: 3. ICCH is measured with all outputs open, inputs P3 and G3 at 4.5 V, and all other inputs grounded.
4. I CCL is measured with all outputs open; inputs GO, <31, and <32 at 4.5 V; and all other inputs grounded.

switching characteristics, Vee = 5 V, TA = 25°e.

I PARAMETER i TEST CONDITIONS MIN TYP MAX UNIT
I tplH Propagation delay time, low-to-high-Ievel output I Cl = 15 pF, Rl =400 n, 11 17 ns
I tpHl Propagation delay time, high-to-Iow-Ievel output 1 See Note 5 15 22 ns

NOTE 5: Load circuit and voltage waveforms are shown on page 3-10.

1076

7-284 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54S182, SN74S182
LOOK-AHEAD CARRY GENERATORS

recommended operating conditions

SN54S182 SN74S182
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, VCC 4.5 5 5.5 4.75 5 5.25 V
High-level output current, IOH -1 -1 mA
Low-level output current, IOL 20 20 mA
Operating free-air temperature, T A -55 125 0 70 °c

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54S182 SN74S182
PARAMETER TEST CONDITIONSt UNIT
MIN TVP:j: MAX MIN TVP:j: MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage O.S O.S V
VIK Input clamp voltage VCC= MIN, II = -1SmA -1.2 -1.2 V
VCC - MIN, VIH=2V,
VOH High-level output voltage 2.5 3.4 2.7 3.4 V
VIL = O.S V, IOH =-1 mA
VCC- MIN, VIH-2V,
VOL Low-ievei ouipui voitage 0.5 0.5 V
VIL = O.S V, IOL =20mA
..'I Input CUiiSfit at maximum input VO:tage Vee = MAX, VI=5.5V i i mA
Cn input 50 50
P3 input 100 100
f:ligh-Ievel P2 input 150 150
IIH VCC= MAX, VI = 2.7 V J.LA
input current PO, P1, or G3 input 200 200
GO or G2 input 350 350
G1 input 400 400
C n input -2 -2
15"3 input -4 -4
I I I
Low-ievei ;>2 input I -6 -61 I
IlL VCC = MAX, VI = 0.5 V mA
input current PO, P1, or <33 input -S -S

•
GO or G2 input -14 -14
G1 input -16 -16
lOS Short-circuit output current § VCC= MAX -40 -100 -40 -100 mA
ICCH Supply current, all outputs high VCC= 5V, See Note 3 35 35 mA
ICCL Supply current, all outputs low VCC - MAX, See Note 4 69 99 69 109 mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
:j: All typical values are at V CC = 5 V, T A = 25° C.
§Not more than one output should be shorted at a time and duration of the short-circuit test should not exceed one second.
NOTES: 3. ICCH is measured with all outputs open, inputs 15"3 and 133 at 4.5 V, and all other inputs grounded. .
4. ICCL is measured with 1111 outputs open; inputs GO, 131, and (32 at 4.5 V; and all other inputs grounded.

switching characteristics, Vee = 5 V, TA = 25°e

FROM TO
PARAMETER~ TEST CONDITIONS MIN TVP MAX UNIT
(INPUT) (OUTPUT)
tPLH GO, G1, G2, G3, Cn+x , Cn+y, 4.5 7
ns
tpHL PO, P1, P2, or P3 or C n+z 4.5 7
tpLH GO, G1, G2, G3, 5 7.5
G ns
tpHL P1, P2, or P3 RL=2S0n, CL=15pF, 7 10.5
tpLH See Note 5 4.5 6.5
Po, P1, P2, or 1>3 I> ns
tpHL 6.5 10
tpLH Cn+x, Cn+y, 6.5 10
Cn ns
tpHL orC n+z 7 10.5
~tpLH == propagation delay time, low-to-high-Ievel output
tpH L == propagation delay time, high-to-Iow-Ievel output
NOTE 5: Load circuit and voltage waveforms are shown on page 3-10.

1076

TEXAS INSTRUMENTS 7-285

INCORPORATED
POST OFFICE BOX 5012 • CALLAS. TEXAS 75222
 TYPES SN54182, SN54S182, SN74182, SN74S182
LOOK-AHEAD CARRY GENERATORS

schematics of inputs and outputs

'182
EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS

-------------~~-VCC
Vcc----------e--------
58 n NOM

INPUT Req NOM

Cn 2.8 kn
1'3 1.4 kn
INPUT
1'2 940 n
PO, P1,G3 700 n
GO, 134 400 n OUTPUT
G1 350 n

'S182
EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS

-------------~~-VCC

50 n NOM

VCC---------.------

INPUT Req NOM

Cn 2.8 kn
1'3 1.4 kn '-----......-OUTPUT
INPUT
P2 940 n
PO,P1, <33 700 n

•
GO, (34 400 n
131 350 n

TYPICAL APPLICATION DATA

64·BIT ALU, FULL-CARRY LOOK-AHEAD IN THREE LEVELS

Remaining inputs and outputs at ·181, 'LS181, 'S181 'S281 , 'S381, and 'S481 are not shown.

1076

7-286 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TTL TYPES SN54H183, SN54LS183, SN74H183, SN74LS183
MSI DUAL CARRY-SAVE FULL ADDERS
BULLETIN NO. DL-S 7611B4B, OCTOBER 1976

• For Use in High-Speed Wallace-Tree Summing SN54H183, SN54LS183 ..• J OR W PACKAGE

SN74H183, SN74LS183 ... J OR N PACKAGE
Networks
(TOP VIEW)

• High-Speed, High-Fan-Out Darlington Outputs

• Input Clamping Diodes Simplify System Design

TYPICAL AVERAGE TYPICAL

PROPAGATION POWER
TYPES DELAY TIME DISSIPATION
'H183 11 ns 110 mW per bit
'LS183 15 ns 23 mW per bit

functional block diagram (each adder) ~~GND

INPUTS OUTPUTS

POS!ti\'2 logic: see function t:;:b!e

NC-No internai connection

FUNCTION TABLE
(EACH ADDER)
B (3,12)
INPUTS OUTPUTS
Cn B A I: Cn +1
L L L L L
A (1,13) L L H H L
L H L H L
L H H L I H I
H L L H L
H L H L H

•
H H L L H
H H H H H
H = high level, L = low level

schematics of inputs and outputs

-
'H183 'LS183
EQUIVALENT OF TYPICAL OF ALL EQUIVALENT OF TYPICAL OF ALL
EACH INPUT OUTPUTS EACH INPUT OUTPUTS

VCC
--~VCC
VCC --

o
58n 6 kn NOM
'NOM NOM
okn INPUT --
INPUT --

__ OUTPUT

description
These dual full adders feature an individual carry output from each bit for use in multiple·input, carry-save techniques
to produce the true sum and true carry outputs with no more than two gate delays. The circuits utilize high-speed,
high-fan-out, transistor-transistor logic (TTLI. but are compatible with both DTL and TTL families. Series 54H and
54LS devices are characterized for operation over the full military temperature range of -55°e to 125°e; Series 74H
o
and 74LS devices are characterized for operation from oOe to 70 e.

1076

TEXAS INSTRUMENTS 7-287

INCORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54H183, SN74H183
DUAL CARRY-SAVE FUll ADDERS

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage VCC (see Note 1) 7V

Input voltage. . . . . . . . 5.5V
Interemitter voltage (see Note 2) 5.5 V
Operating free·air temperature range: SN54H 183 Circuits -55°C to 125°C
SN74H183 Circuits O°C to 70°C
Storage temperature range -65°C to 150°C
NOTES: 1. Voltage values, except interemitter voltage, are with respect to network ground terminal.
2. This is the voltage between two emitters of a multiple-emitter transistor. For this circuit, this rating applies between any two
inputs to the same adder.

recommended operating conditions

SN54H183 SN74H183
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -1 -1 mA
low-level output current, 10l 20 20 mA
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONSt MIN TYP:j: MAX UNIT
VIH High·level input voltage 2 V
Vil low-level input voltage 0.8 V
VIK Input damp voltage Vee= MIN, II = -8 mA -1.5 V
Vee = MIN, VIH = 2 V,
VOH High-level output voltage 2.4 3.5 V
Vil = 0.8 V, 10H = -1 mA
Vee = MIN, VIH =2 V,
VOL low-level output voltage 0.2 0.4 V
Vil = 0.8 V, 10l = 20mA

•
II Input current at maximum input voltage Vee = MAX, VI = 5.5V 1 mA
IIH High-level input current Vee = MAX, VI = 2.4 V 150 /lA
III low-level input current Vee= MAX, VI = 0.4 V -6 mA
lOS Short-circuit output current§ Vee = MAX -40 -100 mA
Vce = MAX, ISN54H183 48 69
leCl Supply current, all outputs low mA
See Note 3 ISN74Hl83 48 75
I leeH Supply current, all outputs high I Vee = MAX, See Note 4 40 I mA I
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
:\: All typical values are at V CC = 5 V, T A = 25° C.
§ Not more than one output should be shorted at a time, and duration of the short circuit should not exceed one second.
NOTES: 3. leCL is measured with all outputs open and all inputs grounded.
4. ICCH is measured with all outputs open and all outputs at 4.5 V.

switching characteristics, Vee = 5 V, TA = 25°e

PARAMETER TEST CONDITIONS MIN TYP MAX
tplH Propagation delay time, low-to-high-Ievel output el=25pF, Rl=280n, 10 15
tPHl Propagation delay time, high-to-Iow-Ievel output See Note 5 12 18

NOTE 5: Load circuit and waveforms are shown on page 3-10.

1076

7·288 TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54LS183. SN74LS183
DUAL CARRY-SAVE FULL ADDERS

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage Vcc (see Note 1) . 7V

Input voltage . . 7V
Operating free-air temperature range: SN54LS183 Circuits -55°C to 125°C
SN74LS183 Circuits . . O°C to 70°C
Storage temperature range -65°C to 150°C

NOTE1: Voltage values, except interemitter voltage, are with respect to network ground terminal.

recommended operating conditions

SN54LS183 SN74LS183
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, VCC 4.5 5 5.5 4.75 5 5.25 V
High·level output current, 10H --400 -400 p,A
Low-I eve! Qt.!tput current, IOL 4 15 rnA
Operating free-air temperature, T A -55 125 0 70 °c

electrical characteristics over recommended operation free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONSt MIN TYP+ MAX MIN TYP+ MAX UNIT
V,H High-level input voltage 2 2 V
V, L Low-level input voltage 0.7 0.8 V
Input clamp voltage Vcc = MIN, " = -18 mA -1.5 -1.5 V
Vcc - MIN,
High-level output voltage 2.5 3.4 2.7 3.4 V
V,L = V,Lmax, 10H = -400 p,A
I Vee - MIN, \'OL =4 rnA 0.25 0.4 0.25 0.4
Low-level output voltage I V,H = 2 V, rf-.----+-------+--------I V

•
V,L = V,Lmax, 10L = 8 rnA 0.35 0.5
Input current at maximum input voltage Vcc = MAX, V, = 7 V 0.3 0.3 rnA
" High-level input current Vcc = MAX, V, = 2.7 V 60 60 p,A
Low-level input current Vcc = MAX, V, =0.4 V -1.2 -1.2 rnA
lOS Short-circuit output current § Vcc = MAX -20 -100 -20 -100 rnA
ICCL Supply current, all outputs low Vcc - MAX, See Note 3 10 17 10 17 rnA
ICCH Supply current, all outputs high Vcc - MAX, See Note 4 8 14 8 14 mA

t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
:tAli typical values are at V CC = 5 V, T A = 25° C.
§Not more than one output should be shorted at a time, and duration of the short circuit should not exceed one second.
NOTES: 3. ICCL is measured with all outputs open and all inputs grounded.
4. ICCH is measured with all outputs open and all outputs at 4.5 V.

switching characteristics, Vee =5 V, TA =25°e

PARAMETER TEST CONDITIONS MIN TYP MAX
tpLH Propagation delay time, low-to-high-Ievel output CL=15pF, RL=2kn, 15 23
tPHL Propagation delay time, high-to-Iow-Ievel output See Note 6 15 23

NOTE 6: Load circuit and waveforms are shown on page 3-11.

)76 DESIGN GOAL

This page provides tentative information on a
product in the developmental stage. Texas
TEXAS INCORPORATED
INSTRUMENTS 7-289
I nstruments reserves the right to change or dis- POST OFFICE B~X 5012 • DALLAS. TEXAS 75222
continue this product without notice.
 TTL TYPES SN54184. SN54185A. SN74184. SN74185A
MSI BCD-lO-BINARY AND BINARY-lO-BCD CONVERlERS
BULLETIN NO. DL·S 7211392, FEBRUARY 1971 - REVISED DECEMBER 1972

SN54184, SN74184 BCD-TO-BINARY CONVERTERS

SN54185A, SN74185A BINARY-TO-BCDCONVERTERS

SN54184. SN54185A ... J OR W PACKAGE

SN74184.SN74185A ... J OR N PACKAGE
description (TOP VIEW)

These monolithic converters are derived from the

custom MSI 256·bit read-only memories SN5488 and
SN7488. Emitter connections are made to provide
direct read·out of converted codes at outputs Y8
through Yl as shown in the function tables. These
converters demonstrate the versatility of a read-only
memory in that an unlimited number of reference
tables or conversion tables may be built into a system
using economical, customized read-only memories.
Both of these converters comprehend that the least
significant bits (LSB) of the binary and BCD codes
are logically equal, and in each case the LSB bypasses
the converter as illustrated in the typical applications. positive logic: see function table
This means that a 6-bit converter is produced in each
case. Both devices are cascadable to N bits.

An overriding enable input is provided on each converter which, when taken high, inhibits the function, causing all

•
outputs to go high. For this reason, and to minimize power consumption, unused outputs Y7 and Y8 of the '185A
and all "don't care" conditions of the '184 are programmed high. The outputs are of the open-collector type.

The SN54184 and SN54185A are characterized for operation over the full military temperature range of -55°C to
125°C; the SN74184 and SN74185A are characterized for operation from O°C to 70°C.

SN54184 and SN74184 BCD-to-binary converters

TABLE I
SN54184, SN74184
The 6·bit BCD-to·binary function of the SN54184 PACKAGE COUNT AND DELAY TIMES
and SN74184 is analogous to the algorithm: FOR BCD·TO-BINARY CONVERSION
a. Shift BCD number right one bit and examine INPUT PACKAGES TOTAL DELAY TIMES (nsl
each decade. Subtract thre.e from each 4-bit (DECADESI REQUIRED TVP MAX
decade containing a binary value greater than 2 2 56 80
seven. 3 6 140 200

b. Shift right, examine, and correct after each 4 11 196 280

shift until the least significant decade contains 5 19 280 400
a number smaller than eight and all other con· 6 28 364 520
verted decades contain zeros.

1076

7-290 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54184, SN54185A, SN74184, SN74185A
BCD-lO-BINARY AND BINARY-lO-BCD CONVERlERS

SN54184 and SN74184 BCD-to-binary converters (continued)

BCDS'S BCD 10'S

6-BIT CONVERTER COMPLEMENT CONVERTER COMPLEMENT CONVERTER
MOO

~
BADes A
r--"---..
sv 0 C B A

~ &oBIT BINARY OUTPUT

~
BCD 10'S COMPLEMENT

FUNCTION TABLE FUNCTION TABLE

BCD-TO-BINARY BCD 9'S OR BCD 10'S
CONVERTER COMPLEMENT CONVERTER

BCD
iNI'UI:; OUTPUTS INPUTS
,See
I'See
OUTPUTS I
'See Note AI
WOROS~-----------.--~----~----~
e D C BAG
'See Note BI
YS Y4 Y3 Y2 Yl
IweBCD Note CI Note DI
RD re=<t.---cD=---:C=---=B--A-:-T-:Gc-T:-cYS=--Y-:7,----Y-i6

0- 1 L L L L L ILL L L L L o LLLLLLHLH

!:~ ~ ~ ~ ~ : ~ ~ ~ ~ ~ :
1 LLLLHLHLL
2 LLLHLLLHH
&7 L L L H H L L L L H H 3 LLLHHLLHL
~ L L H L L iL L L H L L 4 LLHLLLLHH
10-11 5 L L H L L

~I
L H H
~!:~~
6 L
I LLL 7 L L H H
16-17 8 L H L L
i8·i9 IL H L i
I 20-21 H L LIL H L H Li 0 I HL L L L L L L L L
I

•
22-23 H H L L H L H H 1 H L L L H! L H L L
24-25 H L L H L L H H L 2 H L L H L L H L L
I
26-27 H L L H H L H H L 3 H L L H H L L H H
28-29 H L H L L L H H H 4 H L H L L L L H H I
30-31 H H L L L L L H H H H 5 H L H L H L L H L \
32-33 H H L L H L H L L L L 6 H L H H L L L H L
34-35 H H L H L L H L L L H 7 H L H H H L L L H
36-37 H H L H H L H L L H L 8 H H L L L L L L H
38-39 H H H L L L H L L H H 9 H H L L H L L L L
ANY x X X X X H H H H H H ANY X X X X X H H H H

H = high level, L = low level, X = irrelevant H = high level, L = low level, X = irrelevant
NOTES: A. Input conditions other than those shown produce NOTES: C. Input conditions other than those shown produce
highs at outputs Y 1 through Y 5. highs at outputs Y6, Y7, and YB.
B. Outputs Y6, Y7, and YB are not used for BCD·to· D. Outputs Yl through YS are not used -for BCD 9's or
binary conversion. BCD 10's complement conversion.
tWhen these devices are used as complement converters, input E is
used as a mode control. With this input low, the BCD 9's
In addition to BCD-to-binary conversion, the
complement is generated; when it is high, the BCD 10's comple·
SN54184 and SN74184 are programmed to generate
ment is generated.
BCD 9's complement or BCD 10's complement.
Again, in each case, one bit of the complement code
is logically equal to one of the BCD bits; therefore,
these complements can be produced on three lines.
As outputs Y6, Y7, and Y8 are not required in the
BCD-to-binary conversion, they are utilized to
provide these complement codes as specified in the
function table (above, right) when the devices are
connected as shown above the function table.

1272

TEXAS INSTRUMENTS 7-291

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54184, SN54185A, SN74184, SN74185A
BCD-lO-BINARY AND BINARY-lO-BCD CONVERlERS

6-BIT CONVERTER
SN54185A and SN74185A binary-to-BCD converters

The function performed by these 6-bit binary-to-BCD

converters is analogous to the algorithm:
a. Examine the three most significant bits. If
the sum is greater than four, add three and
shift left one bit.
b. Examine each BCD decade. If the sum is ~ MSo
greater than four, add three and shift left
one bit.
FUNCTION TABLE
c. Repeat step b until the least·significant
INPUTS OUTPUTS
binary bit is in the least-significant BCD BINARY
BINARY SELECT ENABLE
location. WORDS
E D B
C A G YB Y7 Y6 Y5 V4 V3 V2 Vl
o· 1 L L L L L L H H L L L L L L
I
2·3 L L L L H L H H L L L L L H
I 4·5 L L L H L L H H L L L L H L
6·7 L L L H H L H H L L L L H H
TABLE II
8·9 L L H L L L H H L L L H L L
SN54185A, SN74185A 10· 11 L L H L H H
I~
L L L H L L L
PACKAGE COUNT AND DELAY TIMES 12· 13 L L H H L L H L L H L L H I
14· 15 L L H H H L H H L L H L H L I
FOR BINARY-TO-BCD CONVERSION
16· 17 !L H L L L i L H H L L H L H H
INPUT PACKAGES TOTAL DELAY TIME Ins) 18· 19 L H L L Hi L H H L L H H L L

~I
(BITS) REQUIRED TYP MAX 20 21 L H L H L H H L H L L L L
4to6 1 25 40 22· 23 ' L H L H L IH H L H L L L H
7 or 8

10
9
6
3
4
50
75
100
80
120
160
l~:. 24· 25 ~ L

29
27 i L
L
30· 31 i L
!
H
H
H
H
H

H
H
H
L
L
H
H
L
HI
L
Hi
i

!
L
L
L
L
I:
iH
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
H
L
L
H
L
H
H
L
L
L
H i
L
L
I
1

11 7 125 200 ! 32· 33 1 H L L L L ! L iH H L H H L L H I

12 8 125 200 134 35 I H L L L H L IH H L H H L H L I

•
13 10 150 240 36· 37 H L L H L L H H L H H L H H
38 39 H L L H H L H H L H H H L L
14 12 175 280
40· 41 H L H L L L H H H L L L L L
15 14 175 280 42 43 H L H L H L H H H L L L L H
113 16 200 320 44· 45 H L H H L L H H H L L L H L
17 19 225 360 46 47 H L H H H L H H H L L L H H

18 21 225 360
48 49 H H L L L I L H H H L L H L L i

19
20
24
27
250
275
400
440
50· 51
52· 53
54· 55 , H
H
H
H
H
H
L
L
L
L
H
H
:i
H
L
L
L
iH
H
H
H
H
H
H
H
L
L
H
H
H
L
L
L
L
L
H
H L L H L i
56· 571 H H H L L L H H H L H L H H
58· 59 H H H L H L H H H L H H L L
I
I
60· 61 H H H H L L H H H H L L L L
I
62 63 ! H H H H H L H H H H L L L H
ALL Ix x x x X H IH H H H H H H H

H -: high level, L low level, X ~ irrelevant

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, VCC (see Note 1) ......... . 7V

Input voltage. . . . . . . . . . . . . . . . . . . 5.5V
Operating free-air temperature range: SN54184, SN54185A -55°C to 125°C
SN74184,SN74185A O°C to 70°C
Storage temperature range _65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

1272

7-292 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54184, SN54185A, SN74184, SN74185A
BCD-lO-BINARY AND BINARY-lO-BCD CONVERlERS

recommended operating conditions

SN54184, SN54185A SN74184, SN74185A
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, VCC 4.5 5 5.5 4.75 5 5.25 V
Low-level output current, IOL 12 12 mA
Operating free-air temperature, T A -55 125 0 70 °c
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONSt MIN TYP+ MAX UNIT
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
VIK Input clamp voltage VCC= MIN, II = -12 mA -1.5 V
VCC= MIN, VIH = 2 V,
IOH High-level output current 100 /lA
VIL = 0.8 V, VOH = 5.5 V
VCC= M!N, VIH=2V,
VOL Low-level output voltage 0.4 V
VIL = 0.8 V, IOL=12mA
II I nput current at maximum input voltage VCC= MAX, VI = 5.5 V 1 mA
ilH High-ievei input current VCC= MAX, VI = 2.4 V 40 /lA
IlL Low-level input current VCC= MAX, VI = 0.4 V -1 mA
ICCH Supply current, all outputs high 50
VCC= MAX mA
ICCL Supply current, all programmed outputs low 62 99

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
:tAli typical values are at V CC =5 V, T A = 25°C.
switching characteristics, Vee = 5 V, TA = 25°e
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tpLH Propagation delay time, low-to-high-Ievel output from enable G CL = 15 pF, 19 30 ns
tpHL Propagation delay time, high-to-low-level output from enable G RL1 = 400 n, 22 3::> ns
tPLH Propagation delay time, low-to-high-Ievel output from binary select RL2 = 600 n, 27 40 ns

•
tpHL Propagation delay time, high-to-Iow-Ievel output from binary select See Figure 1 and Note 2 23 40 ns

schematics of inputs and outputs

PARAMETER MEASUREMENT
INFORMATION EQUIVALENT OF TYPICAL OF
ALL INPUTS ALL OUTPUTS

VCC
Vcc ________._-------

FROM OUTPUT-----...
UNDER TEST

RL2
------I1
600 n
30 pF

CL -=
INPUT

CL includes probe and jig capacitance.

LOAD CIRCUIT
FIGURE 1

NOTE 2: Voltage waveforms are shown on page 3-10.

1076

TEXAS INCORPORATED
INSTRUMENTS 7-293
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54184, SN54185A, SN74184, SN74185A
BCD-TO-BINARY AND BINARY-TO-BCD CONVERTERS

TYPICAL APPLICATION DATA

SN54184, SN74184

~r-"-..r-"-..~,----"--..~
os CS 85 AS 04 C4 B4 A4 03 C3 83 A3 02 C2 82 A2 01 C1 a1 Al DO CO 80 AD

FIGURE 1-BCD-TO-BINARY CONVERTER

FOR TWO BCD DECADES

.
BCD

• II

1j j
FIGURE 2-BCD-TO-BINARY CONVERTER FIGURE 3-BCD-TO-BINARY CONVERTER
FOR THREE BCD DECADES FOR SIX BCD DECADES

MSD-most significant decade

LSD-least significant decade
Each rectangle represents an SN54184 or SN74184.

127:

7·294 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54184, SN54185A, SN74184, SN74185A
BCD-lO-BINARY AND BINARY-lO-BCD CONVERlERS

TYPICAL APPLICATION DATA

SN54185A,SN74185A

IIINARV

FIGURE 4-6-BIT BINARV-TO-BCD

CONVERTER

........ y

~
I I I I I I I

FIGURE 7-12-BIT BINARV-TO-BCD

CONVERTER (SEE NOTE B)

\ MSD
..
BCD

•
FIGURE 5-8-BIT BINARV-TO-BCD
CONVERTER

~'--..r-----'
\ MSD V LSD I

BCD

FIGURE 6-9-BIT BINARV-TO-BCD

CONVERTER V
BCD

FIGURE 8-16-BIT BINARV-TO-BCD

MSD-Most significant decade
CONVERTER (SEE NOTE B)
LSD-Least significant decade
NOTES: A. Each rectangle represents an SN54185A or an SN74185A.
B. All unused E inputs are grounded.

02

TEXAS INSTRUMENTS 7-295

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54190, SN54191, SN54LS190, SN54LS191,
SN14190, SN14191, SN14LS190, SN14LS191
SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROL
BULLETIN NO. DL-S 7611865, DECEMBER 1972-REVISED OCTOBER 1976

SN54', SN54LS' ••. J OR W PACKAGE

• Counts 8-4-2-1 BCD or Binary SN74', SN74LS' •.• J OR N PACKAGE
(TOP VIEW)
• Single Down/Up Count Control Line INPUTS OUTPUTS INPUTS
r--'--,..-;;.r--. ,,..--'--__
• Count Enable Control Input DATA
A
RIPPLE MAXI
CLOCK CLOCK MIN· LOAD
DATA
C
DATA
0

• Ripple Clock Output for Cascading

• Asynchronously Presettable with Load Control
• Parallel Outputs
• Cascadable for n-Bit Applications
TYPICAL
AVERAGE TYPICAL
MAXIMUM
TYPE PROPAGATION POWER
CLOCK
DELAY DISSIPATION 0B 0A ENABLE flOWNI Oc 0D
B G UP
FREQUENCY
' - - ' '--v--' ' - . . - - ' '-v----'
'190, '191 20 ns 25 MHz 325 mW INPUT OUTPUTS ...INPUTS OUTPUTS

'LS190, 'LS191 20 ns 25 MHz 100 mW asynchronous inputs: Low input to load sets 0A=A,
Os = S, 0c = C, and 00 = 0
description
The '190, 'LS190, '191, and 'LS191 are synchronous, reversible up/down counters having a complexity of 58
equivalent gates. The '191 and 'LS191 are 4-bit binary counters and the '190 and 'LS190 are BCD counters.
Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change
coincident with each other when so instructed by the steering logic. This mode of operation eliminates the output
counting spikes normally associated with asynchronous (ripple clock) counters.
The outputs of the four master-slave flip-flops are triggered on a low-to-high-Ievel transition of the clock input if the
enable input is low. A high at the enable input inhibits counting. Level changes at the enable input should be made only
when the clock input is high. The direction of the count is determined by the level of the down/up input. When low,
the counter counts up and when high, it counts down. Level changes at the down/up input of the 'LS198 and 'LS191
should be made only when the clock input is high.

•
These coooters are fully programmable; that is, the outputs may be preset to either level by placing a low on the load
input and entering the desired data at the data inputs. The output will change to agree with the data inputs independ-
ently of the level of the clock input. This feature allows the counters to be used as modulo-N dividers by simply
modifying the count length with the preset inputs.

The clock, down/up, and load inputs aie buffered to !ovver the drive requirement which significantly ieduces the
number of clock drivers, etc., required for long parallel words.

Two outputs have been made available to perform the cascading function: ripple clock and maximum/minimum count.
The latter output produces a high-level output pulse with a duration approximately equal to one complete cycle of the
clock when the counter overflows or underflows. The ripple clock output produces a low-level output pulse equal in
width to the low-level portion of the clock input when an overflow or underflow condition exists. The counters can be
easily cascaded by feeding the ripple clock output to the enable input of the succeeding counter if parallel clocking is
used, or to the clock input if parallel enabling is used. The maximum/minimum count output can be used to accomplish
look-ahead for high-speed operation.

Series 54' and 54LS' are characterized for operation over the full military temperature range of -55°C to 125°C; Series
14' and 14LS' are characterized for operation from.O°C to 10°C.

1076

7-296 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 501~ • DALLAS. TEXAS 75222
 TYPES SN54190, SN54191, SN54LS190, SN54LS191,
SN74190, SN74191, SN74LS190, SN74LS191
SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROL
functional block diagrams

en
"
w
I-
2:
::>
o(.)
>
"<C
2: ,
ill
II
iii 4lI----IItl+-++--+------+++-~~~_++____++l+____, II III
I III

en
"w
I-
2:
::>
o(.)
•
w
C
<C
()
w
o
o
C'l
I,
I J
4->--t+---<i>l----+-+++-+__++__++__' II

en : !

~ ::l

o· .S
u
0')
~ .~
>
Cl

1272

TEXASINCORPORATED
INSTRUMENTS 7-297
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54190, SN54LS190, SN74190, SN74LS190
SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROL

'190, 'LS190 DECADE COUNTERS

typical load, count, and inhibit sequences

Illustrated below is the following sequence:

1. Load (preset) to BCD seven.
2. Count up to eight, nine (maximum), zero, one, and two.
3. Inhibit.
4. Count down to one, zero (minimum), nine, eight, and seven.

LOAD~
I I
A Ij""---r1 ---
-.-.J i l L . -
I I

DATA
S.s:Tla... --I I
INPUTS I I
Ij"""'""""'j1 -
C
--1: ;L_
D
Ir-
I ,

CLOCK

DOWNlUP--'L...~---i"-'_ _ _ _ _ _ _ _ _""'"

ENABLEIL..~---":~_ _ _ _ _ _ _.......I

• QC----r-jia...
___ ..J
___ ,
QD ____
I 1I

L-JJ
I
I

QB::::IIlL..I _____---II,
I

I
I
__________________~_________~~__________________.......
I
r___
~
II

MAX/MIN =::J :: II
I I

RIPPLE CLOCK ==~J I I U I U

: 7:: B 9 2 2: 1 0 9

I II----
....::.....,..;
COUNT UP _ ! - , N H , B , T --I I--- ~
COUNT DOWN - - -....

LOAD

1272

7-298 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54191, SN54LS191, SN74191, SN74LS191
SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROL

'191, 'LS191 BINARY COUNTERS

typical load, count, and inhibit sequences

Illustrated below is the following sequence:

1. Load (preset) to binary thirteen.
2. Count up to fourteen, fifteen (maximum), zero, one, and two.
3. Inhibit.
4. Count down to one, zero (minimum), fifteen, fourteen, and thirteen.

ENABLE IL..-:----7-:-______-!r----l!---:--_ _ _ _ _ _ __
I

II
II

Go::] :; II

II

•
MAX/MIN=-=~~----~------7-~--~
II
n L.._________
II

RIPPLE CLOCK ==J ::

: 13 I I 14
U
15 0 1 2. 2
I
I 2 1
U
0 15 14

I II----COUNTUP--+INHIBIT--! I----COUNTDOWN---!
~
LOAD

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, VCC (see Note 1) . . . . 7V

Input voltage: SN54', SN74' Circuits. . . 5.5 V
SN54LS', SN74LS' Circuits. 7V
Operating free-air temperature range: SN54', SN54LS' Circuits. · -55°C to 125°C
SN74', SN74LS' Circuits. · . O°C to 70°C
Storage temperature range · -65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.

1272

TEXAS INSTRUMENTS
I1'-.CORPORATED
7-299
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54190, SN54191, SN74190, SN74191
SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROL

recommended operating conditions

SN54190, SN54191 SN74190, SN74191
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -SOO -SOO fJ.A
Low-level output current, 10L 16 16 mA
Input clock frequency, fclock 0 20 0 20 MHz
Width of clock input pulse, tw(clock) 25 25 ns
Width of load input pulse, twOoad) 35 35 ns
Data setup time, t setup (See Figures 1 and 2) 20 20 ns
Data hold time, thold 0 0 ns
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54190, SN54191 SN74190, SN74191
PARAMETER TEST CONDITIONSt UNIT
MIN TYP:j: MAX MIN TYP:j: MAX
VIH High-level input voltage Vee = MIN 2 2 V
VIL Low-level input voltage Vee= MIN O.S O.S V
VIK Input clamp voltage Vee = MIN, 11=-12mA -1.5 -1.5 V
Vee= MIN, VIH=2V,
VOH High-Isvel output voltage 2.4 3.4 2.4 3.4 V
VIL = O.S V, 10H = -SOOfJ.A
Vee= MIN, VIH = 2V,
VOL Low-level output voltage
VIL = O.S V, 10L = 16mA
9. 2 0.4 0.2 0.4 V

High-level input current at

II Vee = MAX, VI = 5.5V 1 1 mA
maximum input voltage

•
High-level input current
IIH 40 40 fJ. A
at any input except enable
Vee= MAX, VI=2.4V
High-level input current
IIH 120 120 fJ. A
at enable input
Low~level input current
IlL i -1.6 I -1.6 mA
at any mput except enable
t-----L-ow--'--Iev-e'-Ii-n-pu-t-c-'-u-rr-e-nt------i Vee = MAX, VI = 0.4 V
-4.S -4.S mA
IlL at enable input
lOS Short-circuit output current§ Vee= MAX -20 -65 -1S -65 mA
ICC Supply current Vee = MAX, See Note 2 65 99 65 105 mA

tFor conditions shown as MAX or MIN, use appropriate value specified under recommended operating conditions.
:j:AII typical values are at Vee = 5 V, T A = 25°C.
§ Not more than one output should be shorted at a time.
NOTE 2: ICC is measured with all inputs grounded and all outputs open.

1076

7-300 TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54190, SN54191, SN74190, SN74191
SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROL

switching characteristics, vee = 5 V, TA = 25° C

FROM TO '190, '191
PARAMETER~ TEST CONDITIONS UNIT
(INPUT) (OUTPUT) MIN TYP MAX
f max 20 25 MHz
tpLH 22 33
Load QA, QB, QC. QD ns
tpHL 33 50
tpLH 14 22
Data A. B. C. D QA. QB. QC. QD ns
tpHL 35 50
tpLH 13 20
Clock Ripple Clock CL=15pF, RL = 400 n, ns
tpHL 16 24
See Figures 1 and 3 thru 7
tPLH 16 24
Clock QA, QB, QC, QD ns
tPHL I 24 36
tpLH 28 42
Clock Max/Min ns
tPHL
"t'Ln
37
.)u
52
45 i I
tPHL
, tPLH
Down/Up Ripple Clock
30
21
45
33
I ns
1
Down/Up Max/Min
tpHL 22 33 I ns
I
~fmax == maximum clock frequency
tpLH == propagation delay time, low-to-high-Ievel output
tpHL == propagation delay time, high-to-Iow-Ievel output

schematics of inputs and outputs

•
EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS

vcc--------e------- ----+------v cc

INPUT

OUTPUT

Enable input: Req = 1.3 kn NOM

All other inputs: Req = 4 kn NOM

1272

TEXAS Il'<CORPORATED
INSTRUMENTS 7-301
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54LS190, SN54LS191, SN74LS190, SN74LS191
SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROL
REVISED OCTOBER 1976

recommended operating conditions

SN54LS190 SN74LS190
SN54LS191 SN74LS191 UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, VCC 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -400 -400 IJ.A
Low-level output current, 10L 4 8 mA
Clock frequency, fclock 0 20 0 20 MHz
Width of clock input pulse, tw(clock) 25 25 ns
Width of load input pulse, tw(load) 35 35 ns
Data setup time, tsetup (See Figures 1 and 2) 20 20 ns
Data hold time, thold 0 0 ns
Count enable time, tenable- (see Note 3)) 20 20 ns
Operating free-air temperature, T A -55 125 0 70 °c

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS190 SN74LS190
PARAMETER TEST CONDITIONSt SN54LS191 SN74LS191 UNIT
MIN TYP:j: MAX MIN TYp:j: MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
VIK I nput clamp voltage VCC= MIN, II = -18mA -1.5 -1.5 V
Vec= MIN, VIH=2V,
VOH High-level output voltage 2.5 3.4 2.7 3.4 V
VIL = VIL max, 10H = -4001J.A
Vee = MIN, VIH=2V, pOL=4mA 0.25 0.4 0.25 0.4
VOL Low-level output voltage I VIL = VIL max V

•
pOL=8mA 0.35 0.5
High-level input
Enable 0.3 0.3
II current at maximum - Vee= MAX, VI =7V mA
input voltage Others 0.1 0.1

High-level Enable 60 60
, IIH input current
-
, Others,
Vec=MAX, VI = 2.7 V
20 20,
iJ.A

~
Low-level -1.2 -1.2
IlL Vce= MAX, VI = 0.4 V mA
input current Others -0.4 -0.4
lOS Short-circuit output current§ Vee= MAX, -20 -100 -20 -100 mA
ICC Supply current VCC=MAX, See Note 2 20 35 20 35 rnA

tFor conditions shown as MAX or MIN, use appropriate value specified under recommended operating conditions for the applicable device
type.
:j:AII typical values are at VCC = 5 V, TA = 25°C.
§ Not more than one output should be ·shorted at a time, and duration of the short-circuit should not exceed one second.
NOTES: 2. ICC is measured with all inputs grounded and all outputs open.
3. Minimum count enable time is the interval immediately preceeding the rising edge of the clock pulse during which interval the
count enable input must be low to ensure counting.

1076

7-302 TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54LS190, SN54LS191, SN74LS190, SN74LS191
SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROL
REVISED OCTOBER 1976

switching characteristics, Vee =5 V, TA =25°e

FROM TO 'LS190, 'LS191
PARAMETER~ TEST CONDITIONS UNIT
(INPUT) (OUTPUT) MIN TVP MAX
f max 20 25 MHz
tpLH 22 33
Load QA, QB, QC, QD ns
tPHL 33 50
tpLH 20 32
Data A, B, C, D QA, QB, QC, QD ns
tpHL 27 40
tpLH 13 2q
Clock Ripple Clock CL = 15pF, RL = 2 kn, ns
tpHL 16 24
See Figures 1 and 3 thru 7
tPLH 16 24
Clock QA, QB, QC, QD ns
tpHL I 24 36
tPLH I
!
28 42
Clock rv1axJMin ns
tPHL 37 52
tPLH 30 45-
LrML
Down/Up Ripple Clock .,,, ...... ns

tpLH 21 33
DO\Nn!Up Max/Min
tPHL 22 33
tpLH 21 33
Enable Ripple Clock
tpHL 22 33

~ f max
== maximum clock frequency
tpLH == propagation delay time, low-to-high-Ievel output
tpHL == propagation delay time, high-to-Iow-Ievel output

schematics of inputs and outputs

EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS

VCC--------~------

INPUT--~~~~--~~
--~"",_Vcc

120 n NOM

•
'---+- OUTPUT

Enable input: Req = 8_33 kn NOM

Load input: Req = 25 kn NOM
All other inputs: Req = 17 kn NOM

1076

TEXAS INCORPORATED
INSTRUMENTS 7-303
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54190, SN54191, SN54LS190, SN54LS191,
SN74190, SN74191, SN74LS190, SN74LS191
SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROL
PARAMETER MEASUREMENT INFORMATION

OUTPUT VCC

....,.J 1.-0;.10n5

~::::----::9O%~'-_:_- -- -- -- 3V

Vref :
(SEE NOTE B)
MAX/MIN, : 10%

RIPPLE CLOCK,---~~""","""'~~""''''''--I'''-_r---, I I

~
tpLH~ I ------vOH
0A, 0B, 0C, OR 00 NONINVERTlNG I I I V ef
CL = 15 pF OUTPUT : Vref I r I

(SEE NOTE A)
J
FIGURE 1-LOAD CIRCUIT ~UV~0~NG
I

I
: I V,ef
".
~tpHL~
I·
tplH--..t

Vref
I

I
VOL

VOH

~ tpHL -1 - - - - - - VOL
FOR SWITCHING TIME MEASUREMENT

....... "'101'tS --+i

DATA
, /90%
:
;'-=-------="1;"'
9O%X-!-,
See waveform sequences in figures 4 through 7 for propaga-

:~~~~-Vref Vre1~,.,~,:.;:.:O%,--_ _ _ __ tion times from a specific input to a specific output. For
simplification, pulse rise times, reference levels, etc., have
not been shown in figures 4 through 7.

FIGURE 3-GENERAL VOLTAGE WAVEFORMS FOR

___---J/ PROPAGATION TIMES

FIGURE 2-DATA SETUP TIME VOLTAGE WAVEFORMS

NOTES: A. CL includes probe and jig capacitance.

B. All diodes are 1 N3064.
C. The input pulses are supplied by generators having the following characteristics: Zout = 50 n, duty cycle'; 50%, PRR .; 1 MHz.
D. Vref = 1.5 V for '190 and '191; 1.3 V for 'LS190 and 'LS191.

LOAD
LJ LJ
I

•
I
ANY DATA INPUT I
I I
I
I
CORRESPONDING-
Q OUTPUT- -
- -
-
-
-
-
-
-l
-
! I
' - - - - - - . : . . ,- ' ,
I
I
I
I
'- I I
I
I
I
I I I I
tPLH~ :- --'I ;.-tPHL tPLH--: ~
I
-t :-tPHL

NOTE E: Conditions on other inputs are irrelevant.

FIGURE 4-LOAD TO OUTPUT AND DATA TO OUTPUT

DOWN/UP
L-
I
I
CLOCK

ENABLE G

t PHL- : l- -: I
,.... 'PLH
RIPPLE CLOCK
I I
MAX/MIN

NOTE F: All data inputs are low.

FIGURE 5-ENABLE TO RIPPLE CLOCK, CLOCK TO RIPPLE CLOCK, DOWN/UP TO RIPPLE CLOCK, AND DOWN/UP TO MAX/MIN

1076

7-304 TEXAS I"iCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54190, SN54191, SN54LS190, SN54LS191,
SN74190, SN74191, SN74LS190, SN74LS191
SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROL
PARAMETER MEASUREMENT INFORMATION

switching characteristics (continued)

LOAD-U
u
DATA INPUTS- - - - - - - - - - - -
ISEENOTESGTO\) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---' _ _ _ _
--I

DOWN/UP

COUNT
UI
-: : - tPLH
WI
~ : - tpHL
OUTPUT lSI UNDER TEST= =- ~:..I _______I ....... I-j-------------.....:..---;LI__________
ENABLE = LOW

NOTES: G. to test C A , C8, and QC outputs of '190 and 'LS190: Data :r:puts A, a, and C are shc~'Vn by the se!!d !ine. Data input D :s s.'1cwr:
by the dashed line.
H. To test QD output of '190 and 'LS190: Data inputs A and D are shown by the solid line. Data inputs Band C are held at the low
logic level.
I. To test QA. QB. QC. and QD outputs of '191 and 'LS191: All four data inputs are shown by the solid line.

FIGURE 6-CLOCK TO OUTPUT

LOAD~ u
DATA A
II
~~~~~T~·J~NDD_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____II _ _ _ _ _ _ _ _ _ _

DOWN/UP

COUNT
u-'
I
, u_, I
,.'-_tP_L_H_ _ _....:I"--;'- tpHL
U,I,
--j .--
U , tpLH ~ ,-tPHL

MAX/MIN_ _ _ _ _ _ -'I &.. 1_________--...&i-I----...!.-'L-

ENABLE = LOW

NOTE J: Data inputs Band C are shown by the dashed line for the '190 and 'LS190 and the solid line for the '191 and 'LS191: Data input D
is shown by the solid line for both devices.

FIGURE 7-CLOCK TO MAXIMIN

1272

TEXAS INSTRUMENTS 7·305

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54192, SN54193, SN54L192, SN54L193, SN54LS192, SN54LS193
SN74192, SN74193, SN74L192, SN74L193, SN74LS192, SN74LS193
SYNCHRONOUS 4-81T UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)
BULLETIN NO. DL-S 7611828, DECEMBER 1972- REVISED OCTOBER 1976

SN54', SN54LS' ... J OR W PACKAGE

• Cascading Circuitry Provided Internally SN54L' ... J PACKAGE
SN74', SN74L', SN74LS' ..• J OR N PACKAGE
• Synchronous Operation (TOP VIEW)
• Individual Preset to Each Flip-Flop
• Fully Independent Clear Input

TYPICAL MAXIMUM TYPICAL

TYPES
COUNT FREQUENCY POWER DISSIPATION
'192, '193 32MHz 325mW
'L192, 'L193 7 MHz 43mW
'LS192, 'LS193 32 MHz 95mW

description
These monolithic circuits are synchronous reversible DATA
B
(up/down) counters having a complexity of 55 INPUT

equivalent gates. The '192, 'L 192, and 'LS192

logic: Low input to load sets 0A = A,
circuits are BCD counters and the '193, 'L 193 and
'LS193 are 4-bit binary counters. Synchronous opera- Os = S, 0c = C, and 0D = 0
tion is provided by having all flip-flops clocked
simultaneously so that the outputs change coinci-
dently with each other when so instructed by the
steering logic. This mode of operation eliminates the
output counting spikes which are normally associated with asynchronous (ripple-clock) counters.

The outputs of the four master-slave flip-flops are triggered by a low-to-high-Ievel transition of either count (clock)
input. The direction of counting is determined by which count input is pulsed while the other count input is high.
All four counters are fully programmable; that is, each output may be preset to either level by entering the dasired data
at the data inputs while the load input is low. The output will change to agree with the data inputs independently of
the count pulses. This feature allows the counters to be used as modulo-N dividers by simply modifying the count
length with the preset inputs.

A clear input has been provided which forces all outputs to the low level when a high level is applied. The clear function

•
is independent of the count and load inputs. The clear, count, and load inputs are buffered to lower the drive require-
ments. This reduces the number of clock drivers, etc., required for long words .
These counters were designed to be cascaded without the need for external circuitry. Both borrow and carry outputs
are available toc'!scade both the up- and down-counting functions. The ~[[()~~gutproduces a pulse equal in width
to the count-down inQut when the counter underflows. Similarly, the carry QIl1;pJ.lt produces a pulse equal in width to
the coU;t~ninPut~;hen an overflow condition exists. The counte;:"s can then be easi!y cascaded by feeding the
borro-Wand carry outputs to the count-down and count-up inputs respectively of the succeeding counter.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

SN54' I
SN54L' ISN54LS' SN74' ISN74L' ISN74LS' UNIT
Supply voltage, V CC (see Note 1) 7 1 8 J 7 7 I 8 I 7 V
Input voltage 5.5 I 5.5 I 7 5.5 I 5.5 I 7 V
Operating free-air temperature range -55 to 125 o to 70 °c
Storage temperature range -65 to 150 -65 to 150 °c

NOTE 1: Voltage values are with respect to network ground terminal.

1076

7·306 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54192, SN54193, SN54L192, SN54L193, SN54LS192, SN54LS193,
SN74192, SN74193, SN74L192, SN74L193, SN74LS192, SN74LS193
SYNCHRONOUS 4-81T UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)
functional block diagrams

«
...."'
o o
....
::J ::J
....
::J
....
::J
o o

Iii rll !III I 1III I nil

« 0

...."'
;;:
0 0 & 0
....
....
.... ....
~~ ~~

•
::J ::J ::J ::J

~
0::J «::J
....
::J
....
::J
.... ....
::J
",0 '-'0 ::J
0 0 0 0
~
g ~ § ~ § E ~
'"
B
]
.c
Cl
:.c
'E"
~
c
:~
c
'"
'"
>
D

I:J

.~
t)

~
0
« Cl
.... «
::J g
2

-*-
1272

TEXAS Ir-CORPORATED
INSTRUMENTS 7·307
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54192, SN54193, SN54L192, SN54L193, SN54LS192, SN54LS193,
SN74192, SN74193, SN74L192, SN74L193, SN74LS192, SN74LS193
SYNCHRONOUS 4-81T UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)
REVISED OCTOBER 1976

schematics of inputs and outputs

EQUIVALENT OF INPUTS TYPICAL OF OUTPUTS

OF '192, '193, 'L 192, 'L 193 OF '192, '193, "L 192, 'L 193

----4..--- VCC

VCC--~ __- -

INPUT
.....--OUTPUT

'192, '193: Req = 4 kn NOM '192, '193: R=130 n NOM

'L 192, 'L 193: Req = 40 kn NOM 'L 192, 'L 193: R = 5:;0 n NOM

•
EQUIVALENT OF INPUTS TYPICAL OF OUTPUTS
OF 'LS192, 'LS193 OF 'LS192, 'LS193

- - - - -....- - V C C

CC 120 n NOM
V ---.'---

INPUT --t~~ __- __

'---__.--OUTPUT

Load input: Req = 25 kn NOM

All other inputs: Req = 17 kn NOM

1076

7·308 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54192, SN54L192, SN54LS192, SN74192, SN74L192, SN74LS192
SYNCHRONOUS 4-81T UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)

'192,'L 192, 'LS192 DECADE COUNTERS

typical clear, load, and count sequences

Illustrated below is the following sequence:

1. Clear outputs to zero.

2. Load (preset) to BCD seven.
3. Count up to eight, nine, carry, zero, one, and two.
4. Count down to one, zero, borrow, nine, eight, and seven.

CLEAR
--.J
n I
I
LOAD
LJ
A
i~--------~!
L--
- --
__ --_--
_ --
_ --
__
--1
I
~------~I
L--
- __________
-- -- - -- -- _
.J I
DATA
~-----~I--
C
-.J L-
I
D r-
COUNT
UP u'"LJ"'UL.Jl.J

•
COUNT
DOWN

°A

I I
°B
=:1 ~ ____---,II
OUTPUTS I I
°c
=--, I
~--------_____----,II
I
°D
=:1 ~
I
CARRY
u
BORROW
U I

SEQUENCE
iLLUSTRATED r---
1 1 0 9

COUNT DOWN
8

~
71

NOTES: A. Clear overrides load, data, and count inputs.

B. When counting up, count-down input must be high; when counting down, count-up input must be high.

1272

TEXAS INSTRUMENTS 7·309

INCORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54193, SN54L193, SN54LS193, SN74193, SN74L193, SN74LS193
SYNCHRONOUS 4-81T UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)

'193, 'L 193, 'LS193 BINARY COUNTERS

typical clear, load, and count sequences

Illustrated below is the following sequence:

1. Clear outputs to zero.

2. Load (preset) to binary thirteen.
3. Count up to fourteen, fifteen, carry, zero, one, and two.
4. Count down to one, zero, borrow, fifteen, fourteen, and thirteen.

CLEAR ~________________________________________________________________

LOAD
UI
A-.J IC
I
r-
_ _ _ _ _ _ _.......1 _
DATA
~ . . ------.L
I

COUNT
UP

•
COUNT
DOWN

CARRY
u
BORROW

I
U I
21 I 1
SEQUENCE
ILLUSTRATED r--- 14 15

COUNT UP
0

~
1

r---1 0 15

COUNT DOWN
14

~
13

NOTES: A. Clear overrides load, data, and count inputs.

B. When counting up, count-down input must be high; when counting down, count-up input must be high.

1272

7-310 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54192, SN54193, SN74192, SN74193
SYNCHRONOUS 4-811 UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)

recommended operating conditions

SN54192 SN74192
SN54193 SN74193 UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, VCC 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -400 -400 ;LA
Low-level output current, 10L 16 16 mA
Clock frequency, f clock 0 25 0 25 MHz
Width of any input pulse, tw 20 20 ns
Data setup time, tsu (see Figure 1) 20 20 ns
Data hold time, th 0 0 ns
Operating free-air temperature, T A -55 125 0 70 °c

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54192 SN74192
I PARAMETER TEST CONDITIONSt SN54193 SN74193
MIN TYP+ MAX MIN TYP+
I VIH High-level input voltage 2 I 2
VIL Low-ievei input voitage u.8 0.8 V
V!K Input clamp voltage VCC= MIN, II = -12mA -1.5 -1.5 V
VCC = MIN, VIH=2V,
VOH High-level output voltage 2.4 3.4 2.4 3.4 V
VIL = 0.8 V, 10H = -400;LA
VCC= MIN, VIH = 2 V
VOL Low-level output voltage 0.2 0.4 0.2 0.4 V
VIL = 0.8 V, 10L = 16mA
II I nput current at maximum input voltage VCC = MAX, VI = 5.5 V 1 1 mA
IIH High-level input current VCC = MAX, VI = 2.4 V 40 40 ;LA
IlL Low-level input current VCC = MAX, VI=O.4V -1.6 -1.6 mA
lOS Short-circuit output current§ VCC = MAX -20 -65 1-18 -65 mA
ICC Supply current VCC = MAX, See Note 2 65 89 65 102 mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
+AII typical values are at V CC = 5 V, T A = 25°C.
§ Not more than one output should be shorted at a time.
NOTE 2: ICC is measured with all outputs open, clear and load inputs grounded, and all other inputs at 4.5 V.
II
switching characteristics, Vee = 5 V, TA = 25°e
FROM TO
PARAMETER~ TEST CONDITIONS MIN TYP MAX UNIT
INPUT OUTPUT
f max 25 32 MHz
tpLH 17 26
Count-up Carry ns
tPHL 16 24
tPLH 16 24
Count-down Borrow CL = 15 pF, ns
tpHL 16 24
RL = 400 n,
tpLH 25 38
Either Count Q See Figures 1 and 2 ns
tpHL 31 47
tpLH 27 40
Load Q ns
tpHL 29 40
tpHL Clear Q 22 35 ns

~fmax "" maximum clock frequency

tpLH "" propagation delay time, low-to-high-Ievel output
tpH L "" propagation delay time, high-to-Iow-Ievel output

1076

TEXASINCORPORATED
INSTRUMENTS 7-311
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54L192. SN54L19J. SN74L192. SN74L19J
SYNCHRONOUS 4-81T UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)

recommended operating conditions

SN54L192 SN74L192
SN54L 193
I SN74L193 UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, V CC 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -100 -200 p.A
Low-level output current, 10L 2 3.6 mA
Clock frequency, fclock 0 3 0 3 MHz
Width of any input pulse, tw 200 200 ns
Data setup time, tsu (see Figure 1) 100 100 ns
Data hold time, th 0 0 ns
Operating free-air temperature range, T A -55 125 0 70 °c

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONSt

I SN54L192
SN54L193
SN74L192
SN74L193 UNIT
MIN TYP:j: MAX MIN TYP:j: MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.7 V
VIK Input clamp voltage VCC = MIN, II = -12mA -1.5 i -1.5 V
VCC = MIN, VIH = 2 V,
VOH High-level output voltage
VIL = 0.7 V, 10H = MAX
2.4 3.3 I 2.4 3.2 V

VCC = MIN, VIH = 2 V

VOL Low-level output voltage 0.15 0.3 0.2 0.4 V
VIL = 0.7 V, 10L = MAX
II Input current at maximum input voltage VCC = MAX, VI = 5.5 V 100 100 p.A
IIH High-level input current VCC= MAX, VI = 2.4 V 10 10 p.A
IlL Low-level input current VCC = MAX, VI = 0.3 V -0.18 -0.18 mA
lOS Short-circuit output current§ VCC = MAX -3 -15 -3 -15 mA
ICC Supply current VCC= MAX, See Note 2 8.5 15 8.5 15 mA

• tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type .
~AII typical values are at Vee = 5 V, T A = 25°C.
§Not more than one output should be shorted at a time.
NOTE 2: ICC is measured with all outputs open, clear and load inputs grounded, and all other inputs at 4.5 V.

switching characteristics, Vee

PARAMETER'
= 5 V, TA = 25°C
FROM
INPUT
TO
OUTPUT
TEST CONDITIONS MIN TYP MAX UNIT

f max 3 7 MHz
tPLH 65 130
Count-up Carry ns
tpHL I 65 130
tpLH 65 130
Count-down Borrow CL=50pF, ns
tpHL 65 130
RL = 4 kn,
tPLH 104 200
Either Count Q See Figures 1 and 2 ns
tpHL 135 240
tPLH 130 240
Load Q ns
tpHL 105 200
tPHL Clear Q 110 200 ns

~fmax "" maximum clock frequency

tpLH "" propagation delay time, low-to-high-Ievel output
tpH L =' propagation delay time. high-to-Iow-Ievel output

1076

7-312 TEXAS I"iCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 7524:2
 TYPES SN54LS192, SN54LS193, SN74LS192, SN74LS193
SYNCHRONOUS 4-81T UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)
REVISED OCTOBER 1976

recommended operating conditions

SN54LS192 SN74LS192
SN54LS193 SN74LS193 UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, VCC 4.5 5 5.5 4.75 5 5.25 V
High·level output current, 10H -400 -400 JlA
Low-level output current, 10L 4 8 rnA
Clock frequency, fclock 0 25 0 25 MHz
Width of any input pulse, tw 20 20 ns
Data setup time, tsu (see Figure 1) 20 20 ns
Data hold time, th 0 0 ns
Operating free-air temperature range, T A -55 125 0 70 °c

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS192 SN74LS192
PARAMETER TEST CONDITIONSt SN54LS193 SN74LS193 UNIT
_ ... , ..... +
iviii~ .,,...+
......... roo+
iviAX iviiN ITt"'+ MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
VIK Input clamp voltage VCC= MIN, 11=-18mA -1.5 -1.5 V
VCC= MIN, VIH = 2 V,
VOH High-level output voltage 2.5 3.4 2.7 3.4 V
VIL = VIL max, 10H = -400 JlA
VCC = MIN, VIH=2V, IIOL =4 rnA 0.25 0.4 0.15 0.4
VOL Low-level output voltage V
VIL = VIL max IIOL = 8mA 0.35 0.5
Input current at maximum
II VCC = MAX, VI =7V 0.1 0.1 rnA
input voltage
IIH High-level input current I Vee = MAX, VI =2.7V I 20 I 20 I J.!A
IlL Low-level input current VCC = MAX, VI = 0.4 V -0.4 -0.4 rnA
lOS Short-circuit output current§ VCC= MAX -20 -100 - 20 -100 rnA
ICC Supply current VCC = MAX, See Note 2 19 34 19 34 rnA

: For conditions shown as MI N or MAX, use othe appropriate value specified under recommended operating conditions for the applicable type.
+AII typical values are at V CC = 5 V, T A = 25 C.
§Not more than one output should be shorted at a time. ,and duration of the short-circuit should not exceed one second.
II
NOTE 2: ICC is measured with all outputs open, clear and load inputs grounded, and all other inputs at 4.5 V.

switching characteristics, Vee = 5 V, TA = 25°e

FROM TO
PARAMETER~ TEST CONDITIONS MIN TYP MAX UNIT
INPUT OUTPUT
f max 25 32 MHz
tPLH 17 26
Count-up Carry ns
tpHL 21 23

tPLH 16 24
Count-down Borrow CL=15pF, ns
tPHL 21 33
RL=2k.ll.,
tPLH 25 38
Either Count Q See Figures 1 and 2 ns
tpHL 31 47
tPLH 27 40
Load Q ns
tpHL 29 40
tpHL Clear Q 22 35 ns

~fmax == maximum clock frequency

tpLH == propagation delay time, low·to-high-Ievel output
tpH L == propagation delay time, high-to·low-Ievel output

1076

TEXASINCORPORATED
INSTRUMENTS 7-313
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54192, SN54193, SN54L192, SN54L193, SN54LS192, SN54LS193,
SN74192, SN74193, SN74L192, SN74L193, SN74LS192, SN74LS193
SYNCHRONOUS 4-BIT UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)
PARAMETER MEASUREMENT INFORMATION

DATA ,---------- --------.,

PULSE BORROW OPEN I I
GENERATOR
OPEN I RL I
(See Note A) CARRY
I I
Q
CLEAR A I
PULSE I Note C)
GENERATOR Os I (See
I
;~-:
(See Note A)

LOAD
Dc
00
T-=- CL
(See Note B) ;
"".:?-
JOpF
(used with
'54L/74L
I
I
I
only)
PULSE
GENERATOR
LOAD IL _____ ~~~~~~:~ _____ J
I
(See Note A)

r-----~;~;.~~~------1
L _____ ~=:~~;:~~ J _____

.---
r------------------~
LOAD CIRCUIT 2 I
L _____ '~'::,~"!<::C.::2)_____ ~
------------.,
LOAD CIRCUIT 4
L ____ ~': :,L.::.,lId":i::,u!!..l':"' ____ ~
I

TEST CIRCUIT

tr -.I I+- --+I '-- tf .

I 1 1 I
1 I I I
CLEAR
~r:% 90%~:------------------------------::

I DATA
I
i
--I l-tr
10%J.Liol!:r--~~----------~~~ref""'"\Lt:'1~I-~:
--I I4-tf

---- ---------"
INPUT
! ~ VI of~ OV

II I-
-I t-tf
t", -:
1 I. t.., ~I ~~_ _ _ __
LOAD I 9O%~i V re f Z 90i ~ V'ef~9M. 3V
INPUT --I tpHL I- .,,10% 10% Fj 1 1cr:]jll~ _______ 0V
I 1 --I t-tr I +I ~tr
1 I.--tPLH _----..!I.==!tp:!!H,!;;L====:~:d.---- VOH
-I
Q
OUTPUT
~...vr_ef_ _ _ _ _ _ _ _ _ _ _ _/Vref ~Vref
- , " , - - _ VOL

VOLTAGE WAVEFORMS

NOTES: A. The pulse generators have the following characteristics: Zout '" 50 n and for the data pulse generator PRR";; 500 kHz, duty
cycle = 50%; for the load pulse generator PR R is two times data PRR, duty cycle = 50%.
B. CL includes probe and jig capacitance.
C. Diodes are 1 N3064 for '192, '193, 'LS192, and 'LS193; 1 N916 for 'L 192 and 'L 193.
D. tr and tf ,,;; 7 ns for '192, '193, 'LS192, and 'LS193;";; 25 ns for 'L 192 and 'L 193.
E. Vref is 1.5 volts for '192 and '193; 1.3 volts for 'L192, 'L193; 'LS192, and 'LS193,

FIGURE 1-CLEAR, SETUP, AND LOAD TIMES

1076

7-314 TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54192, SN54193, SN54L192, SN54L193, SN54LS192, SN54LS193,
SN74192, SN74193, SN74L192, SN74L193, SN74LS192, SN74LS193
SYNCHRONOUS 4-81T UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)
PARAMETER MEASUREMENT INFORMATION

OUTPUTS

4V
r----"----..
Co Oc OsQ A CARRY BORROW

r------- ----- -- ~
PULSE I RL I
GENERATOR
BORROW I :
(See Note AI
I
CARRY H-+-+-+-~
Q
A
I
I
T CL
(See Note BI
...L

i
(See Note CI
:'T"~ 30 pF
(used WIth
I
I
I
Os I -= "7..7 '54LI'74L I
I only I I
Oc
IL ______________
LOAD CIRCUIT 1 _ .J'

'"- - .
CLEAR Co
' - - - - - + - 0 LOAD
r~----~=~:~;----,

III w
_.!~:!O~~:;,'.: ____ j
,..- --- -70::C:~,;3- - - - -,
I -------------.-----I
L _ _ _ (Same as load Circuit 1)

r------------------.
II

G
~ iSa~:O~C~::~lJ
L ___________. _____ ~
:
I~----------------~
L ____ ~::=~~~c:\!.! ____ J
LOAD CI RCUIT 5 •

r-------~--------~
I LOAD CIRCUIT 6 I
(Same as Load CirCUit 1) I
TEST CIRCUIT L _________ - - - - - - - J

tl -l r-~ r-tr

~ 90% li_yJI ~vrel ~5

COUNT
9 Vrel 16 V -;---3V
UP re
INPUT 10% --
I I -t---- OV
(See Note OJ
-l'PLHi-
I
I ! V OH
OUTPUT

(See Note EI ---------------1t

Vrel

I
--+t 'PHL ~
:~'PHL~
: -\:::.
VOL I
'.!~'PLH~ V OH
CARRY
OUTPUT Vref~~e~
- - - VOL

COUNT
OOWN
INPUT
(See Note 01
~ 1
tl::l:~\...:....7t
90%
10%

-------------.......,.1
-2-'
--
,
r-\
i
--''PHLf--
Vret ~
,{h .
" ~
r--\,
Vrel -x...:.Jt
, + -,- -
1
I
r---3V

-!'PLHI4-
v:t

~
0 V

VOH
i ~::::e~
OUTPUT
'Vret I
(See Note EJ
__________________________ -+j tpHL
~~ ::l t
,PLH~ 1-
-- VOL
V

OH
BORROW
OUTPUT Vref~V~f_
VOLTAGE WAVEFORMS --- VOL

NOTES: A. The pulse generator has the following characteristics: PRR"';; 1 MHz, Zout '" 50 n, duty cycle = 50%.
B. CL includes probe and jig capacitance.
C. Diodes are 1 N3064 for '192, '193, 'LS192, and 'LS193; 1 N916 for 'L192 and 'L 193.
D. Count-up and count-down pulse shown are for the '193, 'L193, and 'LS193 binary counters. Count cycle for '192, 'L192,
and 'LS192 decade counters is 1 through 10.
E. Waveforms for outputs 0A, 0B, and 0c are omitted to simplify the drawing.
F. trand tf"';; 7 nsfor '192, '193, 'LS192, and 'LS193;"';; 25 nsfor'L192 and 'L193.
G. Vrsf is 1.5 volts for '192 and '193; 1.3 volts for'L 192, 'L193, LS192, and 'LS193.
FIGURE 2-PROPAGATION DELAY TIMES

1076

TEXAS INSTRUMENTS INCORPORATED

7-315
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TTL TYPES SN54194, SN54LS194A, SN54S194,
SN74194, SN74LS194A, SN74S194
MSI 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS
BULLETIN NO. DL-S 7611866. MARCH 1974-REVISED OCTOBER 1976

SN54194, SN54LSl94A, SN54S194 .•. J OR W PACKAGE

• Parallel Inputs and Outputs SN74194, SN74LSl94A, SN74S194 " . J OR N PACKAGE
(TOP VIEW)
• Four Operating Modes:
Vcc OA Os 0c OD CLOCK S1 so
Synchronous Parallel Load
Right Shift
Left Shift
Do Nothing

• Positive Edge-Triggered Clocking

• Direct Overriding Clear

TYPICAL
TYPICAL
MAXIMUM
TYPE POWER
CLOCK
OISSIPATION
FREQUENCY CLEAR ~~~~~ \ A DI SL~I;;
'194 36 MHz 195mW SERIAL PARALLEL INPUTS SERIAL
INPUT INPUT
'L5194A 36 MHz 75mW
'5194 105 MHz 425mW
positive logic: see function table
description

These bidirectional shift registers are designed to incorporate virtually all of the features a system designer may want in
a shift register. The circuit contains 46 equivalent gates and features parallel inputs, parallel outputs, right-shift and
left-shift serial inputs, operating-mode-control inputs, and a direct overriding clear line. The register has four distinct
modes of operation, namely:
Parallel (broadside) load
Shift right (in the direction GA toward GO)
Shift left (in the direction GO toward GA)
Inhibit clock (do nothing)
Synchronous parallel loading is accomplished by applying the four bits of data and taking both mode control inputs, SO
and Sl, high. The data are loaded into the associated flip-flops and appear at the outputs after the positive transistion

I of the clock input. During loading, serial data flow is inhibited.

Shift right is accomplished synchronously with the rising edge of the clock pulse when SO is high and Sl is low. Serial
data for this mode is entered at the shift-right data input. When SO is low and Sl is high, data shifts left synchronously
<lnd new data is entered at the shift-left serial input.

Clocking of the flip-flop is inhibited when both mode control inputs are low. The mode controls of the
SN54194/SN74194 should be changed only while the clock input is high.

FUNCTION TABLE
INPUTS OUTPUTS H = high level (steady state)

~I I xL == low
SERIAL PARALLEL level (steady state)
CLEAR CLOCK QA QB Qc QD irrelevant (any input. including tran·
Sl SO LEFT RIGHT A B C D
sitions)
L X X X X X X X X X L L L L t = transition from low to high level
H X X L X X X X X X QAO QBO QCO QDO a. b. c. d = the level of steady·state input at
inputs A. B. C. or D. respectively.
H H H t X X a b c d a b c d
0AO. 0BO. 0CO. ODD = the level of 0A.
H L H t X H X X X X H QAn QBn QCn 0B. 0C. or 0D. respectively. before the
H L H t X L X X X X L QAn QBn QCn indicated steady·state input conditions
were established.
H H L t H X X X X X QBn QCn QO n H
0An. 0Bn. 0Cn. 0Dn = the level of 0A.
H H L t L X X X X X QBn QCn QO n L 0B. 0C. respectively. before the most-
H L L X X X X X X X QAO QBO QCO QOO recent t transition of the clock.

1076

. 7-316 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54194, SN54LS194A, SN54S194,
SN74194, SN74LS194A, SN74S194
4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS
functional block diagrams
'194

SHIFT PARALLEL INPUTS SHIFT

~---------------------------------~---------------------------------~\ S~~~L
RIGHT
SERIAL
INPUT A B D INPUT
(2) (3) (4) (5) (6) (7)

(15) (14) (13) (12)

QA Os Oc QD

v
PARALLEL OUTPUTS

'LS194A, 'S194

.
PARALLEL INPUTS

MODE
51
(51 (61
I
CONTROL
INPUTS
{
so

SHIFT SHIFT

:~~~L-=------' ..-+++__1"(1,,-) ~~~~L

INPUT

DB 00 ,

374

TEXAS INSTRUMENTS
I~CORPORATED
7·317 .
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54194, SN54LS194A, SN54S194,
SN74194, SN74LS194A, SN74S194
4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS
typical clear, load, right-shift, left-shift, inhibit, and clear sequences

a:

1~
I-
iii
J:
2

----- ----------- --- ------ -------+

l-
LL.
W
...J
l-
LL.
J:

______________________________________1
-- ---- --- --- --- --- --- --- --- --- ---- -T
I-

•
J:
t::I
a:
l-
LL.
J:
CI)

--t---~-- --------' --- --- ------- --~~~__ ]_ ~_ ].l

-- -- - - --- -- --- -- :t--~ --i--:' -- ---- -- --- - -- ~
" --- --- ---- ---- --- ---- --r- --r- --r --,... --<C
I I I I I I I I I I I I W
I I I I I I I I I I I I ...J
~ 0 ... a: a: ...J <C co u 0 <C co U 0 U
9 ~ ~ '-v--/\ v /\ 0 0 v a 0 /
U ...J ...J...J CI)...J en
woCl) U <C<CI- W en I-
o a:
I- -I-~ ...J<CI- ~
ol-~ a:<c~ ...JI-~ ~
2 w02 <C<C~ I-
:2:0~ en - a:02 ~
U <C - 0
~

374

7-318 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54194, SN54LS194A, SN54S194,
SN74194, SN74LS194A.· SN74S194
4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS
REVISED OCTOBER 1976

schematics of inputs and outputs

'194

EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS

---+--VCC
V C C - - -.....- -

INPUT

OUTPUT

Clock input: Req = 4 kn NOM

All other inputs: R,,'1 = 6 kn NOM

'LS194A

EQUIVALENT OF R, L, EQUIVALENT OF CLEAR, TYPICAL OF ALL OUTPUTS

A, B, C, AND D INPUTS CLOCK, SO, AND S1 INPUTS
- - - -......- - - VCC
120nNOM

' - - -.....- - OUTPUT

I
'S194

EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS

- - - -......- - - V CC
50 n NOM
V CC - - -.....- -

INPUT
~~..--- OUTPUT

Clear, shift/load: Req = 4 kn NOM

All other inputs: Req = 2.8 kr2 NOM

1076

TEXAS Ir-.CORPORATED
INSTRUMENTS 7-319
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54194, SN14194
4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS
REVISED MARCH 1974

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) .... . 7V
Input voltage . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range: SN54194 -55°C to 125°C
SN74194 oOe to 70°C
Storage temperature range -65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54194 SN74194
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, IOH -SOO -SOO J,lA
Low-level output current, IOL 16 16 mA
elock frequency, f clock 0 25 0 25 MHz
Width of clock or clear pulse, tw 20 20 ns
I Mode control 30 30 ns
Setup time, tsu I Serial and parallel data 20 20 ns
I elear inactive-state 25 25 ns
Hold time at any input, th 0 0 ns
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54194 SN74194
PARAMETER TEST CONDITIONSt UNIT
MIN TYP+ MAX MIN TYP+ MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage O.S O.S V
VIK I nput clamp voltage Vee = MIN, 11= -12 mA -1.5 -1.5 V
Vee= MIN, VIH=2V,
VOH High-level output voltage 2.4 3.4 2.4 3.4 V
VIL=O.SV, IOH= -SOOJ,lA
Vee = MIN, VIH = 2 V,
VOL Low-level output voltage 0.2 0.4 0.2 0.4 V

I
VIL = O.S V, IOL = 16 mA
II Input current at maximum input voltage Vee = MAX, VI = 5.5V 1 1 mA
IIH High-level input current Vee - MAX, VI - 2.4 V 40 40 J,lA
IlL Low-level input current Vee = MAX, VI = 0.4 V -1.6 -1.6 mA
i iOS Short-circuit output current§ Vee = MAX -20 -57 i -18 -57 rnA i
lee Supply current Vee = MAX, See Note 2 39 63 39 63 mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at VCC = 5 V, T A = 25°C.
§Not more than one output should be shorted at a time.
NOTE 2: With all outputs open, inputs A through D grounded, and 4.5 V applied to SO, 51, clear, and the serial inputs, ICC is tested with a
momentary GND, then 4.5 V applied to clock.

switching characteristics, Vee = 5 V, TA = 25°e

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f max Maximum clock frequency 25 36 MHz
eL=15pF,
tPHL Propagation delay time, high-to-Iow-Ievel output from clear 19 30 ns
RL = 400 n,
tPLH Propagation delay time, low-to-high-Ievel output from clock 14 22 ns
See Figure 1
tPHL Propagation delay time, high·to·low-Ievel output from clock 17 26 ns

1076

7-320 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54LS194A, SN74LS194A
4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS
REVISED OCTOBER 1976

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ...... . 7V
Input voltage . . . . . . . . . . . . . . . 7V
Operating free-air temperature range: SN54LS194A -55°C to 125°C
SN74LS194A oOe to 70°C
Storage temperature range -65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54LS194A SN74LS194A
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -400 -400 jJ.A
Low-level output current, 10L 4 8 rnA
elock frequency, f clock 0 25 0 25 MHz
Width of clock or clear pulse, tw 20 20 ns
! Mode "ontrol 30 30 n~

Setup time, tsu I Serial and parallel data 20 20

elear inactive-state 25 25
Hold time at any input, th o o
Operating free-air temperature, T A -55 125 o 70

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS194A SN74LS194A
PARAMETER TEST CONDITIONSt UNIT
MIN TYP:j: MAX MIN TYP:j: MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage I 0.7 I 0.8 V
VIK Input clamp voltage Vee- MIN, 11- -18 rnA -1.5 -1.5 V
Vee- MIN, VIH=2V,

•
VOH High-level output voltage 2.5 3.5 2.7 3.5 V
VIL = VIL max, 10H = -400jJ.A
Vee = MIN, VIH=2V, iIOL=4mA 0.25 0.4 0.25 0.4
VOL Low-level output voltage V
VIL = VIL max iloL = 8 rnA 0.35 0.5
Input current at
II Vee = MAX, VI = 7V 0.1 0.1 rnA
maximum input voltage
IIH High-level input current Vee= MAX, VI = 2.7 V 20 20 jJ.A
IlL LOW-level input current Vee - MAX, VI-0.4V -0.4 -0.4 rnA
lOS Short-circuit output current § Vee= MAX -20 -100 -20 -100 rnA
lee Supply current Vee= MAX, See Note 2 15 23 15 23 rnA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
fAil typical values are at Vee = 5 V, T A = 25°C.
§ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
NOTE 2: With all outputs open, inputs A through D grounded, and 4.5 V applied to SO, S1, clear, and the serial inputs, ICC is tested with a
momentary GND, then 4.5 V, applied to clock.

switching characteristics, Vee = 5 V, T A = 25°e

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f max Maximum clock frequency 25 36 MHz
eL=15pF,
tpHL Propagation delay time, high-to-Iow-Ievel output from clear 19 30 ns
RL = 2 kn,
tpLH Propagation delay time, low-to-high-Ievel output from clock 14 22 ns
See Figure 1
tpHL Propagation delay time, high-to-Iow-Ievel output from clock 17 26 ns

1076
TEXAS INCORPORATED
INSTRUMENTS 7-321
POST OFFICE BOX 5012" • DALLAS. TEXAS 75222
 TYPES SN54S194, SN74S194
4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS
REVISED MARCH 1974

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) 7V
Input voltage . . . . . . . ..... . 5.5 V
Operating free-air temperature range: SN54S194 -55°C to 125°C
SN74S194 o°c to 70°C
Storage temperature range -65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54S194 SN74S194
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -1 -1 rnA
Low-level output current, 10L 20 20 rnA
Clock frequency, fclock 0 70 0 70 MHz I
Width of clock pulse, tw(clock) 7 7 ns
Width of clear pulse, tw(clead 12 12 ns
I Mode control 11 11 ns
Setup time, tsu I Serial and parallel data 5 5 ns
I Clear inactive-state 9 9 ns
Hold time at any input, th 3 3 ns
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54S194 SN74S194
PARAMETER TEST CONDITIONSt UNIT
MIN TVP:j: MAX MIN TVP:j: MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
VIK Input clamp voltage Vee; MIN, II ;-18mA ! -1.2 -1.2 V
Vee; MIN, VIH;2V,
VOH High-level output voltage 2.5 3.4 2.7 3.4 V

I
VIL; 0.8 V, 10H; -1 rnA
Vee; MIN, VIH=2V,
VOL Low-level output voltage 0.5 0.5 V
VIL; 0.8 V, 10L; 20 rnA
II Input current at maximum input voltage Vee = MAX, VI = 5.5 V 1 1 rnA
ilH High-level input current 'Vee; MAX, Vi = 2.4 V 50 ' 50 ' p.A
IlL Low-level input current Vee; MAX, VI; 0.4 V -2 -2 rnA
lOS Short-circuit output current§ Vee; MAX -40 -100 -40 -100 rnA
Vee - MAX, See Note 2 85 135 85 135

ICC Supply current VCC = MAX,

T A ; 125° e,
I W package
rnA
110
See Note 2 I
t For conditions shown as M IN or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at V r r ; 5 V, T A; 25°C.
§ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
NOTE 2: With all outputs open, inputs A through D grounded, and 4.5 V applies to SO, 51, clear, and the serial inputs, ICC is tested with a
momemtary GND, then 4.5 V, applied to clock.

switching characteristics, Vee = 5 V, T A = 25°e

PARAMETER TEST CONDITIONS MIN TVP MAX UNIT
f max Maximum clock frequency 70 105 MHz
CL;15pF,
tpHL Propagation delay time, high-to-Iow-Ievel output from clear 12.5 18.5 ns
RL;280n,
tPLH Propagation delay time, low-to-high-Ievel output from clock 4 8 12 ns
See Figure 1
tPHL Propagation delay time, high-to-Iow-Ievel output from clock 4 11 16.5 ns

1076

7-322 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54194, SN54LS194A, SN54S194,
SN74194, SN74LS194A, SN74S194
4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS
PARAMETER MEASUREMENT INFORMATION

TEST TABLE FOR SYNCHRONOUS INPUTS

OUTPUT VCC DATA INPUT OUTPUT TESTED

S1 SO
FOR TEST (SEE NOTE E)
FROM A 4.5V 4.5V QA at tn+1
OUTPUT B 4.5V 4.5V QB at tn+1
UNDER C 4.5V 4.5V QC at tn+1
TEST
D 4.5V 4.5V QD at tn+1
L Serial Input 4.5V OV QA at tn+4
R Serial Input OV 4.5V QD at tn+4
LOAD FOR OUTPUT UNDER TEST

I" al tw(clearl

w~:-------------------
3V
CLEAR
OV
I I
Vffif
I
I
r-- n
tr-- tsu tn+1
(See Note F)
n
t
tn+1

~
3V
CLOCK I Vref

"'l !++.th OV

~
3V
I

•
DATA I
INPUT I Vref I _~r~ _ _ _
(SEE TEST I OV
TABLE) I I I
I I

OUTPUT Q
tPHL ~
I

\Vref
I
I"'PlH

VOLTAGE WAVEFORMS
p1 V:---
Vref
f----.t-:-tp H L
I
VOH

VOL

NOTES: A. The clock pulse generator has the following characteristics: Zout'" 50 nand PRR .;; 1 MHz, For '194, tr';; 7 ns and tf';; 7 ns.
For 'LS194A, tr .;; 15 ns and tf';; 6 ns. For 'S194, tr .;; 2.5 ns and tf .;; 2.5 ns. When testing f max , vary PRR.
B. CL includes probe and jig capacitance.
C. All diodes are 1 N3064 or 1 N916.
D. A clear pu lse is applied prior to each test.
E. For '194 and 'S194, Vref = 1.5 V; for 'LS194A, Vref = 1.3 V.
F. Propagation delay times (tpLH and tpHLl are measured at tn+1' Proper shifting of data is verified at tn+4 with a functional test.
G. tn = bit time before clocking transition.
tn+1 = bit time after one clocking transition.
tn+4 = bit time after four clocking transitions.

FIGURE 1-SWITCHING TIMES

1076

TEXAS INCORPORATED
INSTRUMENTS 7·323
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TTL TYPES SN54195, SN54LS195A, SN54S195,
SN74195, SN74LS195A, SN74S195
MSI 4-81T PARALLEL-ACCESS SHIFT REGISTERS
BULLETIN NO. DL·S 7611 MARCH 1974-REVISED OCTOBER 1976

SN54195, SN54LS195A, SN54S195 ••• J OR W PACKAGE

SN74195, SN74LS195A, SN74S195 ..• J OR N PACKAGE
• Synchronous Parallel Load (TOPVIEWI

• Positive-Edge-Triggered Clocking ~ ______ OUTPUTS

________
~A~ ~

_ \ SHIFT!
• Parallel Inputs and Outputs from OB aD aD CLOCK LOAD

Each Flip-Flop
• Direct Overriding Clear
• J and K Inputs to First Stage
• Complementary Outputs from Last Stage
• For Use in High-Performance:
Accu mu lators/Processors
Serial-to-Parallel, Parallel-to-Serial Converters

description CLEAR K A GND

~\ v~-_--J
These 4-bit registers feature parallel inputs, parallel SERIAL INPUTS PARALLEL INPUTS

outputs, J-K serial inputs, shift/load control input,

and a direct overriding clear. All inputs are buffered positive logic: see function table

to lower the input drive requirements. The registers

have two modes of operation: TYPICAL TYPICAL
TYPE MAXIMUM CLOCK POWER
Parallel (broadside) load FREQUENCY DISSIPATION
Shift (in the direction QA toward QD) '195 39 MHz 195mW
'LS195A 39 MHz 70mW
Parallel loading is accomplished by applying the four 'S195 105 MHz 350mW
bits of data and taking the shift/load control input
low. The data is loaded into the associated flip-flop and appears at the outputs after the positive transition of the clock
input. During loading, serial data flow is inhibited.

• Shifting is accomplished synchronously when the shift/load control input is high. Serial data for this mode is entered at
the J·K inputs. These inputs permit the first stage to perform as a J-K, D-, or T-type flip-flop as shown in the function
table.

The high-performance '5195, with a 105-rnegahertz typical maximum shift-frequency, is particular!y attractive for very-
high-speed data processing systems. In most cases existing systems can be upgraded merely by using this
Schottky-clamped shift register.

FUNCTION TABLE
H ; high level (steady state)
INPUTS OUTPUTS
L; low level (steady state)

CLEAR
SHIFTI
CLOCK
SERIAL PARALLEL x; irrelevant (any input. including transitions)
LOAD J K A B C 0
QA QB Oc Qo aD t ; transition from low to high level
a. b, c, d = the level of steady-state input at A. B.
L X X X X X X X X L L L L H
- C. or D. respectively
H L t X X a b c d a b c d d 0AO. 0BO. 0CO. 0DO ; the level of 0A. 0B. 0C.
H H L X X X X X X QAO QBO QCO QOO aDO or 0D. respectively. be-
fore the indicated steady-
H H t L H X X X X QAO QAO QBn QCn aCn
- state input conditions
H H t L L X X X X L QAn QBn QCn QCn were established
-
H H t H H X X X X H QAn QBn QCn QCn 0An. 0Bn. 0Cn ; the level of 0A, 0B, or 0C,
respectively, before the most-
H H t H L X X X X DAn QAn QBn QCn DCn recent transiti on of the clock

1076

7-324 TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54195, SN54LS195A, SN54S195,
SN74195, SN74LS195A, SN74S195
4-811 PARALLEL-ACCESS SHIFT REGISTERS
functional block diagram
SERIAL
INPUT PARALLEL INPUTS

~ f~A----------------~A~----------------~~
121 131 141 lSI 161

~~I!~/ (9)
~~+--+-.4-------~~--------~~--------~
' 'I
CONTROL

CLOCK~.....f--1-+-}~-+---t-1------------t--~-----t--+---J
CLEAR 1 1 1 . c{:>o)-----+I-+---.--f+-\-+-----.--++-i-~t_-r__+-_r__-___,

(14) 1131

OA Os Oc

\~--------------~v~-----------------~
PARALLEL OUTPUTS
tThis connection is made on '195 only.

typical clear, shift, and load sequences

SERIAL
CLOCK

CLEAR

J
I
I
____~____~r--r-1~______________________~_____+----------------------
I I
•
-----~----~~~----------------------~'----~----------------------
INPUTS { R
I
SHIFT LOAD -----~------~-------------------------,Ll_J
I

----~------~----------------------~~~~~--------------------
I
L I
PARALLEL{ :
DATA I
INPUTS C
----~------~----------------------~~~~~--------------------
I
o L I
I I

~
A ---"""~~______~r----1,_--------------------~r----1...---------------------
--- : I I
08 ---~ I I
OUTPUTS ---~:--------~I----~
Oc ---, I
---~:--------~I--------~
00 ---~ I
, I
14'
..- - - - - SE R IA L SH I FT --------t ~ SERIAL S H I F T _

CLEAR LOAD

374

TEXAS I ....INSTRUMENTS
CORPORATED
7-325
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54195, SN54LS195A, SN54S195, SN74195, SN74LS195A, SN74S195
4-81T PARALLEL-ACCESS SHIFT REGISTERS
REVISED OCTOBER 1976

schematics of inputs and outputs

'195

EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS

VCC--------~-------
-----4.------ V cc

INPUT

OUTPUT

Clock input: Req =4 kf!. NOM

All other inputs: Req =6 kf!. NOM

'LS195A

EQUIVALENT OF J, K, EQUIVALENT OF CLEAR, CLOCK, TYPICAL OF ALL OUTPUTS

A, B, C, AND D INPUTS ANDSHIFT/LOAD INPUTS
--------------....- - - - V CC
120 f!. NOM
VCC--------~------- VCC---------~-------

15 kf!. NOM 17 kf!.

INPUT----~~------ INPUT--~~~----e-
' - - -......- - OUTPUT

• 'S195

TYPICAL OF ALL OUTPUTS

EQUIVALENT OF EACH INPUT

-------------....- - - - V CC
50 f!. NOM
VCC------~-------

INPUT
L-.___....____ OUTPUT

Clear, shift/load: Req = 4 kf!. NOM

All other inputs: Req = 2.8 kf!. NOM

1076<

7-326 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54195, SN74195
4-81T PARALLEL-ACCESS SHIFT REGISTERS

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) 7V
Input voltage . . . . . . . . 5.5 V
Operating free-air temperature range: SN54195 -55°C to 125°C
SN74195 O°C to 70°C
Storage temperature range -65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54195 SN74195
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -800 -800 !LA
Low-level output current, 10L 16 16 mA
Clock frequency, fclock 0 30 0 30 MHz
Width of dock !nput pu!se, tw(ciock) 'u i6 ns
Width of clear input pulse, tw(clear) 12 12 ns
I Shift/load 25 25
Setup time, tsu (see Figure 1) I Serial and parallel data 20 20 ns
1 Clear inactive-state 25 25
Shift/load release time, trelease (see Figure 1) 10 10 ns
Serial and parallel data hold time, th (see Figure 1) 0 0 ns
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST eONDITIONSt MIN TYP+ MAX UNIT
VIH High·level input voltage 2 V

•
VIL LO)l\l·level input voltage 0.8 V
VIK Input clamp voltage Vee = MIN, 11= -12 mA -1.5 V
Vee = MIN. VIH = 2 V,
VOH High·level output voltage 2.4 3.4 V
VIL = 0.8 V, 10H = -800}.LA
Vee = MIN, VIH = 2 V,
VOL Low-level output voltage 0.2 0.4 V
VIL = 0.8 V, 10L = 16 mA
II Input current at maximum input voltage Vee = MAX. VI = 5.5 V 1 mA
IIH High·level input current Vee= MAX. VI=2.4V 40 }.LA
IlL Low-level input current Vee = MAX, VI = 0.4 V -1.6 mA

Short·circuit output current§ Vee = MAX

I SN54195 -20 -57
mA
lOS
I SN74195 -18 -57
ICC Supply current Vee= MAX, See Note 2 39 63 mA

t For conditions shown as M IN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at Vee = 5 V, T A = 25°e.
§ Not more than one output should be shorted at a time.
NOTE 2: With all outputs open, shift/load grounded, and 4.5 V applied to the J, K, and data inputs, lee is measured by applying a
momentary ground, followed by 4.5 V, to clear and then applying a momentary ground. followed by 4.5 V, to clock.

switching characteristics, Vee = 5 V, TA = 25°e

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f max Maximum clock frequency 30 39 MHz
eL = 15 pF,
tPHL Propagation delay time, high-to-Iow-Ievel output from clear 19 30 ns
RL=400n,
tPLH Propagation delay time, low-to-high-Ievel output from clock 14 22 ns
See Figure 1
tpHL Propagation delay time, high-to-Iow-Ievel output from clock 17 26 ns

·076

TEXASINCORPORATED
INSTRUMENTS 7-327
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54LS195A, SN14LS195A
4-81T PARALLEL-ACCESS SHIFT REGISTERS
REVISED OCTOBER 1976

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply Voltage, Vee (see Note 1) 7V
Input voltage 7V
Operating free-air temperature range: SN54LS195A -55°e to 125°e
SN74LS195A oOe to 700e
0
Storage temperature range -65°e to 150 e

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54LS195A SN74LS195A
UNIT
MIN NOM MAX MIN NOM MAX
Supply VOltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -400 -400 /-LA
Low-level output current, 10L 4 8 mA
Clock frequency, fclock 0 30 0 30 MHz
Width of clock or clear pulse, tw(clock) 16 16 ns
Width of clear input pulse, tw(clear) 12 12 ns

I Shift/load 25 25
Setup time, tsu (see Figure 1) I Serial and parallel data 15 15 ns

I Clear inactive-state 25 25
Shift/load release time, trelease (see Figure 1) 10 10 ns
Serial and parallel data hold time, th (see Figure 1) 0 0 ns
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS195A SN74LS195A
PARAMETER TEST eONDlTlONSt UNIT
MIN TYP+ MAX MIN TYP+ MAX

•
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
VIK Input clamp voltage Vee = MIN, II = -18 mA -1.5 -1.5 V
Vee - MIN, VIH - 2 V,
VOH High-level output voltage 2.5 3.4 2.7 3.4 V
VIL = VIL max, 10H = -400 /-LA
Vee - MIN, VIH-2V,IIOL=4mA 0.25 0.4 0.25 0.4
, VOL Low-!evel output voltage V
VIL = Vil. max i I OL=8mA iI 0.35 0.5' !
Input current at
II Vee= MAX, VI = 7 V 0.1 0.1 mA
maximum input voltage
IIH High-level input current Vee= MAX, VI=2.7V 20 20 /-LA
IlL Low-level input current Vee = MAX, VI = 0.4 V -0.4 -0.4 mA
lOS Short-circuit output current§ Vee= MAX -20 -100 -20 -100 mA
ICC Supply current Vee= MAX, See Note 2 14 21 14 21 mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:~AII typical values are at V CC = 5 V, T A = 25' C.
~Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second,
NOTE 2: With all outputs open, shift/load grounded, and 4.5 V appl,ed to the J, K, and data inputs, ICC IS measured by applYing a momentary
ground, followed by 4.5 V, to clear and then applying a momentary ground, followed by 4.5 V, to clock.

switching characteristics, Vee = 5 V, TA = 25°e

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f max Maximum clock frequency 30 39 MHz
eL=15pF,
tpHL Propagation delay time, high-to-Iow·level output from clear 19 30 ns
RL = 2 kl2,
tpLH Propagation delay time, low·!o-high·level output from clock 14 22 ns
See Figure 1
tpHL Propagation delay time, high·to-Iow-Ievel output from clock 17 26 ns

1076

7-328 INSTRUMENTS
TEXAS I"'CORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54S195, SN74S195
4-81T PARALLEL-ACCESS SHIFT REGISTERS
REVISED MARCH 1974

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) 7V
Input voltage . . . . . . . 5.5 V
Operating free-air temperature range: SN54S195 -55°C to 125°C
SN74S195 aOe to 7aoe
Storage temperature range -65°C to 15aoe

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54S195 SN74S195
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -1 -1 rnA
Low-jevei output current, iOL 20 20 rnA
Clock frequency, fclock 0 70 0 70 MHz
Width of clock input pulse, tw(clockl 7 7 n~

Width of clear input pulse, w(clearl 12 12 ns

i Shift!ioaci 11 11
Setup time, tsu (see Figure 11 I Serial and parallel data 5 5 ns
I Clear inactive-state 9 9
Shift/load release time, trelease (see Figure 11 6 6 ns
Serial and parallel data hold time, th (see Figure 11 3 3 ns
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
i i i
I PARAMETER
I
TEST CONDITIONSt MIN TYPt MAX UNIT
V,H High-level input voltage 2 V

•
V,L Low-level inpUt voltage 0.8 V
V,K Input clamp voltage Vee = MIN, II = -18mA -1.2 V
Vee = MIN, V,H = 2V, ISN54S195 2.5 3.4
High-level output voltage V
VOH
V,L = 0.8 V, 10H=-lmA I SN74S195 2.7 3.4
Vee= MIN, V,H = 2 V,
VOL Low-level output voltage 0.5 V
V,L = 0.8 Y, 10L = 20 rnA
I, Input current at maximum input voltage Vee = MAX, V,=5.5V 1 rnA

"H High-level input current Vee = MAX, V, = 2.7 V 50 IJA

I,L Low-level input current Vee= MAX, V, =0.5V -2 rnA
lOS Short-circuit output current§ Vee = MAX -40 -100 rnA

Supply current Vee = MAX, See Note 2

I SN54S195 70 99
mA
ICC
I SN74S195 70 109

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAli typical values are at V CC = 5 V, T A = 25° C.
§ Not more
than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
NOTE 2: With all outputs open, shift/load grounded, and 4.5 V applied to the J, K, and data inputs, ICC is measured by applying a momentary
ground, followed by 4.5 V, to clear, and then applying a momentary ground, followed by 4.5 V, to clock.

switching characteristics, Vee = 5 V, T A = 25° C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f max Maximum clock frequency 70 105 MHz
eL=15pF,
tPHL Propagation delay time, high-to-Iow-Ievel output from clear 12.5 18.5 ns
RL = 280 n,
tPLH Propagation delay time, low-to-high-Ievel output from clock 8 12 ns
See Figure 1
tpHL Propagation delay time, high-to-Iow-Ievel output from clock 11 16.5 ns

'076

TEXAS INCORPORATED
INSTRUMENTS 7-329
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54195. SN54LS195A, SN54S195.
SN74195, SN74LS195A, SN74S195
4-81T PARALLEL-ACCESS SHIFT REGISTERS
PARAMETER MEASUREMENT INFORMATION

OUTPUT VCC

FROM OUTPUT
---e~~-4~~ __ M-~~
UNDER TEST
CL; 15 pF
(See Note B)

LOAD FOR OUTPUT UNDER TEST

I- _; tw(clearl
----... l 1 3V~'
CLEAR
~.:: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ OV
--I
tsu
tn....,
r+ t n+l tn
r+
+-; tn+l
____ 3V

CLOCK Vref Vref

1~--~~~~:7~~----'1
fool tw(clock) ~ th
I th
...r-t- OV

DATA
(See Note Gl ______.....;_________.J
,rtsetup:
Vref
~..
1"\:.:::.J
p~
\
tsu
Vref
11
I
1, . - - - - - 3V
Vref OV

~ tsu ----.t r- tsu --.j

SHIFT/LOAD
-----+----'\'{
I

~
v __ < -1'
,_

Vref
..,
I
I
trelease
2~ ..
1

~~~i-------
rr--
I- -, trelease
3V
OV

•
~tPHL ---.-.I ...... tPLw---i \4--tPHL-.I
I Ir2t---
ASSOCIATED
OUTPUT Q \ Vref t Vref ~
VOH

VOL
VOLTAGE WAVEFORMS

NOTES: A. The clock pulse generator has the following characteristics: Zout '" 50 nand PRR .;; 1 MHz. For '195, tr .;; 7 ns and tf .;; 7 ns.
For 'LS195A, tr';; 15 ns and tf';; 6 ns. For 'S195, tr; 2.5 ns and tf = 2.5 ns. When testing f max , vary the clock PRR.
B. CL includes probe and jig capacitance.
C. ,1>.11 diodes are 1 N3064.
D. A clear pulse is applied prior to each test.
E. For '195 and 'S195, Vref = 1.5 V; for 'LS195A, Vref; 1.3 V.
F. Propagation delay times ItPLH and tPH L) are measured at t n +l' Proper shifting of data is verified at tn+4 with a functional test.
G. J and K inputs are tested the same as data A, B, C, and 0 inputs except that shift/load input remains high.
H. tn = bit time before clocking transition.
tn+l ; bit time after one clocking transition.
t n +4; bit time after four clocking transitions.

FIGURE 1-SWITCHING TIMES

107

7-330 TEXAS INSTRUMENTS INCORPORATED

POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54196, SN54197, SN54LS196, SN54LS197,SN54S196, SN54S197,
SN74196, SN74197, SN74LS196, SN74LS197, SN74S196, SN74S197
50/30/100 -MHz PRESETTABLE DECADE OR BINARY COUNTERS/LATCHES
BULLETIN NO. DL-S 7611806, OCTOBER 1976

• Performs BCD, Bi-Quinary, or Binary

Counting
VCC CLEAR aD
• Fully Programmable
• Fully Independent Clear Input
• Input Clamping Diodes Simplify
System Design
• Output QA Maintains Full Fan-out
Capability In Addition to Driving
Clock-2 Input

GUARANTEED
TYPICAL
- TYPES COUNT FREQUENCY
POWER DISSIPATION
CLOCK 1 CLOCK 2
'1nc '1n'"7 n 1":"1"1. • • ,1 ,..", .......
IvV, 'ui v-~u IVln£ u-.:::::o IVlnz 240mW
'LS196, 'LS197 0-30 MHz 0-15 MHz 80mW asynchronous input: LO\AJ !nput to dear sets QA.
'S196, 'S197 0-100 MHz 0-50 MHz 375mW 0B, QC, and aD low.

description
These high-speed monolithic counters consist of four doc coupled, master-slave flip-flops, which are internally
interconnected to provide either a divide-by-two and a divide-by-five counter ('196, 'LS196, 'S196) or a divide-by-two
and a divide-by-eight counter ('197, 'LS197, 'S197). These four counters are fully programmable; that is, the outputs
may be preset to any state by placing a Iowan the count/load input and entering the desired data at the data inputs.
The outputs will change to agree with the data inputs independent of the state of the clocks,

During the count operation, transfer of information to the outputs occurs on the negative-going edge of the clock pulse.

•
These counters feature a direct clear which when taken low sets all outputs low regardless of the states of the clocks .

These counters may also be used as 4-bit latches by using the count/load input as the strobe and entering data at the
data inputs. The outputs will directly follow the data inputs when the count/load is low, but will remain unchanged
when the count/load is high and the clock inputs are inactive.

All inputs are diode-clamped to minimize transmission-line effects and simplify system design. These circuits are
compatible with most TTL and DTL logic families. Series 54, 54LS, and 54S circuits are characterized for operation
over the full military temperature range of -550 C to 1250 C; Series 74, 74LS, and 74S circu its are characterized for
operation from 0 0 C to 70 0 C.

typical count configurations

'196, 'LS196, and 'S196 typical count configurations and function tables are the same as those for '176.
See page 7-260_
'197, 'LS197, and 'S197 typical count configurations and function tables are the same as those for '177.
See page 7-260.

functional block diagrams

'196, 'LS196, and 'S196 functional block diagram is the same as that for '176. See page 7-261.
'197, 'LS197, and 'S197 functional block diagram is the same as that for '177. See page 7-261.

076

TEXAS INSTRUMENTS 7-331

INCORPORATED
POST OFFICE BOX S012 • DAL.L.AS. TEXAS 75222
 TYPES SN54196, SN54197, SN74196, SN74197
50-MHz PRESETIABLE DECADE OR BINARY COUNTERS/LATCHES

schematics of inputs and outputs

EQUIVALENT OF COUNT/LOAD.
EQUIVALENT OF CLOCK INPUTS TYPICAL OF ALL OUTPUTS
CLEAR. AND DATA INPUTS

VCC-----------~--------

INPUT

NOMINAL VALUES OF
R1. R2, and R3
INPUT '196 '197
Countlload, Data: Req; 4 k.l1 NOM Clock 1 4 k.l1 4 k.l1
Clear: Req; 2 k.l1 NOM Clock 2 3 k.l1 6 k.l1

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, VCC (see Note 1) 7V

Input voltage . , . . . . . . 5.5 V
Interemitter voltage (see Note 2) 5.5 V
Operating free·air temperature range: SN54196, SN54197 Circuits -55°C to 125°C
SN74196, SN74197 Circuits O°C to 70°C
Storage temperature range -65°C to 150°C

NOTES: 1. Voltage values are with respect to network ground terminal.

•
2. This is the voltage between two emitters of a multiple·emitter transistor. For this circuit, this rating applies between the clear and
count/load inputs.

recommended operating conditions

SN54196, SN54197
NOM MAX
SN74196. SN74197
MIN NOM MAX
I I
1----'-.....:..-....:....:......---+------'....:....:......-..;;..;..---1. UNIT
MIN
Supply voltage, V CC 4.5 5 5.5 4.75 5 5.25 V
High·level output current, IOH -800 -800 /lA
Low-level output current, IOL 16 16 mA
Clock·1 input 0 50 0 50
Count frequency MHz
Clock·2 input 0 25 0 25
Clock·1 input 20 20
Clock·2 input 30 30
I
Pulse width, tw ns
Clear 15 15
Load 20 20
H igh·level data tw(ioad) tw(ioad)
Input hold time, th ns
Low·level data tw(ioad) tw(ioad)
High-level data 10 10
Input setup time, tsu ns
Low-level data 15 15
Count enable time, tenable (See Note 3) 20 20 ns
Operating free-air temperature, T A -55 125 0 70 °c

NOTE 3: Minimum count enable time is the interval immediately preceding the negative-going edge of the clock pulse during which interval the
count/load and clear inputs must both be high to ensure counting.

107

7-332 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54196, SN54191, SN14196, SN14191
50-MHz PRESETTABLE DECADE OR BINARY COUNTERS/LATCHES

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

SN54196. SN74196 SN54197. SN74197

PARAMETER TEST CONDITIONSt UNIT
MIN TYP:j: MAX MIN TYp:j: MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
VIK Input clamp voltage Vee- MIN, 11=-12mA -1.5 -1.5 V
Vee = MIN, VIH=2V,
VOH High-level output voltage 2.4 3.4 2.4 3.4 V
VIL = 0.8 V, 10H = -800J.LA
Vee - MIN, VIH=2V,
VOL Low-level output voltage 0.2 0.4 0.2 0.4 V
VIL = 0.8 V, 10L = 16mA~
II Input current at maximum input voltage Vee = MAX, VI = 5.5V 1 1 rnA
data, count/load 40 40
IIH High-level input current clear, clock 1 Vee = MAX, VI = 2.4 V 80 80 J.LA
clock 2 120 80

I
data, countlload
-'.61 -1.61
clear -3.2 -3.2
I IlL Low-level input current
clock 1
Vee = MAX, VI = 0.4V
I -4.8 -4.8
rnA

I clock 2 -3.21
I lOS Short-circuit output current § I Vee = MAX
ISN54'
1 SN74'
i -20
1 -18
-57
-57 1-18
j -20 -57
-57
rnA

I ICC Supply current I Vee = MAX, See Note 4

I 48 59 J 48 59 rnA

NOTE 4: ICC is measured with all inputs grounded and all outputs open.
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

:j:AII typical values are at Vee = 5 V, T A = 25°C.

~ QA outputs are tested at 10 L = 16 mA plus the limit value of II L for the clock-2 input. This permits driving the clock-2 input while fanning
out to 10 Series 54174 loads.
§ Not more than one output should be shorted at a time.

switching characteristics, Vee = 5 V, TA = 25°e

PARAMETERO

f max
tpLH
tpHL
tpLH
FROM
(INPUT)

Clock 1

Clock 1

Clock 2
TO
(OUTPUT)

QA

QA

QB
TEST CONDITIONS
MIN
50
SN54196
SN74196
TYP
70
7
10
12
14
MAX

12
15
18
21
MIN
50
SN54197
SN74197
TYP
70
7
10
12
14
MAX

12
15
18
21
UNIT

MHz

ns

ns
•
tpHL
tpLH 24 36 24 36
Clock 2 QC CL = 15 pF, ns
tpHL 28 42 28 42
RL =400n,
tpLH 14 21 36 54
Clock 2 QD See Note 5 ns
tpHL 12 18 42 63
tpLH 16 24 16 24
A,B,C,O QA, QB, Qe, QO ns
tpHL 25 38 25 38
tpLH 22 33 22 33
Load Any ns
tpHL 24 36 24 36
tpHL Clear Any 25 37 25 37 ns

Ofmax == maximum count frequency.

tpLH == propagation delay time, low-to-high-Ievel output.
tpH L == propagation delay time, high-to-Iow-Ievel output.
NOTE 5: Load circuit, input conditions, and voltage waveforms are the same as those shown for the '176, '177 (page 7-264) except that
testing f max , VI L = 0.3 V.

1076

TEXAS INCORPORATED
INSTRUMENTS 7·333
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54LS196, SN54LS197, SN74LS196, SN74LS197
30-MHz PRESETTABLE DECADE OR BINARY COUNTERS/LATCHES
REVISED OCTOBER 1976

schematics of inputs and outputs

r-------------------------__
EQUIVALENT OF EQUIVALENT OF EQUIVALENT OF TYPICAL OF ALL
COUNT/LOAD AND
CLOCK INPUTS DATA INPUTS OUTPUTS
CLEAR INPUTS

VCC
VCC---'---
25 kn
NOM

INPUT
INPUT ......
IW

~~ "
"
NOMINAL
r.7
VALUES OF
R1, R2, and R3
Count/Load: Req = 17 kn NOM INPUT 'LS196 'LS197
Clock 1 8 kn 8 kn
Clear: Req = 9.2 kn NOM
Clock 2 6 kn 15 kn

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, VCC (see Note 1) 7V

Input voltage . . . . . . . 5.5 V
Interemitter voltage (see Note 2). 5.5 V
Operating free·air temperature range: SN54LS196, SN54LS197 Circuits -55°C to 125°C
SN74LS196, SN74LS197 Circuits O°C to 70°C
Storage temperature range -65°C to 150°C

NOTES: 1. Voltage values are with respect to network ground terminal.

•
2. This is the voltage between two emitters of a multiple-emitter transistor. For this circuit, this rating applies between the clear and
count/load inputs .

recommended operating conditions

SN54LSl96, SN54LS197 SN74LS196, SN74LS197 UNIT
; MIN NOM MAX MIN NOM MAX
Supply voltage, VCC 4.5 5 5.5 4.75 5 5.25 V
High-level output current, IOH -400 -400 /lA
Low-level output current, IOL 4 8 mA
Clock-1 input 0 30 0 30
Count frequency MHz
Clock-2 input 0 15 0 15
Clock-1 input I 20 I 20
Clock-2 input 30 30
I
Pulse width, tw ns
Clear 15 15
Load 20 20
High-level data twOoad) twOoad)
Input hold time, th ns
Low-level data tw(load) twOoad)
High-level data 10 10
Input setup time, tsu ns
Low-level data 15 15
Count enable time, tenable (See Note 3) 20 20 ns
Operating free·air temperature, T A -55 125 0 70 °c
NOTE 3: Minimum count enable time is the interval immediately preceding the negative-going edge of the clock pulse during which interval the
count/load and clear inputs must both be high to ensure counting.

1076

7-334 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54LS196, SN54LS197, SN74LS196, SN74LS197
30-MHz PRESETTABLE DECADE OR BINARY COUNTERS/LATCHES
REVISED OCTOBER 1976

electrical characteristics over recommended operating free-air temperature range (urness otherwise noted)
SN54LSl96 SN74LS196
PARAMETER TEST CONDITIONSt SN54LS197 SN74LS197 UNIT
MIN TYP:j: MAX MIN TYP:j: MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
VIK Input clamp voltage VCC= MIN, II = -18mA -1.5 -1.5 V
VCC= MIN, VIH = 2V,
VOH High-level output voltage 2.5 3.4 2.7 3.4 V
VIL = VIL max' 10H = -400 IlA
VCC= MIN, VIH=2V, [IOL =4mA~ 0.25 0.4 0.25 0.4
VOL Low-level output voltage V
VIL = VIL max IIOL =8mA~ 0.35 0.5
Data, count/load 0.1 0.1
Input current
Clear, clock 1 0.2 0.2
II at maximum VCC= MAX, VI = 5.5 V rnA
Clock 2 of 'LS196 0.4 0.4
input voltage
Clock 2 of 'LSi97 0.2 0.2
Data, count/load 20 20
High-level Clear, clock 1 40 40
I I •••

1M mput current I V-.. -..

Clock 2 of 'LS1961 CC
=. iviAX, v = 2.7 V IlA

C!cck 2 of 'LS197 40 40
Data, count/load -0.4 -0,4
Clear -0.8 -0.8
Low-level
IlL Clock 1 VCC = MAX, VI = 0.4 V -2.4 -2.4 rnA
I nput current
Clock 2 of 'LS196 -2.8 -2.8
Clock 2 of 'LS197 -1.3 -1.3
lOS Short-circuit output current§ VCC= MAX -20 -100 -20 -100 rnA
ICC Supply current VCC= MAX, See Note 4 16 27 16 27 rnA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+Aii typicai values are at Vce = 5 V, T A = 25°C.
§ Not more than one output should be shorted at a time, and duration of the short-<:ircuit should not exceed one second.
~ QA outputs are tested at specified IOL plus the limit value of II L for the clock-2 input. This permits driving the clock-2 input while maintain-

•
ing full fan-out capability.
NOTE 4: ICC is measured with all inputs grounded and all outputs open.

switching characteristics, Vee = 5 V, TA = 25°e

SN54LS196 SN54LS197
FROM TO
PARAMETERO TEST CONDITIONS SN74LS196 SN74LS197 UNIT
(INPUT) (OUTPUT)
MIN TYP MAX MIN TYP MAX
f max Clock 1 QA 30 40 30 40 MHz
tpLH 8 15 8 15
Clock 1 QA ns
tpHL 13 20 14 21
tpLH 16 24 12 19
Clock 2 QB ns
tPHL 22 33 23 35
tPLH 38 57 34 51
Clock 2 QC CL = 15pF, ns
tpHL 41 '62 42 63
RL = 2 kn,
tpLH 12 18 55 78
Clock 2 QD See Note 6 ns
tPHL 30 45 63 95
tpLH 20 30 18 27
A,B,C,D QA,QB, QCQD ns
tpHL 29 44 29 44
tPLH 27 41 26 39
Load Any ns
tpHL 30 45 30 45
tpHL Clear Any 34 51 34 51 ns
Of max ;; maximum count frequency
tPLH ;; propagation delay time, low-to-high-Ievel output, tPH L ;; propagation delay time, high-to-Iow-Ievel output
NOTE 6: Load circuit, input conditions, and voltage waveforms are the same as those shown for the '176, '177 (page 7-264) except that
tr';;; 15 ns, tf';;; 6 ns, and Vref = 1.3 V (as opposed to 1.5 V)

1076 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
7-335
 TYPES SN54S196, SN54S197, SN74S196, SN74S197
100-MHZ PRESEnABLE DECADE AND BINARY COUNTERS/LATCHES

schematics of inputs and outputs

EQUIVALENT OF COUNT/LOAD,
EQUIVALENT OF CLOCK INPUT TYPICAL OF ALL OUTPUTS
CLEAR, AND DATA INPUTS

VCC - - - . - - VCC - - 1......- ----------~---VCC

50n
Req
.---------e NOM
INPUT
- .......>-.--'

Clock 1 Req = 1.2 kn NOM

Count/Load, Clear: Req = 2.3 kn NOM Clock 2 'S196 Req = 700 n NOM
Data: Req = 2.8 kn NOM Clock 2 'S197 Req = 1.4 kn NOM

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) 7V
Input voltage 5.5 V
Operating free-air temperature range: SN54S196, SN54S197 Circuits -55°C to 125°C
SN74S196, SN74S197 Circuits O°C to 70°C
Storage temperature range -65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.

• recommended operating conditions

Supply voltage, VCC

High-level output current, IOH
Low-level output current, IOL

Clock frequency
Clock-1 input
i MIN

:
SN54S196, SN54S197

4.5

0
NOM
5
MAX
5.5
-1
20
100
i
I
SN74S196, SN74S197
MIN
4.75

0
NOM
5
MAX
5.25
-1
20
100
i
I
UNIT

V
rnA
mA

MHz
I

Clock-2 input 0 50 0 50
Clock-1 input 5 5
Clock-2 input 10 10
I Pulse width, tw ns
Clear 30 I 30 i
Load 5 5

Input hold time, th

High-level data 3t 3t ns
Low-level data 3t 3t
Input setup time, tsu
High-level data at at ns
Low-level data at at
Count enable time, tenable (see Note 3) 12 12 ns
Operating free-air temperature, T A -55 125 0 70 °c

NOTE 3: Minimum count enable time is the interval immediately preceding the negative-going edge of the clock pulse during which interval the
count/load and clear inputs are both high to permit counting.

, 07~
7-336 TEXAS INSTRUMENTSINCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54S196, SN54S197, SN74S196, SN74S197
100-MHZ PRESETTABLE DECADE AND BINARY COUNTERS/LATCHES

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54S196, SN54S197,
PARAMETER TEST CONDITIONSt SN74S196 SN74S197 UNIT
MIN TYP+ MAX MIN TYP+ MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
VIK Input clamp voltage VCC= MIN, II = -18mA -1.2 -1.2 V
VCC= MIN, VIH = 2V, l54S 2.5 3.4 2.5 3.4
VOH High-level output voltage V
VIL = 0.8 V, 10H = -1 mA 174S 2.7 3.4 2.7 3.4
VCC= MIN, VIH=2V,
VOL Low-level output voltage 0.5 0.5 V
VIL = 0.8 V, 10L = 20 mA~
Input current at maximum
II VCC= MAX, VI = 5.5 V 1 1 mA
input voltage I
ilH High-level input current VCC= MAX, VI=2.7V I 50 50 Il A
I data, count/load
0.75 0.75 mA
Low-level input clear !
IlL
i
current I clock 1
V cc = MAX, V = 0.5 V
~I
i ciock 2 -10 -61 mA I
lOS Short-circuit output current § VCC= MAX -30 -110 -30 -110 I mA I
Supply current See Note 4
I54S 75 110 75 110 i I
ICC Vec= MAX,
174s 75 120 75 120 I mA
I
NOTE 4: ICC is measured with all inputs grounded and all outputs open.
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+All typical values are at V CC = 5 V, T A= 25°C.
, QA outputs are tested at IOL = 20 mA plus the limit value of II L for the clock-2 input. This permits driving the ciock-2 input while fanning
out to 10 Series 54S/74S loads.
§ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.

switching characteristics, Vee

PARAMETERO

f max
tpLH
tpHL
tpLH
I
FROM
(INPUT)

Clock 1

Clock 1
= 5 V, TA = 25° C
TO
(OUTPUT)

QA

QA
TEST CONDITIONS
SN54S196,
SN74S196
MIN
100
TYP
140

6
5

5
MAX

10
10
10
S1\!54S197,
SN74S197
MIN
100
TYP
140
5
6
5
MAX

10
10
10
UNIT

MHz

ns
•
Clock 2 QS ns
tPHL I 8 12 I 8 12
tpLH 12 18 ! 12 18 I 1
i

Clock 2 QC CL=15pF, ns
tPHL I I 16 24 15 22
RL =280 n,
tpLH I 5 10 18 27
Clock 2 QO See Note 7 ns
tpHL 8 12 22 33
tPLH 7 12 7 12 I
A,S,C,D QA, QS, QC, QO ns
I
tpHL 12 18 12 18 I
tPLH 10 18 10 18
Load Any ns
tPHL 12 18 12 18 I
tPHL Clear Any 26 37 26 37 ns

°f max == maximum input countY frequency.

tpLH == propagation delay time, low-to-high-Ievel output.
tpHL == propagation delay time, high-to-Iow-Ievel output.
NOTE 7: Load circuit, input conditions, and voltage waveforms are the same as those shown for the '176, '177 on page 7-264.

)76

TEXAS INCORPORATED
INSTRUMENTS 7-337
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TTL TYPES SN64198, SN64199, SN74198, SN74199
MSI 8-BIT SHIFT REGISTERS
BULLETIN NO. DL-S 7611841, DECEMBER 1972-REVISED OCTOBER 1976

description
SN54198 ..• J OR W PACKAGE
These 8-bit shift registers are compatible with most SN74198 •.. J OR N PACKAGE
other TTL, DTL, and MSI logic families. All inputs (TOP VIEW)
SHIFT
are buffered to lower the drive requirements to one LEFT
SERIAL INPUT INPUT INPUT INPUT
G F E
normalized Series 54/74 load, and input clamping 51 INPUT H

diodes minimize switching transients to simplify

system design. Maximum input clock frequency is
typically 35 megahertz and power dissipation is
typically 360 mW.
Series 54 devices are characterized for operation over
the full military temperature range of -55°C to
125°C; Series 74 devices are characterized for
operation from O°C to 70°C.
SN5419S and SN7419S
These bidirectional registers are designed to incorpo-
positive logic: see function table
rate virtually all of the features a system designer may
want in a shift register. These circuits contain 87
equivalent gates and feature parallel inputs, parallel outputs, right-shift and left-shift serial inputs, operating-mode-
control inputs, and a direct overriding clear line. The register has four distinct modes of operation, namely:
Parallel (Broadside) Load
Shift Right (In the direction OA toward 0H)
Shift Left (In the direction OH toward 0A)
Inhibit Clock (Do nothing)
Synchronous parallel loading is accomplished by applying the eight bits of data and taking both mode control inputs,
SO and Sl, high. The data is loaded into the associated flip-flop and appears at the outpuLS after the positive transition
of the clock input. During loading, serial data flow is inhibited.

•
Shift right is accomplished synchronously with the rising edge of the clock pulse when SO is high and Sl is low. Serial
data for this mode is entered at the shift-right data input. Wh~n SO is low and Sl is high, data shifts left synchronously
and new data is entered at the shift· left serial input.
Clocking of the flip-flop is inhibited when both mode cont inputs are low. The mode controls should be changed
only while the clock input is high.
'198
FUNCTION TABLE
INPUTS OUTPUTS
MODE SERIAL PARALLEL
CLEAR I---- CLOCK °A °B ... ~ °H
S1 So LEFT RIGHT A ... H
L X X X X X X L L L L
H X X L X X X QAO QBO QGO QHO
H H H t X X a ... h a b 9 h
H L H t X H X H QAn QFn <lGn
H L H t X L X L QAn QFn QGn
H H L t H X X QBn QCn °Hn H
H H L t L X X QBn QCn QHn L
H L L X X X X QAO QBO QGO QHO
H = high level (steady state), L = low level (steady state)
X = irrelevant (any input, including transitions)
t = transition from low to high level
a ... h = the level of steady-state input at inputs A thru H, respectively.
0AO, 0BO, 0GO, 0HO = the level of 0A, 0B. 0G, or 0H, respectively, before the indicated steady-state input conditions were established.
0An' 0Bn' etc. = the level of 0A, 0B, etc., respectively, before the most-recent t transition of the clock.

10'

7-338 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54199, SN74199
8-BIT SHIFT REGISTERS

SN54199 ... J OR W PACKAGE

SN54199 and SN74199 SN74199 .•• J OR N PACKAGE
- (TOP VIEW)
These registers feature parallel inputs, parallel INPUT
E QE CLEAR CLOCK
outputs, J·K serial inputs, shift/load control input, a
direct overriding clear line, and gated clock inputs.
The register has three modes of operation:
Parallel (Broadside) Load
Shift (In the direction OA toward 0H)
Inhibit Clock (Do nothing)
Parallel loading is accomplished by applying the eight
bits of data and taking the shift/load control input
low when the clock input is not inhibited. The data is
SERIAL INPUTS
loaded into the associated flip-flop and appears at the
outputs after the positive transition of the clock positive logic: see function table
input. During loading, serial data flow is inhibited.

Shifting is accomplished synchronously when shift/load is high and the clock input is not inhibited. Serial data for this
mode is entered at the J-K inputs. See the function table for levels required to enter serial data into the first f!ip-f!op.

Both of the clock inputs are identical in function and may be used interchangeably to serve as clock or clock-inhibit
inputs. Holding either high inhibits clocking, but when one is held low, a clock input applied to the other input is
passed to the eight flip-flops of the register. The clock·inhibit input should be changed to the high level only while the
clock input is high.

These shift registers contain the equivalent of 79 TTL gates. Average power dissipation per gate is typically 4.55 mW.

'199
FUNCTION TABLE
INPUTS OUTPUTS

•
SHIFTI CLOCK SERIAL PARALLEL
CLEAR CLOCK - QA QB Qc ... QH
LOAD INHIBIT J K A •.. H
L X X X X X X L L L L
H X L L X X X QAO QBO Qeo QHO
H L L t X X a ... h a b c h
H H L t L H X QAO QAO QBn QGn
H H L t L L X L QAn QBn ClGn
H H L t H H X H QAn QBn QGn
-
H H L t H L X QAn QAn QBn QGn
H X H t X X X QAO QBO QBO QHO

H = high level (steady state), L = low level (steady state)

X = irrelevant (any input, including transitions)
t = transition from low to high level
a ... h = the level of steady·state input at inputs A thru H, respectively.
QAO, QBO, QCO· .. QHO = the level of QA, QB, or QC thru QH, respectively, before the
indicated steady·state input conditions were established.
QAn, QBn ... QGn = the level of Q A or QB thru QG, respectively, before the most·recent t
transition of the clock.

1076

TEXAS INCORPORATED
INSTRUMENTS 7-339
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54198, SN54199, SN74198, SN74199
8-BIT SHIFT REGISTERS

functional block diagrams

'198 '199
CLOCK...'-(''''')C-..-----jl >....,

CLOCK (13)

CLOCKINHIBIT~
SERIAL INPUTS {~ ~) i
SHIFT/LOAO-'='(23"'-'I"".-d ..........~

B (5)

B (5)

(6) Os

C (7)

C (7)

(B)

o (9)

o (9)

(10) 00

E (15)

E (16)

I t------++--+-~ Oe

F (17)
F(18)

•
t+-:=-_ _ _++_ _+_..!.2(1~6) OF

G (191
G (20)

(18) OG

H (21)
H (22)

SE~~!~;~;0i ..:.:(2;=:2)_ _ _ _ _+--1_ ~

CLEAR .-'-'('-"'3)_<Do--_ _ + ____...J

L...------4-~OH CLEAR'-'(14"-)-----<C>o_--'

schematics of inputs and outputs

EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS

VCC---_--

INPUT

Clear, A thru H: Req = 6 kn NOM

All others: Req = 4 kn NOM

1 07E

7·340 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • CALLAS. TEXAS 75222
 TYPES SN54198. SN74198
8-BIT SHIFT REGISTERS

SN54198, SN74198
typical clear, load, right-shift, left-shift, inhibit, and clear sequences

~
IIII IIII III III

•
--I

I
,,:
u
0
til iii a:
; '-v-' \...«_
a: oJ '" _u_C (!l:r:
-..J_ _ _ ~I\
«
0 o'" 0
u C
0
w
0
3u u oJ til

~~~
~Cl~

076

TEXAS INSTRUMENTS
INCORPORATED
7-341
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54199, SN74199
8-BIT SHIFT REGISTERS

SN54199, SN74199

typical clear, shift, load, and inhibit sequences

•
~ ~ cc ..., I~
u
~
u
g a
..J
u u U

1272'

7·342 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54198, SN54199, SN74198, SN74199
8-BIT SHIFT REGISTERS

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, Vcc (see Note 1) . . . . . . . 7V

Input voltage . . . . . . . . . . . . . . . 5.5V
Operating free-air temperature range: SN54' Circuits -55°C to 125°C
SN74' Circuits aOc to 7aoC
Storage temperature range -65°C to 15aoC
NOTE1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54198 SN74198 I I
t--_S_N_5:...4_1..:.99.:....-_-+-__S=:,;N..:.7:...4:....:1..::.99=--_--1 UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, V CC 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -BOO -BOO Jl.A
Low·level output current, 10L 16 16 mA
Clock frequency, fctock C 25 0 25 MHz
Width of clock or clear pulse, tw (see Figure 1) 20 20 ns
Mode·control setup time, tsu 30 30 ns
Data setup time, tsu (see Figure 1) 20 20 ns
Hold time at any input, th (see Figure 1) 0 0 ns
Operating free-air temperature, T A -55 125 0 70 I °c I

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST COi~DiTiOi~S'
I SN54198 I SN74198
SN54199 SN74199 UNITl

•
MIN TYP:j: MAX MIN TYP:j: MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage O.B O.B V
VIK Input clamp voltage VCC = MIN, II =-12mA -1.5 -1.5 V
VCC= MIN, VIH=2V,
VOH High-level output voltage 2.4 3.4 2.4 3.4 V
VIL = O.B V, 10H =-BOOJl.A
VCC- MIN, VIH-2V,
VOL Low-level output voltage 0.2 0.4 0.2 0.4 V
VIL = O.B V, IOL=16mA
II Input current at maximum input voltage VCC - MAX, VI- 5.5 V 1 1 mA
IIH High-level input current VCC = MAX, VI = 2.4 V 40 40 Jl.A
IlL Low-level input current ' VCC - MAX, VI- 0.4 V -1.6 -1.6 mA
lOS Short-circuit output current ~ VCC - MAX -20 -57 -lB -57 mA
ICC Supply current VCC= MAX, See Table Below 72 104 72 116 mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

+AII typical values are at Vee = 5 V, T A = 25°C.

§ Not more than one output should be shorted at a time.

TEST CONDITIONS FOR ICC

(ALL OUTPUTS ARE OPEN)
FIRST GROUND,
TYPE APPLY 4.5 V GROUND
THEN APPLY 4.5 V
SN5419B, SN7419B Serial Input, So, Sl Clock Clear, Inputs A thru H
SN54199, SN74199 J, K, Inputs A thru H Clock Clock inhibit, Clear, Shift/Load

076

TEXAS INCORPORATED
INSTRUMENTS 7·343
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54198, SN54199, SN74198, SN74199
8-BIT SHIFT REGISTERS

switching characteristics, Vee = 5 V, T A = 25°e

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f rnax Maximum clock frequency 25 35 MHz
Propagation delay time, high-ta-
tpHL I 23 35 ns
low-level output from clear
CL=15pF, RL = 400 n,
Propagation delay time, high-to-
tpHL See Figure 1 20 30 ns
low-level output from clock
Propagation delay time, low-to-
tpLH 17 26 ns
high-level output from clock

PARAMETER MEASUREMENT INFORMATION

SN54198, SN74198 SN54199, SN74199
TEST TABLE FOR SYNCHRONOUS INPUTS TEST TABLE FOR SYNCHRONOUS INPUTS

DATA INPUT OUTPUT TESTED DATA INPUT OUTPUT TESTED

Sl SO SHIFT/LOAD
FOR TEST (SEE NOTE E) FOR TEST (SEE NOTE E)
A 4.5V 4.5V 0A at tn+1 A OV 0A at tn+1
B 4.5V 4.5V 0B at tn+1 B OV Os at tn+1
C 4.5V 4.5V 0c at tn+1 C OV 0c at tn+1
D 4.5 V 4.5 V 0D at tn+1 D OV 0D attn+1
E 4.5V 4.5V 0E at tn+1 E OV 0E at tn+1
F 4.5 V 4.5 V OF at tn+1 F OV OF at tn+1
G 4.5V 4.5V 0G at tn+1 G OV 0G at tn+1
H 4.5 V 4.5V 0H at tn+1 H OV 0H at tn+1
L Serial Input 4.5 V OV 0A at tn+8 J and R 4.5V QH at tn+8
R Serial Input OV 4.5V 0H at tn+8

.-.oj tw(ele.r) I~------------------ 3 V

~~5~

•
CLEAR INPUT ___ _
---OV

OUTPUT

FROM
1 fVCC
RL =4oon
CLOCK INPUT
tn

I
~ (See Note F) tn

-
~
~---3V

~"~th Lov
~~6~~T
TEST ~ 14 ~ ~ ~
(5 . . Note CI 1_1
~tSU'~3V
DATA
/f':'CL = 15 pF INPUT 1.5V~1~V_ _ _ _ ov
"*(588 Note BI
(SEE TEST _ _ _--i. _ _ _ _ _J

TABLE) I
LOAD FOR OUTPUT UNDER TEST tpHL -.l r-
(clear·O) --1
I
I.-
tpLH (CLK·O)
-I tPHLt--
(CLK'O)~t--------v--=--- - VOH
a
OUTPUT ----""'""\15 V
1 1 SV
. L- VOL

VOLTAGE WAVEFORMS

NOTES: A. The clock pulse has the following characteristics: tw(clock) ;. 20 ns and PRR = 1 MHz. The clear pulse has the following
characteristics: tw(clear);' 20 ns and thold = 0 ns. When testing f max , vary the clock PRR.
B. CL includes probe and jig capacitance.
C. All diodes are 1 N3064.
D. A clear pulse is applied prior to each test.
E. Propagation delay times (tPLH and tpHL) are measured at t n +1' Proper shifting of data is verified at tn+8 with a functional test.
F. tn = bit time before clocking transition
tn+1 = bit time after one clocking transition
t n +8 = bit time after eight clocking transitions
FIGURE 1

1076

7-344 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TTL TYPES SN54S226, SN74S226
MSI 4-BIT PARALLEL LATCHED BUS TRANSCEIVERS
BULLETIN NO. DL-S 7612477, OCTOBER 1976

• Universal Transceivers for Implementing

System Bus Controllers SN54S226 ... J PACKAGE
SN74S226 ... J OR N PACKAGE
• Dual-Rank 4-Bit Transparent Latches
Provide
(TOP VIEW)
- Exchange of Data Between 2 Buses In One
BUS B INPUTS/OUTPUTS
Clock Pulse STB SEL,~-------A------_
- Bus-to-Bus Isolation VCC GAB S2 B1 B2 B3 B4
13
- Rapid Data Transfer
- Full Storage Capability
• Hysteresis at Data Inputs Enhances Noise
Rejection
• Separate Output Control Inputs Provide
Independent Enable/Disable for Either
Bus Output
II
II I I I I I I I
Al A2 A3 A4 :::r III
I I
• 3-State Outputs Drive Bus Lines Directly
~
STB Sl A1 A2 A3 A4 OCBA GND
GBA SEL l I

BUS A INPUTS/OUTPUTS
description
SEE FUNCTION TABLES

These high'performance Schottky TTL quadruple bus

transceivers employ dual-rank bidirectional four-bit
transparent latches and feature three-state outputs
designed specifically for driving highly-capacitive or
relatively low-impedance loads. The bus-management

•
functions implemented and the high-impedance con-
trols offered provide the designer with a controller/ functional block diagram
transceiver that interfaces and drives system bus-
organized lines directly. They are particularly attrac-
tive for implementing:
DUAL-RANK DUAL-RANK
Bidirectional bus transceivers LATCHES LATCHES
Data-bus controllers

The bus-management functions, under control of the

function-select (S1, S2) inputs, provide complete data
integrity for each of the four modes described in the
function table. Directional transparency provides for
routing data from or to either bus, and the dual store
and dual readout capabilities can be used to perform
the exchange of data between the two bus lines in the
equivalent of a single clock pulse. Storage of data is
accomplished by selecting the latch function, setting
up the data, and taking the appropriate strobe input
low. As long as the strobe is held low, the data is DCAB
latched for the selected function. Further control is SELECT
STROBE OUTPUT
GAB CONTROL
offered through the availability of independent
output controls that can be used to enable or

DESIGN GOAL
1076
This page. provides tentative information on a TEXA sIN S T RUM EN T S 7-345
i~~~~~en'~ r!::rv=:~~:~;~~~~ c~:~~ :e;:~ INCORPORATED
continue this product without notice. POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54S226, SN74S226
4-BIT PARALLEL LATCHED BUS TRANSCEIVERS

BUS-MANAGEMENT FUNCTION TABLE OUTPUT-CONTROL FUNCTION TABLE

OPERATION S2 Sl LATCH FUNCTIONS OCAB OCBA OUTPUT FUNCTION

DRIVE BUS B L L Pass Bus A Data to Bus B L X Disable Bus B Outputs (Hi-Z)
DRIVE BUSA H L Pass Bus B Data to Bus A H X Enable Bus B Outputs
EXCHANGE H H Store Bus A and Bus B Data X L Disable Bus A Outputs (Hi-Z)
BUS A AND B L H Readout Stored Data X H Enable Bus A Outputs

disable the outputs as shown in the output-control function table, regardless of the latch function in process. Store
operations can be performed with the outputs disabled to a high impedance (Hi-Z). In the Hi-Z state the inputs/outputs
neither load nor drive the bus lines significantly. The p-n-p inputs feature typically 400 millivolts of hysteresis to
enhance noise rejection.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, Vee (see Note 1) 7V

Input voltage .5.5 V

•
Off-state output voltage .5.5 V
Operating free-air temperature range: SN54S226 -55°C to 125°C
SN74S226 oOe to 70°C
Storage temperature range -65°C to 150°C

NOTE1: Voltage values are with respect to network ground terminaL

DESIGN GOAL 1076

7-346 :~~~';C~gei~r~~i:e~::;I:~~:ni;aflor;::!~n T~:a:TEXAS IN STRU M ENTS

Instruments reserves the right to change or dis· INCORPORATED
continue this product without notice. POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54S226, SN74S226
4-BIT PARALLEL LATCHED BUS TRANSCEIVERS

recommended operating conditions

SN54S226 SN74S226
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output voltage, VOH 5.5 5.5 V
High-level output current, 10H -6.5 -10.3 rnA
Data (A or B) 5. 3.
Data setup time, tsu ns
Select 5. 3.
Data (A or B) 5. 3.J.
Data hold time, th ns
Select 5. 3.
Operating free-air temperature, T A -55 125 a 70 °e

~ The arro"..... indicates that the high-to-:ovv transition of the enable input is used for reference.

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDlTlONSt MIN TYP:j: MAX UNIT

VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
VIK Input clamp voltage Vee= MIN, II = -18 rnA -1.2 V

VOH High-level output voltage

I SN54S226 Vee= MIN, VIH = 2 V, ISN54S226 2.4 3.3
V
I SN74S226 VIL = 0.8 V, I
IOH = MAX SN74S226 2.4 2.9
I Vee = MIN, VIH = 2 V,
VOL Low-level output voltage 0.5 V
VIL = 0.8 V, IOL = 20mA

•
Off-state output current, Vee = MAX, VIH = 2 V,
IOZH 100 IlA
high-level voltage applied Va = 2.4 V
Off-state output current, Vee = MAX, VIH = 2 V,
IOZL -100 IlA
low-level voltage applied VO= 0.5 V
II Input current at maximum input voltage Vee= MAX, VI = 5.5 V 1 rnA
IIH High-level input current Vee = MAX, VI = 2.7 V 100 IlA
IlL Low-level input current Vee - MAX, VI- 0.5 V -300 IlA
lOS Short-circuit output current§ Vee = MAX -50 -180 rnA
lee Supply current Vee- MAX, See Note 2 125 rnA

t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at Vee = 5 V, T A = 25°C.
§Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
NOTE 2: I CC is measured with all inputs (and outputs) grounded.

076 DESIGN GOAL

This page provides tentative information on a
product in the developmental stage. Texas TEXAS INCORPORATED
INSTRUMENTS 7-347
Instruments reserves the right to change or dis-
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
continue this product without notice.
 TYPES SN54S226, SN74S226
4-BIT PARALLEL LATCHED BUS TRANSCEIVERS

switching characteristics, Vee = 5 V, TA = 25°e

FROM TO
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
(INPUT) (OUTPUT)
tPLH 14
A orB BorA ns
tPHL 14
tpLH 12
Select Any ns
tpHL CL = 50 pF, RL = 280 n, 12
tPLH Strobe GBA See Note 2 12
AorB ns
tPHL or GAB 12
tpZH Output Control 9
AorB ns
tPZL OCBA orOCAB 9
tpHZ Output Control CL = 5 pF, RL = 280 n, 7
AorB ns
tPLZ OCBAor OCAB See Note 2 7

tPLH == pro~~~ion del~_.!ime, low-to-nigh-Ie:-el output

tPH L == propagation delay time, low-to-nigh-Ievel output
tZH == output enable time to high level
tZL == output enable time to low level
tHZ == output disable time from high level
tLZ == output disable time from low level
NOTE 2: Load circuits and voltage waveforms are shown on page 3-10,

applications

The following examples demonstrate four fundamental bus-management functions that can be performed with the
'S226_ Exchange of data on the two bus lines can be accomplished with a single high-to-Iow transition at S2 when S1 is
high,

• 'S226 'S226 'S226 'S226

~ ~ L.....,--J
CONTROL CONTROL CONTROL CONTROL
BUS B .....BUS A BUSA..-BUSB STORE A AND/OR B READOUT A AND B

-- - - - - - VIH
Vll
CONTROL {S2
VIH

S1------------------------------------~--~ - - - - - - - - - - - - - - - - - - VIL

DESIGN GOAL

7-348
This page. provides tentative information on a
product on the develop~ental stage. Tex~s
TEXAS I N STRUM ENTS
INCORPORATED
Instruments reserves the roght to change or d.s-
continue this product without notice. POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TTL TYPES SN54LS245, SN74LS245
MSI OCTAL BUS TRANSCEIVERS WITH 3·ST ATE OUTPUTS
BULLETIN NO. DL-S 7612471, OCTOBER 1976

• Bi-clirectional Bus Transceiver in a SN54LS245 ••• J PACKAGE

High-Density 20-Pin Package SN74LS245 ... J OR N PACKAGE
(TOP VIEW)
• 3-State Outputs Drive Bus Lines Directly
• P-N-P Inputs Reduce D-C Loading on ENABLE
Vee G B1 62 63 64 B5 66 67 B8
Bus Lines
• Hysteresis at Bus Inputs Improve Noise
Margins
• Typical Propagation Delay Times,
Port-to-Port ... 12 ns
• Typical Enable/Disable Times ... 17 ns

IOL IOH
TYPE (SINK (SOURCE
CURRENT) CURRENT)
ill'll OIT L.;;)L"+O 140 rnM -1.£ (11M.

SN74LS245 24mA -15mA

positive logic: see function table

description

These octal bus transceivers are designed for asynchronous two-way communication between data buses. The control
function implementation minimizes external timing requirements.

The device allows data transmission from the A bus to the B bus or from the B bus to the A bus depending upon the
logic level at the direction control (DI R) input. The enable input (<3) can be used to disable the device so that the buses
are effectively isolated.

•
The SN54LS245 is characterized for operation over the full military t~mperature range of -55°C to 125°C. The
SN74LS245 is characterized for operation from aOe to 7aoe.

schematics of inputs and outputs FUNCTION TABLE

EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS DIRECTION

ENABLE
Vec CONTROL OPERATION
Q(IO'
. 1) DIR (t)
L L Etdata to A bus
L H.• ~ da~a to B bus
OUTPUT H X Isolation" -

H = high level. L = low level, X = irrelevant

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, Vee (see Note 1) ..... 7 V

Input voltage . . . . . . . . ..... 7 V
Operating free-air temperature range: SN54LS245 -55"e to 125°C
SN74 LS245 aOe to 7aoe
Storage temperature range -65°C to 15aoe

NOTE 1: Voltage values are with respect to network ground terminal.

'1076
DESIGN GOAL
This page provides tentative information on a TEXAS IN ST RUM ENTS 7-349
product in the developmental stage. Texas INCORPORATED
Instruments reserves the right to change or dis- POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
continue this product without notice.
 TYPE~ SN54LS245, SN74LS245
OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

recommended operating conditions

SN54LS245 SN74LS245
PARAMETER UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High·level output current, 10H -12 -15 rnA
Low·level output current, 10L 12 24 rnA
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS245 SN74LS245
PARAMETER TEST CONDITIONSt UNIT
MIN TYPt MAX MIN TYPt MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
VIK Input clamp voltage Vee = MIN, II = -18mA -1.5 -1.5 ; V
Hysteresis (VT+ - VT_)A or B input Vee= MIN 0.2 0.4 0.2 0.4 V
Vee = MIN, 10H =-3 rnA 2.4 3.4 2.4 3.4
VOH High-level output voltage VIH=2V, V
VIL = VIL max 10H = MAX 2 2
Vee = MIN, 10L = 12mA 0.4 0.4
VOL Low-level output voltage VIH = 2 V, V
VIL = VIL max 10L = 24 rnA 0.5
Off-state ou tpu t cu rrent,
10ZH VO=2.7V 20 ! 20
high-level voltage applied Vce= MAX,
jJ.A
Off-state output current, G at2 V
10ZL Va = 0.4 V -20 -20
low-level voltage applied
Input current at maximum
II Vee = MAX, VI =7V 0.1 0.1 rnA
input voltage

•
IIH High-level input current Vee = MAX, VIH = 2.7 V 20 20 jJ.A
IlL Low-level input current Vee = MAX, VIL=OAV -0.2 -0.2 rnA
lOS Short-circuit output current~ Vee = MAX -40 -225 -40 -225 rnA
I Total, outputs high 25 46 25 46
lee Supply current I Total, outputs low Vee = MAX, Outputs open 58 100 58 100 rnA
IOutputs at Hi-Z 64 105 64 105

t For conditi'ons shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAli typical-values are at Vee = 5 V, TA = 25°e.
~ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.

switching characteristics, Vee = 5 V, TA = 25°e

PARAMETER 1 TEST CONDITIONS MIN TYP MAX I UNIT
Propagation delay time,
tpLH 12 18 ns
low-to-high-level output
Propagation delay time,
tPHL eL=45pF, RL = 667 n, See Note 2 12 18 ns
hiltJ-to-low-leveloutput
tpZL Output enable time to low level 20 30 ns
tpZH Output enable time to high leve! 15 25 ns
tpLZ Output disable time from low level 15 25 ns
eL=5pF, RL = 667 n, See Note 2
tpHZ Output disable time from high level 10 18 ns

NOTE 2: Load circu it and waveforms are, shown on page 3-11.

DESIGN GOAL 1076

This page provides tentative information on a
7-350 product in the developmental stage. Texas TEXASINCORPORATED
INSTRUMENTS
InstrUments reserves the right to change or dis-
continue this product without notice. POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TTL TYPES SN54246 THRU SN54249, SN54LS247 THRU SN54LS249,
SN74246 THRU SN74249, SN74LS247 THRU SN74LS249
MSI BCO-TO- SEVEN-SEGM ~NT OECOOJRS/OIUVEBS
BULLETIN NO. DL-S 7612078, MARCH 1974- REVISED OCTOBER 1976

'246, '247, 'LS247 '248, 'LS248 '249, 'LS249

feature feature feature

• Open-Collector Outputs • Internal Pull-Ups Eliminate • Open-Collector Outputs

Drive Indicators Directly Need for External Resistors
• Lamp-Test Provision
• Lamp-Test Provision • Lamp-Test Provision
• Leading/Trailing Zero
• Leading/Trailing Zero • Leading!Trailing Zero Suppression
Suppression Suppression
• All Circuit Types Feature Lamp Intensity Modulation Capability
DRIVER OUTPUTS TYPICAL
TYPE ACTIVE OUTPUT SINK MAX POWER PACKAGES
LEVEL CONFIGURATION CURRENT VOLTAGE DISSIPATION
SN54246 low open-collector 40mA 30V 320mW J,W
SN54247 low open-collector 40mA 15V 320mW J,W
ISi~54248 high 2-kn puii-up 6.4mA 5.5 V 265 rn\N J, 'v·v
SN54249
SN54LS247
I high
low
I open-collector
open-collector
I 10mA
12mA
I 5.5V
15V
265mW
35mW
J,W
J,W
SN54LS248 high 2-krl pull-up 2mA 5.5 V 125mW J,W
SN54LS249 high open-collector 4mA 5.5V 40mW J,W
SN74246 low open-collector 40mA 30V 320mW J, N
SN74247 low open-collector 40mA 15V 320mW J, N
SN74248 high 2-krl pull-up 6.4 mA 5.5 V 265mW J, N
SN74249 high open-collector 10mA 5.5V 265mW J, N
ISN74LS247 low open-collector 24mA 15V 35mW J, N
I SN74LS248 high I 2-krl pull-up I 6mA 5.5V 125mW I
I J, N
ISN74LS249 high open-collector 8mA 5.5V 40mW J, N
'246, '247, 'LS247 '248, '249, 'LS248, 'LS249

•
(TOP VIEW) (TOP VIEW)

OUTPUTS
r-------~A~------~

positive logic: see function tables

description
The '246 through '248 are electrically and functionally identical to the SN5446A/SN7446A, SN5447A/SN7447A, and
SN5448/SN7448, respectively, and have the same pin assignments as their equivalents. Also the 'LS247 and 'LS248 are
electrically and functionally identical to the SN54LS47/SN74LS47 and SN54LS48/SN74LS48, respectively, and have
the same pin assignments as their equivalents. They can be used interchangeably in present or future designs to offer
designers a choice between two indicator fonts. The '249 and 'LS249 are 16-pin versions of the 14-pin SN5449 and
SN54LS49/SN74LS49, respectively. Included in the '249 and 'LS249 circuits is the full functional capability for lamp
test and ripple blanking, which is not available in the '49 and 'LS49 circuits. The '46A, '47A, '4£, '49, 'LS47, 'LS48,
and 'LS49 compose the b and the g without tails and the '246 through '249 and 'LS247, 'LS248, and 'LS249

1076

TEXAS INSTRUMENTS 7-351

INCORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54246 THRU SN54249, SN54LS247 THRU SN54LS249,
SN74246 THRU SN74249, SN74LS247 THRU SN74LS249
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
description (continued)
compose the 5 and the S with tails. Composition of all other characters, including display patterns for BCD inputs
above nine, is identical. The '246, '247, and 'LS247 feature active·low outputs designed for driving indicators directly,
and the '248, '249, 'LS248, and 'LS249 feature active-high outputs for driving lamp buffers. All of the circuits have full
ripple-blanking input/output controls and a lamp test input. Segment identification and resultant displays are shown
below. Display patterns for BCD input counts above 9 are unique symbols to authenticate input conditions.
All of these circuits incorporate automatic leading and/or trailing-edge zero-blanking control (RBI and RBO). Lamp test
(LT) of these types may be performed at any time when the BI/RBO node is at a high level. All types contain an
overriding blanking input (BI) which can be used to control the lamp intensity by pl,llsing or to inhibit the outputs.
Inputs and outputs are entirely compatible for use with TTL or DTL logic outputs.
Series 54 and Series 54LS devices are characterized for operation over the full military temperature range of _55°C to
125°C; Series 74 and Series 74LS devices are characterized for operation from O°C to 70°C.

r:-Ib
el-Ie
-d- NUMERICAL DESIGNATIONS AND RESULTANT DISPLAYS
SEGMENT
IDENTIFICATION
'246, '247, 'LS247
FUNCTION TABLE

DECIMAL
INPUTS OUTPUTS
OR BI/RBOt NOTE
FUNCTION LT RBI D C B A a b c d e f 9
0 H H L L L L H ON ON ON ON ON ON OFF
1 H X L L L H H OFF ON ON OFF OFF OFF OFF
2 H X L L H L H ON ON OFF ON ON OFF ON
3 I H X L L H H H ON ON ON ON OFF OFF ON
4 H X L H L L H OFF ON ON OFF OFF ON ON
/ 1

•
5 H X L H L H H ON OFF ON ON OFF ON ON
6 H X L H H L H ON OFF ON ON ON ON ON
7 H X L H H H H ON ON ON OFF OFF OFF OFF
1
8 H X H L L L H ON ON ON ON ON ON ON
9 H X H L L H H ON ON ON ON OFF ON ON
I
10 H X H L H L H , OFr ,OFr IOFF I ON ! ON OFF, ON I
11 H i X H L H H H OFF OFF ON ON OFF OFF ON
12 H X H H L L H OFF ON OFF OFF OFF ON ON
13 H X H H L H H ON OFF OFF ON OFF ON ON
14 H X H H H L H OFF OFF OFF ON ON ON ON
15 H X H H H H H OFF OFF OFF OFF OFF OFF OFF
BI X 1 X X X X X L OFF OFF OFF OFF OFF OFF OFFI 2
RBI H L L L L L L OFF OFF OFF OFF OFF OFF OFFI 3
LT L I X X X X X H ON ON ON ON ON ON ON 4 I
H = high level, L = low level, X = irrelevant
NOTES: 1. The blanking input (BI) must be open or held at a high logic level when output functions 0 through 15 are desired. The
ripple-blanking input (RBI) must be open or high if blanking of a decimal zero is not desired.
2. When a low logic level is applied directly to the blanking input (BI), all segment outputs are off regardless of the level of any other
input.
3. When ripple-blanking input (RBI) and inputs A, B, C, and D are at a low level with the lamp test input high, all segment outputs
go off and the ripple·blanking output (RBO) goes to a low level (response condition).
4. When the blanking input/ripple blanking output (BI/RBO) is open or held high and a low is applied to the lamp-test input, all
segment outputs are on.
tBI/RBO is wire-AND logic serving as blanking input (BI) and/or ripple-blanking output (RBO).

374

7-352 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54246 THRU SN54249, SN54LS247 THRU SN54LS249,
SN74246 THRU SN74249, SN74LS247 THRU SN74LS249
BCD-TO- SEVEN-SEGM ENT DECODERS/DRIVERS

'248, '249, 'LS248, 'LS249

FUNCTION TABLE

DECIMAL
INPUTS OUTPUTS
OR BI/RBOt NOTE
FUNCTION LT RBI D C B A a b c d e f g
0 H H L L L L H H H H H H H L 1
1 H X L L L H H L H H L L L L 1
2 H X L L H L H H H L H H L H
3 H X L L H H H H H H H L L H
4 H X L H L L H L H H L L H H
5 H X L H L H H H L H H L H H
6 H X L H H L H H L H H H H H
7 H X L H H H H H H H L L L L 1
8 H X H L L L H H H H H H H H
9 H X H L L H H H H H H L H H
10 H X H L H L H L L L H H L H
11 H X H L H H H L L H H L L H
12 H X H H L L H L H L L L H H
13 H X H H L H H H L L H L H H
14 H X H H H L H L L L H H H H
H H H H L L L L L L
x X X X L L L L L L L
L L L L L L L L L L L
X X X X H H H H H H H

H = high level, L = low level, X = irrelevant

NOTES: 1. The blanking input (BI) must be open or held at a high logic level when output functions 0 through 15 are desired. The
ripple-blanking input (RBI) must be open or high if blanking of a decimal zero is not desired.
2. When a low logic level is applied directly to the blanking input (BI), all segment outputs are low regardless of the level of any
other input.
3. When ripple-blanking input (RBI) and inputs A, B, C, and D are at a low level with the lamp test input high, all segment outputs
go low and the ripple-blanking output (RBO) goes to a low level (response condition).
4. When the blanking input/ripple-blanking output (BIIRBO) is open or held high and a low is applied to the lamp-test input, all
segment outputs are high.
tBI/RBO is wire-AND logic serving as blanking input (BI) and/or ripple-blanking output (RBO)_

'246, '247, 'LS247 '248, '249, 'LS248, 'LS249

•
BURBO
BLANKING

RI,.t~k~:'NG-,=I",---+__~ RtPP~!1~~~~ING-""4I'---t_ _-!

INPUT
LAMP-TEST !'3)

--t==--____.::::EU
RIPPLEi~~~KING-"I5,,---1

374

TEXASINCORPORATED
INSTRUMENTS 7-353
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54246 THRU SN54249, SN74246 THRU SN74249
BCD-TO- SEVEN-SEGM ENT DECODERS/DRIVERS

schematics of inputs and outputs

'246, '247, '248, '249 '246, '247, '248, '249

-
EaUIVALENT OF EACH INPUT EaUIVALENT OF BI/RBO
EXCEPT BI/RBO
Vee

v ee

Q
6 kil NOM

INPUT --

'246, '247 '248

TYPICAL OF OUTPUTS TYPICAL OF OUTPUTS

a THRU 9 a THRU 9

-----------.--.------vee
OUTPUT ------------1Ir-----.- vee
2kil
NOM

•
OUTPUT

'249

TYPICAL OF ALL OUTPUTS

------------1Ir----- v ee

OUTPUT

37,

7-354 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54LS247 THRU SN54LS249, SN74LS247 THRU SN74LS249
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS

schematics of inputs and outputs

'LS24 7, 'LS248, 'LS249 'LS247, 'LS248, 'LS249

-
EQUIVALENT OF EACH INPUT EQUIVALENT OF BI/RBO
EXCEPT BI/RBO

Vee

q
vee
Req

INPUT --

L T and RBI: Req = 20 kO NOM

A, B, e, and D: Req = 25 kO NOM

'LS247 'LS248

TYPICAL OF OUTPUTS TYPICAL OF OUTPUTS

a THRU 9 a THRU 9

----------.----.-----vee ----------~--~~vee

2kO
NOM
OUTPUT

•
OUTPUT

'LS249

TYPICAL OF OUTPUTS
a THRU 9

----------~----vee

OUTPUT

374

TEXAS INSTRUMENTS
Il'OCORPORATED
7-355
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54246, SN54247, SN74246, SN74247
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
REVISED MARCH 1974

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1) . . . . . 7V
Input voltage . . . . . . . . . . . . . 5.5 V
Current forced into any output in the off state 1 rnA
Operating free-air temperature range: SN54246, SN54247 -55°C to 125°C
SN74246, SN74247 aOc to 7aoC
Storage temperature range -65°C to 15aoC
NOTE1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54246 SN54247 SN74246 SN74247
UNIT
MIN NOM MAX MIN NOM MAX MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.5 5 5.5 4.75 5 5.25 4.75 5 5.25 V
Off-state output voltage, VO(off) a thru g 30 15 30 15 V
On-state output current, 10(on) a thru g 40 40 40 40 mA
High·level output current, 10H BI/RBO -200 -200 -200 -200 IJ.A
Low-level output current, 10L BI/RBO S S S S mA
Operating free-air temperature, T A -55 125 -55 125 0 70 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONSt MIN TYP+ MAX UNIT
VIH High-level input voltage 2 V
VIL Low-level input voltage O.S V
VIK Input clamp voltage Vee; MIN, II; -12 mA 1.5V V
Vee- MIN, VIH - 2 V,
VOH High-level output voltage BI/RBO 2.4 3.7 V
VIL; O.S V, 10H; -2oo1J.A
Vee- MIN, VIH-2V,
VOL Low-level output voltage BI/RBO 0.27 0.4 V
VIL; O.S V, 10L; SmA
Vee- MAX, VIH - 2 V,
10(offl Off-state output current a thru g 250 IJ.A
VIL = O.S V, VO(off) ; MAX

•
Vee; MAX, VIH;2V,
VO(on) On-state output voltage a thru g 0.3 0.4 V
VIL = O.S V, 10(on) = 40 mA
Any input
II Input current at maximum input voltage Vee = MAX, VI = 5.5V 1 mA
except BI/RBO
Any input
,1!H High-level input current ,..,Vee=MAX, VI; 2.4 V 40 jJ.A
except BI/RBv
"
Any input
-1.6
IlL Low-level input current except BI/RBO Vee; MAX, VI; 0.4 V mA
BI/RBO -4
lOS Short-circuit output current BI/RBO Vee; MAX -4 mA
lee Supply current Vee= MAX, See Note 2 64 103 mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at VCC = 5 V, T A; 25°C. '
NOTE 2: ICC is measured with all outputs open and all inputs at 4.5 V.

switching characteristics, Vee =5 V, TA = 25°e

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
toff Turn-off time from A input 100
ns
ton Turn-on time from A input eL=15pF. RL = 120 n, 100
toff Turn-off time from RBI input See Note 3 100
ns
ton Turn-on time from RBI input 100
NOTE 3: Load circuit and voltage waveforms are shown on page 3·10; toft corresponds to tpLH and ton corresponds to tpH L·

1076

7-356 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54LS247, SN74LS247
BCD-TO- SEVEN-SEGM ENT DECODERS/DRIVERS
REVISED OCTOBER 1976

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1) ...... . 7V
Input voltage . . . . . . . . . . . . . . . 7V
Peak output current (tw::;;; 1 ms, duty cycle::;;; 10%) 200mA
Current forced into any output in the off state . . 1mA
Operating free-air temperature range: SN54LS247 -55°C to 125°C
SN74LS247 . O°C to 70°C
Storage temperature range -65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54LS247 SN74LS247
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
Off-state output voltage, VO(off) a thru g 15 15 V
On-state output current, IO(on) a thru g 12 24 rnA
High-level output current, 10H BI/RBO -50 -50 }.LA
Low-level output current, 10L BI/RBO 1.6 3.2 rnA
I Uperatlng tree-air temperature, I A I IV I- -- .~-
I"::"
~ ~~ ~

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS247 SN74 LS247
PARAMETER TEST CONDITIONSt UNIT
MIN TYP+ MAX MIN TYP+ MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
VIK Input clamp voltage Vee - MIN, II - -18 rnA -1.5 -1.5 V
Vec - MIN, VIH-2V,
VOH High-level output voltage BI/RBO
VIL = VIL max, 10H = -50}.LA
Vee= MIN,
llOL = 1.6 rnA
1I
2.4 4.2

0.25 0.4 I
2.4 4.2

0.25 0.4
V

Low-ievei output voltage 8i/R8G 1 V

I VOL IVIH=2V,
VIL = VIL max /IOL = 3.2 mA 0.35 0.51
I
Vee - MAX, VIH-2V, I

•
I o(off) Off-state output current a thru g 250 250 }.LA
VIL = VIL max, VO(off) = 15 V
Vee- MAX,
lIO(on) = 12 rnA 0.25 0.4 0.25 0.4
VO(on) On-state output voltage a thru g VIH =2 V, V
VIL = VIL max 110(on) = 24 rnA 0.35 0.5

II Input current at maximum input voltage Vee - MAX, VI = 7 V 0.1 0.1 rnA
IIH High-level input current Vee- MAX, VI - 2.7 V 20 20 }.LA
Any input
-0.4 -0.4
IlL Low-level input current except BI/RBO Vee= MAX, VI = 0.4 V mA
BI/RBO -1.2 -1.2
Short-circuit
lOS BI/RBO Vee = MAX -0.3 -2 -0.3 -2 rnA
output current I

lee Supply current Vee = MAX, See Note 2 7 13 7 13 rnA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at VCC = 5 V, T A = 25°C.
NOTE 2: ICC is measured with all outputs open and all inputs at 4.5 v.

switching characteristics, Vee = 5 V, T A = 25° C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
toff Turn·off time from A input 100
ns
ton Turn-on time from A input eL=15pF, RL=665n, 100
toff Turn-off time from RBI input See Note 4 100
ns
ton Turn-on time from RBI input 100
NOTE 4: Load cIrcuIt and voltage waveforms are shown on page 3-11; toff corresponds to tpLH and ton corresponds to tpH L.

1076

TEXAS INSTRUMENTS 7-357

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54248. SN14248
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
REVISED MARCH 1974

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . 7V
Input voltage . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range: SN54248 -55°C to 125°C
SN74248 oOe to 70°C
Storage temperature range -65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminals.

recommended operating conditions

SN54248 SN74248
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
a thru g -400 -400
High-level output current, 10H /lA.
BI/RBO -200 -200
a thru g 6.4 6.4
Low-level output current, 10L mA
BI/RBO 8 8
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONSt MIN TYP+ MAX UNIT
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
VIK Input clamp voltage Vee= MIN, II = :-12 mA -1.5 V
a thru g Vee = MIN, VIH = 2V, 2.4 4.2
VOH High-level output voltage V
BI/RBO VIL = 0.8 V, 10H = MAX 2.4 3.7
Vee = MIN, Va = 0.85 V,
10 Output current a thru g -1.3 -2 mA
Input conditions as for VOH
Vee- MIN, VIH-2V,
VOL Low-level output voltage 0.27 0.4 V
VIL = 0.8 V, 10L = MAX I

•
Any input
II Input current at maximum input voltage Vee = MAX, VI = 5.5 V 1 mA
except SI/RBO
Any input
IIH High-level input current Vee = MAX, VI=2.4V 40 p,A
except BI/RBO
Any input
-1.6
I!L Low-leve~ input current I except B!/RBO Vee= M.A.X. VI = OAV mA

Short-circuit output current

BI/RBO
SI/RBO Vee = MAX
-4
-4 mA
i
lOS
lee Supply current Vee - MAX. See Note 2 53 90 mA
. . ..
tFor condItIons shown as MIN or MAX. use the approproate value specIfIed under recommended operatmg cond,t,ons .
..
+AII typical values are at VCC = 5 V. T A = 25°C.
NOTE 2: ICC is measured with all outputs open and all inputs at 4.5 V.

switching characteristics, Vee = 5 V, TA = 25° C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tpHL Propagation delay time. high-to-Iow-Ievel output from A input 100
ns
tPLH Propagation delay time, low-to-high-Ievel output from A input CL= 15pF. RL = 1 kil. 100
tpHL Propagation delay time. high-to-Iow-Ievel output from RSI input See Note 5 100
ns
tPLH Propagation delay time, low-to-high-Ievel output from RBI input 100
NOTE 5: Load CirCUIt and voltage waveforms are shown on page 3·10.

1076

7-358 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54lS248. SN74lS248
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
REVISED OCTOBER 1976

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ..... . 7V
Input voltage . . . . . . . . . . . . . . 7V
Operating free-air temperature range: SN54LS248 -55°C to 125°C
SN74LS248 aOe to 7aoe
Storage temperature range -65°C to 15aoe
NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54LS248 SN74LS248
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
a thru g -100 -100
High-level output current, IOH p,A
BI/RBO -50 -50
a thru g 2 6
Low-level output current, IOL mA
BI/RBO 1.6 3.2
Operating free-air temperature, T A -55 125 a 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS248 SN74LS248
PARAMETER TEST CONDITIONSt UNIT
iViii~ TYP+ MAX MiN IYP+ MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
VIK Input clamp voltage Vee= MIN, 11=-18mA -1.5 -1.5 V
a thru g and Vee - MIN, VIH-2V,
VOH High-level output voltage 2.4 4.2 2.4 4.2 V
BI/RBO VIL = VIL max, IOH = MAX
Vee = MIN, Vo = 0.85 V,
10 Output current a thru g -1.3 -2 -1.3 -2 mA
Input conditions as for VOH I
Vee = MIN,
I 10L = 2 rnA 0.25 0.4 0.25 0.4 ! I
I a thru g VIH=2V, V
10L =6 rnA 0.35 0.5
VIL = VIL max
I VOL Low-level output voltage
Vee- MIN,
10L = 1.6 rnA 0.25 0.4 0.25 0.4
i
BI/RBO VIH=2V, V

II
I nput current at
maximum input voltage
Any input
except BilBRO
VIL = VIL max

Vee = MAX,
10L = 3.2 rnA

VI =7 V 0.1
0.35 0.5

0.1 mA
II
Any input
IIH High-level input current Vee = MAX, VI = 2.7 V 20 20 p,A
except BI/RBO i

Any input
-0.4 I -0.4
IlL Low-level input current except B I/RBO Vee = MAX, VI = 0.4 V i mA
BI/RBO -1.2 -1.2
Short-circu it
lOS BI/RBO Vee = MAX -0.3 -2 :-0.3 -2 rnA
output current
lee Supply current Vee = MAX, See Note 2 25 38 25 38 mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at V CC = 5 V. T A 25° C.
NOTE 2: ICC is measured with all outputs open and all inputs at 4.5 v.
switching characteristics, Vee = 5 V, T A = 25°e
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tpHL Propagation delay time. high-to-Iow-Ievel output from A input eL=15pF, RL =4 k!1, 100
ns
tPLH Propagation delay time, low-to-high-Ievel output from A input See Note 6 100
tPHL Propagation delay time, high-to-Iow-Ievel output from RBI input eL=15pF, RL =6 k!1, 100
ns
tpLH Propagation delay time, low-to-high-Ievel output from RBI input See Note 6 100
NOTE 6: Load circuit and voltage waveforms are shown on page 3-11.

1076

TEXAS INSTRUMENTS 7-359

INCORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54249, SN74249
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1) .... . 7V
Input voltage . . . . . . . . . . . . . 5.5V
Current forced into any output in the off state 1 rnA
Operating free-air temperature range: SN54249 -55°C to 125°C
SN74249 O°C to 70°C
Storage temperature range -65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54249 SN74249
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output voltage, VOH 5.5 5.5 V
High-level output current, 10H IBI/RBO -200 -200 j.lA

Low-level output current, 10L

I a thru g 10 10
mA
IBI/RBO 8 8
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONSt MIN TVP:j: MAX UNIT
VIH High·level input voltage 2 V
VIL LOW-level input voltage 0.8 V
VIK Input clamp voltage Vee= MIN, 11=-12mA -1.5 V
Vee= MIN, VIH = 2V,
VOH High-level output voltage BI/RBO 2.4 3.7 V
VIL = 0.8 V, 10H = MAX
Vee= MIN, VIH=2V, I
10H High-level output current a thru g 250 j.lA
VIL = 0.8 V, VOH = 5.5 V
Vee= MIN, VIH = 2 V,

•
VOL Low-level output voltage 0.27 0.4 V
VIL = 0.8 V, 10L = MAX
Any input
II Input current at maximum input voltage Vce= MAX, VI = 7V 1 mA
except BI/RBO
Any input
IIH High-level input current Vee = MAX, VI = 2.4 V 40 j.lA
except BI/RBO
Any input
-1.6
IlL Low-level input current except BI/RBO Vce = MAX, VI = 0.4 V mA
BI/RBO -4
lOS Short-circuit output current BI/RBO Vce = MAX -4 mA
ICC Supply current Vce = MAX, See Note 2 53 90 mA
tFor
..
conditions shown as MIN or MAX, use the
..
approproate value specified under recommended
..
operatong conditions .
tAli typical values are at Vee = 5 V, TA = 25°C.
NOTE 2: ICC is measured with all outputs open and all inputs at 4.5 V.

switching characteristics, Vee = 5 V, T A = 25° C

PARAMETER TEST CONDITIONS MIN TVP MAX UNIT
tPHL Propagation delay time, high·to-Iow-Ievel output from A input 100
ns
tPLH Propagation delay time, low-to-high-Ievel output from A input CL=15pF, RL=667n, 100
tPHL Propagation delay time, high-to-Iow-Ievel output from RBI input See Note 5 100
ns
tpLH Propagation delay time, low-to-high-Ievel output from RBI input 100
NOTE 5: Load CirCUit and voltage waveforms are shown on page 3-10.

1076

7-360 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • CALLAS, TEXAS 75222
 TYPES SN54LS249, SN74LS249
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
REVISED OCTOBER 1976

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1) 7V
Input voltage . . . . . . . . . . . . . . 7V
Current forced into any output in the offstate . . . . 1 rnA
Operating free-air temperature range: SN54LS249 -55°C to 125°C
SN74LS249 . O°C to 70°C
Storage temperature range -65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.
recommended operating conditions
SN54LS249 SN74LS249
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output voltage, VOH a thru g 5.5 5.5 V
Hi!tl-Ievel output current, 10H BI/RBO -50 -50 J1.A
a thru g 4 8
Low-level output current, 10L mA
Bl/RBO 1.6 3.2
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (m'!!ess otherwise noted)
PARAMETER TEST COND!T!ONS
SN54LS249 SN74 LS249 I Ur-~IT
MIN TYP:j: MAX MIN TYP:j: MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
VIK Input clamp voltage Vee = MIN, 11=-18mA -1.5 -1.5 V
Vee= MIN, VIH=2V,
VOH High-level output voltage BI/RBO 2.4 4.2 2.4 4.2 V
VIL = VIL max, 10H = -50 J1.A
Vee= MIN, VIH=2V,
10H High-level output current a thru g 250 250 J1.A
VIL = VIL max, VOH = 5.5 V
Vee = MIN, I
10L = 1.6mA 0.25 0.4 0.25 0.4
I I BI/RBO VIH=2V, V I

VOL Low-level output voltage

VIL = VIL max
10L = 3.2 mA
I 0.35 0.5
I
Vee = MIN,
10L = 4 mA 0.25 0.4 0.25 0.4
a thru g VIH=2V, V

II
I n put current at
maximum input voltage
Any input
except BI/RBO
VIL = VIL max

Vee = MAX,
10L = 8 mA

VI = 7V 0.1
0.35 0.5

0.1 mA
II
Any input
IIH High-level input current Vee= MAX, VI = 2.7 V 20 20 J1.A
except BI/RBO
Any input
-0.4 -0.4
IlL Low-level input current except BI/RBO Vee= MAX, VI = 0.4 V mA
BI/RBO -1.2 -1.2
Short-circuit
lOS BI/RBO Vee = MAX -0.3 -2 -0.3 -2 mA
output current
ICC Supply current Vee = MAX, See Note 2 8 15 8 15 mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at VCC = 5 V, T A = 25°C.
NOTE 2: ICC is measured with all outputs open and inputs at 4.5 V.

switching characteristics, Vee = 5 V, TA = 25°e

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPHL Propagation delay time, high-to-Iow-Ievel output from A input eL=15pF, RL=2kn, 100
ns
tpLH Propagation delay time, low-to-high-Ievel output from A input See Note 6 100
tpHL Propagation delay time, high-to·low-Ievel output from RBI input eL-15pF, RL = 6 kn, 100
ns
tPLH Propagation delay time, low-to-high-Ievel output from RBI input See Note 6 100

NOTE 6: Load circu it and voltage waveforms are shown on page 3·11.

U.S.A
1076

TEXAS INCORPORATED
INSTRUMENTS 7-361
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TTL TYPES SN64261, SN64LS261. SN64S261,
SN74261, SN74LS261 (TIM99061. SN74S261
MSI DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS
BULLETIN NO. DL-S 7611 DECEMBER 1972-REVISED ER 1976

SN54251, SN54LS251, SN54S251 .•• J OR W PACKAGE

SN74251, SN74LS251, SN54S251 ••. J OR N PACKAGE
(TOP VIEW)
• Three-State Versions of '151, 'LS151, 'S151
• Three-State Outputs Interface Directly with
System Bus
• Perform Parallel-to-Serial Conversion
• Permit Multiplexing from N-lines to One Line
• Complementary Outputs Provide True and
Inverted Data
• Fully Compatible with Most TTL and DTL
Circuits

positive logiC: see function table

MAX NO. TYPICAL AVG PROP TYPICAL
TYPE OF COMMON DELAY TIME POWER
OUTPUTS (DTOY) DISSIPATION functional block diagram
SN54251 49 17 ns 250mW
SN74251 129 17 ns 250mW
SN54LS251 49 17 ns 35mW IE~:~~-,,,,,-I ---<l>------r-----.------.
SN74LS251 129 17 ns 35mW
SN54S251 39 8 ns 275mW 01 III

SN74S251 129 8 ns 275mW

02 ~21

03 (1)

description 04 115]

These monolithic data selectors/multiplexers contain 06 il).

full on-chip binary decoding to select one-of-eight

01 (12'
data sources and feature a strobe-controlled three-

~
i

•
state output. The strobe must be at a low logic level
to enable these devices. The three-state outputs per-
mit a number of outputs to be connected to a com-
'e':.~~~{: : :
tSTNlI.RV,
A, , e
c 191 C

mon bus. When the strobe input is high, both outputs

are in a high-impedance state in which both the upper
and iower transistors of each totem-pole output are
off, and the output neither drives nor loads the bus
significantly. When the strobe is low, the outputs are FUNCTION TABLE
activated and operate as standard TTL totem-pole INPUTS OUTPUTS
outputs. SELECT STROBE
Y W
C B A S
To minimize the possibility that two outputs will X x X H Z Z
attempt to take a common bus to opposite logic L L L L DO 00
levels, the output control circuitry is designed so that L L H L 01 01
the 'average output disable time is shorter than the L H L L 02 52
average output enable time. The SN54251 and L H H L 03 OJ
SN74251 have output clamp diodes to attenuate H L L L 04 54
reflections on the bus line. H L H L 05 Os
H H L L 06 66
H H H L 07 OJ
H = high logic level, L = low logic level
X = irrelevant, Z = high impedance (off)
DO, 01 ... 07 = the level of the respective 0 input

1076

7-362 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALL.AS. TEXAS 75222
 TYPES SN54251, SN74251
DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) 7V
Input voltage . . . . . . . 5.5V
Off-state output voltage 5.5 V
Operating free-air temperature range: SN54251 -55°C to 125°C
SN74251 O°C to 70°C
Storage temperature range -65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54251 SN74251
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -2 -5.2 rnA
Low-level output current, 10L 16 16 rnA
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDlTlONSt MIN TYP+ MAX UNIT
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
VIK Input clamp voltage Vee = MIN, 11= -12mA -1.5 V
Vee- MIN, VIH - 2 V,
VOH High-level output voltage 2.4 3.2 V
VIL = 0.8 V, 10H = MAX
Vee- MIN, VIH-2V,
VOL Low-level output voltage 0.2 0.4 V
VIL = 0.8 V, 10L = 16mA
Vee = MAX, Vo = 2.4 V 40
I I o (oft) Off-state (high-impedance-state) output current
I VIH = 2 V Vo = 0.4 V -40
JJA

Vee = MAX, 10=-12mA -1.5

Vo Output clamp voltage V
VIH = 4.5 V IO=12mA Vee+ 1. 5
II
IIH
Input current at maximum input voltage
High-level input current
Vee= MAX,
Vee = MAX,
VI = 5.5 V
VI = 2.4 V
1
40
rnA
/lA
II
IlL Low-level input current Vee - MAX, VI - 0.4 V -1.6 rnA
lOS Short-circuit output current!l Vee= MAX -18 -55 rnA
Vee = MAX, All inputs at4.5 V,
ICC Supply current 38 62 rnA
All outputs open

tFor conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
+AII typical values are at V CC = 5 V, T A = 25° C.
§Not more than one output should be shorted at a time.

1076

TEXAS INCORPORATED
INSTRUMENTS 7-363
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54251, SN74251
DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS

switching characteristics, Vee = 5 V, TA = 25°e

FROM TO
PARAMETER~ TEST CONDITIONS MIN TYP MAX UNIT
(INPUT) (OUTPUT)
tPLH A, B, or C 29 45
y ns
tPHL (4 levels) 28 45
tpLH A, B,orC 20 33
W ns
tpHL (3 levels) 21 33
tPLH 17 28
Any 0 y CL; 50 pF, ns
tpHL 18 28
RL ;400 n,
tPLH 10 15
Any D W See Note 2 ns
tpHL 9 15
tZH y 17 27
Strobe ns
tZL 26 40
tZH 17 27
Strobe W ns
tZL 24 40
tHZ 5 8
Strobe y CL; 5 pF, ns
tLZ 15 23
RL; 400 n,
tHZ 5 8
Strobe W See Note 2 ns
tLZ 15 23

~ tpLH '" Propagation delay time, low-to-high-Ievel output

tpH L == Propagation delay time, high-to-Iow-Ievel output
tZH '" Output enable time to high level
tZL '" Output enable time to low level
tHZ == Output disable time from high level
tLZ '" Output disable time from low level
NOTE 2: See load circuits and waveforms on page 3-10.

schematics of inputs and outputs

EQUIVALENT OF EACH INPUT TYPICAL OF BOTH OUTPUTS

--~vcc
II vcc-------.------

INPUT
--Uf OUTPUT

Select: Req; 6 kn NOM

Other inputs: Req; 4 kn NOM

1272

7·364 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • bALLAS, TEXAS 75222
 TYPES SN54LS251, SN74LS251 (TIM9905)
DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS
REVISED OCTOBER 1976

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) 7V
Input voltage . . . . . . . . 7V
Off-state output voltage 5.5V
Operating free-air temperature range: SN54LS251 55°C to 125°C
SN74LS251 oOe to 70°C
Storage temperature range -65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54LS251 SN74 LS251
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -1 -2.6 mA
Low-Ieve! output current, 'OL 4 8 mA
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS251 SN74 LS251
PARAMETER TEST CONDITIONSt UNIT
MIN TYP:j: MAX MIN TYp:j: MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
VIK Input clamp voltage Vee= MIN, II = -18 mA -1.5 -1.5 V
Vee = MIN, V!H = 2 V,
VOH High·level output voltage 2.4 3.4 2.4 3.1 V
VIL = MAX, 10H = MAX

Vee = MIN, IOL=4mA 0.25 0.4 0.25 0.4

VOL Low-level voltage VIH = 2 V, V
VIL = VIL max IOL =8 mA 0.35 0.5

10(oft)
Off-state (high-impedance-state)
output current
Vee= MAX,
VIH = 2V
VO=2.7V
Va = 0.4 V
20
-20
20
-20
!LA I
II Input current at maximum input voltage Vee= MAX, VI- 7 V 0.1 0.1 mA
IIH High-level input current Vee= MAX, VI = 2.7 V 20 20 !LA
IlL Low-level input current Vee = MAX, VI - 0.4 V -0.4 -0.4 mA
lOS Short-circuit output current§ Vee = MAX -30 -130 -30 -130 mA
Vee= MAX, Condition A 6.1 10 6.1 10
ICC Supply current mA
See Note 3 Condition 8 7.1 12 7.1 12

tFor conditions shown as II(1IN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
:j:AII typical values are at VCC = 5 V.:J A = 25°C.
§Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
NOTE 3: ICC is measured with the outputs open and all data and select inputs at 4.5 V under the following conditions:
A. Strobe grounded.
B. Strobe at 4.5 V.

1076

TEXAS INSTRUMENTS 7-365

INCORPORATED
POST OFFICE BOX 5012 • CALLAS. TEXAS 75222
 TYPES SN54LS25_1. SN74LS251 (TIM9905)
DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS

switching characteristics, Vee = 5 V, TA = 25°e

FROM TO
PARAMETER~ TEST CONDITIONS MIN TYP MAX UNIT
(INPUT) (OUTPUT)
tPLH A, B,orC 29 45
Y ns
tpHL (4 levels) 28 45
tPLH A, B,orC 20 33
W ns
tpHL (3 levels) 21 33
tpLH 17 28
Any D Y CL=15pF, ns
tpHL 18 28
RL=2kn,
tpLH See Note 4 10 15
Any D W ns
tpHL 9 15
tZH 30 45
Strobe Y ns
tZL 26 40
tZH 17 27
Strobe W ns
tZL 24 40
tHZ 30 45
Strobe Y CL = 5 pF, ns
tLZ 15 25
RL = 2 kn,
tHZ 37 55
Strobe W See Note 4 ns
tLZ 15 25

~ tpLH "" Propagation delay time, low-to-high-Ievel output

tpH L "" Propagation delay time, high-to-Iow-Ievel output
tZH "" Output enable time to high level
tZL"" Output enable time to low level
tHZ"" Output disable time from high level
tLZ "" Output disable time from low level
NOTE 4: See load circuits and waveforms on page 3-11.

schematics of inputs and outputs

EQUIVALENT OF EACH INPUT TYPICAL OF BOTH OUTPUTS

Vee

I ~
Req

INPUT
~

~~
,
.. r-
.. ~

r.7

A, B, e, S: Req = 20 kn NOM
DO thru 07: Req = 17 kn NOM

1076

7-366 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54S251. SN74S251
DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) 7V
Input voltage . . . . . . . . 5.5 V
Off-state output voltage 5.5 V
Operating free-air temperature range: SN54S251 -55°e to 125°e
SN74S251 oOe to 700e
0
Storage temperature range -65°e to 150 e
NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54S251 SN74S251
UNIT
MiN NOM MAX MIN i-.lOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -2 -6.5 rnA
Low-level output current, 10L 20 20 rnA
7n
I Operating free-air temperature, T A I- 55 125 0 .- I °c

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST eONDlTlONSt MIN TYP+ MAX UNIT
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
VIK Input clamp voltage Vee= MIN, 11=-18mA -1.2 V

I VOH High-level output voltage

Vee= MIN, VIH=2V, I SN54S' 2.4 3.4
V I
VIL = 0.8 V, 10H = MAX i SN74S' 2.4 3.2
Vee = MIN, VIH=2V.
VOL Low-level output voltage 0.5 V
VIL = 0.8 V, 10L = 20 rnA

I o (oft) Off·state (high-impedance-state) output current

Vee = MAX, I Vo = 2.4 V 50
p.A

II
IIH
Input current at maximum input voltage
High-level input current
VIH = 2 V
Vee= MAX,
Vee - MAX,
I
VI-2.7V
Vo = 0.5 V
VI = 5.5V
-50
1
50
rnA
p.A
I
IlL Low-level input current Vee = MAX, VI = 0.5 V -2 rnA
lOS Short-circuit output current!< Vee - MAX -40 -100 rnA
Vee = MAX, All inputs at 4.5 V,
ICC Supply current 55 85 rnA
All outputs open

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
+AII typical values are at Vee = 5 V, T A = 25°C.
§ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.

1076

TEXAS INSTRUMENTS 7-367

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54S251, SN74S251
DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS

switching characteristics, Vee = 5 V, TA = 25°e

FROM TO
PARAMETER~ TEST CONDITIONS MIN TYP MAX UNIT
(INPUT) (OUTPUT)
tpLH A, B,orC 12 18
Y ns
tpHL (4 levels) 13 19.5
tpLH A, B, or C CL=15pF, 10 15
W ns
tpHL (3 levels) RL = 280 n, 9 13.5
tpLH See Note 2 8 12
Any 0 Y ns
tpHL 8 12
tpLH 4.5 7
Any 0 W ns
tpHL 4.5 7
tZH 13 19.5
Strobe Y CL = 50pF, ns
tZL 14 21
RL=280n,
tZH 13 19.5
Strobe W See Note 2 ns
tZL 14 21
tHZ 5.5 8.5
Strobe Y CL = 5 pF, ns
tLZ 9 14
RL = 280 n,
tHZ 5.5 8.5
Strobe W See Note 2 ns
tLZ 9 14

~tpLH := Propagation delay time, low-to-high-Ievel output

tpH L:= Propagation delay time, high-to-Iow-Ievel output
tZH := Output enable time to high level
tZL := Output enable time to low level
tHZ := Output disable time from high level
tLZ:= Output disable time from low level
NOTE 2: See load circuits and waveforms on page 3-10.

I
schematics of inputs and outputs

vcc

INPUT
-
EQUIVALENT OF EACH INPUT

xW 2.8 kn NOM

--
TYPICAL OF BOTH OUTPUTS

----------~----vcc

OUTPUT

1272

7·368 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TTL TYPES SN54LS253, SN74LS253
DUAL 4-UNE-TO-1-UNE DATA SELECTORS/MULTIPLEXERS
MSI WITH 3-STATE OUTPUTS
BULLETIN NO. DL-S 7611790, SEPTEMBER 1972-REVISED OCTOBER 1976

SN54LS253 ••• J OR W PACKAGE

SN74LS253 .•. J OR N PACKAGE
(TOP VIEW)
• Three-State Version of SN54LS153/SN74LS153
DATA INPUTS
• Schottky-Diode-Clamped Transistors r -____ ~A~ ______ ~

• Permits Multiplexing from N Lines to 1 Line

• Performs Parallel-to-Serial Conversion
• Typical Average Propagation Delay Times:
Data Input to Output ... 12 ns
Control Input to Output ... 16 ns
Select I nput to Output ... 21 ns
• Fully Compatible with Most TTL and DTL
Circuits
• Low Power Dissipation ... 35 mW Typical
(Enabled) ~----~v~------~
DATA INPUTS

logic: see function table

description
Each of these Schottky-clamped data selectors/multiplexers contains inverters and drivers to supply fully
complementary, on-chip, binary decoding data selection to the AND-OR gates. Separate output control inputs are
provided for each of the two four-line sections.

The three-state outputs can interface with and drive data lines of bus-organized systems. With all but one of the
common outputs disabled (at a high-impedance state) the low-impedance of the single enabled output will drive the bus
line to a high or low logic level.

logic functional block diagram

FUNCTION TABLE
SELECT OUTPUT
DATA INPUTS OUTPUT

DATA'{:::~:::
INPUTS CONTROL
B
X
L
A
X
L
CO
X
L
Cl
X
X
C2
X
X
C3
X
X
G
H
L
Y
z
L 'C2.",{4,-' ----++-+-ffL.J
I
L L H X X X L H 1C3\31
L H X L X X L L
L H X H X X L H
H L X X L X L L
H L X X H X L H

DATA2{2::~::::
H H X X X L L L
H H X X X H L H

Address inputs A and B are common to both sections. ZC2(12)

H = high level, L = low level, X = irrelevant, Z = high impedance (off)

1131
2C3

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) 7V
Input voltage . . . . . . . . . 7V
Off-state output voltage . . . . . 5.5 V
Operating free-air temperature range: SN54LS253 -55°C to 125°C
SN74LS253 oOe to 70°C
Storage temperature range . . . . -65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.

1076

TEXAS INSTRUMENTS 7-369

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TeXAS 75222
 TY~ES_~N54LS253, SN74~S253
DUAL 4:LlNE-TO-1-LlNE DATA S_ELECTOIJS/
MULTIPLEXERS WITH 3-STATE OUTPUTS
REVISED OCTOBER 1976

recommended operating conditions

SN54lS253 SN74lS253
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, VCC 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -1 -2.6 mA
low-level output current, 10l 4 8 mA
Operating free-air temperature, T A -55 125 0 70 °c

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54lS253 SN74lS253
PARAMETER TEST CONDITIONSt UNIT
MIN TYP+ MAX MIN TYP+ MAX
VIH High-level input voltage 2 2 V
Vil low-level input voltage 0.7 0.8 V
VIK I nput clamp voltage VCC= MIN, 11=-18mA -1.5 -1.5 V
VCC= MIN, VIH = 2V, i
High-level output voltage 2.4 3.4 2.4 3.1 V
VOH
Vil = VILmax, 10H = MAX I
VCC= MIN, VIH=2V, IOl = 4mA 0.25 0.4 0.25 0.4
Val Low-level output voltage V
VI'L = VIL max 10L =8mA 0.25 0.5
Off-State (high-impedance Vo = 2.7 V 20 20
10Z Vec = MAX, VIH = 2 V ,.,.A
state) output current Va = 0.4 V -20 -20
I nput current at
II Vec = MAX, VI = 7V 0.1 0.1 mA
maximum input voltage
IIH High-level input current VCC = MAX, VI = 2.7 V 20 20 ,.,.A
IlL low-level input current VCC = MAX, VI = 0.4 V -0.4 -0.4 mA
lOS Short-circu it output current § VCC = MAX' -30 -130 -30 -130 mA
Condition A 7 12 7 12
ICC Supply current VCC= MAX, See Note 2 mA
Condition B 8.5 14 8.5 14

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.,

•
+AII typical values are at VCC =5 V, T A = 25°C.
§ Not more than one output should be shorted at a time, and duration for the.short-circuit should exceed one second .
NOTE 2: ICC is measured with the outputs open under the following conditions:
A. All inputs grounded.
B. Output control at 4.5 V, all inputs grounded.

switching characteristics, Vee =5 V, TA = 25°C

FROM TO
PARAMETERlI TEST CONDITIONS MIN TYP MAX UNIT
(INPUT) (OUTPUT)
tpLH 17 25
Data Y ns
tpHL 13 20
tplH CL=15pF, RL = 2 kn, 30 45
Select y ns -
tpHL See Note 3 21 32
tZH Output 15 28
Y ns
tZl Control 15 23
tHZ Output ~ = 5 pF, RL = 2 kn, 27 41
Y ns
tlZ Control See Note 3 18 27
11 tpLH == Propagation delay time, low-to-high-Ievel output
tPHL == Propagation delay time, high-to-Iow-Ievel output
tZH == Output enable time to high level
tZL == Output enable time to low level
tHZ == Output disable time from high level
tLZ == Output disable time from low level
NOTE 3: Load circuit and waveforms are shown on page 3-11.

1076

7-370 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • OALLAS, TEXAS 75222
 TYPES SN54LS253. SN74LS253
DUAL 4-LlNE~TO-1-LlNE DATA SELECTORS/
MULTIPLEXERS WITH 3-STATE OUTPUTS
REVISED OCTOBER 1976

schematic (each selector/multiplexer, and the common select section)

CO (6.10)

Cl (5. II)

-+-+-+-+-+:ij.....
C3 --'(....:.3._13""")_ _

~VCC
TO OTHER SELECTOR/MUL TlPLEXER
(SEE FUNCTIONAL BLOCK DIAGRAM)
M 1 [JGND

w ... VCC bus

Resistor values shown are nominal and in ohms.

PRINTED IN USA
1076

TEXAS INCORPORATED
INSTRUMENTS 7-371
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54LS257A, SN54LS258A, SN54S257, SN54S258,
TIL SN74LS257A, SN74LS258A, SN74S257, SN74S258
MSI QUADRUPLE 2-UNE-TO-1-UNE DATA SELECTORS/MULTIPLEXERS
BULLETIN NO. DL-S 7611734. OCTOBER 1976

SN54LS257A, SN54S257 •• , J OR W PACKAGE

• Three-State Outputs Interface Directly
SN74LS257A, SN74S257 ••• J OR N PACKAGE
with System Bus (TOP VIEW)

• 'LS257 A and 'LS258A Offer Three INPUTS INPUTS

OUTPUT ~OUTPUT ~ OUTPUT
Times the Sink-Current Capability VCCCONTROL4A 4B 4Y 3A 38 3Y
of the Original 'LS257 and 'LS258
• Same Pin Assignments as SN54LS157,
SN74LS157,SN54S157,SN74S157,and
SN54LS158, SN74LS158, SN54S158,
SN74S158
s 3Y
• Provides Bus Interface from Multiple
Sources in High-Performance Systems 1A 18 lY 2A 28 2Y

AVERAGE PROPAGATION TYPICAL

DELAY FROM POWER
DATA INPUT DISSIPA TIONO SELECT ~ lY ~ 2Y GND
'LS257A 12 ns 60mW INPUTS OUTPUT INPUTS OUTPUT
'LS258A 12 ns 60mW
4.8 ns 320mW positive logic: see function table
'S257
'S258 4 ns 280mW
SN54LS258A, SN54S258 ••• J OR W PACKAGE
00ff state (worst case)
SN74LS258A, SN74S258 ••• J OR N PACKAGE
!TOPVIEW.)
description INPUTS INPUTS
OUTPUT r--"-..
OUTPUT ~ OUTPUT
VCCCONTROL4A 48 4Y 3A 38 3Y
These Schottky·clamped high-performance multi-
plexers feature three-state outputs that can interface
directly with and drive data lines of bus-organized
systems. With all but one of the common outputs
disabled (at a high-impedance state) the low impe-
dance of the single enabled output will drive the bus
I line to a high or low logic level. To minimize the
possibility that two outputs will attempt to take a
common bus to opposite logic levels, the output-
epable circuitry is designed such that the output
disable times are shorter than the output enable
times.
SELECT ~ lY ~ 2Y GND
INPUTS OUTPUT INPUTS OUTPUT
This three-state output feature means that n-bit
(paralleled) data selectors with up to 258 sources can positive logic: see function table
be implemented for data buses. It also permits the use
of standard TTL registers for data retention
throughout the system. FUNCTION TABLE
INPUTS OUTPUTY

Series 54LS and 54S are characterized for operation OUTPUT 'LS257A 'LS258A
SELECT A B
over the full military temperature range of -55°e to CONTROL 'S257 '8258
125°e; Series 74LS and 74S are characterized for H X X X Z Z
o
operation from oOe to 70 e. L L L X L H
L L H X H L
L H X L L H
L H X H H L
H ~ high level, L ~ low level, X ~ irrelevant, Z ~ high impedance (off)

1076

7-372 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54lS257A, SN54lS258A, SN54S257, SN54S258,
SN74lS257A, SN74lS258A, SN74S257, SN74S258
QUADRUPLE 2-UNE-TO-1-UNE DATA SELECTORS/MUlTIPLEXERS
functional block diagrams
'LS257A, 'S257 'LS258A, 'S258

CONTROL CONTROL
lA lA

(3) lY (3) lY
18 18

(5) (5)
2A 2A

(6) 2Y (6) 2Y
28 28

3A ( 111 (11)
3A

(10) 3Y (10) 3Y
38 3B

4A
(14)
,~ ~"41
I ti--r L; <121
4Y 4B~ 4Y
4B

SELECT SELECT (1)

schematics of inputs and outputs

- -
'LS257A, 'LS258A 'S257, 'S258

EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS

VCC

INPUT

q Req
--
---.---VCC

OUTPUT
V CC

INPUT

c
Req

--
---.---VCC

OUTPUT •
Select: Req ~ 9.5 kU NOM Select: Req ~ 1.4 kU NOM
All other inputs: Req = 19 kn NOM All other inputs: Req = 2.8 kn NOM

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, VCC (see Note 1) 7V

Input voltage: 'LS257A, 'LS258A Circuits 7V
'S257, 'S258 Circuits 5.5V
Off-state output voltage . . . . . . . 5.5 V
Operating free-air temperature range: SN54LS', SN54S' Circuits -55°C to 125°C
SN74LS', SN74S' Circuits aOc to 7aoC
Storage temperature range -65°C to 15aoC

NOTE 1: Voltage values are with respect to network ground terminal.

1076

TEXAS INSTRUMENTS
INCORPORATED
7-373
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54LS257A, SN54LS258A, SN74LS257A, SN74LS258A
QUADRUPLE 2-LlNE-TO-1-LlNE DATA SELECTORS/MULTIPLEXERS

recommended operating conditions

SN54LS' SN74LS'
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vce 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -1 -2.6 mA
Low-level output current, 10L 12 24 mA
Operating free-air temperature, T A -55 125 0 70 °c

electrical characteristics over recommended operating free-air

-
temperature range (unless otherwise noted)
SN54LS' SN74LS'
PARAMETER TEST CONDITIONSt UNIT
MIN TYP:j: MAX MIN TYp:j: MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
VIK Input clamp voltage Vee= MIN, 11=-18mA -1.5 -1.5 V
Vce = MIN, VIH=2V,
VOH High-level output voltage 2.4 3.4 2.4 3.1 V
VIL = VIL max, 10H = MAX
Vce= MIN, 0.25 0.4 0.25 0.4
IOL=12 mA
VOL Low-level output voltage VIH = 2 V, V
IOL=24mA 0.35 0.5
VIL = VIL max
Off-state output current, Vee = MAX, VIH=2V,
20 20 p,A
10ZH high-level voltage applied Vo =2.4 V
Off-state output current, Vee = MAX, VIH=2V,
10ZL -20 -20 p,A
low-level voltage applied Vo = 0.4 V
Input current at S input 0.2 0.2
II Vec = MAX, VI = 7V mA
maximum input voltage Any other 0.1 0.1
High-level S input 40 40
IIH Vce= MAX, VI = 2.7 V p,A
input current Any other 20 20
Low-level S input -0.8 -0.8
IlL VCC= MAX, VI = 0.4 V mA
input current Any other -0.4 -0.4
lOS Short-circuit output current§ Vec= MAX -30 -130 -30 -130 mA
All outputs high

•
6.2 10 6.2 10
All outputs low 'LS257A 10 16 10 16
All outputs off Vce= MAX, 12 19 12 19
ICC Supply current mA
All outputs high See Note 2 4. 7 4.5 7
All outputs low 'LS258A 8.8 14 8.8 14
1 Ai! outputs off 12 19 , 12 19,

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at Vee = 5 V, T A = 25°e.
§N.ot more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
NOTE 2: lee is measured with all outputs open and all possible inputs grounded while achieving the stated output conditions.
switching characteristics, Vee = 5 V, T A = 25°e, RL ';·667 kU
PARAMETER~
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS MIN
'LS257A
TYP MAX MIN
'LS258A
TYP MAX
UNIT I
tpLH 12 18 12 18
Data Any ns
tpHL 12 18 12 18
tpLH CL =45 pF, 14 21 14 21
Select Any ns
tpHL See Note 3 14 21 14 21
tpZH Output 20 30 20 30
Any ns
tpZL Control 20 30 20 30
tpHZ Outout CL=5pF, 18 30 18 30
Any ns
tpLZ Control See Note 3 16 25 16 25

~tpLH == propagation delay time, low-to-high-Ievel output tpZL == output enable time to low level
tpHL == propagation delay time, high-to-Iow-Ievel output tpHZ == output disable time from high level
tpZH == output enable time to high level tpLZ == output disable time from low level
NOTE 3: Load circuit and waveforms are shown on page 3-11.

DESIGN GOAL
1076
This page provides tentative information on a
1-314 product in the developmental stage. Texas TEXAS INCORPORATED
INSTRUMENTS
Instruments reserves the right to change or dis-
continue this product without notice. POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54S257, SN54S258, SN74S257, SN74S258
QUADRUPLE 2-UNE-TO-1-UNE DATA SELECTORS/MULTIPLEXERS

recommended operating conditions

SN54S257, SN54S258 SN74S257, SN74S258
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -2 -6.5 rnA
Low-leI(el output current, 10L 20 20 rnA
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN545257, SN74S257 SN54S258, SN74S258
PARAMETER TEST CONDITIONSt UNIT
MIN TYp:j: MAX MIN TYp:j: MAX
VIH High-level input voltage 2 2 V
VIL LoW'level input voltage 0.8 0.8 V
ViK Input clamp voltage Vee= MIN, Ij=-18mA -i.2 -1.2 V
Vee- MIN, VIH = 2V, I SN54S' 2.4 3.4 2.4 3.4
High-level output voltage V
VOH
VIL = 0.8 V, 10H = MAX I SN74S' 2.4 3.2 2.4 3.2

'VOL Low-level output voltage

Vee = MIN, VIH = 2 V,
0.51 0.51 V ,
V-'L. .- -,
OAV ·UL. -?O .....
d

Off-state output current, Vee = MAX, VIH= 2V,

10ZH 50 " 50 IJ.A
high-level voltage applied VO=2.4V
'
Off-state output current, Vee = MAX, VIH = 2 V,
10ZL -50 -50 IJ.A
low-level voltage applied VO=0.5V
I nput current at maximum
II Vee= MAX, VI = 5.5V 1 1 rnA
input voltage
High-level S input 100 100
IIH Vee = MAX, VI = 2.7 V p.A
input current Any other 50 50
LO'J"J-!s'..'e! S input I -4 -4
IlL Vee = MAX, VI = 0.5 V rnA
input current Any other -2 -2

•
lOS Short-circuit output current§ Vee= MAX -40 -100 -40 -100 rnA
All outputs high 44 68 36 56
ICC Supply current All outputs low Vee = MAX, See Note 2 60 93 52 81 rnA
All outputs off 64 99 56 87

tFor conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at VCC = 5 V, T A = 25°C.
§Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
NOTE 2: ICC is measured with all outputs open and all possible inputs grounded while achieving the stated output conditions.

switching characteristics, Vee = 5 V, TA = 25°e, RL = 280 Q

FROM TO TEST SN54S257, SN74S257 SN54S258, SN74S258
PARAMETER~ UNIT
(INPUT) (OUTPUT) CONDITIONS MIN TYP MAX MIN TYP MAX
tpLH 5 7.5 4 6
Data Any "ns
tpHL 4.5 6.5 4 6
tpLH eL=15pF, 8.5 15 8 12
Select Any ns
tpHL See Note 4 8.5 15 7.5 12
tpZH Output 13 19.5 13 19.5
Any ns
tpZL Control 14 21 14 21
tpHZ Output eL - 5 pF, 5.5 8.5 5.5 8.5
Any ns
tpLZ Control See Note 4 9 14 9 14

~ tp LH == propagation delay time, low-to-high-Ievel output tpZL'= output enable time to low level
tpH L == propagation delay time, high-to-Iow-Ievel output tPHZ '= output disable time from high level
tpZH '= output enable time to high level tpLZ'= output disable time from low level
NOTE 4: Load circuit and waveforms are shown "on pages 3-10_

1076

TEXAS INCORPORATED
INSTRUMENTS 1-315
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TTL TYPES SN54259. SN54LS259. SN74259. SN74LS259 (TIM9906)
MSI 8~BIT ADDRESSABLE LATCHES
BULLETIN NO. DL-S 7612347, OCTOBER 1976

• 8-Bit Parallel-Out Storage Register SN54259, SN54LS259 •. , J OR W PACKAGE

Performs Serial-to-Parallel Conversion With SN74259, SN74LS259 ... J OR N PACKAGE
Storage (TOP VIEW)
• Asynchronous Parallel Clear OUTPUTS
EN· DATA
• Active High Decoder CLEAR ABLE IN Q7
~
os 05 04
• Enable/Disable Input Simplifies Expansion
• Direct Replacement for Fairchild 9334
• Expandable for N-Bit Applications
• Four Distinct Functional Modes
D
• Typical Propagation Delay Times:
B
'259 'LS259 C
Enable-to-Output. .. 12 17
Data-to-Output .... 12 18
Address-to-Output .. 16 20
Clear-to-Output 16 20
• Fan-Out
IOL (Sink Current)
ABC QO Q1 02 Q3 GND
'259 ............. 16 mA ~ ~
LATCH SEL OUTPUTS
SN54LS259 ....... 4 mA
SN74LS259 ....... 8 mA
IOH (Source Current) logic: see function table
'259 ............. -0.8 mA
'LS259 ........... -0.4 mA
• Typical ICC
'259 ............. 60mA
'LS259 ........... 22 mA
description FUNCTION TABLE

These 8-bit addressable latches are designed for OUTPUT OF EACH

INPUTS
general purpose storage applications in digital sys- ADDRESSED OTHER FUNCTION

•
CLEAR G
tems. Specific uses include working registers, serial- LATCH OUTPUT
holding registers, and active-high decoders or demul- H L D GiO Addressable Latch
tiplexers. They are multifunctional devices capable of H H GiO GiO Memory
storing single-line data in eight addressable latches, L L D L 8-Line Demultiplexer
and being a 1-of-8 decoder or demultiplexer with L H L L Clear
active-high outputs.
Four distinct modes of operation are selectable by LATCH SELECTION TABLE
controlling the clear and enable inputs as enumerated
in the function table. In the addressable-latch mode, SELECT INPUTS LATCH
data at the data-in terminal is written into the C B A ADDRESSED
addressed latch. The addressed latch will follow the
data input with all unaddressed latches remaining in
L
L
L
L
L
H
I 0
1
their previous states. In the memory mode, all latches L H L 2
remain in their previous states and are unaffected by L H H 3
the data or address inputs. To eliminate the possibil- H L L 4
ity of entering erroneous data in the latches, the H L H 5
enable should be held high (inactive) while the H H L 6
address lines are changing. In the 1-of-8 decoding or H H H 7
demultiplexing mode, the addressed output will
follow the level of the D input with all other outputs
H"" high level, L "" low level
low. In the clear mode, all outputs are low and D;; the level at the data input
unaffected by the address and data inputs. 0iO =' the level of 0i (i = 0, 1, ... 7, as appropriate) before the indio
cated steady·state input conditions were established.

1076

7-376 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54259, SN54LS259, SN74259, SN74LS259 CTIM99061
8-BIT ADDR~SSABLE LATCHES

schematic of inputs and outputs

-'259

EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS

- - - - - - - - - -......- - - VCC

Vcc------~-----
100 n NOM

INPUT
'----.....- - - OUTPUT

Latch select, data in, or clear: Req

=
_______________________________________
Enable: kn Rcq
=4
2_2
kn NOM
NOM
~I
I I_______________________________________________________
~I ~

'LS259 'LS259

EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS

--~VCC
VCC __ ~120nNOM
Req = 17 kn NOM

INPUT Dol
..,-.. - L...-_ _....._ _ _ OUTPUT

~~
~,
....
~~

n7 •
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage (see Note 1) . 7V

Input voltage: SN54259, SN74259 . . 5.5 V
SN54LS259,SN74LS259 . 7V
Operating free-air temperature range: SN54259, SN54LS259 -55°C to 125°C
SN74259,SN74LS259 oOe to 70°C
Storage temperature range . -65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

1076

TEXAS INCORPORATED
INSTRUMENTS 7-377
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54259,SN74259
8-BIT ADDRESSABLE LATCHES

recommended operating conditions

SN54259 SN74259
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -800 -800 JlA
Low-level output current, 10L 16 16 mA
Width of clear or enable pulse, tw 15 15 ns
Data 15i 15t
Setup time, tsu ns
Address 5t 5t
Data ot ot
Hold time, th ns
Address 20t 20t
Operating free-air temperature, T A -55 125 0 70 °e

tThe arrow indicates that the rising edge of the enable pulse is used for reference.

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54259 SN74259
PARAMETER TEST CONDITlONSt UNIT
MIN TYP:j: MAX MIN TYP:j: MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 : V
VIK Input clamp voltage Vee = MIN, II = 12 mA -1.5 I -1.5 V !
Vee = MIN, VIH = 2 V, I
VOH High-level output voltage 2.4 3.4 2.4 3.4 V
VIL = 0.8 V, IOH = --800 JlA ! i
Vee = MIN, VIH = 2 V,
VOL Low-level output voltage 0.2 0.4 0.2 0.4 I V
VIL = 0.8 V, IOL = 16mA
II Input current at maximum input voltage Vee = MAX, VI = 5.5 V 1 1 mA
High-level input Enable 80 80
IIH Vee = MAX, VI = 2.4 V JlA
current Other inputs 40 40
Low-level input Enable -3.2 -3.2
IlL Vee = MAX, VI = 0.4 V mA
current Other inputs -1.6 -1.6

I lOS
ICC
Short-circuit output current§
Supply current
Vee= MAX
Vee = MAX, See Note 2
-18
60
-57
90
-18
60
-57
90
mA
mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAli typical values are at V CC ~ 5 V, T A = 25° C.
§ Not more than one output should be shorted at a time,
NOTE 2: ICC is measured with the inputs grounded and the outputs open.

switching characteristics, Vee = 5 V, TA = 25° C

I I FROM TO
PARAMETER I (INPUT) (OUTPUT) I TEST CONDITIONS
I MIN TYP MAX I UNIT
I

tPHL Clear Any Q 16 25 ns

tpLH 14 24
Data Any Q ns
tpHL eL=15pF, 11 20
tPLH RL = 400n, 15 28
Address Any Q ns
tPHL See Note 3 17 28
tPLH 12 20
Enable Any Q ns
tPHL 11 20

tpLH == propagation delay time. low-to-high-Ievel output

tPH L == propagation delay time, high-to-Iow-Ievel output
NOTE 3: Load circuit is shown on page 3-10.

1076

7-378 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54LS259, SN74LS259 ITIM9906)
8-BIT ADDRESSABLE LATCHES

recommended operating conditions

SN54LS259 SN74 LS259
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, IOH -400 -400 J.lA
Low-level output current, IOl 4 8 mA
Width of clear or enable pulse, tw 15 15 ns
Data 15T 15t
Setup time, tsu ns
Address 15t 15t
Data ot ot
Hold time, th ns
Address ot ot
Operating free-air temperature, T A -55 125 0 70 °e

tThe arrow indicates that the rising edge of the enable pulse is used for reference.

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
f---=SN:.:.54:....:..::L==S:::2=59=---t_-'S:::.N::.:7c.::4:.=L=S2:::5::::9~-I UNIT

I VIH
PARAMETER

High level input voltage

TEST eONDITIONSt
IM!~ TYP+ MAX IM!~ TYpt MAX I V I
VIL Low level input voltage 0.7 0.8 V
VIK Input clamp voltage Vee= MIN, II = -18 mA -1.5 -1.5 V
Vee = MIN, VIH = 2 V
VOH High-level output voltage 2.5 3.4 2.7 3.4 V
VIL = VIL max, IOH = -0.4 mA
Vee = MIN, VIH = 2 V, llOL =4 mA 0.25 0.4 0.25 0.4
VOL Low-level output voltage V
VIL = VIL max. iloL =8 mA 0.35 0.5
Input current at maximum
II Vee = MAX. VI =7V 0.1 0.1 mA
input voltage
IIH High-level input current Vee = MAX, VI=2.7V 20 20 1 ;.tA
I
IlL Low-level input current I Vee= MAX. VI=0.4V -0.4 -0.4 mA J
lOS Short-circuit output current§ Vee = MAX -20 -100 -20 -100 mA

•
ICC Supply current Vee = MAX. See Note 2 22 36 22 36 mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAli typical values are at Vee = 5 V, T A = 25°e.
§ Not more than one output should be shorted at a time, and duration short-circuit should not exceed one second.
NOTE 2: ICC is measured with the inputs grounded and the outputs open.

switching characteristics, Vee = 5 V, TA = 25°e

FROM TO
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
(INPUT) (OUTPUT)
tpHL Clear Any Q 17 27 ns
tPLH 20 32
Data Any Q eL=15pF, ns
tPHL 13 21
RL = 2 kU,
tPLH Any Q
24 38
Address See Note 3 ns
tpHL 18 29
tpLH 22 35
Enable Any Q ns
tPHL 15 24

tpLH == propagation delay time. low-to-high-Ievel output

tpHL == propagatiOn delay time, high-to-Iow-Ievel output
NOTE 3: Load circuit is shown on pa!!e 3-11. •

1076

TEXAS INCORPORATED
INSTRUMENTS 7-379
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TIL TYPES SN54LS261, SN74LS261
MSI 2-BIT-BY-4-BIT PARALLEL BINARY MULTIPLIERS
BULLETIN NO. DL·S 7612123. MARCH 1974-REVISED OCTOBER 1976

• Fast Multiplication ... 5-Bit Product in 26 ns Typ SN54LS261 ••• J OR W PACKAGE

SN74LS261 ..• J OR N PACKAGE
• Power Dissipation ... 110 mW Typical (TOP VIEW)
• Latch Outputs for Synchronous Operation OUTPUTS
~
VCC 62 61 60 M1 MO 00 01
• Expandable for m-Bit-by-n-Bit Applications
• Fully Compatible with Most TTL and Other
Saturated Low-Level Logic Families
• Diode-Clamped Inputs Simplify System
Design
G 01

description

These low-power Schottky circuits are designed to be

used in parallel mUltiplication applications. They
perform binary multiplication in two's-complement 63 B4 LATCH
M2~ GND
form, two bits at a time. CONTROL
G OUTPUTS

The M inputs are for the multiplier bits and theB inputs positive logic: see description

are for the multiplicand. The Q outputs represent the

partial product as a recoded base-4 number. This
recoding effectively reduces the Wallace-tree FUNCTION TABLE
hardware requirements by a factor of two.
INPUTS OUTPUTS
LATCH
The outputs represent partial products in one's- MULTIPLIER
CONTROL 04 Q3 Q2 Q1 QO
complement form generated as a result of mUltiplica- M2 M1 MO
G
tion. A simple rounding scheme using two additional
L X X X 040 030 02 0 01 0 000
gates is needed for each partial product to generate
H L L L H L L L L

•
two's complement.
H L L H B4 B4 B3 B2 Bl
H L H L B4 B4 B3 B2 Bl
The leading (most-significant) bit of the product is
inverted for ease in extending the sign to square (left
H L H H B4 B3 B2 Bl BO
H H L L B4 83 82 81 80
justify) the partial-product bits. -
H H L H B4 B4 B3 82 81

The SNS4LS261 is characterized for operation over

H H H L 84 B4 83 82 181

the full military temperature range of -ssoe to

H IH H H H L L L L
o
12S e; the SN74LS261 for operation from oOe to H ; high level. L; low level. X ; irrelevant
o
70 e. 040 ..• aoo ; The logic level of the same output before the
high-to-Iow transition of G.
schematics of inputs and outputs B4 •.. BO; The logic level of the indicated multiplicand (B) input.

EQUIVALENT OF EACH INPUT TYPICAL OF QQ. Q1. Q2. Q3 OUTPUTS TYPICAL OF 04 OUTPUT
---~t--Vcc -----+-VCC
VCC--'---
17 kn NOM

INPUT.....,.~ _ _....

OUTPUT OUTPUT

G: R eq ;17knNOM
B or M2: Req; 20 kn NOM
MO or MI:Re = 10 kn NOM

1076

7·380 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE sox 5012 • DALLAS, TEXAS 75222
 TYPES SN54LS261, SN14LS261
2-BIT-BY-4-BIT PARALLEL BINARY MULTIPLIERS

functional block diagram

BO (13)

MO
•
M1--.......~

374

TEXAS INCORPORATED
INSTRUMENTS 7-381
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54LS261, SN74LS261
2-BIT-BY-4-BIT PARALLEL BINARY MULTIPLIERS
REVISED OCTOBER 1976

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ..... . 7V
Input voltage . . . . . . . . . . . . . . 7V
Operating free·air temperature range: SN54LS261 -55°C to 125°C
SN74LS261 O°C to 70°C
Storage temperature range -65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54LS261 SN74LS261
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -400 -400 jJ.A
Low-level output current, 10L 4 8 mA
Width of enable pulse, tw 25 25 ns
Any M input 17.[ 17.[
Setup time, tsu ns
Any B input 15.[ 15.[
Any M input 0.[ OJ,
Hold time, th ns
Any B input OJ, 0,[
Operating free-air temperature, T A -55 125 0 70 °e

.[ The arrow indicates that the falling edge of the enable pulse is used for reference.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS261 SN74LS261
PARAMETER TEST CONDITIONSt UNIT
MIN TYPt MAX MIN TYPt MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
VIK Input clamp voltage Vee - MIN, 11--18mA -1.5 -1.5 V
Vee = MIN, VIH=2V,
VOH High-level output voltage 2.5 3.4 2.7 3.4 V
VIL = VIL max, 10H =-400jJ.A
Vee= MIN, VIH = 2 V, 10L = 4 mA ,0.25 0.4 0.25 0.4

•
VOL Low-level output voltage V
VIL = VIL max 10L - 8 mA ,0.35 '0.5
Input current at MOorMI 0.2 0.2
II Vee= MAX, VI = 7 V mA
maximum input voltage All others 0.1 0.1
MOorMI 40 40
IIH High-level input current Vee = MAX, VI = 2.7 V jJ.A
All others 20 20
, MOorM! -0,8 -0.8 I
IlL Low-level input current Vee = MAX, VI = O.4'V rnA
All others -0.4 -0.4
lOS Short-circuit output current~ Vee = MAX -20 -100 -20 -100 mA
Vee - MAX, All inputs at 0 V,
ICC Supply current 22 38 20 40 mA
OUtputsopen ,
tAli typical values <Ire at VCC = 5 V, T A = 25°C.
§Not more than one output should be shorted at a time and duratlc)ri of the output short-circuit should not exceed one second.
switching characteristics, Vee = 5 V, TA = 25°C
FROM TO
PARAMETER 11 TEST CONDITIONS MIN TYP MAX UNIT
(INPUT) (OUTPUT)
tPLH 22 35 ns
Enable G AnyQ
tpHL 20 30 . ns
eL=15pF,
tPLH 25 40 ns
Any M input AnyQ RL=2kn,
tpHL 22 35 ns
See Note 2
tPLH 27 42 ns
Any B input AnyQ
tpHL 24 37 ns

11 tp LH == propagation delay time, low-to-high-Ievel output; tpH L "" propagation delay time, h igh-to-Iowlevel output.

NOTE 2: Load circuit and voltage waveforms are shown on page 3-11,

1076

7-382 TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54LS261, SN74LS261
2-BIT-BY-4-BIT PARALLEL BiNARY MULTIPLIERS
TYPICAL APPLICATION DATA

Multiplication of the numbers 26 (multiplicand) by 29 (multiplier) in decimal, binary, and 2-bit-at-a-time-binary is

shown here:

DECIMAL BINARY 2-BIT-AT-A-TIME BINARY

Sign Sign
Bit

•
Bit

B
M
26
29
011010
011101
•
011010
(+2) (-1) (+1)

R
234

754
011010
000000
011010 lI 6
00000011010
111100110
0110100
1 3
Partial
... Products
p",,;, ,
+~
011010
011010 " Products
Product
C;nn
uuuuuu V'~II

QJ011110010, Bit
f~
Sign Product
Bit

Two points should be noted in the two-bit-at-a-time-binary example above. First, in positioning the partial products
beneath each other for final addition, each partial product is shifted two places to the left of the partial products above
it instead of one place as is done in regular multiplication. Second, the msb of the partial product (the sign bit) is
extended to the sign-bit column of the final answer.

A substantial reduction of multiplication time, cost, and power is obtained by implementing a parallel

•
partial-product-generation scheme using a 2-bit-at-a-time algorithm, followed by a Wallace Tree summation .

Partial-product-generation rules of the algorithm are:

1. Examine two bits of multiplier M plus the next lower bit. For the first partial product (PP1) the next lower bit is
zero.

374

TEXAS INCORPORATED
INSTRUMENTS 7-383
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54LS261, SN14LS261
2-BIT-BY-4-BIT PARALLEL BINARY MULTIPLIERS

TYPICAL APPLICATION DATA

2. Generate partial product (PPi) as shown in the following table:

MUL TIPLIER BITS FROM

OPERATOR
STEP 1 TO OBTAIN PARTIAL PRODUCT
SYMBOL
221-1 221-2 2 21 - 3
0 0 0 0 Replace multiplicand by zero
0 0 1 +1 B Copy multiplicand
0 1 0 +1 B Copy multiplicand
0 1 1 +2 B Shift multiplicand left one bit
1 0 0 -2B Shift two's complement of multiplicand left one bit
1 0 1 -1 B Replace multiplicand by two's complement
1 1 0 -1B Replace multiplicand by two's complement
1 1 1 0 Replace multiplicand by zero

3. Weight the partial products by indexing each two places left relative to the next-less-significant product.

4. Extend the most-significant bit of the partial product to the sign-bit place value of the final product.

EXAMPLE OF ALGORITHM

Operator
M 29 011101 B = 26 = 011010
Symbol

yjota +1 B 00000011010
+110 -lB 111100110
011 +2 B 0110100

• The summation of these partial products was shown in the 2-bit-at-a-time binary multiplication example above.

The 'LS261 generates partial products according to this algorithm with two exceptions:

i. The one's complement is generated fo; the cases requiring the tI,"JO'S complement. The two's comp!ement can be
obtained by adding one to the one's complement; this rounding can be done by using one NAND gate and one AND
gate as shown in Figure B.

2. The most-significant bit is complemented to reduce the hardware required to extend the sign bit. This extension can
be accomplished by adding a hard-wired logic 1 in bit position 22i+15 of each partial product and also in bit
position 2 16 of the first partial product (PP1).

37<

7·384 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54LS261, SN74LS261
2-BIT-BY-4-BIT PARALLEL BINARY MULTIPLIERS

LATCH
CONTROL

~--------------------~v~--------------------~
20 INPUTS TO WALLACE TREE

FIGURE A-FIRST PARTIAL PRODUCT, PP1

LATCH

CONTROL -rrI ~ B4 B3 B2

'LS261
B1~~
:~

"JF
I IIII1
.+
\2 2,'15 2 2 14

~------------------'9-'N-P-UT--'S
TOVWAllACE TREE

FIGURE B-OTHER PARTIAL PRODUCTS, PPi

•
FIGURE C-MANIPULATION OF PARTIAL PRODUCTS FOR ENTRY INTO WALLACE TREE

In general, the 4 x 2 bit 'LS261 can be expanded for use in 4m x 2n bit multipliers. Partial~product generation uses
m x n 'LS261s m x n -;-16 'LSOOs, and m x n -;-16 'LS08s. The size of the Wallace tree and ALU requirements vary
depending on the size of the problem. The count for the 16 x 16 bit mu Itiplier is:

32 SN54LS261/SN74LS261
2 SN54LSOO/SN74LSOO
2 SN54LS08/SN74LS08
56 SN54H183/SN74H183
7 SN54LS181/SN74LS181
2 SN54LS182/SN74LS182

74

TEXAS INCORPORATED
INSTRUMENTS 7-385
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TTL TYPES SN54LS266, SN74LS266
QUADRUPLE 2-INPUT EXCLUS'IVE-NOR GATES
MSI WITH OP'EN-COLLECTOR OUTPUTS
BULLETIN NO. DL-S 7611843, DECEMBER 1972-REVISED OCTOBER 1976

SN54LS266 ••. J OR W PACKAGE

SN74LS266 •.. J OR N PACKAGE
• Can Be Used as a 4-Bit Digital Comparator (TOP VIEW)
• Input Clamping Diodes Simplify System
Design Vcc 4B 4A 4Y 3Y 3B 3A

• Fully Compatible with Most TTL and

DTL Circuits

FUNCTION TABLE

INPUTS OUTPUT
r--.a:-s Y
L L H
L H L
H L L
H H H
H = high level, L = low level
1B 1Y 2Y 2A 2B GND

description positive logic: Y = A<±lB = AB + AS

The 'LS266 is comprised of four independent 2-input exclusive-NOR gates with open-collector outputs. The open-
collector outputs permit tying outputs together for multiple-bit comparisons.

schematics of inputs and outputs

•
EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS

U--
VCC::C--
12.5 kn NOM T VCC

f V-0UTPUT

'NeUT

--Q

10

7-386 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54LS266. SN74LS266
QUADRUPLE 2-INPUT EXCLUSIVE-NOR GATES
WITH OPEN-COLLECTOR OUTPUTS
REVISED OCTOBER 1976

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, Vee (see Note 1) ..... . 7V

Input voltage . . . . . . . . . . . . . . 7V
Operating free-air temperature range: SN54LS266 -55°C to 125°C
SN74LS266 O°C to 70°C
Storage temperature range -65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54LS266 SN74 LS266
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output voltage, VOH 5.5 5.5 V
Low·level output current, IOL 4 8 mA
Operating free-air temperature, T A -55 125 0 70 °e

eiectricai characteristics over recommended operating free-air temperature range (uniess otherwise notedj
SN54LS266 SN74 LS266
PARAMETER TEST eONDITIONst UNIT
MIN TYP+ MAX MIN TYP+ MAX

VIH High-level input voltage 2 2 V

VIL Low-level input voltage 0.7 0.8 V

VIK Input clamp voltage Vee= MIN, II = -18mA -1.5 -1.5 V
Vee= MIN, VIH = 2 V,
IOH High-level output current 100 100 J.LA
VIL = VIL max, VOH = 5.5 V
Vee= MIN,

VOL Low-level output voltage VIH = 2 V,

riaL =4 mA 0.25 0.4 0.25 0.4
V I
I
VIL = VIL max riaL = 8 mA I 0.35 0.51 I
II Input current at maximum input voltage Vee = MAX, VI = 7V 0.2 0.2 mA

IIH
IlL
lee
High-level input current
Low-level input current
Supply current
Vee = MAX,
Vee - MAX,
Vee = MAX,
VI = 2.7 V
VI = 0.4 V
See Note 2 8
-0.8
40

13 8

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
+AII typical values are at VCC = 5 V, T A = 25"C.
NOTE 2: ICC is measured with one input of each gate at 4.5 V, the other inputs grounded, and the outputs open.
40
-0.8
13
J.LA
mA
mA

•
switching characteristics, Vee = 5 V, TA = 25° C
FROM
PARAMETER~ TEST CONDITIONS MIN TYP MAX UNIT
(INPUT)
tpLH 18 30
A orB Other input low eL=15pF, ns
tpHL 18 30
RL = 2 kU,
tpLH 18 30
A orB Other input high See Note 3 ns
tpHL 18 30

~ tpLH == propagation delay time, low-to-high·level output

tpH L == propagation delay time, high·to-Iow·level output
NOTE 3: Load circuit and voltage waveforms are shown on page 3-11.

1076

TEXAS INSTRUMENTS 7-387

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TIL TYPES SN54273, SN54LS273, SN74273, SN74LS273
MSI OCTAL D-TYPE FLIP-FLOP WITH CLEAR
BULLETIN NO. DL·S 7612091, OCTOBER 1976

• Contains Eight Flip-Flops with SN54273, SN54LS273 ... J PACKAGE

Single-Rail Outputs SN74273, SN74LS273 , .. J OR N PACKAGE

• Buffered Clock and Direct Clear Inputs

• Individual Data Input to Each Flip-Flop
• Applications Include:
Buffer/Storage Registers
Shift Registers
Pattern Generators

description

These monolithic, positive-edge-triggered flip-flops

utilize TTL circuitry to implement D-type flip-flop
logic with a direct clear input. CLEAR 20 20 30 3D 40

Information at the D inputs meeting the setup time

positive logic: see function table
requirements is transferred to the Q outputs on the
positive-going edge of the clock pulse. Clock
triggering occurs at a particular voltage level and is FUNCTION TABLE
not directly related to the transition time of the (EACH FLIP-FLOP)
positive-going pulse. When the clock input is at either INPUTS OUTPUT
CLEAR CLOCK D Q
the high or low level, the D input signal has no effect
at the output. L X X L
H t H H
These flip-flops are guaranteed to respond to clock H t L L
frequencies ranging from 0 to 30 megahertz while H L X 00
maximum clock frequency is typically 40 megahertz.
Typical power dissipation is 39 milliwatts per See explanation of fu netion tables on page 3·8.

flip-flop for the '273 and 10 milliwatts for the

• 'LS273 .
schematics of inputs and output

EQUIVALENT OF EACH INPUT ,

VCC~--

w--
'273
TYPICAL OF ALL OUTPUTS

-
EQUIVALENT OF EACH INPUT
'LS273
! TYPICAL OF ALL OUTPUTS

o
I

INPUT
loon
-}vcc
NOM
VCC
20 kn NOM
--~VCC
~~O!! NOM

INPUT --
OUTPUT
OUTPUT

Clear: Req = 3 kn NOM

Clock: Ffeq = 6 kn NOM m
All ather inputs: Req = 8 kn NOM

functional block diagram

1076

7-388 TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54273, SN74273
OCTAL D-TYPE FLIP-FLOP WITH CLEAR

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1). . . . . . ..... 7 V
Input voltage . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range: SN54273 _55°C to 125°C
SN74273 aOe to 7aoe
Storage temperature range -65°C to 15aoe
NOTE1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54273 SN74273
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, VCC 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -800 -800 /lA
Low-level output current, 10L 16 16 rnA
Clock frequency, fclock 0 30 0 30 MHz
Width of clock or clear pulse, tw 16.5 16.5 ns

I Data input 20t 20t

Sl::!t-liP tim~~ tsu
Clear inactive state I 25t 25t
ii5

Data hold time, ttl 5t 5t ns

Operating free-air temperature, T A -55 125 o 70

tThe arrow indicates that the rising edge of the clock pulse is used for reference.

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONSt MIN TYP+ MAX UNIT
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
VIK Input clamp voltage VCC= MIN, II = -12 rnA -1.5 V
VCC = MiN, VIH = 2 V,
VOH High-level output voltage 2.4 3.4 V
VIL = 0.8 V, 10H = -800/lA

•
VCC= MIN, VIH=2V,
VOL Low-level output voltage 0.4 V
VIL = 0.8 V, 10L = 16 rnA
II Input current at maximum input voltage VCC = MAX, VI = 5.5 V 1 rnA
Clear 80
IIH High-level input current VCC = MAX, VI = 2.4 V /lA
Clock or D 40
Clear -3.2
IlL Low-level input current VCC = MAX, VI = 0.4 V rnA
Clock or D -1.6
lOS Short-circuit output current § VCC = MAX -18 -57 rnA
ICC Supply current VCC = MAX, See Note 2 62 94 rnA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at Vee = 5 V, T A = 25°C.
§Not more than one output should be shorted at a time.
NOTE 2: With all outputs open and 4.5 V applied to all data and clear inputs, ICC is measured after a momentary ground, then 4.5 V, is
applied to clock.

switching characteristics, Vee = 5 V, TA = 25°e

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f max Maximum clock frequency 30 40 MHz
CL=15pF,
tPHL Propagation delay time, high-to-Iow-Ievel output from clear 18 27 ns
RL = 400 n,
tpLH Propagation delay time, low-to-high-Ievel output from clock 17 27 ns
See Note 3
tpHL Propagation delay time, high-to-Iow-Ievel output from clock 18 27 ns

NOTE 3: Load circuit and voltage waveforms are shown on page 3-10.

1076

TEXASINCORPORATED
INSTRUMENTS 7-389
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54LS273, SN74LS273
OCTAL O-TYPE FLIP-FLOP WITH CLEAR

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ..... . ..... 7 V
Input voltage . . . . . . . . . . . . . . . . . . . 7V
Operating free·air temperature range: SN54LS273 -55°C to 125°C
SN74LS273 O°C to 70°C
Storage temperature range 65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal

recommended operating conditions

SN54lS273 SN74lS273
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -400 -400 Il A
low·level output current, 10l 4 8 mA
Clock frequency, fclock 0 30 0 30 MHz
Width of clock or clear pulse, tw 20 20 ns

Set-up time, tsu

I Data input 20t 20t
ns
I Clear inactive state 25t 25t
Data hold time, th 5t 5t ns
Operating free-air temperature, T A -55 125 0 70 °e

tThe arrow indicates that the rising edge of the clock pulse is used for reference.

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS273 SN74LS273
PARAMETER TEST CONDITIONSt UNIT
MIN TYP* MAX MIN TYP* MAX
VIH High·level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V

•
VIK Input clamp voltage VCC = MIN, II = -18 mA -1.5 -1.5 V
Vee - MIN, VIH -2 V,
VOH High-level output voltage 2.5 3.4 2.7 3.4 V
VIL = Vilmax, 10H = -400IlA
Vee - MIN, VIH - 2 V,POL - 4 mA 0.25 0.4 0.25 0.4
VOL Low-level output voltage V
VIL = VILmax POL = 8mA 0.35 0.5
I
Ii Input current at maximum input voitage Vee = MAX, V; =7 V 0.1 I
0" mA
IIH High-level input current Vee MAX, VI- 2.7 V 20 20 IlA
III low-level input current Vee = MAX, VI = -0.4 V -0.4 -0.4 mA

lOS Short-circuit output current § Vee = MAX -20 -100 -20 -100 mA
ICC Supply current Vee - MAX, See Note 2 17 27 17 27 mA

i For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at Vee = 5 V, T A = 25°e.
§ Not more than one output should be shorted at a time and duration of short circuit should not exceed one second.
NOTE 2: With all outputs open and 4.5 V applied to all data and clear inputs, lee is measured after a momentary ground, then 4.5 V is
applied to clock.

switching characteristics, Vee = 5 V, TA = 25°e

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f max Maximum clock frequency 30 40 MHz
tpHL Propagation delay time, high-to-Iow-Ievel output from clear eL = 15 pF, 18 27 ns
tplH Propagation delay time, low-to-high-Ievel output from clock RL =2 kn, 17 27 ns
tpHL Propagation delay time, high-to-Iow-Ievel output from clock See Note 4 18 27 ns

NOTE 4: Load circuit and voltage waveforms are shown on page 3-11.

10

7-390 TEXAS INCORPORATED

INSTRUMENTS
I='OST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54LS275, SN54S274, SN54S275,
TTL SN74LS275, SN74S274, SN74S275
4-BIT-BY-4-BIT BINARY MULTIPLIER WITH 3-STATE OUTPUTS
LSI 7-BIT-SLICE WALLACE TREES WITH 3-STATE OUTPUTS
BULLETIN NO. DL-S 7612121, OCTOBER 1976

• 'S274 Provides 8-Bit Product in Typically SN54S274 ••. J PACKAGE

SN74S274 ••• J OR N PACKAGE
45 ns
(TOP VIEW)

• 'S274 Can Provide Sub-Multiple Products

for n-Bit-by-n-Bit Binary Numbers

• 'LS275 and 'S275 Accept 7 Bit-Slice Inputs

and 2 Carry I nputs for Reduction to 4 Lines
in Typically 45 ns

• These High-Complexity Functions Can Reduce

Package Count by Nearly 50% in Most
Parallel Multiplier Designs
A2' A2"+1 p,Z'+2 ~3 82" 2" 2"+12"+22"""3
• When SN74S274 is Combined With SN74H183 ~'--y-.J'-y----I
~~~TB
(or SN74LS183) and Schottky Look-Ahead WORD A INPUTS A. B OUTPUTS

Adders, Multiplication Times are Typically:

positive logic: When either (or both) G input(s) is
(are) high, all eight outputs are off. ___ _
J
16-Bit Product in 75 ns (79 ns)
32-Bit Product in 116 ns (132 ns)

SN54LS275, SN54S275 ... J PACKAGE

description SN74LS275, SN74S275 ... J OR N PACKAGE
(TOP VIEW)
These high-complexity Schottky·damped TTL cir-
cuits are designed specifically to reduce the delay
time required to perform high-speed parallel binary
multiplication and significantly reduce package
count. The 'S274 is a basic 4-bit-by-4-bit parallel

•
multiplier in a single package, and as such, no
additional components are required to obtain an 8-bit
product. For word lengths longer than 4 bits, a
number of 'S274 multipliers can be combined to
generate sub-multiple partial products. These partial
products can then be combined in Wallace trees to
obtain the final product. See Typical Application
Data. p p p p ~ ~ 2" GND
'-y------' '-v--' SLICE
INPUT
SLICE INPUTS CARRY IN
The 'LS275 and 'S275 expandable bit-slice Wallace
trees have been designed to accept up to seven positive logic: When G is high, all four outputs are off.
bit-slice inputs and two carry inputs from previous
slices for reduction to four lines.

076

TEXAS INSTRUMENTS 7-391

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54LS275,SN54S274,SN54S275, SN74LS275, SN74S274, SN74S275
4-BIT-BY-4-BIT BINARY MULTIPLIER WITH 3-STATE OUTPUTS
7-BIT-SLICE WALLACE TREES WITH 3-STATE OUTPUTS
functional block diagram
'LS275, 'S275
.
BIT·SLICE INPUTS OF 2"

NOTE: When one of of the C2 n carry inputs is not used, it must be

grounded. If neither C2 n carry input is used, both C2 n
inputs are grounded and the C2 n + 1 output is normally left
open.

schematics of inputs and outputs

- 'LS275 'S274, 'S275

•
EaUIVALENT OF TYPICAL OF ALL OUTPUTS EaUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS
EACH INPUT
VCC -----.--VCC

I Nt>UT
h Req

--
V C C - . f l - __
----.--VCC

W
"l-I!f.!--t-- OUTPUT
OUTPUT

Enable G:
Req = 18 k!1 NOM
Others: Req = 6 k!1 NOM

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, Vcc (see Note 1) · 7V

Input voltage: 'LS275 . . . . · 7V
'S274, 'S275 5.5 V
Off·state output voltage: 'LS275 · 7V
'S274, 'S275 5.5V
Operating free-air temperature range: SN54LS, SN54S Circuits -55°C to 125°C
SN74LS, SN74S Circuits O°C to 70°C
Storage temperature range -65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.

10j

7-392 TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54LS215, SN14LS215
1-BIT-SLICE WALLACE TREES WITH ~-STATE OUTPUTS

recommended operating conditions

SN54LS275 SN74LS275
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -1 -2.6 mA
Low-level output current, IOL 12 24 mA
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS275 SN74LS275
PARAMETER TEST eONDITIONSt UNIT
MIN TYP:j: MAX MIN TYp:j: MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
VIK Input clamp voltage Vee= MIN, 11=-18mA -1.5 -1.5 V
Vee = MIN, VIH = 2 V,
VOH High-level output voltage 2.4 3.2 2.4 3.1 V
VIL = VILrnax IOH = MAX
V,...,... - ~.~IN I. .. - - - .
~1_IO_L__
=_I_~_m_A-+I______U_.~_b____U_._441_______
U_.l_b____u_.4~1 V
VOL Low-level output voltage
VIL = VILrnax I iOL = 24 rnA 0.35 0.5
Off-state output current, Vee = MAX, VIH = 2 V,
IOZH 20 20 J.l.A
high-level voltage applied Vo = 2.7 V
Off-state output current, Vee= MAX, VIH = 2 V,
10ZL -20 -20 J.l.A
low-level voltage applied Va = 0.4 V
Input current at Enable G 0.1 0.1
II Vee = MAX, VI =7V mA
maximum input voltage All others 0.3 0.3
High-level Enable G 20 20
IIH Vee = MAX, VI = 2.7 V J.l.A
input current All others 60 60
Low-level Enable G I -0.4 I -0.4 I
IlL Vee = MAX, VI = 0.4 V mA
input current All others 1 -1.21 -1.21

•
lOS Short-circuit output current§ Vee = MAX -30 -130 -30 -130 mA
lee Supply current Vee = MAX 25 40 25 40 mA
t For conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at VCC =5 V, T A = 25°C.
§ Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.

switching characteristics, Vee = 5 V, TA = 25°e

FROM TO
PARAMETER~ TEST CONDITIONS MIN TYP MAX UNIT
(INPUT) (OUTPUT)
tpLH eL =45 pF, RL = 667 .n, 41 62
Any Slice or earry Any ns
tpHL See Note 2 44 66
tpZH 15 23
ns
tpZL eL=5pF, RL = 667.n, 15 23
Any Enable Any
tpHZ See Note 2 10 15
ns
tpLZ 10 15

~ tpLH == Propagation delay time, low-to-high-Ievel output

tpHL == Propagation delay time, high-to-Iow-Ievel output
tpZH == Output enable time to high level
tpZL == Output enable time to low level
tpHZ == Output disable time from high level
tpLZ == Output disable time from low level
NOTE 2: Load circuit and voltage waveforms are shown on page 3-11.

1076 DESIGN GOAL

This page provides tentative information on a TEXAS INSTRUMENTS 7-393
product in the developmental stage. Texas INCORPORATED
I nstruments reserves the right to change or dis- POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
continue this product without notice.
 TYPES SN54S274, SN54S275, SN74S274, SN74S275
4-BIT-BY-4-BIT BINARY MULTIPLIER WITH 3-STATE OUTPUTS
7-BIT-SLICE WALLACE TREES WITH 3-STATE OUTPUTS
recommended operating conditions
SN54S274 SN74S274
SN54S275 SN74S275 UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -2 -6.5 rnA
Low-level output current, 10L 12 12 rnA
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54S274 SN74S274
PARAMETER TEST CONDITIONSt SN54S275 SN74S275 UNIT
MIN TYP:!: MAX MIN TYP:!: MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
VIK Input clamp voltage Vee= MIN, II = -18mA -1.2 -1.2 V
Vee = MIN, VIH=2V,
VOH High-level output voltage 2.4 3.4 2.4 3.2 V
VIL = 0.8 V, 10H = MAX
Vee= MIN, VIH = 2V,
VOL Low-level output voltage 0.5 0.5 V
VIL = 0.8 V, IOL=12mA
Off-state output current, Vee= MAX, VIH=2V,
50 50 J.IA
10ZH high-level voltage applied Vo = 2.4 V
Off-state output current, Vee= MAX, VIH=2V,
10ZL . -50 -50 J.IA
low-level voltage applied Vo =0.5 V
II Input current at maximum input voltage Vee= MAX, VI - 5.5 V 1 1 rnA
IIH High·level input current Vee= MAX, VI = 2.7V 25 25 J.IA
IlL Low-level input current Vee = MAX, VI = 0.5 V -0.25 -0.25 rnA
lOS Short-circuit output current§ Vee = MAX -30 -100 -30 -100 rnA
lee Supply current Vee = MAX 105 155 105 155 rnA

• switching characteristics over recommended ranges of T A and

PARAMETERl1

tPHL

tpLH
FROM
(INPUT)

Any A or B ('5274), or
Any Slice or Carry ('5275)
TO
(OUTPUT)

Any
TEST CONDITIONS

CL=30pF,
RL=400n,
See Note 3
Vee (unless otherwise noted)

MIN
SN54S274
SN54S275
TYP:!:

50

50
MAX

95

95
i
MIN
SN74S274
SN74S275
TYP:!:
50

50
MAX
70

70
I
UNIT

ns

tpZH 15 45 15 30
eL=5pF, ns
tPZL 15 45 15 30
Any Enable Any RL = 400 n,
tpHZ 10 40 10 25
See Note 3 ns
tPLZ 10 40 10 25

1 For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:!:AII typical values are at VCC = 5 V, T A = 25°C.
§ Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
11 tPLH ;: Propagation delay time, low-to-high-Ievel output
tPH L;: Propagation delay time, high-to-Iow-Ievel output
tPZH ;: Output enable time to high level
tPZL;: Output enable time to low level
tPHZ ;: Output disable time from high level
tpLZ ;: Output disable time from low level
NOTE 3: Load circuit and voltage waveforms are shown on page 3-10.

1076

7-394 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54LS275, SN54S274,SN54S275, SN74LS275, SN74S274, SN74S275
4-BIT-BY-4-BIT BINARY MULTIPLIER WITH 3-STATE OUTPUTS
7-BIT-SLICE WALLACE TREES WITH 3-STATE OUTPUTS
TYPICAL APPLICATION DATA

~sub-multiplepartialprQductbits ~sub-mult:iplepartial~uctbi1s
thatcontributa to the;i"+O product that tontribute to1he 2"+0 product
(See Note AI {See Note A)

~ ~ ';;7inputsperbit·s1ice
....--4-..j....4-l--t-iI-+--..., :07~n==ondelaytime - --, ~;=::~!s~~deJaytime
1 package per bit-slice ,..-I,-~""""',....J:-iL.:-t I
I
I
: -r2 -r' 2""': I
2"+~ carrybittOthe2"~~ tree _ • • • • oJ"" ... ']"' _">~ ca~bi~
0
2"''''''Yb;'1o",e2".'''''''1= .. 1. I. IT.." '''''''''OIBA'
• 3-INPUT •
I
'LS275/'S275 : ADDER :
I c-r' I
:~r··v
I

_, I. ...... I _. L---~ti~
. ""."'~'''''_t''DU'''y
tothe2"""' product.UsuaJly
this carry bi1: andthe:z"l+l
productoutput(from'then+l
2""'",oductoutput
2' ..... car::rbitthatcontnbtltesy2""""Pfoductoutput
to1he:zn product.Usuaily
'
thiscanybitandthe2"+1
proouctoutput(from%hen+l
Wallace tree) are fed intDa Wallace tree} are fed into a
summmgackier. summing adder.

FIGURE 1-BASIC BIT -SLICE WALLACE TREE FIGURE 2-HIGH-SPEED BIT-SLiCE WALLACE TREE

~ 7 inputs per bit-slice

61 ns typical propagation delay time

•
1 1/4 packages per bit-slice
BIT SLICE BIT SLICE BIT SLICE BIT SLICE

See
To next CO Note A

To n+2
tree ~------------------------~vr-----------------------J
To final summing adder

FIGURE 3-MODERATE-SPEED BIT -SLICE WALLACE TREE

NOTE A: All unused inputs must be grounded.

1076

TEXAS INSTRUMENTS 7-395

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54LS215,SN54S214, SN54S215, SN14LS215, SN14S214·, SN14S215
4-BIT-BY-4-BIT BINARY MULTIPLIER WITH 3-STATE OUTPUTS
1-BIT-SLICE WALLACE TREES WITH 3-STATE OUTPUTS
TYPICAL APPLICATION DATA

'" 15 inputs per bit·slice

101 nstypicalpropagationdelaytime
31/2,-"

~+-------~--+-~-------... }romn-1
}::~....
See
Note
A

. - - - - - , .... From n-2 Tree

Fromn-1 Tree

I
SeeN01IIC
I
L ________ _
~
To Final Summing Adder

NOTES: A. Ground unused inputs.

B. These outputs from preceeding trees may go to any of the inputs of the 'LS275";'S275.
C. The circuit within the dotted lines may be either the basic bit-slice Wallace tree or the high-speed Wallace tree. I n the latter case
both carry inputs of the 'LS2751'S275 must be grounded.
FIGURE 4-15-BIT-SLICE WALLACE TREE FOR 32-BIT X 32-BIT MULTIPLIER

•
See Note A
'LS275/
!"' -'5275 .,
I (27 Bits) i
i
i
i DETAIL A

i
L.

r~ ________________ ~
'-----------'j1
iL._._._._._._._. __ DETAIL A

2"+2 bit from 2"-2 tree

2"+1 bit from 2"-1 tree

"2'+2 bit to 2"'+2 tree

:z"+1 bit to 2"+1 tree

2"

~
To final summing adder

NOTES: A. Ground unused inputs.

B. The number of bits in parentheses is the maximum number of bits this tree can combine if the remaining 'LS2751'S275 (all having
a higher number in the parentheses) were not connected.

FIGURE 5-7-TO-31-BIT-SLICE WALLACE TREE FOR UP TO 64-BIT X 64-BIT MULTIPLIERS

107'

7·396 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54LS275, SN54S274,SN54S275, SN74LS275, SN74S274, SN74S275
4-BIT-BY-4-BIT BINARY MULTIPLIER WITH 3-STATE OUTPUTS
7-BIT-SLICE WALLACE TREES WITH 3-STATE OUTPUTS
TYPICAL APPLICATION DATA

'·_·_·_·_·_·_·_·-1
. 2 upper half of n X iower half of 11 •
,·_·_·_·....l·_·_·_·,·_·_·_·_·-1.·_·_·_·_· 1.
i.1 upper half of n X 2upper half of n . 210wer half of n X 210wer half of n
. _._._.,._._._.-1.._._._._.,._._._._)
. 210wer half of n X 2upper half of n .
L.!._._._._._._._._I
NOTE A: The left·hand half of each rectangle is the portion of
word one used to obtain the product shown within the
rectangle. Similarly, the right-hand half of each rectangle
is the portion of word two used.
FIGURE 6-UNIVERSAL METHOD OF
ADDING %
-BIT PRODUCTS TO
I
OBTAIN AN n-BIT PRODUCT I 1I
I I I
~I I~I i i i I 1(/)1 1
• I~H 1 I I I I~I t
I~I I I I I I~I~I~I~I I I I I I~I
CO

:-·(21S-;;;231·;x·(20·-;21s·)-!
r-·_·_·_·-L.·_·_·_·_·_·_-_·_·-1.·_·_·_·_· 1 1;1 I I I 1 I~I~I~I~I I I I I I~I
L(~~~·~!4!~~~·~)_·~·.E°~·~~~·~·~2~._j It-I I I I 1 I~I~I~I~I 1 I I I I~I
L.E~~.~~)~_~6...!?~1.~i
I~J 1 I I I I~ I~ I~ I~ I I I I I e~1
FIGURE 7-METHOD OF ADDING - ~ ~ ~ ~ ~ ~N ~ ~ ~ ~ ~ ~ ~ ~
32-BIT PRODUCTS TO OBTAIN A I~I~I~I~I~I~I~I~I~I~I~I~I~I~I~I~-I
64-BIT PRODUCT FIGURE a-FINAL PRODUCTS AND
ARRAY SUBPRODUCT ADDITIONS FOR
~&4 64 MULTIPLIER ARRAY
It.
32-BIT X 32-BIT MULTIPLIER

I I I I
•
I II I I I
I II I I I I I I
I I I II I I I I II I
II III I I I I I I I I I I I
I I I II I I I I I I I I I I I I I
I I I I I I I I I I I I I I I I I II I I I
I II II I I I I I I I I! I I I I I I I I I
I ~I I I I I I I I I I I I I I I I I I I I I I I ~I
I~I I I I I I I I I I I I I I I I I I i I I I I I I I I I ~I
I~I I I I I I I l::ll::ll::ll l::ll::ll::ll l::ll I l::ll::ll I l::ll::ll I I l::ll l::ll ~I
I{I 1 I 1 I I I I~I~I~I I~I~I~I I~I I I~I~I 1 I~I~I 1 I I~I 1~lil
I~I 1 I I I I I I~I~I~I I~I~I~I I~I I I~I~I 1 I~I~I I I I~I I~I':I
[if I I 1 I I I 1 I~I~INI 1:<:1~11l1 1;:;1 I I:<:I~I I I~I~I I 1 I~I 1;;17-..1
[!U:I:I~I:I 1 1 1:1:1:1 I:I:I~I 1:1 I I~I:I 1 1:1:1 I I~I~I~I~I~I
NOTE A: See Note B of Figure 6 for designing trees with any number of inputs up to 31.
AGURE 9-ARRAY ARRANGEMENT FOR VARIOUS MULTIPLIERS
INCLUDING ARRAYSUBPRODUCT ADDITIONS FOR 64-BIT X 64-BIT
MULTIPLIER

1076

TEXAS INCORPORATED
INSTRUMENTS 7-397
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54LS215.SN54S214. SN54S215. SN14LS215. SN14S214. SN14S215
4-BIT-BY-4-BIT BINARY MULTIPLIER WITH 3-STATE OUTPUTS
1-BIT-SLICE WALLACE TREES WITH 3-STATE OUTPUTS

TYPICAL APPLICATION DATA

. ~.
L.....----J~ &. ~
0
a.c:
0
'+'
E
iii
~ z
0
b i=
u
i
:0
w
Z
z
0
u
2 ~
M ::>
Q.
~ ~
::>
N 0
I
.,.,
.r:
CO)
II..
en
...0
~ ~
W
~ W
:J
C> J:
u:: ~
., OJ II:
en W
:i
~
"0
Q.
i=

•
0 ..J
a. ::>
:E
iii
~
"5 iii
0.
~
.-'" X
., ~
.c
iii
~ I cD

~ ::!
:c w II:
:c ::>
.;. CI
u::
:c
I-
*

1076

7-398 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 o-J

c:= ]
Ol

....
-<
1:1
~ . 'S274
"'a
m
(I)

/ =-r";;-
(I)

/~:F- ~·f
217~
4 22722622522 223222221220
Z
8, '/
~
4 U"I
J
r---- 8,
I
4
....
,f:IiI
(I)

,),~:~r::l,
N
~
I
.....
U"I
=-

'I, J-- J
16.
12
C:.:":",,,4
r
_~ _ _
J. L':r=:n,,,J
} ~ 4/ ~
."
g,~(I)
....
-
-
~z
=
=I N
(I)

U"I
..... -<,f:IiI

.....
n
»
1_,f:IiI
(I) .... _

r !::=(I)
n_Z
~
"0
mZU"l
r :el>,f:IiI
_::xli(/)
n
~ ....
--<N
.....
(5 S;3!:~
Z nC(I)
m!:tZ
C
~
.... - .....
::xlI"'a,f:lil
» m!:: ....
mm(l)
(I)::xlIN
:e:e~
4 ~~Cn
20 :C:CZ
12 28
WW .....
I I ,f:IiI
20 5 15 en en (I)
2 15 2'3 29 28 -I-IN
28 l>l> .....
-I-I,f:IiI
--~
mm'(n
) OOZ

2 31 230 2 29 2 28 227 2 26 225 224 2 23 222 221

'5 n7
2 20 :Z'9 2 18 217
7
2 16
7
CC .....
-I-I,f:IiI
-a-acn
CCN
-1-1 .....
FIGURE 10-16-8IT X 16-81T MULTIPLIER (SHEET 2 OF 3-oUTPUT CONNECTIONS)
en en U"I
.....
w
CCI
CCI

II
 TYPES SN54LS275,SN54S274,SN54S275, SN74LS275, SN74S274, SN74S275
4-BIT-BY-4-BIT BINARY MULTIPLIER WITH 3-STATE OUTPUTS
7-BIT-SLICE WALLACE TREES WITH 3-STATE OUTPUTS

TYPICAL APPLICATION DATA

• *Each starred block may be either a basic bit-5lice Wallace tree('LS275 or 'S275 only) or a high-5peed bit-slice Wallace tree ('LS275 plus 1/2
'LS183 or 'S275 plus 1/2 'Hl83). In either case the function of the terminal is the same as the similarly located terminal of the basic biHlice
(Figure 1) or high-speed biHlice Wallace tree (Figure 2). Also for either tree, when only five inputs of the seven-input adder of the
'LS275/'S275 are used, the remaining two inputs must be grounded. When the high-5peed adder is used, the C2 n inputs of the 'LS275/'S275
must be grounded.
t For improved performance SN74LS181/SN74S181 ALUs with SN74S182 look-ahead generators can be substituted for the
SN74283/SN74LS283/SN74S283 adders. Typically, the multiplication time will be reduced by 18 to 32 nanoseconds.

FIGURE 10-16-BIT X 16-BIT MULTIPLIER

(SHEET 3 OF 3-SUMMING PARTIAL PRODUCTS)

1076

7-400 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TTL TYPES SN54276, SN74276
MSI QUADRUPLE J-K FLIP-FLOPS
BULLETIN NO. DL-S 7612460, OCTOBER 1976

SN54276 . , . J PACKAGE
features SN74276 .•. J OR N PACKAGE
• Four J-K Flip-Flops in a Single Package ... (TOP VIEW)

Can Reduce FF Package Count by 500..b VCC 4J 4CK 4;( 40 30 3;( 3CK 3J PRESET

• Separate Negative-Edge-Triggered Clocks with

Hysteresis ... Typically 200 mV
• Typical Clock Input Frequency ... 50 MHz

• Fully Buffered Outputs

description
These quadruple TTL J-K flip-flops incorporate a
number of third-generation Ie features that can CLEAR lJ lCK 1;( 10 2Q 2;( 2CK 2J GND
simplify system design and r~duce flip-flop package
count by up to 50%. They feature hysteresis at each
clock input, fully buffered outputs, and direct clear
capabil itv, and arc prcscttab!c through a buffer that
also features an input hysteresis loop. The negative- schematics of inputs and outputs
edge-triggering clocks are directly compatible with EQUIVALENT OF EACH INPUT
earlier Series 54/74 single and dual pulse-triggered
Vcc---.---
flip-flops. These circuits can be used to emulate
D- or T-type flip-flops by hard-wiring the inputs, or
to implement asychronous sequential functions.
INPUT
The SN54276 is characterized for operation over the
full military temperature range of -55°C to 125°C;
the SN74726 is characterized for operation from oOe
to 70°C.
Clear, J, K: Req = 4 kU NOM
Clock: Req = 10.2 kU NOM

•
FUNCTION TABLE (EACH FLIP-FLOP)
Preset: Req = 11.6 kU NOM
COMMON INPUTS INPUTS OUTPUT
PRESET CLEAR CLOCK J K Q TYPICAL OF ALL OUTPUTS
L H X X X H -------~---vcc

H L X X X L
L L X X X Ht
H H + L H Qo
H H t H H H
Q
H H + L L L
H H t H L TOGGLE
H H H X X Qo

tThis configuration is nonstable; that is, it may not

persist when preset and clear return to their inactive
(high) level.

See explanation of function tables on page 3·8.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, Vee (see Note 1) ..... 7 V

Input voltage . . . . . . . . . . . . 5.5 V
Operating free-air temperature range: SN54276 _55°C to 125°C
SN74276 oOe to 70°C
Storage temperature range -65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

1076

TEXAS INSTRUMENTS 7-401

INCORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54276, SN74276
QUADRUPLE J-K FLIP-FLOPS

recommended operating conditions

SN54276 SN74276
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, VCC 4.5 5 5.5 4.75 5 5.25 V
High·level output current, 10H -800 -800 J.l.A
Low·level output current, 10L 16 16 mA
Clock frequency 0 35 0 35 MHz
Clock high 13.5 13.5
Pulse width, tw Clock low 15 15 ns
Preset or clear low 12 12
J, K inputs 3. 3./.
Setup time, tsu ns
Clear and preset inactive state 10. 10.
Input hold time, th 10. 10./. ns
Operating free-air temperature, T A -55 125 0 70 °c

./. The arrow indicates that the falling edge of the clock pulse is used for reference.

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONSt MIN TYP:j: MAX UNIT
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
VIK Input clamp voltage VCC - MIN, 11--12mA -1.5 V
VCC = MIN, VIH -2 V,
VOH High-level output voltage 2.4 3.4 V
VIL = 0.8 V, 10H = -8ooJ.l.A
VCC = MIN, VIH =2 V,
VOL Low-level output voltage 0.2 0.4 V
VIL = 0.8 V, IOL=16mA
II Input current at maximum input voltage Vee = MAX, VI = 5.5 V 1 mA
IIH High-level input current Vce = MAX, VI = 2.4 V 40 J.l.A
IlL Low·level input current VCC - MAX, VI - 0.4 V -1.6 mA

•
lOS Short-circuit output current§ Vce = MAX -30 -85 mA
ICC Supply current Vec = MAX 60 81 mA

t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at VCC = 5 V, T A = 25°C.
§Not more than one output should be shorted at a time.

switching characteristics, Vee = 5 V, T A = 25° C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

f max Maximum clock frequency 35 50 MHz

tPLH Propagation delay time, low-to-hi!tl-level output from preset CL=15pF, 15 25 ns
tPHL Propagation delay time, high-to-low-Ievel output from clear RL = 400.11, 18 30 ns
tPLH Propagation delay time, Iow-to-high-Ievel output from clock See Note 2 17 30 ns
tPHL Propagation delay time, high-to-Iow-level output from clock 20 30 ns

NOTE 2: Load circuit and voltage waveforms are shown on page 3-10.

1076

7-402 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TIL TYPES SN54278, SN74278
MSI 4-BIT CASCADABLE PRIORITY REGISTERS
BULLETIN NO. DL-S 7211729, MAY 1972-REVISED DECEMBER 1972

SN54278 ••• J OR W PACKAGE

SN74278 .•. J OR N PACKAGE
• Latched Data Inputs Serve as Buffer Register ___ ~VIEW)
and Can also: INPUTS OUTPUTS
Synchronize Data Acquisition
vcc~ NC~
"Debounce" Mechanical Switch Input
• Cascading Input PO and Output P1
Provides "Busy"Signal Inhibiting All
Lower-Order Bits
• Full TTL Compatibility
• Use for:
Priority Interrupt
Synchronous Priority Line Selection ~~GNO
INPUTS OUTPUTS
description
positive logic: see function table
The SN54278 and SN74278 each consist of four data
latches. full priority output gating, and a cascading NC-No internal connection
gate. The highest-order data applied at a D latch input
is transferred to the appropriate Y output while the FUNCT;CN TABL.E
strobe input is high. and when the strobe goes low all INTERNAL
data is latched. The cascading input PO is fully INPUTS OUTPUTS
LATCH NODES
overriding and on the highest-order package this input PO G 01 02 03 D4 01 02 Q3 04 V1 V2 V3 V4 P1
must be held at a low logic level. The P1 output is L H H X X X L X X X H L L L H
intended for connection to the PO input of the next L H L H X X H L X X L H L L H
lower-order package and will provide a "busy" L H L L H X H H L X L L H L H
(high-level) signal to inhibit all subsequent Iower- L H L L L H H H H L L L L H H
order packages. L H L L L L H H H H L L L L L
Same function of Q
After the overriding PO input, the order of priority is
L L X X X X Latched when nodes as on 1st
D1, D2, D3, and D4, respectively, within the package.
G goes low 5 lines

•
H L X X X X L L L L H
Internal Q levels are same
H H function of 0 inputs as on L L L L H
functional block diagram first 5 lines

H = high level, L = low level, X = irrelevant

INPUT STROBE INPUT INPUT INPUT INPUT

PO G D4 03 02 01

OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT

P1 Y4 V3 Y2 Y1

1272

TEXASINCORPORATED
INSTRUMENTS 7-403
POST OFFICE BOX 5012 • CALLAS, TEXAS 75222
 TYPES SN54278, SN74278
4-81T CASCADABLE PRIORITY REGISTERS

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1) 7V
Input voltage . . . . . . . . 5.5V
Interemitter voltage (see Note 2) 5.5 V
Operating free-air temperature range: SN54278 Circuits -55°C to 125°C
SN74278 Circuits O°C to 70°C
Storage temperature range -65°C to 150°C
NOTES: 1. Voltage values, except interemitter voltage, are with respect to network ground terminal.
2. This is the voltage between two emitters of a multiple·emitter transistor. For this circuit, this rating applies between the strobe
input and any of the four data inputs.

recommended operating conditions

SN54278 SN74278
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High·level output current, 10H -800 -800 ~A

Low·level output current, 10L 16 16 mA

Data setup time, tsu (see Figure 1) 20 20 ns
Data hold time, th (see Figure 1) 5 5 ns
Strobe pulse width, tw (see Figure 1) 20 20 ns
Operating free·air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONSt MIN TYP MAX UNIT
VIH High·level input voltage 2 V
VIL Low-level input voltage 0.8 V
VIK Input clamp voltage Vee= MAX, II = -12 mA -1.5 V
Vee= MIN, VIH = 2 V,
VOH H igh·level output voltage 2.4 3.4 V
VIL = 0.8 V, 10H = -800~A I

•
Vee= MIN, VIH = 2V,
VOL Low-level output voltage 0.2 0.4 V
VIL = 0.8 V, 10L = 16 mA
II Input current at maximum input voltage Vee = MAX, VI = 5.5 V 1 mA
I Any D input 80
IIH High·level input current I PO input Vee= MAX, VI = 2.4 V 200 ~A
! G mout , 320 i

I Any D input -3.2

IlL Low-level input current I PO input Vee= MAX, VI=O.4V -8 mA
I G input -12.8
I SN54278 -18 -55
lOS Short·circuit output current§
Vee = MAX rSN74278 -18 -57
mA

ICC Supply current Vee= MAX, See Note 3 55 80 mA

t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
+AII typical values are at Vee = S V, T A = 2Soe.
§ Not more than one output should be shorted at a time.
NOTE 3: lee is measured with the PO input grounded, all other inputs at 4.S V, and outputs open.

1076

7-404 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54278. SN74278
4-BIT CASCADABLE PRIORITY REGISTERS

switching characteristics, Vee =5 V, TA =25°e

FROM TO TEST
PARAMETER~ WAVEFORMS MIN TYP MAX UNIT
(INPUT) (OUTPUT) CONDITIONS
tPLH AandC 30
Data Y ns
tpHL (with strobe high) 39
tpLH Aand D 38
Data Y ns
tPHL (with strobe highl 31
tpLH A and E 46
Data P1 CL=15pF, ns
tpHL (with strobe highl 39
RL=400n,
tpLH Band C 30
Strobe AnyY See Figure 1 ns
tpHL or Band D 31
t ... LH 38
Strobe P1 Band E ns
tpHL 42
tPLH 23
.'PHL PO P1 F and G
30
ns

~tpLH == propagation delay time, low-to-high-Ievel output

tpHL == propagation delay time, high-to-Iow-Ievel output

schematics of inputs and outputs PARAMETER MEASUREMENT INFORMATION

Vcc
EQUIVALENT OF EACH INPUT

V CC---tl----

1 ' CL =15 P F

C L includes probe and jig capacitance_

INPUT
An diodes are 1 N3064.

LOAD CIRCUIT

Any D: Req = 2_5 kn NOM

PO: Req
G: Req
= 1 kn NOM
= 0_6 kn NOM
~:;~I~~~~ ~I ~.5 V

STROBE INPUT G
(WAVEFORM Bl

~~~~~iERTING
(WAVEFORM C)
:
i I
t

r---tw~

rtprL_H
-

_ - - ; - _ - : - '_ _ I
I I
~lw---tlo4

_-:-_+-'.----..~. ~~l_ _
I

_ _ _ VOH

VOL
•
TYPICAL OF ALL OUTPUTS :tpLH~
~tl»HL
,---- VOH
INVERTING I I I l.5V
OUTPUT
--"--VCC (WAVEFORM DJ ~q>HL~II''---""~-q>-L-"H;--C--./..'-1-- - - - - - - VOL

1 !.-tpLH...-.j I ~tpHL"""
OUTPUTPl
(WAVEFORM E)
[
I4---tPLH~
l'sv i
~tPHL~
~::~
::'~TE~~RMFI~SV ~~~--------
~tPlH-eoj r+-tpHL.....,
OUTPUT OUTPUTP' !,r.,------"""\l.1.S V - VOH
(WAVEFORM GI _ _ _ _ _ /
J
1.5 v ~ VOL

VOLTAGE WAVEFORMS

NOTE: Input pulses are supplied by a generator having the following

characteristics: tr';;; 7 ns, tf';;; 7 ns, PRR .;;; 1 MHz, Zout "" 50 n.
FIGURE l-SWITCHING TIMES

1076
TEXAS I,,"CORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222 7-405
 TTL TYPES SN54LS280, SN54S280, SN74LS280, SN74S280
MSI 9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS
BULLETIN NO. DL-S 7611829, DECEMBER 1972-REVISED OCTOBER 1976

SN54LS280, SN54S280 ..• J OR W PACKAGE

• Generates Either Odd or Even Parity SN74LS280, SN74S280 •.. J OR N PACKAGE
for Nine Data Lines (TOP VIEW)

• Cascadable for n-Bits

• Can Be Used to Upgrade Existing
Systems using MSI Parity Circuits
• Typical Data-to-Output Delay of Only 14 ns
for 'S280 and 33 ns for 'LS280
• Typical Power Dissipation:
'LS280 ... 80 mW
'S280 ... 335 mW

FUNCTION TABLE

~
NC I ~ ~ GNO
NUMBER OF INPUTS A OUTPUTS ;NPUT~
INPUTS
THRU I THAT ARE HIGH k EVEN kODD OUTPUTS
0,2,4,6,8 H L
1,3,5,7,9 L H logic: see function table

H = high level, L = low level NC-No internal connection

description

These universal, monolithic, nine-bit parity generators/checkers utilize Schottky-clamped TTL high-performance
circuitry and feature odd/even outputs to facilitate operation of either odd or even parity application. The word-length
capability is easily expanded by cascading as shown under typical application data.

Series 54LS/74LS and Series 54S/74S parity generators/checkers offer the designer a trade-off between reduced power
consumption and high performance. These devices can be used to upgrade the performance of most systems utilizing

•
the '180 parity generator/checker. Although the 'LS280 and 'S280 are implemented without expander inputs, the
corresponding function is provided by the availability of an input at pin 4 and the absence of any internal connection
at pin 3. This permits the 'LS280 and 'S280 to be substituted for the '180 in existing designs to produce an identical
function even if 'LS280's and 'S280's are mixed with existing '180's.

These devices are fuliy compatible with most other TTL and DTL circuits. A!! 'LS280 and 'S280 inputs are buffered to
lower the drive requirements to one Series 54LS/74LS or Series 54S/74S standard load, respectively.

schematics of inputs and outputs

- -
'LS280 'S280

EQUIVALENT OF INPUTS TYPICAL OF OUTPUTS EQUIVALENT OF INPUTS TYPICAL OF OUTPUTS

---~-Vcc
vcc ~~~VCC

o o
VCC
20 kn NOM 2.8 kn NOM
INPUT __
OUTPUT
INPUT --
u~OUTPUT

1lIJ
1076

7-406 TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54LS280, SN74LS280
9-BIT ODD/EVENi PARITY GENERATORS/CHECKERS

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage (see Note 1) 7V

Input voltage 7V
Operating free-air temperature range: SN54 LS280 -55°C to 125°C
SN74LS280 oOe to 70°C
Storage temperature range -65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54lS280 SN74lS280
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 b b.5 4.15 5 5.25 V
High-level output current, 10H -0.4 .4 mA
low-level output current, 10L 4 8 mA
----

Operating free-air temperature, T A -55 125 0 70 °c

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54lS280 SN74lS280
UNIT
PARAMETER TEST CONDITIONSt MIN TYP+ MAX MIN TYP+ MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
VIK Input clamp voltage Vee = MIN, II =-18mA -1.5 -1.5 V
Vee - MIN, VIH = 2 V,
VOH High-level output voltage 2.5 3.4 2.7 3.4 V
VIL=MAX, 10H = -0.4 mA
Vee - MIN, VIH = 2 V, 0.25 0.4 0.25 0.4
VOL Low-level output voltage V

II
IIH
Input current at maximum input voltage
High-level input current
VIL = MAX
Vee = MAX,
Vee = MAX,
VI =7V
VI = 2.7 V
0.1
20
0.35 0.5
0.1
20
mA
/lA
II
IlL Low-level input current Vee = MAX, VI = 0.4 V -0.4 -0.4 mA
lOS Short-circuit output current§ Vee - MAX -20 -100 -20 -100 mA
lee Supply current Vee = MAX, See Note 2 16 27 16 27 mA

t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at V CC = 5 V, T A = 25° C.
§ Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second.
NOTE 2: ICC is measured with all inputs grounded and all outputs open.

switching characteristics, Vee = 5 V, TA = 25° C

FROM TO
PARAMETER~ TEST CONDITIONS MIN TYP MAX UNIT
(INPUT) (OUTPUT)
tPLH 33 50
Data LEven ns
tpHL eL=15pF,RL=2kn, 29 45
tPLH See Note 3 23 35
Data L Odd ns
tPHL 31 50

~tPLH == propagation delay time, low-to-high-Ievel output; tpHL == propagation delay time, high-to-Iow-Ievel output
NOTE 3: Load circuit and VOltage waveforms are shown on page 3-11.

1076

TEXAS INCORPORATED
INSTRUMENTS 7-407
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54S280, SN14S280
9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage (see Note 1) 7V

Input voltage 5.5 V
Operating free-air temperature range: SN54S280 -55°C to 125°C
SN74S280 oOe to 70°C
Storage temperature range -65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54S280 SN74S280
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -1 -1 mA
Low-level output current, 10L 20 20 mA
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONSt MIN TYPt MAX UNIT
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
VIK Input clamp voltage Vee= MIN, II = -18mA -1.2 V
Vee = MIN, VIH=2V, TSN54S' 2.5 3.4
VOH High-level output voltage V
VIL = 0.8 V, 10H = -1 mA I SN74S' 2.7 3.4
Vee = MIN, VIH=2V,
VOL Low-level output voltage 0.5 V
VIL = 0.8 V, 10L = 20mA
II Input current at maximum input voltage Vee= MAX, VI = 5.5V 1 mA

I IIH High-level input current Vee = MAX, VI=2.7V 50 JlA

IlL Low-level input current Vee = MAX, VI=0.5V -2 mA
lOS Short-circuit output current§ Vee= MAX -40 -100 mA
SN54S280 67 99
Vee = MAX, See Note 2 mA
SN74S280 67 105
ICC Supply current
Vee = MAX, TA=125°C,
SN54S280N 94 mA
See Note 2

t F or conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
~AII typical values are at Vee = 5 V. T A = 25°C.
§ Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second.
NOTE 2: ICC is measured with all inputs grounded and all outputs open.

switching characteristics, Vee = 5 V, TA = 25° C

FROM TO
PARAMETER~ TEST CONDITIONS MIN TYP MAX UNIT
(INPUT) (OUTPUT)
tPLH 14 21
Data ~ Even ns
tpHL eL=15pF, RL = 180n, 11.5 18
tpLH See Note 4 14 21
Data ~ Odd ns
tpHL 11.5 18

~ tpLH "" propagation delay time, low-to-high-Ievel output; tpH L '" propagation delay time, high-to-Iow-Ievel output
NOTE 4: Load circuit and voltage waveforms are shown on page 3-10.

1076

7-408 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54LS280. SN54S280. SN74LS280. SN74S280
9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS

functional block diagram

TYPICAL APPLICATION DATA

2S-LINE PARITY/GENERATOR CHECKER 81-LINE PARITY/GENERATOR CHECKER

I
Three 'LS280's or 'S280's can be Longer word lengths can be imple-
used to implement a 25-line parity mented by cascading 'LS280's or
generator/checker. This arrangement 'S280's. As shown here, parity can be
will provide parity in typically 75 or generated for word lengths up to 81
A A
B 25 nanoseconds respectively. bits in typically 75 or 25 nano-
C ~ :!:
EVEN seconds respectively.
EVEN o
E E
F F
G G
'LS280/ H 'LS280/
'S280 'S280

A A A
B B :!: I-----"'--IB
EVEN
C ~ H = EVEN C :!: H = EVEN
o EVEN l=ODO o .....----10 EVEN l=OOD
E E
F l: H =000 F l: H = EVEN
GOOD l = EVEN GOOD l=OOO
H 'LS280/ H 'LS280/ H 'LS280/
'S280 '8280 'S280

A A

C ~ C l:
0 EVEN As an alternative, the outputs of two o EVEN
or three parity generators/checkers E
F
can be decoded with a 2-input ('S86 F ~
G G TO OTHER
'LS280/ 'LS86) or 3-input ('S135) H 'LS280/ 'LS280/
'S280 'S280 'S280
exclusive-OR gate for 18- or 27-line
parity applications.

1076
TEXAS INCORPORATED
INSTRUMENTS 7-409
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TTL TYPES SN54S281, SN74S281
LSI 4-BIT PARALLEL BINARY ACCUMULATORS
BULLETIN NO. DL-S 7612065, FEBRUARY 1974 - REVISED OCTOBER 1976

• Full 4-Bit Binary Accumulator in

a Single Package
SN54S281 ... J OR W PACKAGE
• 15 Arithmetic/Logic-Type Operations: SN74S281 ... J OR N PACKAGE
Add (TOP VIEW)
Subtract (B-A or A-B)
Complement
Increment
Transfer
Plus 10 Other Functions
• Full Shifting Capabilities:
Logic Shift (Left or Right)
Arithmetic Shift (Left or Right)
for Sign Bit Protection
Hold
Parallel Load
• Expandable to Handle n-Bit Words
with Full Carry Look-Ahead logic: see description and function tables

• Logic Mode Operation Provides Seven

Boolean Functions of the Two Variables

description

These Schottky-clamped four-bit accumulators integrate high-performance versions of an arithmetic logic unitlfunction
generator and a shift/storage matrix on a single monolithic circuit bar. The arithmetic logic unit (ALU) portion, similar
to the SN54S181/SN74S181 circuit, incorporates the capability to perform 16 arithmetic/logic·type operations as
detailed in Table 1. The accumulator includes an exchange of subtract operands by which either A-8 or 8-A can be
accomplished directly. The ALU is controlled by three function-select inputs (ASO, AS1, AS2) and a mode-control
input (M). When the mode-control input is hi9h, the ALU is placed in a logic mode that performs any of seven logic
functions on two binary variables as detailed in Table 2. Full carry look-ahead is provided for fast, simultaneous carry
I generation for the full four binary bits. The carry input (C n ) and propagate and generate outputs (p, G) are
implemented for direct use with the SN54S182/SN74S182 look-ahead carry generators. This permits systems to be
Implemented with the added advantage of full look-ahead across any word length to minimize the accumulator delay
times. Once data is loaded ir!to the accumulator, the typical add time with full look-ahead is 29 nanoseconds for 16-bit
words.

The shift/storage matrix is analogous in its capabilities to the SN54S194/SN74S194 universal bidirectional shift register
with the added advantages of multiplexed input/output (I/O) cascading lines that comprehend arithmetic shift
functions having a sign bit, such as 2's complements. The matrix can be used to perform either logic or arithmetic shifts
in either direction (left or right), parallel load, or hold. Control of the register is accomplished with three inputs:
register control (RC) and register selection (RSO, RS1). The cascading input/output lines incorporate three-state
outputs multiplexed with an input. The least-significant cascading bit is combined with the AO, FO circuitry to provide
the shift-right input and the shift-left output (RI/LO)' and the most significant bit is coupled with the A3, F3 circuitry
to provide the shift-left input and the shift-right output (L1/RO).

Series 54S circuits are characterized for operation over the full mil itary temperature range of _55° C to 125° C; Series
74S circuits are characterized for operation from O°C to 70°C.

1076

7-410 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOx 5012 • DALLAS. TEXAS 75222
 TYPES SN54S281, SN74S281
4-BIT PARALLEL BINARY ACCUMULATORS

FUNCTION TABLES

TABLE 1-ARITHMETIC FUNCTIONS TABLE 2-LOGIC FUNCTIONS

Mode Control (M) = Low Mode Control (M) = High
Carry Input (C n ) = X (Irrelevant!
ALU ACTIVE-HIGH DATA
SELECTION Cn=H Cn = L ALU
ACTIVE-HIGH
AS2 AS1 ASO (with carry) (no carry) SELECTION
DATA FUNCTION
L L L FO = L. F1 = F2 = F3 = H Fn = H AS2 AS1 ASO
L L H F = B MINUS A F = B MINUS A MINUS 1 L L L Fn = L
L H L F =A MINUS B F = A MINUS B MINUS 1 L X H Fn=An 0 Bn
L H H F = A PLUS B PLUS 1 F = A PLUS B L H L Fn = An 0 Bn
H L L F = B PLUS 1 Fn = Bn H L L Fn = AnBn
- -
H L H F = B PLUS 1 Fn = Bn H L H Fn=An+Bn
H H L F = A PLUS 1 Fn = An H H L Fn = AnBn
-
H H H F= A PLUS 1 I F n =A H H H F =A +B

TABLE 3 - SHIFT-MODE FUNCTIONS

Cn = M = ASO = AS1 = L, and AS2 =' H (F n ~ Sn)

INPUTS BEFORE t OUTPUTS AFTER t

SHIFT-MATRIX
REGISTER INPUT! INPUT! INPUT/ INPUT/
REGISTER SHIFT-MATRIX CLOCK OUTPUTS
FUNCTION CONTROL OUTPUT OUTPUT OUTPUT OUTPUT
SELECTION INPUTS INPUT (ALU B INPUTS)
INPUT RI/LO LI/RO RI/LO LI/RO
RSO RS1 FO F1 F2 F3 °A °B °c °D
LOAD L L X Z to f1 f2 f3 Z t Z to f1 f2 f3 Z
LSL L H L QA QA QB QC QD Ii t QBn QBn QCn QDn Ii Ii
LSA I L H I H QA QA QB QC QD Ii t QBn QS n QCn Ii QDO Ii
RSL H L L ri QA QB QC QD QD t ri ri QAn QBn QCn QCn
RSA H L Ii H ri QA QB QC QD QC t
I ri ri QAn QBn QDO QBn

•
H H X X QA QB QC QD X t Z QAO QBO QCO QDO Z
HOLD
X X X X QA QB QC QD X L RilLa QAO QBO QCO QDO LltRO

H = high level (steady state)

L = low level (steady state)
X = irrelevant (any input, including transitions)
Z = high impedance (output off)
t = transition from low to high level
fO, f1, f2, f3, ri, Ii = the level of steady-state conditions at FO, F 1. F2. F3. R liLa. or U/RO respectively
QAO, QBO. QCO, QDO = the level of QA, QB, QC. or QD, respectively, before the indicated steady-state input conditions were established
QAn. QBn' QCn' QDn = the level of QA. QB, QC, or QD. respectively, before the most recent transition of the clock
See explanation of function tables on page 3-8.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage. Vee (see Note 1) .......... . 7V

Input voltage . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range: SN54S281 (see Note 2) -55°C to 125°C
SN74S281 oOe to 70°C
Storage temperature range -65°C to 150°C

NOTES: 1. Voltage values are with respect to network ground terminal.

2. An SN54S281 in the W package operating at free-air temperatures above 110°C requires a heat sink that provides thermal
o
resistance from case to free-air, ROCA. of nOt more than 20 C/W.

1076

TEXAS INCORPORATED
INSTRUMENTS 7-411
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54S281, SN74S281
4-BIT PARALLEL BINARY ACCUMULATORS

recommended operating conditions

SN54S281 SN74S281
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee I 4.5 5 5.S 4.75 5 5.25 V
Any output except Ll/RO and RI/LO -1 -1
High-level output current, 10H mA
Ll/RO and RI/LO -2 -2
Any output except Ll/RO and RI/LO 20 20
Low-level output current, 10L mA
Ll/RO and RI/LO 10 10
elock frequency, fclock (for shifting) 0 50 0 50 MHz
Width of clock pulse, tw(clock) 8 8 ns
Data setup time with respect to clock, tsu ot ot ns
Data hold time with respect to clock, th 18t 18t ns
Operating free-air temperature, T A (see Note 2) -55 125 0 70 °e
tThe arrow indicates that the rising edge of the clock pulse is used for reference.
NOTE 2: An SN54S281 in the W package operating at free-air temperatures above 110°C requires a heat sink that provides thermal resistance
from case to free-air, ReCA, of not more than 20°C/W.

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SNS4S281 SN74S281
PARAMETER TEST CONDITIONSt UNIT
MIN TYP:j: MAX MIN TYP:j: MAX
VIH High-level input voltage 2 2 ! V
VIL Low-level input voltage 0.8 0.8 V
Any input except
VIK Input clamp voltage Vee = MIN, II = -18mA -1.2 -1.2 V
Ll/RO and RI/LO
Any output except
High-level Vee = MIN, VIH=2V, 2.5 3.4 2.7 3.4
VOH L1/RO and RI/LO V
output voltage VIL = 0.8 V, 10H = MAX 2.4 3.4 2.4 3.4
Ll/RO, RI/LO
Vee = MIN, VIH = 2V,
VOL Low-level output voltage 0.5 0.5 V
VIL = 0.8 V, 10L = MAX

•
II Input current at maximum input voltage Vee = MAX, VI = S.5 V 1 1 mA
RSO, RS1 SO 50
M, elock 150 i 150
High-level Vee = MAX, VI = 2.7 V,
IIH LI/RO, RI/LO 200 200 IlA
input current See Note 3
AS2 300 300
All others I 250 250
RSO, RS1, Ll/RO -2 -2
RI/LO -3 -3
Low-level Vee = MAX, VI =0.5V
IlL M, elock -4 -4 mA
input current See Note 3
ASO,AS1 -6 -6
All others -8 -8
lOS Short-circuit output current§ Vee = MAX -40 -110 -40 -110 mA
Vee = MAX'l W package
190
lee Supply current TA = 12Soe only mA
Vee = MAX I All packages 144 230 144 230
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at V CC = 5 V, T A = 25° C.
§ Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
NOTE 3. When testing input current at the R lILa or Ll/RO terminals, the output under test must be in the high-impedance (off) state.

1076

7-412 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • CALLAS, TEXAS 75222
 TYPES SN54S281, SN74S281
4-BI1 PARALLEL BINARY ACCUMULATORS

switching characteristics, Vee =5 V, TA = 25°e

FROM TO
PARAMETER~ TEST CONDITIONS MIN TYP MAX UNIT
(INPUT) (OUTPUT)
tPLH 10 20
Cn C n+4 ns
tpHL 10 20
tpLH 18 30
Any A Cn+4 ns
tpHL 18 30
tpLH 10 20
Cn Any F ns
tpHL 10 20
tPLH
Any A
- 14 24
G ns
tpHL 14 24
tPLH 12 20
Any A P ns
tpHL 12 20
tpLH 20 35
Ai Fi ns
tD
,H~
I 20 35
CL=15pF, 30 45
AO RI/LO ns
I/O outputs: RL = 560 fl,
Other outputs: HL = 280 n,
30
30
45
45
I I
A3 LI/RO
See Figure 1 30 45 I ns
I
tpLH 7 11
FO RI/LO ns
tpHL 7 11
tPLH 7 11
F3 LI/RO ns
tpHL 7 11
tpLH Any F or 28 45
Any AS ns
tpHL C n+4 28 45
tpLH 20 33
Any AS PorG ns
tpHL 20 33
tpLH I 30 45 I I
Ciock Any F ns
tpHL I I 30 45 I I
tpLH RI/LOor 35 55
Clock ns
tpHL LI/RO 35 55 I
~ tpLH
tpHL
== Propagation delay time, low-to-high-Ievel
== Propagation delay time, high-to-Iow-Ievel
output
output II
PARAMETER MEASUREMENT INFORMATION

INPUT ~~.;V-- -3V

Jl"~v ~OV
l-tPLH..... I-tPHL--t
IN.PHAS~I
I : -:--VOH
OUTPUT ~ 1.5 V I 1.5 V
I VOL
I I
r-tPHL -I t-tPLH-oi

~
: iVOH
OUT·OF·PHASE 1.5 V 1.5 V
OUTPUT
- - -VOL
LOAD CIRCUIT
VOLTAGE WAVEFORMS

NOTES: A. Input pulse is supplied by a generator having the following characteristics: t r " 2.5 ns, tf" 2.5 ns, PRR " 1 MHz, Zout "" 50 fl.
B. C L inlcudes probe and jig capacitance.
C. All diodes are 1 N916 or 1 N3064.
FIGURE 1

1076

TEXAS INCORPORATED
INSTRUMENTS 7-413
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54S281, SN74S281
4-BIT PARALLEL BINARY ACCUMULATORS
TYPICAL APPLICATION OAT A

RIGHT LEFT
RI/LO LI/RO RI/LO LI/RO RI/LO LI/RO RI/LO Ll/RO
DATA IN DATA IN
CARRY Cn Cn+4 Cn Cn +4 CARRY
Cn Cn+4
INPUT OUTPUT
'S281 'S281 'S281 'S281

ENTER AND STORE TIME: 38 ns typical

EACH SUCCESSIVE ADDITION TO STORED DATA: 44 ns typical

FIGURE A-16-BIT BINARY ACCUMULATOR USING FOUR SN54S281/SN74S281 CIRCUITS

IN RIPPLE-CARRY MODE

RIGHT LEFT
RI/LO Ll/RO RI/LO Ll/RO RI/LO LI/RO RI/LO Ll/RO DATA IN
DATA IN
CARRY Cn 'S281 Cn 'S281 Cn 'S281 Cn+4 CARRY
INPUT OUT
G P G P

C n+ x

'S182

ENTER AND STORE TIME: 37 ns typical

EACH SUCCESSIVE ADDITION TO STORED DATA: 29 ns typical

FIGURE B-16-BIT BINARY ACCUMULATOR USING FOUR SN54S281/SN74S281 CIRCUITS

AND ONE SN54S182/SN74S182 IN FULL LOOK-AHEAD CARRY MODE

I RIGHT
DATA IN
CARRY
RI/LO
4
LI/RO RI/LO 4
LI/RO RI/LO
4
Ll/RO ·RI/LO
4
Ll/RO
LEFT
DATA IN
CARRY
INPUT OUT

G P G P G P G P

GO PO Cn+ x G1 P1 Cn+y G2 P2 Cn+ z G3 P3

Cn
'S182

ENTER AND STORE TIME: 42 ns typical

EACH SUCCESSIVE ADDITION TO STORED DATA: 34 ns typical

FIGURE C-64-BIT BINARY ACCUMULATOR USING 16 SN54S281/SN74S281 CIRCUITS AND

FIVE SN54S182/SN74S182 CIRCUITS FOR FULL CARRY LOOK-AHEAD

A inputs and F outputs of 'S281 are not shown.

1076

7-414
 TYPES SN54283, SN54LS283, SN54S283,
TTL
SN74283, SN74LS283, SN74S283
MSI 4-BIT BINARY FULL ADDERS WITH FAST CARRY
BULLETIN NO. DL-S 7611832, OCTOBER 1976

SN54283, SN54LS283 ... J OR W PACKAGE

• Full-Carry Look-Ahead Across the Four
SN54S283 ..• J PACKAGE
Bits SN74283, SN74LS283, SN74S283 .•• J OR N PACKAGE
• Systems Achieve Partial Look-Ahead (TOP VIEW)
Performance with the Economy of Ripple
Carry vcc B3 A3 ~3 A4 C4

• Supply Voltage and Ground on Corner

Pins to Simplify P-C Board Layout

TYPICAL ADD TIMES

~2 C4
TWO TWO TYPICAL POWER
8-BIT 16-BIT DISSIPATION
TYPE WORDS WORDS PER ADDER

'283 23ns 43ns 310 mW

'LS283 25ns 45ns 95 mW
'S283 15ns 30ns 510 mW
positive logic: S€'e' function table

description

The '283 and 'LS283 adders are electrically and

functionally identical to the '83A and 'LS283,
respectively; only the arrangement of the terminals FUNCTION TABLE

has been changed. The 'S283 high performance

versions are also functionally identical.

These improved full adders perform the addition of

two 4-bit binary words. The sum (L) outputs are
provided for each bit and the resultant carry (e4) is H
obtained from the fourth bit. These adders feature H H H
full internal look-ahead across all four bits generating
the carry term in ten nanoseconds, typically, for the
'283 and 'LS283, and 7.5 nanoseconds for the 'S283.
H
L
H
H
H
H
H
H
H
H
H
H
H
I
H
This capability provides the system designer with H H H H H
partial look-ahead performance at the economy and H H H H H H
reduced package count of ripple-carry L L L H H H L
H H H H L H
implementation.
H H H H
H H H H H H
The adder logic, including the carry, is implemented H H H H H
in its true form. End around carry can be accomplish- H H H H H
H H H H H
ed without the need for logic or level inversion.
H H H H H H H
H = high level, L = low level
Series 54, Series 54LS, and Series 54S circuits are NOTE: Input conditions at A 1, B1, A2, B2, and CO are used to
characterized for operation over the full temperature determine outputs ~1 and ~2 and the value of the internal
range of -55°C to 125°C. Series 74, Series 74LS, and carry C2. The values at C2, A3, B3, A4, and B4 are then
used to determine outputs 2:3, 2:4, and C4.
Series 74S circuits are characterized for oOe to 70°C
operation.

1076

TEXAS INCORPORATED
INSTRUMENTS 7415
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54283, SN54LS283, SN54S283,
SN74283, SN74LS283, SN74S283
4-BIT BINARY FULL ADDERS WITH FAST CARRY
functional block diagram and schematics of inputs and outputs
'283
EQUIVALENT OF TYPICAL OF ALL
EACH INPUT OUTPUTS

vce3--
INPUT
Req

--
----..--Vee

OUTPUT

CO input: Req = 4 kn NOM e4 output: R = 100 n NOM

Any A or B: Req = 3.5 kn NOM Any E: R = 120 n NOM

'LS283
EQUIVALENT OF TYPICAL OF ALL OUTPUTS
EACH INPUT

Vee--..._-- -----+--Vee
Req
INPUT-+.... ~ __

OUTPUT

CO input: Req = 17 kn NOM

Any A or B: Req = 8.5 kn NOM

--a
'8283

EQUIVALENT OF TYPICAL OF ALL OUTPUTS

I EACH INPUT

Vee

INPUT

w- _ T
~2.8knN-OM --
on NOM

~OUTPUT
Vee

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) 7V
Input voltage: '283, 'S283 5.5V
'LS283 . . . . 7V
Interemitter voltage (see Note 2) 5.5V
Operating free-air temperature range: SN54283, SN54LS283, SN54S283 . . -55°C to 125°C
SN74283, SN74LS283, SN74S283 . oOe to 70°C
Storage temperature range . -65°eto 150°C
NOTES: 1. Voltage values, except interemitter voltage,. are with respect to network ground terminal.
2. This is the voltage between two emitters of a multiple-emitter transistor. This rating applies for the '283 and 'S283 only between
the following pairs: A 1 and B1, A2 and 82, A3 and 83, A4 and B4.

1076

7-416 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54283, SN74283
4-BIT BINARY FULL ADDERS WITH FAST CARRY

recommended operating conditions

SN54283 SN74283
UNIT
MIN NOM MAX MIN NOM MAX
Supply Voltage, VCC 4.5 5 5.5 4.75 5 5.25 V
Any output except C4 -800 -800
High·level output current, 10H /J. A
Output C4 --400 -400
Any output except C4 16 16
Low-level output current, 10L rnA
Output C4 8 8
Operating free-air temperature, T A -55 125 0 70 °c

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54283 SN74283
PARAMETER TEST CONDITIONst
MIN TYP:j: MAX MIN TYp:j: MAX UNIT
ViH High-Ieve! input voltage 2 V
VIL Low-level input voltage 0.8 0.8 V
VIK Input clamp voltage VCC = MIN, II = -12 mA -1.5 -1.5 V

, VOH High-level output voltage

-.. -'-'ptcc"= MIN~~ H-------2-V-,--l-'-2-.-4--3-.6-----+-'-2.-4--3-.6----+--V----1

VIL = 0.8 V, IOH = MAX

VCC= MIN, VIH=2V,
VOL Low-level output voltage 0.2 0.4 0.2 0.4 V
VIL = 0.8 V, 10L = MAX
Input current at maximum
II VCC = MAX, VI = 5.5 V 1 1 mA
input voltage
IIH High-level input current VCC = MAX, VI = 2.4 V 40 40 /J.A
IlL Low-level input current VCC= MAX, VI = 0.4 V -1.6 -1.6 mA
Short-circuit I Any output except C4 -20 -55 -18 -55
mA
lOS VCC = MAX
output current § I Output C4 -20 -70 -18 -70
I All B low, other
56 56
VCC = MAX, inputs at 4.5 V
I ICC mA

•
Supply current
Outputs open All inputs at
4.5 V
66 99 66 110
I
t For conditions shown as MIN or MAX, use the :::ppropriate value specified under recommended operating conditions.
tAli typical values are at Vee = 5. V, T A = 25°C.
§Only one output should be shorted at a time.

switching characteristics, Vee = 5 V, T A = 25°e

PARAMETER~ FROM (INPUT) TO (OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT

tPLH 14 21
CO Any:E ns
tpHL CL=15pF, RL = 400 n, 12 21

tpLH See Note 3 16 24

AiorBi :Ei ns
tpHL 16 24

tpLH 9 14
CO C4 ns
tpHL CL=15pF, RL = 780 n, 11 16
tpLH See Note 3 9 14
Ai orBi C4 ns
tpHL 11 16

~ tp LH == Propagation delay time, low·to·high·level output

tpH L == Propagation delay time, high·to·low·level output
NOTE 3: Load circuit and voltage waveforms are shown on page 3-10.

1076

TEXAS INCORPORATED
INSTRUMENTS 7-417
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54LS283, SN74LS283
4-BIT BINARY FULL ADDERS WITH FAST CARRY

recommended operating conditions

SN54LS283 SN74LS283
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -400 -400 IJ.A
Low-level output current, 10l 4 S mA
Operating free-air temperature, T A -55 125 0 70 De

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54lS283 SN74LS283
PARAMETER TEST CONDITIONSt UNIT
MIN TYP+ MAX MIN TYP+ MAX
VIH High-level input voltage 2 2 V
Vil low-level input voltage 0.7 O.S V
VIK Input clamp voltage Vee= MIN, II = -1SmA -1.5 -1.5 V
Vee= MIN, VIH = 2V, Vil = Vil max,
VOH High-level output voltage 2.5 3.4 I 2.7 3.4 V
10H =-400IJ.A
Vee= MIN, VIH = 2V, 10l = 4mA 0.25 0.4 0.25 0.4
Val low-level output voltage V
Vil = Vil max 10l - SmA 0.35 0.5
I nput current
Any A or B 0.2 0.2
II at maximum Vee= MAX, VI = 7V mA
input voltage eo 0.1 0.1

High-level Any A or B 40 40
IIH Vee= MAX, VI = 2.7 V IJ.A
input current eo 20 20
low-level Any A or B -O.S -O.S
III Vee= MAX, VI = 0.4 V mA
input current eo -0.4 -0.4
lOS Short-circuit output current§ Vee= MAX -20 -100 -20 -100 mA
All inputs
22 39 22 39
grounded
Vee= MAX, All B low, other
lee Supply current 19 34 19 34 mA
Outputs open inputs at 4.5 V
All inputs at
19 34 19 34

I 4.5V

t For conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions.
D
!AII typical values are at V CC =5 V, T A = 25 C.
§Oniy One output shouid be shorted at a tin,.:! and duration of the short-circuit should not exceed ona second.

switching characteristics, Vee = 5 V, TA = 25°e

PARAMETER. FROM (INPUT) TO (OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT
tPlH 16 24
eo Any ~ ns
tpHl 15 24
tplH 15 24
Aior Bj ~j ns
tpHl el = 15pF, Rl=2kn, 15 24
tPlH See Note 4 11 17
eo C4 ns
tPHl 11 22
tPlH 11 17
Ai or Bj C4 ns
tPHl 12 17

.tPLH == Propagation delay time, low·to·high·level output

tPHL == Propagation delay time, high-to-Iow·level output
NOTE 4: Load circuit and voltage waveforms are shown on page 3-11.

1076

7-418 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • OALLAS. TEXAS 75222
 TYPES SN54S283, SN74S283
4-BIT BINARY FULL ADDERS WITH FAST CARRY

recommended operating conditions

SN54S283 SN74S283
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
Any output except C4 -1 -1 mA
High-level output current, IOH
Output e4 -500 -500 /LA
Any output except e4 20 20
Low-level output current, IOL mA
Output C4 10 0
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONSt MIN TYpf MAX UNIT

VIH High-level input voltage 2 V
V;L L~~!-~e'!e! !!"!p!.!t vc~t~e no \I

VIK I nput clamp voltage Vee = MIN, II =-18mA -1.2 V

ISN54S283 VCC= MIN, VIH = 2 V, 2.5 3.4
VOH High-level output voltage V
ISN74S283 VIL = 0.8 V, IOH = MAX 2.7 3.4
VCC = MIN, VIH = 2V,
VOL Low-level output voltage 0.5 V
VIL = 0.8 V, IOL = MAX
Input current at maximum
II Vee = MAX, VI = 5.5 V 1 mA
input voltage
IIH High-level input current Vce = MAX, VI = 2.7 V 50 /LA
IlL Low-level input current VCC - MAX, VI- 0.5 V -2 mA
Short-circuit I Any output except C4 -40 -100 I
I !OS Vee = ~.,1AX rnA
output current§ I Output C4 -20 -100 I
All B low, other

•
SO
lec Supply current
VCC = MAX,
Outputs open
inputs at 4.5 V
All inputs at
mA I
4.5 V 95 160
I
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device
type.
tAli typical values are at VCC =5 V, T A = 25°C.
§ Only one output should be shorted at a time, and duration of the short-circuit should not exceed one second.

switching characteristics, Vee = 5 V, T A = 25°e

PARAMETER~ FROM (INPUT) TO (OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT
tPLH 11 18
CO Any ~ ns
tpHL CL = 15 pF, RL = 280 fl, 12 18
tpLH See Note 3 12 18
Ai or Bi ~i ns
tpHL 11.5 18
tPLH 6 11
CO C4 ns
tpHL CL=15pF, RL = 560 fl, 7.5 11
tpLH See Note 3 7.5 12
Ai or Bi C4 ns
tpHL 8.5 12
~ tp LH = Propagation delay time, low-to-h igh-Ievel output
tpHL = Propagation delay time, high-to-Iow-Ievel output
NOTE 3: Load circuit and voltage waveforms are shown on page 3-10.

1076

TEXAS INSTRUMENTS 7-419

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 nL TYPES SN54284, SN54285, SN74284, SN74285
LSI 4-BI1 -BY-4-BIT PARALLEL BINARY MULTIPLIERS
BULLETIN NO. DL-S 7211741, MAY 1972-REVISED DECEMBER 1972

SN54284 .•• J OR W PACKAGE

• Fast Multiplication of Two Binary Numbers SN74284 .•• J OR N PACKAGE
8-Bit Product in 40 ns Typical (TOP VIEW)

• Expandable for N-Bit-by-n-Bit Applications: OUTPUTS

16-Bit Product in 70 ns Typical ,....----"\..._---.
32-Bit Product in 103 ns Typical
• Fully Compatible with Most OTL and
TTL Circuits

• Diode-Clamped Inputs Simplify System

Design

description

These high-speed TTL circuits are designed to be used

in high-performance parallel mUltiplication applica- ~~GND
tions. When connected as shown in Figure A, these
WORD INPUTS WORD INPUTS
circuits perform the positive-logic multiplication of
two 4-bit binary words. The eight-bit binary product
positive logic: see description
is generated with typically only 40 nanoseconds
delay.
SN54285 ..• J OR W PACKAGE
This basic four-by-four multiplier can be utilized as a SN74285 •.. J OR N PACKAGE
fundamental building block for implementing larger rrQPVIEW)
multipliers. For example, the four-by-four building
WORD ENABLE OUTPUTS
blocks can be connected as shown in Figure B to
generate submultiple partial products. These results IN:~T 'GA"GB'~
can then be summed in a Wallace tree, and, as
illustrated, will produce a 16-bit product for the two
eight-bit words typically in 70 nanoseconds.
SN54H 183/SN74H 183 carry-save adders and
II SN54S181/SN74S181 arithmetic logic units with the
SN54S182/SN74S182 look-ahead generator are used
to achieve this high performance. The scheme is
expandable for implementing N X M bit multipliers.

schematics of inputs and o,..u_t;...pu_t_s_ _ _ _ _ __

EQUIVALENT OF TYPICAL OF ~~GND
EACH INPUT ALL OUTPUTS WORD INPUTS WORD INPUTS

positive logic: see description

V C C63
k!1- -
NOM

INPUT --

The SN54284 and SN54285 are characterized for

operation over the full military temperature range of
-55°C to 125°C; the SN74284 and SN74285 are
characterized for operation from aOc to 70°C.

1076

7·420 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DAL.LAS, TEXAS 75222
 TYPES SN54284, SN54285, SN14284, SN14285
4-8IT-8Y-4-8IT PARALLEL 81NARY MULTIPLIERS

'"
N
g
'l-. 0-

III
~N
II
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C!J
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1076

TEXAS INSTRUMENTS 7-421

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54284. SN54285. SN74284. SN74285
4-BIT -BY-4-BIT PARALLEL BINARY MULTIPLIERS

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1) ...... . 7V
Input voltage . . . . . . . . . . . . . . . 5.5V
Operating free·air temperature range: SN54' Circuits -55°C to 125°C
SN74' Circuits O°C to 70°C
Storage temperature range -65°C to 150°C
NOTE1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54284 SN74284
SN54285 SN74285 UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output voltage, VOH 5.5 5.5 V
Low-level output current, IOL 16 16 mA
Operating free·air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONSt MIN TYP:j: MAX UNIT
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
VI Input clamp voltage Vee- MIN, 11- -12mA -1.5 V
Vee= MIN, VIH = 2V,
IOH High-level output current 40 /J A
VIL = 0.8 V, VOH = 5.5V
Vee = MIN,
IOL = 12mA 0.4
VOL Low-level output voltage VIH = 2 V, V
IOL = 16mA 0.45
VIL =0.8V

•
II Input current at maximum input voltage Vee = MAX, VI = 5.5 V 1 mA
IIH High-level input current Vee - MAX, VI = 2.4 V 40 /JA
IlL Low-level input current Vee - MAX, VI- 0.4 V -1 mA
Vee - MAX,
SN54284, SN54285
TA = 125°e, 99
N package only

I'cc
Supply current i See Note 2
Vee = MAX, SN54284, SN54285
i
92 110
'rnA I
See Note 2 SN74284, SN74285 92 130

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device
type.
:j:AII typical values are at V CC = 5 V, T A = 25° C.
NOTE 2: With outputs open and both enable inputs grounded, ICC is measured first by selecting an output product which contains three or
more high-level bits, then by selecting an output product which contains four low-level bits.

switching characteristics, Vee = 5 V, TA = 25°e

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tpLH Propagation delay time, low-to-high-Ievel output from enable eL = 30 pF to GND, 20 30
ns
tpH L Propagation delay time, high-to-Iow-Ievel output from enable RL1 = 300 n to Vee, 20 30
tPLH Propagation delay time, low-to-high-Ievel output from word inputs RL2 = 600 n to GND, 40 60
ns
tPH L Propagation delay time, high-to-Iow-Ievel output from word inputs See Note 3 40 60

NOTE 3: Load circuit is as described above; waveforms are shown on page 3-10.

1076

7-422 TEXAS INSTRUM ENTS

1 .... ( OIU'OH!\11 J)

POST OFFICE BOX 5012 • DALLAS. TEXAS 75222

 TTL TYPES SN54290. SN54293. SN54LS290. SN54LS293
SN74290. SN74293. SN74LS290. SN74LS293
MSI DECADE AND 4-BIT BINARY COUNTERS
BULLETIN NO. DL-S 7611833, MARCH 1974-REVISED OCTOBER 1976

SN54290, SN54LS290 ... J OR W PACKAGE

'290, 'LS290 ... DECADE COUNTERS SN74290, SN74LS290 ... J OR N PACKAGE
(TOP VIEW)
'293, 'LS293 ... 4-BIT BINARY COUNTERS
OUTPUTS
IN~UT IN~UT ~
• GND and Vec on Corner Pins Vee RO(2)

(Pins 7 and 14 Respectively)

description
R9(1) Qo

The SN54290/SN74290, SN54LS290/SN74LS290,

SN54293/SN74293, and SN54LS293/SN74LS293
counters are electrically and functionally identical to
the SN5490A/SN7490A, SN54LS90/SN74LS90,
SN5493A/SN7493A, and SN54LS93/SN74LS93,
respectively. Only the arrangement of the terminals
has been changed for the '290, , LS290, '293, and positive logic: see function tables
'LS293.

SN54293, SN54LS293 ..• J OR W PACKAGE

Each of these monolithic counters contains four SN74293, SN74LS293 •• _J OR N PACKAGE
master-slave flip-flops and additional gating to pro- (TOP VIEW)
vide a divide-by-two counter and a three-stage binary
counter for which the count cycle length is divide-
by-five for the '290 and 'LS290 and divide-by-eight
for the '293 and 'LS293.

All of these counters have a gated zero reset and the

•
'290 and 'LS290 also have gated set-to-nine inputs for
use in BCD nine's complement applications.

To use the maximum count length (decade or four-bit

binary) of these counters, the B input is connected to
the QA output. The input count pulses are applied to
input A and the outputs are as described in the
appropriate function table. A symmetrical divide-by-
positive logic: see function tables
ten count can be obtained from the '290 and 'LS290
NC-No internal connection
counters by connecting the QD output to the A input
and applying the input count to the B input which
gives a divide-by-ten square wave at output QA.

1076

TEXAS INSTRUMENTS 1-423

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54290, SN54293, SN54LS290, SN54LS293,
SN74290, SN74293, SN74LS290. SN74LS293
DECADE AND 4-BIT BINARY COUNTERS
'290, 'LS290 '290, 'LS290 '293, 'LS293
BCD COUNT SEQUENCE BI-QUINARY (5-21 '290, 'LS290 COUNT SEQUENCE
(See Note AI (See Note BI RESET/COUNT FUNCTION TABLE (See Note CI
OUTPUT OUTPUT RESET INPUTS OUTPUT OUTPUT
COUNT COUNT COUNT
00 0c 0B 0A 0A 00 0c 0B ROOI RO(2) R9(11 R9(2) 00 Dc OB OA 00 Dc °B °A
0 L L L L 0 L L L L H H L X L L L L 0 L L L L
1 L L L H 1 L L L H H H X L L L L L 1 L L L H
2 L L H L 2 L L H L X X H H H L L H 2 L L H L
3 L L H H 3 L L H H X L X L COUNT 3 L L H H
4 L H L L 4 L H L L L X L X COUNT 4 L H L L
5 L H L H 5 H L L L L X X L COUNT 5 L H L H
6 L H H L 6 H L L H X L L X COUNT 6 L H H L
7 L H H H 7 H L H L 7 L H H H
8 H L L L 8 H L H H 8 H L L L
9 H L L H 9 H H L L '293, 'LS293 9 H L L H
RESET/COUNT FUNCTION TABLE 10 H L H L
RESET INPUTS OUTPUT 11 H L H H
NOTES: A. Output QA is connected to input B for BCD count.
Roell Roe21 00 Dc °B °A 12 H H L L
B. Output QD is connected to input A for bi·quinary
H H L L L L 13 H H L H
count.
C. Output QA is connected to input B. L X COUNT 14 H H H L
D. H = high level, L = low level, X = irrelevant X L COUNT 15 H H H H

functional block diagrams

'290, 'LS290 '293, 'LS293

INPUT A . ;. (1_0..;..)_ _ _+-__--<11> INPUT A . .:.(. ;. ;10"-')_ _ _ _-01>

(5)
(5) OB OB

II (11) INPUT B .:. .(1:. . ;1. :. )_ _ _ _t-<l1>

INPUT B ---_.++----(1)

(4) Oc

(8)
00

(8) 00

The J and K inputs shown without connection are for reference only and are functionally at a high level.

1076

7-424 TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54290, SN54293, SN74290, SN74293
DECADE AND 4-81T BINARY COUNTERS

schematics of inputs and outputs

EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS

vee3-- Req Vee

INPUT --

OUTPUT
INPUT Req NOM
A 2.5 kU
B ('290) 1.25 kU
B ('293) 2.5 kU
All resets 6kU

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, VCC (see Note 1) 7V

Input voltage . . . . . . . . 5.5 V
!nteremitter vo!tage (see Note 2) 5.5 V
Operating free·air temperature range: SN54' Circuits -55°C to 125°C
SN74' Circuits DoC to 70°C

•
Storage temperature range -65°C to 150°C
NOTES: 1. Voltage values, except interemitter voltage, are with respect to network ground terminal.
2. This is the voltage between two emitters of a multiple-emitter transistor. For these circuits, this rating applies between the two
RO inputs, and for the '290 circuit, it also applies between the two R9 inputs.

recommended operating conditions

----- SN54' SN74'
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, VCC 4.5 5 5.5 4.75 5 5.25 V
High·level output current, IOH -800 -800 !J.A
Low-level output current, IOL 16 16 mA
A input 0 32 0 32
Count frequency, fcount MHz
B input 0 16 0 16
A input 15 15
Pulse width, tw B input 30 30 ns
Reset inpu ts 15 15
Reset inactive-state setup time, tsu 25 25 ns
Operating free-air temperature, T A -55 125 0 70 °c

10i6

TEXAS INCORPORATED
INSTRUMENTS 7-425
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54290, SN54293, SN74290, SN74293
DECADE AND 4-BI1 BINARY COUNTERS

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
'290 '293
PARAMETER TEST CONDITIONSt UNIT
MIN TVP:j: MAX MIN TVP:j: MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
VIK Input clamp voltage Vee= MIN, 11=-12mA -1.5 -1.5 V
Vee = MIN, VIH = 2 V,
VOH High-level output voltage 2.4 3.4 2.4 3.4 V
VIL = 0.8 V, 10H = -800p.A
Vee - MIN, VIH=2V,
VOL Low-level output voltage 0.2 0.4 0.2 0.4 V
VIL = 0.8 V, 10L = 16 mA~
II Input current at maximum input voltage Vee - MAX, VI- 5.5V 1 1 mA
Any reset 40 40
IIH High-level input current A input Vee = MAX, VI = 2.4 V 80 80 p.A
B input 120 80
Any reset -1.6 -1.6
IlL High-level input current A input Vee = MAX, VI = 0.4 V -3.2 -3.2 mA
B input -4.8 -3.2

lOS Short-circuit output current § Vee = MAX

I SN54' -20 -57 -20 -57
mA
l SN74' -18 -57 -18 -57
lee Supply current Vee = MAX, See Note 3 29 42 26 39 mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at Vee = 5 V, T A = 25°C.
§ Not more than one output should be shorted at a time.
~QA outputs are tested at IOL = 16 mA plus the limit value of IlL for the B input. This permits driving the B input while maintaining full
fan-out capability.
NOTE 3: ICC is measured with all outputs open, both RO inputs grounded following momentary connection to 4.5 V, and all other inputs
grounded.

switching characteristics, Vee = 5 V, TA = 25°e

•
FROM TO '290 '293
PARAMETERO TEST CONDITIONS UNIT
(INPUT) (OUTPUT) MIN TVP MAX MIN TVP MAX
A °A 32 42 32 42
f max MHz
B °B 16 16
tpLH
A QA
, 10 16 10 16
ns
tpHL 12 18 12 18
tPLH 32 48 46 70
A 00 ns
tPHL 34 50 46 70
eL=15pF,
tpLH 10 16 10 16
B °B RL = 400 n, ns
tpHL 14 21 14 21
See Note 4
tPLH 21 32 21 32
B ns
tpHL
°e
23 35 23 35 I
tpLH 21 32 34 51
B 00 ns
tpHL 23 35 34 51
tPHL Set-to-O Any 26 40 26 40 ns
tpLH °A,OO 20 30
Set-to-9 ns
tpHL °B,Oe 26 24

Of max == maximum count frequency

tpLH '" propagation delay time, low·to-high·level output
tpH L '" propagation delay time, h igh-to·low·level output
NOTE 4: Load circuit and voltage waveforms are the same as those shown for the '90A and '93A, page 3-10.

1076

7-426 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54LS290, SN54LS293, SN74LS290, SN74LS293
DECADE AND 4-BIT BINARY COUNTERS
REVISED OCTOBER 1976

schematics of inputs and outputs

EQUIVALENT OF EACH RESET INPUT EQUIVALENT OF A AND B INPUTS TYPICAL OF ALL OUTPUTS

----+--VCC

VC~
Vcc - - - + - - - R1 R2 R3 120 n NOM
20 kn NOM

I NP UT _-Wl-+-_~ INPUT -
OUTPUT

NOMINAL VALUES
iNPUT R1 R2 R3
A 10 kn 10 kn 10 kn
B ('LS290) 6.7 kn 6.7 kn 5 kn
!3 ('LS293) ~5 kn 15 k!1 1Q kn

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, Vee (see Note 5) 7V

Input voltage: R inputs 7V
A and B inputs 5.5 V
Operating free-air temperature range: SN54LS290, SN54LS293 -55°C to 125°C
SN74LS290,SN74LS293 oOe to 70°C
Storage temperature range -65°C to 150°C

•
NOTE 5: Voltage values are with respect to network ground terminal.

recommended operating. cond itions

SN54LS' SN74LS'
UNIT
MIN NOM MAX MIN NOM MAX
Supply VOltage, VCC 4.5 5 5.5 4.75 5 5.25 V
High-level output current, IOH -400 -400 p.A
Low-level output current, IOL 4 8 mA
A input 0 32 0 32
Count frequency, fcount MHz
B input 0 16 0 16
A input 15 15
Pulse width, tw B input 30 30 ns
Reset inputs 15 15
Reset inactive-state setup time, tsu 25 25 ns
Operating free-air temperature, T A -55 125 0 70 °c

1076

TEXAS INCORPORATED
INSTRUMENTS 7-427
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54LS290, SN54LS293, SN74LS290, SN74LS293
DECADE AND 4-BI1 BINARY COUNTERS
REVISED OCTOBER 1976

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS' SN74LS'
PARAMETER TEST eONDITIONst UNIT
MIN TYP:j: MAX MIN TYP:j: MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
VIK Input clamp voltage Vee = MIN, 11=-18mA -1.5 -1.5 V
Vee= MIN, VIH = 2 V,
VOH High-level output voltage 2.5 3.4 2.7 3.4 V
VIL = VIL max, 10H =-400IJA
Vee= MIN, VIH = 2 V, IIOL = 4 mA~ 0.25 0.4 0.25 0.4
VOL Low-level output voltage V
VIL = VIL max IIOL=8mA~ 0.35 0.5
Any reset Vee= MAX, VI = 7 V 0.1 0.1
Input current
A input 0.2 0.2
II at maximum mA
B of 'LS290 Vee= MAX, VI=5.5V 0.4 0.4
input voltage
B of'LS293 0.2 0.2
Any reset 20 20
High-level A input 40 40
IIH Vee = MAX, VI = 2.7 V IJA
input current B of 'LS290 80 80
B of'LS293 40 40
Any reset -0.4 -0.4
Low-level A input -2.4 -2.4
IlL Vee= MAX, VI = 0.4 V mA
output current B of 'LS290 -3.2 -3.2
B of 'LS293 -1.6 -1.6
lOS Short-circuit output current§ Vee = MAX -20 -100 -20 -100 mA
I'Ls290 9 15 9 15
ICC Supply current Vee = MAX, See Note 3 mA
J'LS293 9 15 9 15

t For conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions.
tAli tvpical values are at VCC =5 V, T A = 25°C.
§ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
~QA outputs are tested at specified IOL plus the limit value of IlL for the B input. This permits driving the B input while maintaining full
fan-out capability. .

•
NOTE 3: ICC is measured with all outputs open, both RO inputs grounded following momentary connection to 4.5 V, and all other inputs
grounded.

switching characteristics, Vee = 5 V, TA = 25° e

PA-RAMETERO

f max
J_ FROM
(INPUT)
A
TO
(OUTPUT)

°A
TEST CONDITIONS
MIN
32
'LS290
TYP
42
MAX MIN
32
'LS293
TYP
42
MAX
UNIT

MHz
B °B 16 16
tpLH 10 16 10 16
A °A ns
tpHL 12 18 12 18
tPLH 32 48 46 70
A °D ns
tPHL 34 50 46 70
CL=15pF,
tPLH 10 16 10 16 I
B °B RL=2kn., ns
tpHL 14 21 14 21
See Note 6
tpLH 21 32 21 32
B °c ns
tPHL 23 35 23 35
tpLH 21 32 34 51
B °D ns
tPHL 23 35 34 51
tpHL 5et-to-0 Any 26 40 26 40 ns
tpLH °A,OD 20 30
Set-to-9 ns
tpHL °B,Oe 26 40

¢f max == maximum count frequency

tPLH'" propagation delay time, low-to-high-Ievel output
tpH L '" propagation delay time, high-to-Iow-Ievel output
NOTE 6: Load circuit and voltage waveforms are the same as those shown for the 'LS90 and 'LS93, pages 7-80.

107~
7-428 TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TTL TYPES SN54LS295B, SN74LS295 B
4-BIT RIGHT-SHIFT LEFT-SHIFT REGISTERS
MSI WITH 3-STATE OUTPUTS
BULLETIN NO. DL-S 7611780, OCTOBER 1976

• 'LS295B Offers Three Times the SN54LS295B .•. J OR W PACKAGE

Sink-Current Capability of 'LS295A SN74LS295B •.. J OR N PACKAGE
(TOP VIEW)
• Schottky-Diode-Clamped Transistors
• Low Power Dissipation ... 80 mW Typical
(Enabled)
• Applications:
N-Bit Serial-To-Parallel Converter
N-Bit Parallel-To-Serial Converter
N-Bit Storage Register
description
These 4-bit registers feature parallel inputs, parallel
outputs, and clock, serial, mode, and output control SI~~TL ~c~~f.C!EO!" GND
INPUTS
inputs. The registers have three modes of operation:
Parallel (broadside) load
iogic: see function tabie
Shift right ithe direction QA toward GD)
Shift left (the direction GD toward GAl
Parallel loading is accomplished by applying the four bits of data and taking the mode control input high. The data is
loaded into the associated flip-flops and appears at the outputs after the high-to-Iow transition of the clock input.
During parallel loading, the entry of serial data is inhibited.
Shift right is accomplished when the mode control is low; shift left is accomplished when the mode control is high by
connecting the output of each flip-flop to the parallel input of the previous flip-flop (GD to input C,etc.) and serial data
is entered at input D.
When the output control is high, the normal logic levels of the four outputs are available for driving the loads or bus
lines. The outputs are disabled independently from the level of the clock by a low logic level at the output control
input. The outputs then present a high impedance and neither load nor drive the bus line; however, sequential operation
of the registers is not affected.

•
The SN54LS2958 is characterized for operation over the full military temperature range of -55°C to 125°C; the
SN74LS2958 is characterized for operation from O°C to 70°C.

FUNCTION TABLE
INPUTS OUTPUTS
MODE PARALLEL
CLOCK SERIAL OA OB Oc °D
CONTROL A B C D
H H X X X X X °AO QSO QCO QDO
H .j, X a b c ·d a b c d
H .j, X QBt Qct QDt d QS n QCn Oon d
L H X X X X X QAO QSO QCO QDO
L .j, H X X X X H QAn QS n QCn
L .j, L X X X X L QAn °Sn QCn
When the output control is low, the outputs are disabled to the high-impedance state;
however, sequential operation of the registers is not affected.

tShifting left requires external connection of QS to A, QC to B, and Q D to e. Serial data is

entered at input D.

H = high level (steady state), L = low level (steady state), X = irrelevant (any input, including transitions)
.j, = transition from high to low level.
a, b, c, d = the level of steady·state input at inputs A, B, e, or D, respectively.
QAO, QBO, Qeo, QDO = the level of QA' QS, Qe, or QD, respectively, before the indicated steady-state input conditions were established_
QAn, QSn' Qen, QDn = the level of QA' QB, Qe, or QD, respectively, before the most-recent .j, transition of the clock_

See explanation of function tables on page 3-8.

1076 DESIGN GOAL

This page provides tentative information on a
product in the developmental stage. Texas TEXAS INSTRUMENTS 7-429
INCORPORATED
I nstruments reserves the right to change or d is-
F"OST OFFICE BOX 5012 • DALL.AS. TEXAS 75222
continue this product without notice.
 TYPES SN54LS2958. SN74LS2958
4-81T RIGHT-SHIFT LEFT-SHIFT REGISTERS
WITH 3-STATE OUTPUTS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . 7V
Input voltage . . . . . . . . . . . . . . . 7V
Operating free-air temperature range: SN54LS295B -55°C to 125°C
SN74LS295B aOe to 7aoe
Storage temperature range -65°C to 15aoe
NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54LS295B SN74LS295B
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, IOH -1 -2.6 mA
Low-level output current, IOL 12 24 mA
Clock frequency, fclock 0 20 0 20 MHz
Width of clock pulse, tw(clock) 25 25 ns
Setup time, high-level or low-level data, tsu 20 20 ns
Hold time, high-level or low-level data, th 20 20 ns
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS295B SN74LS295B
PARAMETER TEST CONDITIONSt UNIT
MIN TYP:j: MAX MIN TYP:j: MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
VIK Input clamp voltage Vee = MIN, II = -18 mA -1.5 -1.5 V
Vee = MIN, VIH=2V,
VOH High-level output voltage 2.4 3.4 2.4 3.1 V
VIL = VIL max, IOH = MAX

•
Vee - MIN, VIH-2V, IIOL = 12 mA 0.25 0.4 0.25 0.4
VOL Low-level output voltage V
VIL = VIL max IIOL = 24 mA 0.35 0.5
Off-state output current, Vee= MAX, VIL - VIL max,
20 20 p.A
IOZH high-level voltage applied Vo = 2.7 V
Off-state output current, Vee- MAX, VIH-2V,
IOZL -20 -20 p.A
low-level voltage applied VO=O.4 V
Input current at ,
II Vee = MAX, VI =7 V 0.1 0.1 mA
maximum input voltage
IIH High-level input current Vee = MAX, VI=2.7V 20 20 p.A
IlL Low-level input current Vee - MAX, VI = 0.4 V -0.4 -0.4 mA
lOS Short-circuit output current§ Vee = MAX -30 -130 -30 -130 mA

Supply current Vee = MAX, See Note 2

lCondition A 16 27 16 27
mA
ICC
I Condition B 17 29 17 29

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at Vee = 5 V, TA = 25°C.
§Not more than one output should be shorted at a time,and duration of the short·circuit should not exceed one second.
NOTE 2: ICC is measured with the outputs open, the serial input and mode control at 4.5 V, and the data inputs grounded under the following
conditions:
A. Output control at 4.5 V and a momentary 3 V, then ground, applied to clock input.
B. Output control and clock input grounded.

DESIGN GOAL 1076

7-430 ~;~~:c~gei~r~~i:e~:~~I~~~:nitnaflor;:;!~nT~:a: TEXAS INSTRUMENTS

Instruments reserves the right to change or dis· INCORPORATED
continue this product without notice. POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54LS2958 SN74LS2958
4-81T RIGHT-SHIFT LEFT-SHIFT REGISTERS
WITH 3-STATE OUTPUTS
switching characteristics, Vee =5 V, T A = 25 e, RL = 667 n
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f max Maximum clock frequency 25 35 MHz
tpLH Propagation delay time, low-to-high-Ievel output 20 30 ns
CL = 45 pF,
tpHL Propagation delay time, high-to-Iow-Ievel output 23 35 ns
See Note 3
tpZH Output enable time to high level 17 26 ns
tpZL Output enable time to low level 28 42 ns
tpHZ Output disable time from high level CL=5pF, 13 20 ns
tPLZ Output disable time from low level See Note 3 17 26 ns
NOTE 3: Load circuit and voltage waveforms are shown on page 3-11.

functional block diagram

~ ___________________________DATA INPUTS
~i'~______________________________ ~

OUTPUT (8)
CONTROL

•
~~-------------~~---~v~--~------~
OUTPUTS

schematics of inputs and outputs

EQUIVALENT OF SERIAL EQUIVALENT OF CLOCK, TYPICAL OF ALL OUTPUTS

AND DATA INPUTS MODE CONTROL, AND
OUTPUT CONTROL INPUTS

- - - - _ - Vee
vee
Req

INPUT ......
-~

OUTPUT

~~
"
~~
~t
r.
Serial: Req = 30 k.l1 NOM
A,B,C, D: Req = 20 k.l1 NOM

1076
DESIGN GOAL
This page provides tentative information on a 7-431
product in the developmental stage. Texas TEXAS INSTRUMENTS
Instruments reserves the right to change or dis- INCORPORATED
continue this product without notice. POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TTL TYPES SN54298. SN54LS298. SN74298. SN74LS298
MSI QUADRUPLE 2-INPUT MULTIPLEXERS WITH STORAGE
BULLETIN NO. DL-S 7611747, MARCH 1974-REVISED OCTOBER 1976

• Selects One of Two 4-Bit Data Sources

SN54298, SN54LS298 ... J OR W PACKAGE
and Stores Data Synchronously with
SN74298, SN74LS298 .• , J OR N PACKAGE
System Clock (TOP VIEW)
• Applications: OUTPUTS DATA
Dual Source for Operands and Constants ~ WORD INPUT
VCC OA OB Oc 00 ClOCKSElECT
in Arithmetic Processor; Can Release
Processor Register Files for Acquiring New 13
Data
Implement Separate Registers Capable of CK
Parallel Exchange of Contents Yet Retain
External Load Capability B2 C1

Universal Type Register for Implementing A2

Various Shift Patterns; Even Has Compound
Left-Right Capabilities

description
V
These monolithic quadruple two-input multiplexers DATA INPUTS
with storage provide essentially the equivalent
functional capabilities of two separate MSI functions logic: see function table
(SN54157/SN74157 or SN54LS157 /SN74LS157 and
SN54175/SN74175 or SN54LS175/SN74LS175) in a
single 16-pin package.
functional block diagram
When the word-select input is low, word 1 (A 1, B1,
C1, 01) is applies to the flip-flops. A high input to
word select will cause the selection of word 2 (A2,
B2, C2, 02). The selected word is clocked to the

• output terminals on the negative-going edge of the

clock pulse.

Typical power dissipation is 195 milliwatts for the

'298 and 65 milliwatts for the 'LS298. SN54298
and SN54LS298 are characterized for operation over
the full military temperature range of -55°C to
125°C; SN74298 and SN74LS298 are characterized
for operation from O°C to 70°C.
FUNCTION TABLE
lNPUTS OUTPUTS
WORD
SELECT
CLOCK aA aB ac aD

L ~ a1 b1 c1 d1
H ~ a2 b2 c2 d2
X H QAO QBO QCO QDO CLOCK ...!I.:.:",-I- - - - - - - - 1 :>_ _ _ _---'

H = high level (steady state) -J:. ... Dynamic input activated by a transition from a high level
L = low level (steady state) I to a low level
X = irrelevant (any input, including transitions)
• = transition from high to low level
a1, a2, etc. = the level of steady-state input at A 1, A2, etc.
0AO, 0BO, etc. = the level of 0A, 0B, etc. entered on the
most~recent ~ transition of the clock input.

1076

7-432 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54298, SN54LS298, SN74298, SN74LS298
QUADRUPLE 2-INPUT MULTIPLEXERS WITH STORAGE
REVISED OCTOBER 1976

schematics of inputs and outputs

'298 '298
EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS

-----VCC
V C C - -.....- -

INPUT

~~ I-~
OUTPUT

Clock:
All other inputs:
Req
Req
=4
=6
kn NOM
kn NOM
I
L._ _ _ _ _ _ _ _ _ _~

'LS298 'LS29S 'LS298

EQUIVALENT OF DATA INPUTS EQUIVALENT OF OTHER INPUTS TYPICAL OF ALL OUTPUTS

•
- - - -........-VCC
V C C - -......- -
VCC---+---
15 kn NOM
17 kn NOM

INPUT-...,...........- .......
INPUT -...,...........- .......
'L----4t-- 0 UTP UT

76

TEXASINCORPORATED
INSTRUMENTS 7-433
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54298, SN74298
QUADRUPLE 2-INPUT MULTIPLEXERS WITH STORAGE

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . 7V
Input voltage . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range: SN54298 -55°C to 125°C
SN74298 oOe to 70°C
Storage temperature -65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54298 SN74298
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -800 -800 IJ.A
Low-level output current, 10L 16 16 mA
Width of clock pulse, high or low level, tw 20 20 ns
Data 15 15
Setup time, tsu ns
Word select 25 25
Data 5 5
Hold time, th ns
Word select 0 0
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONSt MIN TYP:j: MAX UNIT
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
VIK Input clamp voltage Vee = MIN, 11= -12 mA -1.5 V
Vee = MIN, VIH=2V,
VOH High-level output voltage 2.4 3.2 V
VIL = 0.8 V, 10H = -8001J.A
Vee = MIN, VIH=2V,

•
VOL Low-level output voltage 0.4 V
VIL = 0.8 V, 10L = 16 mA
II Input current at maximum input voltage Vee = MAX, VI = 5.5 V 1 mA
IIH High-level input current Vee = MAX, VI = 2.4 V 40 IJ.A
IlL Low-level input current Vee = MAX, VI = 0.4 V -1.6 mA

Short-circuit output current§

I SN54298 -20 -57
mA
I lOS Vee = MAX ! SN74298 -18 -57
ICC Supply current Vee =MAX, See Note 2 39 65 mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at V CC = 5 V, T A = 25° C.
§Not more than one output should be shorted at a time.
NOTE 2: With all outputs open and all inputs except clock low, ICC is measured after applying a momentary 4.5 V, followed by ground, to
the clock input.

switching characteristics, Vee = 5 V, TA = 25°e

PARAMETER TEST CONDITIONS MIN TYP MAX
r-:tP...:L::.:.H-,--P_ro....:pa---=:.ga_t_io_n_d_e_la..;.y_t_im_e..;.,_lo_w_-_to_-_h·.::lg_h-_le_v_el_o_u_tP;...u_t_ _ _ _ _ _ _-I CL = 15 pF, RL = 400.11, 18 27
tPHL Propagation delay time, high-to-Iow-Ievel output See Note 3 21 32

NOTE 3: Load circuit and waveforms are shown on page 3·10.

10

7-434 TEXAS INSTRUMENTS INCORPORATED

POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54LS298,SN74LS298
QUADRUPLE 2-INPUT MULTIPLEXERS WITH STORAGE
REVISED OCTOBER 1976

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ..... . 7V
Input voltage . . . . . . . . . . . . . . 7V
Operating free-air temperature range: SN54LS298 -55°C to 125°C
SN74LS298 oOe to 70°C
Storage temperature range -65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54LS298 SN74LS298
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -400- -400 /LA
Low-level output current, 10L 4 8 mA
Width of clock pulse, high or low level, tw 20 20 ns
I Data 15 15
Setup time, tsu ns
I Word select 25 25
5 5
Hold time, th
o o
Operating free-air temperature, T A -55 125 o
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54 LS298 SN74LS298
PARAMETER TEST eONDITIONSt UNIT
MIN TYP:j: MAX MIN TYP:j: MAX
VIH High-level input voltage 2 2 V
V,L Low-level input voltage 0.7 0.8 V
VIK Input clamp voltage Vee= MIN, I, =-18mA -1.5 -1.5 V
Vee= MIN, V'H=2V,
VOH High-level output voltage 2.5 3.4 2.7 3.4 V
VIL = VIL max, 10H = -400/LA

•
Vee = MIN, VIH=2V, IIOL = 4 mA 0.25 0.4 0.25 0.4
VOL Low-level output voltage V
V,L = VIL max I'OL =8mA 0.35 0.5
Input current at
II Vee = MAX, VI = 7V 0.1 0.1 mA
maximum input voltage
IIH High-level input current Vee = MAX, V, = 2.7 V 20 20 /LA
I,L Low-level input current .Vee= MAX, VI = 0.4 V -0.4 -0.4 mA
lOS Short-circuit output current§ Vee = MAX -20 -100 -20 -100 mA
lee Supply current Vee = MAX, See Note 2 13 21 13 21 mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are.at V CC = 5 V, T A = 25°C.
§ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
NOTE 2: With all outputs open and all inputs except clock low, ICC is measured after applying a momentary 4.5 V, followed by ground, to
the clock input.

switching characteristics, Vee = 5 V, TA = 25°e

PARAMETER TEST CONDITIONS MIN TYP MAX
tpLH Propagation delay time, low-to-high-Ievel output eL=15pF, RL=2kn, 18 27
tpHL Propagation delay time, high-to-Iow-Ievel output See Note 4 21 32

NOTE 4: Load circuit and waveforms are shown on page 3-11.

1076

TEXAS INCORPORATED
INSTRUMENTS 7-435
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54298, SN54LS298, SN14298, SN14LS298
QUADRUPLE 2-INPUT MULTIPLEXERS WITH STORAGE

TYPICAL APPLICATION DATA

This versatile multiplexer/register can be connected to operate as a shift register that can shift N-places in a single
clock pulse.

The following figure illustrates a BCD shift register that will shift an entire 4-bit BCD digit in one clock pulse.
PARALLEL LOAD
Ir------------------~A~ ________________~\
I I WORD SELECT
I T T
A1 l A1 l A1
A2
WS
QA~
A2
WS QA
- A2
WS
QA

..... B1 '298 - B1 '298 ..... B1 '298

QB~ or QB or QB
B2 'L~;98
~

B2 'LS298 B2 'LS298
"-- C1 REG
1
ac:-::
-- C1 REG
2 Dc ~
-- Cl REG
3 ac
C2 C2 C2
"--- D1 '---- D1 - D1
QD QD CK QD
D2
<;,t< D2 C~ D2
A
~ £ y
CLOCK
- -
~
DIGIT 1
~
DIGIT 2
c..r
DIGIT 3

When the word-select input is high and the registers are clocked, the contents of register 1 is transferred (shifted) to
register 2 and etc. In effect, the BCD digits are shifted one position. In addition, this application retains a parallel-load
capability which means that new BCD data can be entered in the entire register with one clock pulse. This arrangement
can be modified to perform the Shifting of binary data for any number of bit locations.

•
Another function that can be implemented with the '298 or 'LS298 is a register that can be designed specifically for
supporting multiplier or division operations_ The example below is a one place/two-place shift register.

---------1
I '181, 'LS181, or 'S181
(ALU) T-------T
'181, 'LS181, or 'S181
(ALUI
FO F1 F2 F3 FO F1 F2 F3

A 1 A2 B1 B2 C1 C2 D1 D2 A1 A2 B1 B2 C1 C2 D1 D2

WS

WORD
'-----~-~-~~-~--~SELECT

When word select is low and the register is clocked, the outputs of the arithmetic/logic units (ALU's) are shifted one
place. \Nhen word select is high and the registers are clocked, the data is shifted two places.

37~

7·436 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TTL TYPES SN54LS299, SN54S299, SN74LS299, SN74S299
LSI 8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS
BULLETIN NO. DL.S 7612115. MARCH 1974-REVISED OCTOBER 1976

• Multiplexed Inputs/Outputs Provide

Improved Bit Density SN54LS299, SN54S299 ..• J PACKAGE
SN74LS299, SN74S299 •.. J OR N PACKAGE
• Four Modes of Operation: (TOP VIEW)
Hold (Store) Shift Left
Shift Right Load Data
SHIFT SHIFT
LEFT RIGHT
• Operates with Outputs Enabled or at High Z VCC SL CHI H/QH D/QD BiOs CLOCK SR

• 3-State Outputs Drive Bus Lines Directly

• Can Be Cascaded for N-Bit Word Lengths
• SN54LS323 and SN74LS323 Are Similar
But Have Synchronous Clear

• Applications:
Stacked or Push-Dow!"! Registers.

~jRgRLLLL1,L"J II
Buffer Storage, and
Accumulator Registers
GUARANTEED TYPICAL L..:J L.:J L.:.J LJ L..J L:.J L..:.J L:.J L..J L.:J
so ~ GIQG EIQE C/Oc AIQA QA' CLEAR GNO

TyPE SHiFT iCLOCK; POWER OUTPUT

CONTROLS
FREQUENCY DISSIPATION
'LS299 35 MHz 175mW
logic: see ~escription and function table
'S299 50 MHz 700mW

description
These Schottky TTL eight-bit universal registers feature multiprexed inputs/outputs to achieve full eight bit data
handling in a single 20-pin package. Two function-select inputs and two output-control inputs can be used to choose
the modes of operation listed in the function table.

Synchronous parallel loading is accomplished by taking both function-select lines, SO and S1, high. This places the

•
three-state outputs in a high-impedance state, which permits data that is applied on the input/output lines to be clocked
into the register. Reading out of the register can be accomplished while the outputs are enabled in any mode. A direct
overriding input is provided to clear the register whether the outputs are enabled or off.

FUNCTION TABLE

INPUTS INPUTS/OUTPUTS OUTPUTS

FUNCTION OUTPUT
MODE SERIAL
CLEAR SELECT CONTROL CLOCK A/QA B/QB C/Qc D/QD E/QE F/QF GIDG H/QH QA' QH'
S1 SO G1 t G2t SL SR
L X L L L X X X L L L L L L L L L L
Clear
L L X L L X X X L L L L L L L L L L
H L L L L X X X QAO QBO QCO QOO QEO QFO QGO QHO QAO QHO
Hold
H X X L L L X X QAO QBO QCO QOO QEO QFO QGO QHO QAO QHO
H L H L L t X H H QAn QBn Ocn QO n QEn QFn QGn H QGn
Shift Right
H L H L L t X L L QAn QBn QCn QO n QEn QFn QGn L DGn
H H L L L t H X QBn QCn QO n QEn QFn DGn QHn H QBn H
Shift Left
H H L L L t L X QBn QCn QO n QEn QFn QGn QHn L QBn L
Load H H H X X t X X a b c d e f g h a h
tWhen one or both output controls are high the eight input/output terminals are disabled to the high-impedance state; however,
sequential operation or clearing of the register is not affected.

a ... h = the level of the steady-state input at inputs A through H, respectively. These data are loaded into the flip-flops while the flip-flop
outputs are isolated from the input/output terminals. See explanation of function tables on page 3-8.

1076

TEXAS INSTRUMENTS 7-437

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN64LS299, SN64S299, SN74LS299, SN74S299
8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS

functional block diagram

1£ w
>-+---g

• M
= '"
>-+---~

37'

7438 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54LS299, SN74LS299
8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS

schematics of inputs and outputs

EQUIVALENT OF EACH INPUT TYPICAL OF OUTPUTS TYPICAL OF OUTPUTS

QA THRUQH QA'THRUQH'

-----VCC ----+--VCC

OUTPUT OUTPUT

SO, S1: Req= 9 kU NOM

All other inputs: Req= 18 kU NOM

3b~cluta mIDtimum ratings uvCii opaiatiiig fies-air tempSra'Lufe fBilge (unless otherwise nomoj

Supply voltage, Vee (see Note 1) 7V

Input voltage . . . . . . . . 7V
Off-state output voltage 7V
Operating free-air temperature range: SN54LS299 -55°C to 125°C
SN74LS299 aOe to 7aoe
Storage temperature -65°C to 15aoe
NOTE1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54LS299 SN74LS299

•
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, VCC 4.5 5 5.5 4.75 5 5.25 V
QA thru QH -1 -2.6
High-level output current, IOH rnA
QA' or QH' -0.4 -0.4
QA thru QH 12 24
Low-level output current, IOL rnA
QA' orQH' 4 8
Clock .frequency, f clock 0 35 0 35 MHz
Clock high 20 20
Width of ciock pulse, tw(clock) ns
Clock low 20 20
Width of clear pulse, tw(clear) Clear low 20 20 ns
Select 10t 10t
High-level data O 20t 20t
Setup time, tsu ns
Low-level data O 20t 20t
Clear inactive-state 20t 20t
Select 10t 10t
Hold time, th ns
Data O ot ot
Operating free-air temperature, T A -55 125 0 70 °c

0Data includes the two serial inputs and the eight input/output data lines.

76 DESIGN GOAL
This page provides tentative information on a
product in the developmental stage. Texas TEXAS INSTRUMENTS 7-439
INCORPORATED
Instruments reserves the right to change or dis·
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
continue this product without notice.
 TYPES SN54LS299, SN74LS299
8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54lS299 SN74lS299
PARAMETER TEST CONDITIONSt UNIT
MIN TYP:j: MAX MIN TYp:j: MAX
VIH High-level input voltage 2 2 V
Vil low-level input voltage 0.7 0.8 V
VIK Input clamp voltage VCC =MIN, II =-18mA -1.5 -1.5 V
QA thru QH VCC = MIN, VIH = 2 V, 2.4 3.2 2.4 3.1
VOH High-level output voltage V
QA' or QH' Vil = Vilmax, 10H = MAX 2.7 3.4 2.7 3.4
10l = 12 mA 0.25 0.4 0.25 0.4
QA thru QH VCC= MIN,
10L = 24 mA 0.35 0.5
VOL Low-level output voltage VIH=2V, V
10L =4mA 0.25 0.4 0.25 0.4
QA' or QH' VIL = VILmax
10L =8 mA 0.35 0.5
Off-state output current, VCC - MAX, VIH-2V,
10ZH QA thru QH 40 40 /JA
high-level voltage applied VO=2.7V
Off-state output current, VCC = MAX, VIH=2V,
10ZL QA thru QH -400 -400 /JA
low-level voltage applied VO=O.4V
Input current at maximum SO, S1 0.2 0.2
II VCC = MAX, VI = 7V mA
input voltage Any other 0.1 0.1
A thru H, SO, S1 40 40
IIH High-level input current VCC = MAX, VI = 2.7 V /J A
Any other 30 30
SO,S1 -0.8 -0.8
IlL Low-level input current VCC = MAX, VI = 0.5 V mA
Any other -0.4 -0.4
QA thru QH -30 -130 -30 -130
lOS Short-circuit output current§ VCC = MAX mA
QA' or QH' -20 -100 -20 -100
ICC Supply current VCC - MAX 35 66 35 60 mA

t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at VCC = 5 V, T A = 25°C.
§ Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.

•
switching characteristics, Vee = 5 V, TA = 25°e
FROM TO
PARAMETER' TEST CONDITIONS MIN TYP MAX UNIT
(INPUT) (OUTPUT)
f max See Note 2 35 50 MHz
tPLH 15 25
Clock ! QA' or QH' CL=15pF. RL=2k!1, ns
tPHL 15 25
See Note 2
tPHL Clear QA'or QH' 20 35 ns
tPLH 15 25
Clock QA thru QH ns
tpHL 15 25
CL=45pF, RL = 665 n,
tpHL Clear QA thru QH 20 35 ns
See Note 2
tpZH 20 35
<3\<32 QA thru QH ns
tPZL 20 35
tpHZ CL =5pF, RL = 665 n, 15 25
<31,<32 QA thru QH ns
tPLZ See Note 2 15 25

, f max "" maximum clock frequency

tpLH "" propagation delay time, low-to-high-Ievel output.
tpHL "" propagation delay time, high-to-Iow-Ievel output
tpZH "" output enable time to high level
tpZL "" output enable time to low level
tpHZ "" output disable time from high level
tpLZ "" output disable time from low level
NOTE 2: For testing f max , all outputs are loaded simultaneously, each with CL and RL as spacified for the propagation times. See lOad
circuits and waveforms on page 3-11.

DESIGN GOAL 10,

This page provides tentative information on a TEXAS INSTRUMENTS
7-440 product in the developmental stage. Texas INCORPORATED
Instruments reserves the right to change or dis· POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
continue this product without notice.
 TYPES SN54S299, SN74S299
8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS

schematics of inputs and outputs

EQUIVALENT OF CLOCK AND EQUIVALENT OF G1 EQUIVALENT OF A THRU Ht,SO, S1,
CLEAR INPUTS AND G21NPUTS SHIFT RIGHT, AND SHIFT LEFT INPUTS

VCC13--
INPUT
Req

--
VCC~-- 2.8 kn
NOM --
VCC~5;n
NOM

INPUT --
INPUT

Clock: Req = 2.8 kn NOM

Clear: Req = 3.5 kn NOM tWhen 3-state outputs are disabled.

TYPICAL OF OUTPUTS

;;:;;;,;:t V CC
50~

_ ~OUT'Ul
absolute maximum ratings over operatinQ free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . 7V
!nput voltage . . . . . . . . 5.5 V
Off-state output voltage 5.5 V
Operating free-air temperature range: SN54S299 (see Note 2)

•
-55°e to 125°C
SN74S299 aOe to 7aoe
Storage temperature -65°e to 15aoC
NOTES 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54S299 SN74S299
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, VCC 4.5 5 5.5 4.75 5 5.25 V
QA thru QH -2 -6.5
High-level output current, IOH mA
QN or QH' -0.5 -D.5
QA thru QH 20 20
Low-level output current, IOL mA
QA' or QH' 6 6
Clock frequency, fclock 0 50 0 50 MHz
Clock high 10 10
Width of clock pulse, tw(clock} ns
Clo~k low 10 10
Width of clear pulse, tw(clear) Clear low 10 10 ns
Select 15t 15t
High-level data O 7t 7t
Setup time, tsu ns
Low-level data O 5t 5t
CI ear i nactive-state 10t 10t
Select 5t 5t
Hold time, th ns
DataO 5t 5t
Operating free-air temperature, T A -55 125 0 70 °c
°Data includes the two serial inputs and the eight input/output data lines.

1076

TEXAS INSTRUMENTS 7-441

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54S299. SN74S299
8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONSt MIN TYP:j: MAX UNIT

VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
VIK Input clamp voltage Vee = MIN, II =-18mA -1.2 V
QA thru QH Vec = MIN, VIH =2 V, 2.4 3.2
VOH High-level output voltage V
QA' orQH' VIL = 0.8 V, 10H = MAX 2.7 3.4
VCC = MIN, VIH - 2 V,
VOL Low-level output voltage 0.5 V
VIL = 0.8 V, 10L = MAX
Off-state output current, VCC = MAX, VIH -2 V,
10ZH QA thru QH 100 /J A
high-level voltage applied Va = 2.4 V
Off-state output current, VCC = MAX, VIH = 2 V,
10ZL QA thru QH -250 /J A
low-level voltage applied Va = 0.5 V
II Input current at maximum input voltage VCC = MAX, VI = 5.5 V 1 rnA
A thru H, SO, Sl 100
IIH High-level input current VCC= MAX, VI = 2.7 V /JA
Any other 50
Clock or clear -2 rnA
IlL Low-level input current Vec = MAX, VI=0.5V
Any other -250 /JA
QA thru QH -40 -100
lOS Short-circuit output current§ Vee = MAX rnA
QA' or QH' -20 -100
ICC Supply current VCC= MAX 140 225 rnA

t For conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions.
o
:j:AII typical values are at Vee = 5 V, T A = 2S e.
§ Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.

switching characteristics, Vee =5 V, TA =25°e

• PARAMETER.

f max
tPLH
tPHL
tpHL
tPLH
tpHL
FROM
(INPUT)

Clock

Clear

Clock
TO
(OUTPUT)

QA'orQH'

QA' or QH'

QA thru QH
TEST CONDITIONS

See Note 2

CL = 15 pF,
See Note 2
RL = 1 kn,
MIN

50
TYP

70
12
13
14
15
15
MAX

20
20
21
21
21
UNIT

MHz

ns

ns

ns
CL =45 pF, RL = 280n,
tPHL Clear QA thru QH 16 24 ns
See Note 2
tpZH 10 18
<31, <32 QA thru QH ns
tPZL 12 18
tPHZ eL-5pF, RL -280n, 7 12
G1,G2 QA thru QH ns
tPLZ See Note 3 7 12

1 f max == maximum clock frequency

tpLH == propagation delay time, low-to-hi9h-level output.
tpHL == propagation delay time, high-to-Iow-Ievel output
tpZH == output enable time to high level
tpZL == output enable time to low level
tpHZ == output disable time from high level
tpLZ == output disable time from low level
NOTE 3: For testing f max , all outputs are loaded simultaneously, each with eL and RL as specified for the propagation times. See load
circuits and waveforms on page 3-10.

1076

7-442 TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TTL TYPES SN54LS323, SN74LS323
LSI 8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS
BULLETIN NO. DL·S 7612462, OCTOBER 1976

• Multiplexed Inputs/Outputs Provide SN54LS323 .•. J PACKAGE

Improved Bit Density SN74LS323 •.• J OR N PACKAGE
(TOP VIEW)
• Four Modes of Operation:
Hold (Store) Shift Left
Shift Right Load Data SHIFT
LEFT
SHIFT
RIGHT
Vee SL OH' HIOH F/oF D/oD BlOB SR
• Operates with Outputs Enabled or at High Z
• 3-State Outputs Drive Bus Lines Directly
• Can Be Cascaded for N-Bit Word Lengths
• Typical Power Dissipation ... 175 mW
• Guaranteed Shift (Clock) Frequency ... 35 MHz
• Applications:
Stacked or Push-Down Registers,
Buffer Storage, and
A. __ •• _ •• 1...,. .. __ D __ : .. . , . _
I""\."","UIIIUIQLUI I";;;:!::II"'''GI~ so ~ G/QG E/QE clDc AlGA QA' CLEAR GND

e SN54LS299 and SN74LS299 Are Similar OUTPUT

CONTROLS

But Have Direct Overriding Clear

logic: see description and function table
description
These Low-Power Schottky eight-bit universal registers feature multiplexed inputs/outputs to achieve full eight-bit data
handling in a single 20-pin package. Two function-select inputs and two output-control inputs can be used to choose
the modes of operation listed in the function table. Synchronous parallel loading is accomplished by taking both
function-select lines, SO and S1, high. This places the three-state outputs in a high-impedance state, which permits data
that is applied on the input/output lines to be clocked into the register. Reading out of the register can be accomplished
while the outputs are enabled in any mode. The clear function is synchronous and a low level at the clear input clears
the register on the next low-to-high transition of the clock.

•
FUNCTION TABLE

INPUTS INPUTS/OUTPUTS OUTPUTS

FUNCTION OUTPUT
MODE SERIAL
CLEAR SELECT CONTROL CLOCK A/QA B/QB C/Qc D/QD E/QE F/QF G/O(; H/QH QA' QH'
S1 SO~ G1 t G2 t SL SR
L X L L L t X X L L L L L L L L L L
Clear
L L X L L t X X L L L L L L L L L L
H L L L L X X X QAO QBO QCO QDO QEO QFO QGO QHO QAO QHO
Hold
H X X L L L X X QAO QBO QCO QDO QEO QFO QGO QHO QAO QHO
H L H L L t X H H QAn QBn Den QDn QEn QFn QGn H QGn
Shift Right
H L H L L t X L L QAn QBn QCn QDn QEn QFn QGn L DGn
H H L L L t H X QBn QCn QDn QEn QFn QGn QHn H QBn H
Shift Left
H H L L L t L X QBn QCn QDn QEn QFn QGn QHn L QBn L
Load H H H X X t X X a b c d e f g h a h
tWhen one or both output controls are high the eight input/output terminals are disabled to the high-impedance state; however,
sequential operation or clearing of the register is not affected.

a . . . h = the level of the steady·state input at inputs A through H, respectively. These data are loaded into the flip·flops while the flip-flop
outputs are isolated from the input/output terminals. See explanation of function tables on page 3-8.

schematics of inputs and outputs, absolute maximum ratings, recommended operating conditions, and
electrical characteristics

Same as SN54LS299 and SN74LS299, see page 7-439.

DESIGN GOAL
1076
This page provides tentative information on d

product in the developmental stage. Texas TEXAS INCORPORATED

INSTRUMENTS 7-443
I nstruments reserves the right to change or dis-
continue this, product.without notice. POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54LS323, SN74LS323
8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS

functional block diagram

Sl so
(19) (1)

CLEAR ----''''--t-<e----,

SHIFT
r++-+-I--"':'(1;.;;.8,-) LE FT
SHIFT SERIAL
RIGHT INPUT
~~~~i-:(-:-:l1C-)-----hr-.L..iI..i.+L..I.oI,.L.L.I,

FOUR
IDENTICAL
CHANNELS
NOT
SHOWN

CLOCK...:.(~12~)----{)o+-__~~__-H+-__ -+'-__~~

(17) 0H'

(2)
OUTPUT Gl---""--------<;I
CONTROLS { G2-:-:(37")______..J
(7)
A/OA B/Os

•
INPUTS/OUTPUTS NOT SHOWN:
(6) C/Oc (5) E/OE
(14)0/00 (15) F/OF

switching characteristics, Vee = 5 V, T A = 25° C

FROM TO
PARAMETER~ TEST CONDITIONS MIN TYP MAX UNIT
(INPUT) (OUTPUT)
f max See Note 1 35 50 MHz
tPL H CL = 15 pF, RL = 2 kn, 15 25
Clock QA' orQH' ns
tpHL See Note 1 15 25
tpLH 15 25
Clock QA thru QH ns
tpHL CL=45pF, RL = 665 n, 15 25
tPZH See Note 1 20 35
G1,G2 QA thru QH ns
tpZL 20 35
tpHZ CL = 5 pF, RL = 665 n, 15 25
G1,G2 QA thru QH ns
tPLZ See Note 1 15 25

.f max == maximum clock frequency

tpLH == propagation delay time, low-to-high-Ievel output
tpHL == propagation delay time, high-to-Iow-Ievel output
tpZH == output enable time to high level
tpZL == output enable time to low level
tpHZ == output disable time from high level
tpLZ == output disable time from low level
NOTE 1: For testing f max , all outputs are loaded simultaneously, each with CL and RL as specified for the propagation times. See load
circu its and waveforms on page 3-11.

DESIGN GOAL 107E

This page provides tentative information on a
7-444 product in the developmental stage. Texas TEXAS INSTRUMENTSINCORPORATED
I nstruments reserves the right to change or di5~
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
continue this product without notice.
 TTL TYPES SN54LS324 THRU SN54LS327.
SN74LS324 THRU SN74LS327
MSI
VOLTAGE-CONTROLLED OSCILLATORS
BULLETIN NO. DL-S 7612472, OCTOBER 1976

SN54LS' ... J OR W PACKAGE

SN74LS' ... J OR N PACKAGE
• 'LS325, 'LS326 and 'LS327 Have Two 'LS324 (TOP VI EW)
Independent VCO's in a Single Package
• Output Frequency Set by Single External
Component:
Crystal for High-Stability Fixed-
Frequency Operation
Capacitor for Fixed- or Variable-
Frequency Operation
• Separate Supply Voltage Pins for Isolation
of Frequency Control Inputs and Oscillators
from Output Circuitry
logic: see description
• Highly Stable Operation over Specified
Temperature and/or Supply Voltage Ranges
'LS325 (TOP VI EWi

description

With the exception of 'LS324, all of these devices

feature two independent voltage-controlled oscillators
(VeO) in a single monolithic chip. The 'LS324,
'LS325 and 'LS326 have complementary outputs.
The output frequency of each veo is established by
a single external component, either a capacitor or a
crystal, in combination with the voltage-sensitive
inputs, one for frequency control and on the 'LS324,
another one for frequency range. These inputs can be logic: see description

used to vary the output frequency by changing the 'LS325 (TOP VIEW)
voltage applied to them. These highly stable oscillat-
tors can be set to operate at any frequency typically

•
between 0.12 Hz and 30 MHz. With 2 volts applied
to the frequency control input and also to the range
input of the 'LS324, the output frequency can be
approximated as follows:
1 X 10-4
fo=----
Cext
where: fo = output frequency in hertz
Cext = external capacitance in farads.
logic: see description

These devices can operate from a single 5-volt supply. 'LS327 (TOP VIEW)
However, one set of supply-voltage and ground pins
(Vee and GND) is provided for the enable,
synchronization-gating, and output sections, and a
separate set (8Vcc and8GND) is provided for the
oscillator and associated frequency-control circuits so
that effective isolation can be accomplished in the
system. Disabling either veo of the 'LS325 and
'LS327 can be accomplished by removing the appro·
priate 8 Vee. An enable input is provided on the
'LS324 and 'LS326. While this input is low, the
output is enabled. While the enable input is high, logic: see description
Y is high and Y is low.

1076

TEXAS INSTRUMENTS 7-445

INCORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54LS324 THRU SN54LS327. SN74LS324 THRU SN74LS327
VOLTAGE-CONTROLLED OSCILLATORS

description (continued)
The internal oscillator runs continuously even while the output is disabled via the enable input. The enable input is one
standard load, and it and the buffered output operate at standard Schottky-clamped TTL levels.

The pulse synchronization-gating section ensures that the first output pulse is neither clipped nor extended. Duty cycle
of the square-wave output is fixed at approximately 50 percent. Simultaneous operation of both VCO's in the same
package is not recommended.

The SN54LS324 thru SN54LS327 are characterized for operation over the full military temperature range of -55°C to
125°C; the SN74LS324 thru SN74LS327 are characterized for operation from O°C to 70°C.

schematics of inputs and outputs

EQUIVALENT OF EACH EQUIVALENT OF EACH FREQUENCY TYPICAL OF ALL OUTPUTS

ENABLE INPUT CONTROL OR ('LS324 ONLY) RANGE INPUT
('LS324 AND 'LS326)

Vcc
VCC
Vcc
R3
17 kU NOM

R1
INPUT
INPUT
L..--..-.-OUTPUT
R2

NOMINAL VALUES

•
R1 R2 R3
Frequency Control 79 kU 14kU 27 kU
Range ('LS324 only) 85kU 6kU 24kU

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, VCC (see Notes 1 and 2) .7V

Input voltage: Enable input ('LS324 and 'LS326) .7V
Frequency control or range input VCC
Operating free-air temperature range: SN54LS' Circuits -55°C to 125°C
SN74LS' Circuits O°C to 70°C
Storage temperature range -65° C to 150°C

NOTES: 1. Voltage values are with respect to the appropriate ground terminal.
2. Throughout this data sheet, the symbol Vee is used for the voltage applied to both the Vee and 8vee terminals, unless
otherwise noted.

1076
1

7-446 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54LS324 THRU SN54LS327, SN74LS324 THRU SN74LS327
VOLTAG E-CON TR0 LLED 0 SCI LLATO RS
recommended operating conditions
SN54lS' SN74lS'
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
Input voltage at frequency control or range input, VI (frea) or Vllrng) ~ 0 5 0 5 V
High-level output current, IOH -1.2 -1.2 rnA
Low-level output current, IOl 12 24 rnA
1 1 Hz
Output frequency (enabled), fa
20 20 MHz
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54lS' SN74lS'
PARAMETER TEST eONDITIONSt UNIT
MIN TYP:t: MAX MIN TYP:t: MAX
High-level input
VIH 2 2 V
voitage at enable·
low-level input
Vil 0.7 0.8 V
voltage at enable·
VIK Input clamp voltage at enable· Vee = MIN, 11--18mA -I.;J 1" \I

Vee = MIN, V!H - 2V,

.>." 2.7 3.4 V
VOH High-level output voltage 10H = -1.2 mA,See Note 3 ".'"
Vee = MIN, e Vee open IOl = 12mA 0.25 0.4 0.25 0.4
V
VOL low-level output voltage Vil = Vil max 0.35 0.5
IOl = 24mA
Freq control VI =5V 50 250 50 250
II Input current Vee = MAX IlA
or range ~ VI= 1 V 10 50 10 50
Input current
II at maximum Enable+ Vee= MAX, VI =7V 0.1 0.1 mA
input voltage
High-Iavel I
IIH Enable+ Vee= MAX, VI = 2.7 V 20 20 1 1''"'
input current
low-level
III Enable. Vee = MAX, VI =0.4V -0.4 -0.4 mA
input current

II
lOS Short·circuit output current!! Vee= MAX -40 -225 -40 -225 mA

ICC
Supply current, total into Vee - Max I 'LS324, 'lS326 18 30 18 30 mA
VCC and9v'cc pins See Note 4 I 'LS325, 'LS327 30 50 30 50
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
= 5 V, T A = 25° e.
:j: All typical values are at Vee
§ Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second •
• The characteristics involving an enable input are applicable to 'LS324 and 'LS326 only.
NOTES: 3. VOH is measured for Y outputs by connecting a 1-kn resistor from eX1 to Vee and another 1-kn resistor from eX2 to GND.
This procedure is reversed for testing VOH of Y outputs (not applicable to 'LS327). That is, a 1-kn resistor is connected from
eX2 to Vee and another 1-kn resistor from eX1 to GND. During the VOH tests of 'LS324 and 'LS326, the enable pin should
be at VIL max.
4. For 'LS324 and 'LS326, ICC is measured with the outputs disabled and open, and e Vee = MAX. For 'LS325 and 'LS327, ICC is
measured with one e Vee = MAX, and with the other e Vee and outputs open.

switching characteristics, Vee = 5 V (unless otherwise noted), RL = 667 il, eL = 45 pF, TA = 25°e
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Output frequency
lVI(freq) = 5 v, VI(rnQ) = 0 V 20 30
fo Cext = 2 pF MHz
IVI(freq) = 0 V, VI(rng) = 5 V 11 20
to Output frequency (crystal controlled) eVCC=3V, VI(freq) = Vl(rng) = 0 V 10 20 MHz
Output duty cycle Cext = 8.3 pF to 500 IlF 50%
Propagation delay time,
tpHL to;;' 1 Hz 30+* ns
high·to·low·level output from enable
"'The range input is provided only on the 'LS324. 1 X 109
'The delay will typically be 30 ns pulse up to one period of one cycle (I.e. 30 ns + - - - ns I depending upon the timing of the enable
pulse with respect to the signal generated by the internal oscillator. fo(Hz)

1076

TEXAS INCORPORATED
INSTRUMENTS 7-447
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TTL TYPES SN54LS348, SN74LS348 (TIM9908)
MSI 8-UNE-TO-3-UNE PRIORITY ENCODERS
WITH 3-STATE OUTPUTS
BULLETIN NO. D OCTOBER 1976

SN54LS348 •.. J OR W PACKAGE

• 3-State Outputs Drive Bus Lines Directly SN74LS348 •.• J OR N PACKAGE
(TOP VIEW)
• Encodes 8 Data Lines to 3-Line Binary (Octal)
• Applications Include:
N-Bit Encoding
Code Converters and Generators
• Typical Data Delay ... 15 ns
• Typical Power Dissipation ... 60 mW

description

These TTL encoders feature priority decoding of the

inputs to ensure that only the highest-order data line
is encoded. The 'LS348 circuits encode eight data
lines to three-line (4-2-1) binary (octal). Cascading
circuitry (enable input EI and enable output EO) has positive logic: see function table
been provided to allow octal expansion. Outputs AD,
A1, and A2 are implemented in three-state logic for functional block diagram
easy expansion up to 64 lines without the need for EI {51

external circuitry. See Typical Application Data. 0 1101

,(111
FUNCTION TABLE

INPUTS OUTPUTS
21121
EI 0 1 2 3 4 5 6 7 A2 Al AO GS EO
H X X X X X X X X Z Z Z H H
1131
L H H H H H H H H Z Z Z H L 3

L X X X X X X X L L L L L H

•
L X X X X X X L H L L H L H 4{1'
L X X X X X L H H L H L L H
L X X X X L H H H L H H L H
121
L X X X L H H H H H L L L H 5

L X X L H H H H H H L H L H

~ i~
L X L H H H H H H L L H
L L H H H H H H H H L H

H = high logic level. L = low logic level. X = irrelevant

Z = high-impedance state

schematic of inputs and outputs

EQUIVALENT OF EACH INPUT TYPICAL OF OUTPUTS TYPICAL OF OUTPUTS
EO,ES
VCC----- ------.--VCC ----.--VCC

Req

I NPUT_~f-+-__

OUTPUT L.-----""'--OUTPUT

Inputs 1 thru 7: Req = 9 k.!1 NOM

All others: Req = 18 k.!1 NOM

1076
DESIGN GOAL
7-448 This page provides tentative information on a TEXAS INSTRUMENTS
product in the developmental stage. Texas INCORPORATED
Instruments reserves the right to change or dis· POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
continue this product without notice.
 TYPES SN64LS348, SN14LS348 (TIM9908)
8-LlNE-TO-3-LlNE PRIORITY ENCODERS WITH 3-STATE OUTPUTS

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . 7V
Input voltage . . . . . . . . . . . . . . . . . . . 7V
Operating free-air temperature range: SN54LS348 _55°C to 125°C
SN74 LS348 O°C to 70°C
Storage temperature range -65°C to 150°C
NQTE1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54LS348 SN74LS348
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
AO, A1,A2 -1 -2.6 mA
High-level output current, IOH
EO,GS -400 -400 iJA
AO, A1,A2 12 24 mA
Low-level output current, IOL
EO,GS 4 l3 rnA
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS348 SN74LS348
PARAMETER TEST CONDITIONSt UNIT
MIN TYp:j: MAX MIN TYp:j: MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
VIK Input clamp voltage Vee = MIN, II = -18mA -1.5 -1.5 V
Vee= MIN, IOH =-1 rnA 2.4 3.1
High-level AO, A1, A2
VOH VIH =2 V, IOH = -2.6 mA 2.4 3.1 V
output voltage
EO,GS VIL = VIL max IOH = -400jJ,A 2.5 3.4 2.7 3.4

•
IOL = 12mA 0.25 0.4 0.25 0.4
AO, A1, A2 Vee = MIN,
Low-level IOL=24mA 0.35 0.5
VOL VIH = 2V, V
output voltage IOL=4mA 0.25 0.4 0.25 0.4
EO,GS VIL = VILmax
IOL =8mA 0.35 0.5
Input current at maximum Inputs 1 thru 7 0.2 0.2
II Vee= MAX, VI =7V mA
input voltage All other inputs 0.1 0.1
Inputs 1 thru 7 40 40
IIH High-level input cu rrent Vee =MAX, VI = 2.7 V iJ A
All other inputs 20 20
Inputs 1 thru 7 -0.8 -0.8
IlL Low-level input current Vee = MAX, VI =0.4V mA
All other inputs -0.4 -0.4
Outputs AO, A1, A2 -30 -130 -30 -130
lOS Short-circuit output current§ Vee = MAX mA
Outputs EO, GS -20 -100 -20 -100
Vee = MAX, Condition 1 13 25 13 25
ICC Supply current mA
See Note 2 Condition 2 12 23 12 23

NOTE 2: IcC (condition 1) is measured with inputs 7 and EI grounded, other inputs and outputs open. ICC (condition 2) is measured with all
inputs and outputs open.
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
0
:j: All typical values are at V CC = 5 V, T A = 25 C.
§ Not more than one output should be shorted at a time.

DESIGN GOAL
1076
This page provides tentative information on a
product in the developmental stage. Texas TEXAS IN ST RUM ENTS 7449
Instruments reserves the right to change or dis- I NCORPORAT ED
continue this product without notice. POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54LS348, SN74LS348 (TIM9908)
8-UNE-TO-3-UNE PRIORITY ENCODERS WITH 3-STATE OUTPUTS

switching characteristics, VCC = 5 V, T A = 25 C

0

FROM TO
PARAMETER' WAVEFORM TEST CONDITIONS MIN TYP MAX UNIT
(INPUT) (OUTPUT)
tpLH In-phase 11 17
o thru 7 AO, A1, or A2 ns
tpHL output 20 30
tPLH Out-of-phase 23 35
o thru 7 AO,A1,or A2 ns
tpHL output 23 35
tPLH Out-of-phase 12 18
Othru7 EO ns
tPHL output 6 15
CL = 45pF,
tpLH In-phase 15 23
Othru7 GS RL = 667 n, ns
tpHL output 14 21
See Note 3
tpLH In-phase 11 17
EI GS ns
tPHL output 24 36
tpLH In-phase 14 21
EI EO ns
tPHL output 17 25
tPZH 26 39
EI AO, A1, orA2 ns
tPZL 27 41
tpHZ CL - 5 pF, 18 27
EI AO, Al,or A2 ns
tpLZ RL =667 n 23 35

'tPLH = propagation delay time, low-to-high-Ievel output

tpHL = propagation delay time, high-to-Iow-Ievel output
tpZH = output enable time to high level
tpZL = output enable time to low level
tpHZ = output disable time from high level
tpLZ = output disable time from low level
NOTE 3: Load circuits and waveforms are shown on page 3-11_

TYPICAL APPLICATION DATA

• EO 'lS348 EI ENABLE
INPUT

EO 'LS348 EI

lSB STROBE
OUTPUT

FIGURE l-PRIORITV ENCODER WITH UP TO 64 INPUTS.

1076
DESIGN GOAL
7-450 This page provides tentative information on a TEXAS IN ST RU M ENTS
product in the developmental stage, Texas IN ( Of{ POR ArE D
Instruments reserves the right to change or dis- POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
continue this product without notice.
 TTL TYPE SN74351
MSI DUAL DATA SELECTOR/MULTIPLEXER WITH 3-STATE OUTPUTS
BULLETIN NO. DL-S 761211 MARCH 1974 - REVISED OCTOBER 1976

N
• DuaI8-Line-to-1-Line Multiplexer That DUAL-IN-LINE PACKAGE (TOP VIEW)
Can Replace Two SN54151, SN74151 DATA INPUTS
A
Multiplexers in Some Applications
• Four Common Data Lines Permit Simultaneous
Interdigitation with Parallel-to-Serial Conversion
• 4-Bit Organization Is Easily Adapted to
Handle Binary or BCD
• Three-State Outputs Can Be Connected
Directly to System Bus Lines
• Enable Input Controls Impedance Levels of the
12 Data Inputs and Two Outputs
ABC GND

description '-y---/
SELECT INPUTS DATA INPUTS

The SN74351 comprises two 8-line-to-l-line data logic: see function table
selectors/multiplexers with full decoding on one
monolithic chip. Symmetiically sVvitching, comple-
mentary decode generators minimize decoder skew
functional block diagram
during changes at the select inputs and ensure that
potentially erroneous effects are minimized at the
data outputs. Four data inputs are exclusive to each

j
multiplexer and four are common to both_ A
common enable input is provided which, when high, ::-=-:---H±±±--r--..
causes both outputs to assume the high-impedance 103 (9 )
DATA

:l: :
(off) state and simultaneously diverts the majority of INPUTS 0""",',4,,-' --.,.----;!;±±±:!::±::r-.....
the input current, which reduces the load signifi-
cantly on the data input drivers. A low logic level at

•
the enable input activates both outputs so that each
07(11)
will assume the complement of the level of the
selected input.

~~G~~ {: , : , : t<c-H-+-I4+.1
c (5)

FUNCTION TABLE

INPUTS
OUTPUTS
ENABLE SELECT
G C B A 1Y 2Y
H X X X Z Z
L
L
L
L
L
L
L
L
H
L
H
L
-
100 200
101 201
-
102 202
2
INPUTS
f
DATA :'2i-':=::-----..m"Fl==l.....-/
201",'17-,-' -----+=+=t=:t==l-J
-
L L H H 103 203 200 (8 )
- -
L H L L 04 04
-
L H L H 05 55
L H H L 56 -06
- -
L H H H 07 07

H = high level, L = low level, X = irrelevant

Z = high impedance (off)
1 DO, 151, ... OJ = The complement of the level of the respective
D input

1076

TEXASINCORPORATED
INSTRUMENTS 7451
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPE SN74351
DUAL DATA SELECTOR/MULTIPLEXER WITH 3-STATE OUTPUTS
REVISED OCTOBER 1976

schematics of inputs and outputs

vcc=x=--
EQUIVALENT OF EACH INPUT TYPICAL OF BOTH OUTPUTS
Vce

'N'UT W-- OUTPUT

Enable, DO thru 03: Req = 4 kfl. NOM

04 thru 07: Req = 2 kfl. NOM
A, B, or c: Req = 6.5 kfl. NOM

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) 7V
Input voltage . . . . . . . . 5.5V
Operating free-air temperature range oOe to 700e
0
Storage temperature range -6Soe to 150 e
NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

MIN NOM MAX UNIT
Supply voltage, Vee 4.75 5 5.25 V
High-level output current, IOH -0.8 mA
Low-level output current, IOL 16 mA
Operating free-air temperature, T A a 70 °e
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYp:t: MAX UNIT
VIH High-level input voltage 2 V
Vil low-level input voltage 0.8 V

•
VIK Input clamp voltage Vee= MIN, 11=-12mA -1.5 V
Vee = MIN, VIH=2V,
VOH High-level output voltage 2.4 3.4 V
Vil = 0.8 V, 10H =-0.8 rnA
Vee = MIN, VIH = 2V,
VOL Low-level output voltage 0.2 0.4 V
Vil = 0.8 V, 10l = 16 rnA
Vee= MAX, V:H=2V,
10ZH Off-state output current, high-level voltage applied
I

Vo = 2.4 V
40i I
p.A

Vee = MAX, VIH=2V,

IOZL 'Off state output current,low level voltage applied -40 p.A
Va = 0.4 V
II I nput current at maximum input voltage Vee = MAX, VI = 5.5 V 1 rnA
Enable, any select,
40
High-level input current any DO thru 03 VI = 2.4 V p.A
IIH Vee = MAX,
I I
04 thru 07 80
Enable, any select,
-1.6
any DO thru 03 Vee = MAX, VI = 0.4 V rnA
III low-level input current 04 thru 07 -3.2
Vee= MAX, VI =0.5,
AnyO
VI(enable) = 2 V
-40 p.A

lOS Short-circuit output current § Vee = MAX -18 -55 rnA

lee Supply current Vee= MAX, See Note 2 44 66 rnA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:t:AII typical values are at VCC = 5 V, T A = 25°C.
§Not more than one output should be shorted at a time.
NOTE 2: ICC is measured with the enable input grounded, other inputs and both outputs open.

1076

7-452 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPE SN74351
DUAL DATA SELECTOR/MULTIPLEXER WITH 3-STATE OUTPUTS

switching characteristics, Vee = 5 V, TA = 25°e

FROM TO
PARAMETER~ TEST CONDITIONS MIN TVP MAX UNIT
(INPUT) (OUTPUT)
tpLH 20
A, B,or.C Y ns
tpHL 20
tpLH CL = 50 pF, RL=400n, 10
Any D Y ns
tPHL See Note 3 10
tZH 13
G Y ns
tZL 20
tHZ - CL = 5 pF, RL=400n, 6
G Y ns
tLZ See Note 3 10

~tPLH == propagation delay time, low-to-high-Ievel output

tpH L == propagation delay time, high-to-Iow-Ievel output
tZH == output enable time to high level
tZL == output enable time to low level
tHZ == output disable time from high level
tLZ == output disable time from low level
NOTE 3: Load circuit and voltage waveforms are shown on page 3-10.

TYP!CAL APPLlCAT!ON DATA

This application illustrates how common data can be interdigitated onto two serial data lines. It is useful for
transmitting prefixes, suffixes, addresses, or similar functions.

to t1 t2 t3 t4 t5 t6 t7
A .J""l...1"'"
B ~ SELECT {
!NPUTS
C

•
C B A
100" 100
lO'~O 101
VARIABLE {
102..1 0 DATA 102
103' 1 103 to t1 t2 t3 t4 t5 t6 t7
9 (NEGATIVE LOGIC) 1Y OUTPUT~
D4 1Y - . , . . . . . . - '-v----'
D5 9 6
D6 (POSITIVE LOGIC)
.J
COMM~{
D4 0
D7
D5,1
D6 , DATA SN74351
D7 .J 0 D7
6 (NEGATIVE LOGIC)
D6
D5
D4 to t1 t2 t3 t4 t5 t6 t7
2Y OUTPUT~
2D3.J 0 2D3 2Y· • '''-..r---J
2D2..1 0 2D2 8 6
VARIABLE{ (POSITIVE LOGIC)
2D1.J 0

2DO'
DATA 2D1
2DO
G
I VARIABLE
DATA
I COMMON
DATA
I
8 (NEGATIVE LOGIC;
ENABLE
G

.PRINTED IN USA
374 TI cannot assume any responsibility for any circuits shown
or represenf fhal they are free from patent infringement. TEXAS INSTRUMENTS 7-453
INCORPORATED
TEXAS INSTRUMENTS RESERVES THE RIGHT TO MAKE CHANGES AT ANY TIME POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
IN ORDER TO IMPROVI DESIGN AND TO SUPPLY THE BEST PRODUCT POSSIBLE.
 TTL TYPES SN54LS352, SN74LS352
MSI DUAL 4-LlNE-TO-1-LlNE DATA SELECTORS/MULTIPLEXERS
BULLETIN NO. DL-S 7612463, OCTOBER 1976

• Inverting Versions of SN54LS153, SN74LS153 SN54LS352 ••• J OR W PACKAGE

SN74LS352 ••• J OR N PACKAGE
• Schottky-Diode-Clamped Transistors (TOPVIE~I

• Permits Multiplexing from N lines to 1 line

• Performs Parallel-to-Serial Conversion
• Typical Average Propagation Delay Times:
Data Input to Output ... 15 ns
Strobe Input to Output ... 19 ns
Select Input to Output ... 22 ns
• Fully Compatible with most TTL and DTL
Circuits
• Low POVler Dissipation ... 31 mW Typical
(Enabled)
• Inverted Data
logic: see function table

FUNCTION TABLE
SELECT
DATA INPUTS STROBE OUTPUT
INPUTS
B A CO C1 C2 G y
description C3
X X X X X X H H
Each of these Schottky-clamped data selectors/- L L L X X X L H

•
multiplexers contains inverters and drivers to supply L L H X X X L L
fully complementary, on-chip, binary decoding data L H X L X X L H
selection to the AN D-OR-invert gates. Separate strobe L H X H X X L L
inputs are provided for each of the two four-line H L X X L X L H
sections. H L X X H X L L
H H X X X L L H
I H H I X X X H I L L

Select inputs A and B are common to both sections.

H = high level, L = low level, X = irrelevant

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . 7V
Input voltage . . . . . . . . . . . . . . . . . 7V
Operating free-air temperature range: SN54LS352 _55° e to 125°C
SN74LS352 oOe to 70°C
Storage temperature range . -65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

1076

7-454 TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54LS352. SN74LS352
DUAL 4-UNE-TO-1-UNE DATA SELECTORS/MULTIPLEXERS

functional block diagram

STROBE lG (1)
(ENABLE)
lCO --------+-+-+-!

(5)
lCl -------+-+-IH-"i....-..,I

DATA 1
(4)
lC2-----+-f---++-f-L~

lC3 (3)

r
~""l'~

DATA2jr: :::',

2C2 (12)

2C3 (13)

STROBE2G
(ENABLE) (15)

schematics of inputs and outputs

EQUIVALENT OF EACH INPUT TYPICAL OF BOTH OUTPUTS II

----------------.-----VCC

VCC----------e~------
fio.l1 NOM

20 k.l1 NOM

INPUT·-~_""'~---'-
OUTPUT

1076

TEXAS INCORPORATED
INSTRUMENTS 7-455
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54LS352, SN74LS352
DUAL 4-UNE-TO-1-UNE DATA SELECTORS/MULTIPLEXERS

recommended operating conditions

SN54 LS352 SN74LS352
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -400 -400 ",A
Low-level output current, 10L 4 S mA
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS352 SN74LS352
PARAMETER TEST CONDITIONSt UNIT
MIN TYp:j: MAX MIN TYp:j: MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 O.S V
VIK Input clamp voltage Vce= MIN, 11=-lSmA -1.5 -1.5 V
Vee = MIN, VIH = 2V,
VOH High-level output voltage 2.5 3.4 2.7 3.4 V
VIL = VIL max, 10H = -400 ",A
Vee= MIN, VIH=2V, IIOL =4mA 0.25 0.4 0.25 0.4
VOL Low-level output voltage V
VIL = VIL max IIOL -SmA 0.35 0.5
Input current at
II Vce= MAX, VI =7 V 0.1 0.1 mA
maximum input voltage
IIH High-level input current Vee = MAX, VI = 2.7V 20 20 ",A
IlL Low-level input current Vee- MAX, VI- 0.4 V -0.4 -0.4 mA
lOS Short-circuit output current § Vee = MAX -20 -100 -20 -100 mA
leeL Supply current, output low Vee- MAX, See Note 2 6.2 10 6.2 10 mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating.
:j:AII typical values are at VCC = 5 V, T A = 25°C.
§Not more than one output should be shorted at a time,and duration of the short-circuit should not exceed one second.
NOTE 2: ICCL is measured with the outputs open and all inputs grounded.

II switching characteristics, Vee = 5 V, TA = 25°e

I I !OU:~UT! ! IMIN
FROM
PARAMETER' TEST CONDITIONS TYP MAXIUNITI
!INPUT!
tpLH Data Y 13 20 ns
tpHL Data Y 17 26 ns
eL = 15 pF,
tPLH Select Y 19 29 ns
RL =2 kn,
tpHL Select Y 25 38 ns
See Note 3
tPLH Strobe Y 16 24 ns
tPHL Strobe Y 21 32 ns

1 tPLH == propagation delay tlrne, low-to-high-Ievel output

tpHL == propagation delay tim", high-to-Iow·level output
NOTE 3: Load circuits and voltage waveforms are shown On page 3-11.

1076

7456 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TTL TYPES SN54LS353. SN74LS353
DUAL 4-UNE-TO-l-UNE DATA SELECTORS/MULTIPLEXERS
MSI WITH 3-STATE OUTPUTS
BULLETIN NO_ DL-S 7612464, OCTOBER 1976

SN54LS353 _ . _J OR W PACKAGE
SN74LS353 _ •. J OR N PACKAGE
(TOP VIEW)
• Inverting Versions of SN54LS253, SN74LS253
OUTPUT
CONTROL DATA INPUTS
• Schottky-Diode-Clamped Transistors ~ ____ -JA~ ______ ~

• Permits Multiplexing from N Lines to 1 Line

• Performs Parallel-to-Serial Conversion
• Typical Average Propagation Delay Times:
Data Input to Output ... 12 ns
Control Input to Output ... 16 ns
Select Input to Output ... 21 ns
• Fully Compatible with Most TTL and DTL
Circuits
• Low Power Dissipation ... 35 mW Typical
(Enabled) ~----~vr------~
DATA INPUTS
• Inverted Data
logic: see function table
description
Each of these Schottky-clamped data selectors/multiplexers contains inverters and drivers to supply fully
complementary, on-chip, binary decoding data selection to the AND-OR-invert gates. Separate output control inputs are
provided for each of the two four-line sections.

The three-state outputs can interface with and drive data lines of bus-organized systems. With all but one of the
common outputs disabled (at a high-impedance state) the low-impedance of the single enabled output will drive the bus
line to a high or low logic level.

logic
FUNCTION TABLE
SELECT OUTPUT
INPUTS
B
X
A
X
CO
X
DATA INPUTS

Cl
X
C2
X
C3
X
CONTROL
G
H
OUTPUT
y
Z
II
L L L X X X L H
L L H X X X L L
L H X L X X L H
L H X H X X L L
H L X X L X L H
H L X X H X L L
H H X X X L L H
H H X X X H L L
Select inputs A and B are common to both sections.
H = high level, l = low level, X = irrelevant, Z = high impedance (off)

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) 7V
Input voltage . . . . . . . . . 7V
Off-state output voltage . . . . . 5.5 V
Operating free-air temperature range: SN54LS353 -55°C to 125°C
SN74LS353 aOe to 7aoe
Storage temperature range . . . . -65°C to 15aoe
NOTE 1: Voltage values are with respect to network ground terminal.

1076

TEXAS INSTRUMENTS 7-457

INCORPORATED
POST OFFICE BOX 5012 • CALLAS. TEXAS 75222
 TYPES SN54~S353, SN14LS353
DUAL 4-LlNE-TO-l-LiNE DATA SELECTORS/MULTIPLEXERS
WITH 3-STATE OUTPUTS
functional block diagram
OUTPUT
CONTROL
IG

1C1J(5~)----------~~~t-~
DATA 1

(2)

SELECT{ B
A (14)

2CO (10)

2C1 (11)

DATA 2
OUTPUT
2Y

II
OUTPUT (15)
CONTROL
2G

schematics of inputs and outputs

EQUIVALENT OF EACH INPUT TYPICAL OF BOTH OUTPUTS

---->--Vee
Vee
20 kn NOM

INPUT ......
_IW
-- OUTPUT

~~ .... '
~,

n'T

1076

7-458 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54LS353, SN14LS353
DUAL 4-UNE-TO-1-UNE DATA SELECTORS/
MULTIPLEXERS WITH 3-STATE OUTPUTS

recommended operating conditions

SN54LS353 SN74LS353
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, VCC 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -1 -2.6 mA
Low-level output current, 10L 4 8 mA
Operating free-air temperature, T A -55 125 0 70 °c

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS353 SN74LS353
PARAMETER TEST CONDITIONSt UNIT
MIN TYP+ MAX MIN TYP+ MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
VIK I nput clamp voltage VCC= MIN, II = -18 mA -1.5 -1.5 V
VCC = MIN, VIH=2V,
VOH High-ievei output voitage 2.4 3.4 2.4 3.1 V
VIL = VIL max, 10H = MAX
VCC= MIN, VIH=2V, 10L = 4 mA 0.25 0.4 0.25 0.4
VOL Low-level output voltage \ / .• _ \ / •• '-""1
1 ___ 0_1\
n ':Ie:
V
VIL- VIL"'Oro. 'UL.- v III'" V.V

Off-State (high-impedance Vo = 2.7 V 20 20

I~-
·u£. Vee = ~.4.6,X, VIH =2 V ;.:.A
state) output current Vo = 0.4 V -20 -20
Input current at
II Vee= MAX, VI = 7 V 0.1 0.1 mA
maximum input voltage
IIH High-level input current VCC = MAX, VI=2.7V 20 20 !J.A
IlL Low-level input current VCC = MAX, VI = 0.4 V -0.4 -0.4 mA
lOS Short-circuit output current § Vce = MAX -30 -130 -30 -130 mA
Condition A 7 12 7 12
lec Supply current VCC = MAX, See Note 2 mA
Condition B 8.5 14 8.5 14

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAli tvpical values are at V CC = 5 V, T A = 25° C.
§Not more than one output should be shorted at a time, and duration of the short-<:ircuit should not exceed one second.
NOTE 2: ICC is measured with the outputs open under the following conditions:
A. All inputs grounded.
B. Output control at 4.5 V, all inputs grounded. I
switching characteristics, Vee = 5 V, TA = 25°e
FROM TO
PARAMETER~ TEST CONDITIONS MIN TYP MAX UNIT
(INPUT) (OUTPUT)
tpLH 11 25
Data Y ns
tpHL 13 20
tPLH CL=15pF, RL=2kSl, 20 45
Select y ns
tpHL See Note 3 21 32
tpZH Output 11 23
y ns
tpZL Control 15 23
tpHZ Output CL=5pF, RL = 2 kn, 27 41
Y ns
tpLZ Control See Note 3 12 27
~ tp LH == Propagation delay time, low-to-high-Ievel output
tpHL == Propagation delay time, high-to-Iow-Ievel output
tPZH== Output enable time to high level
tpZL == Output enable time to low level
tpHZ == Output disable time from high level
tpLZ == Output disable time from low level
NOTE 3: Load circuit and waveforms are shown on page 3-11.

1076

TEXAS I'CORPORATED
INSTRUMENTS 7-459
POST OFFICE BOX 5012 • DALLAS, TEXA.S 75222
 TTL TYPE SN74LS362 (TIM9904)
MSI FOUR-PHASE CLOCK GENERATOR/DRIVER
BULLETIN NO. DL-S 7612476, OCTOBER 1976

SN74LS362 •.• J OR N PACKAGE

• Clock Generator/Driver for The (TOP VIEW)
TMS 9900 or Other Microprocessors
osc osc ;P2 ;\1
• High-Level 4-Phase Outputs IN OUT TTL TTL Voo ,,1 <1>2

• Complementary TTL 4-Phase Outputs

• Self-Contained Oscillator Can be
Crystal or Capacitor Controlled IN OUT

• External Oscillator Can Be Used TANK 1 <1>2

• Clocked D-Type Flip-Flop With

Schmitt-Trigger Input For Reset
Signal Synchronization

description TANK TANK GNO FFQ FFO 1>3 <1>4 GNO

2
2 1 TTL TTL

The 'LS362 consists of an oscillator, divide-by-four counter, a second divide-by·four counter with gating to generate
four clock phases, high-level (12-volt) output drivers, low-level (5-volt) complementary output drivers, and a Ootype
flip-flop controlled by an external signal and the cp3 clock. The four high-level clock phases provide clock inputs to a
TMS 9900 microprocessor. The four complementary TTL-level clocks can be used to time memory or other logic
functions in a TMS 9900 computer system. The Ootype flip-flop can be used to provide (for example) a reset signal to a
TMS 9900, timed by cp3, on receipt of an input to the FFO input from power turn-on or a manual switch closure. Other
applications are possible. A safety feature has been incorporated in the cp outputs such that if an open occurs in the
VCC supply common to 'LS362 and TMS 9900, the cp outputs will go low thus protecting the TMS 9900.

The frequency of the internal oscillator can be established by a quartz crystal or capacitor and LC circuit. Either a
fundamental or overtone crystal may be used. The LC circuit connected to the tank inputs selects the desired crystal
overtone or establishes the internal oscillator frequency when a capacitor is used instead of a crystal. An LC circuit
must always be used at the tank inputs when using the internal oscillator. An external oscillator can be used, if desired,
see "Applications Information" for details.

typical phase relationships of inputs and outputs (OSC is internal)

OSCIN .-J
osc
OSCOUT~______~r-l~ ______~r-l~_________~r-l~______~r-l~______~r-l~______~r-l~__________~
¢1-'~ ______________________________~

¢2---.J
¢3 ______________~

~---------------------------------~
q;1 .-J
"¢2 ----,~_______J
q;3-------------------,~ ______~
q;4
FFD
FFO- - - - - - - - - - - -I

DESIGN GOAL 1076

This page provides tentative information on a
7-460 product in the developmental stage. Texas TEXAS INSTRUMENTS
INCORPORATED
Instruments reserves the right to change or dis-
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
continue thjs product without notice.
 TYPE SN74LS362 (TIM9904)
FOUR-PHASE CLOCK GENERATOR/DRIVER

functional block diagram

(1)
TANK 1

(2)
TANK 2
OSCILLATOR
(1S)
XTAL1

(19)
XTAL2

I~
OSC!N--'("-17::...:.)----~~~-----__=------y--' 1· L-II
~V
- - - - OSCOUT
(16)

r 12..VSECTiON--,
n-_~....:-I----t1 I (12) ¢1

I I
I (11)
¢2

IS) ¢3

(9) ct>4
I
(14) _
¢1TTL

(15) ~2TTL

(7) ~3TTL

(6) ~TTL

(4)
FFD FFQ

DESIGN GOAL
1076
This page provides tentative information on a
product in the developmental stage. Texas TEXAS INSTRUMENTS 7-461
I nstruments reserves the right to change or dis· INCORPORATED
continue this product without notice. POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPE SN14LS362 (TIM9904)
FOUR-PHASE CLOCK GENERATOR/DRIVER
schematics of inputs and outputs

EQUIVALENT OF D INPUT EQUIVALENT OF OSCIN INPUT EQUIVALENT OF XTAL 1 AND

XTAL 2 INPUTS

Vee---.--- Vee
Vee---.---
20 kn NOM

I NPUT ---1f-:"11e-~-.-
INPUT
INPUT

GNDl GND 1
GND 1

EQUIVALENT OF TYPICAL OF TYPICAL OF OSCOUT. Q. AND

TANK INPUTS q,1. </>2. </>3 AND c/>4 OUTPUTS ALL ;-TTL OUTPUTS
-----.--Vee
V e e - - -.....- -4~---~-e--VDD

----e-~~~~OUTPUT L-.~'--OUTPUT

I NPUT-.....- -..

GND1

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
I Supply voltage: Vee (see Note 1)
VDD (see Note 1)
. 7V
13V
Input voltage: OSelN . . . . . 5.5 V
FFO . . . . . , -0.5 V to 7 V
Operating free-air temperature range aOe to 7aoe
Storage temperature range -65°e to 15aoC
NOTE1: Voltage values are with respect to the network ground terminals connected together.

recommended operating conditions

I MIN NOM MAX I UNIT
Vee 4.75 5 5.25 V
Supply voltages
VDD 11.4 12 12.6 V
</>1,</>2,</>3, </>4 -100 iJA
High-level output current, IOH
All others -400 iJA
</>1,</>2,</>3,</>4 4 rnA
Low-level output current, IOL
All others 8 rnA
I nternal oscillator frequency, f osc 48 54 MHz
External oscillator pulse width, tw(oscl 25 ns
Setup time, FFD input (with respect to falling edge of </>3), tsu 50 ns
Hold time, F F D input (with respect to falling edge of </>3), th -30 ns
Operating free-air temperature, T A 0 70 °e

DESIGN GOAL
1076

7-462 ;~~~:C~gei~r~~i:e~;~~I::~~:ni;aflor:aa~!~\~~a: TEXAS IN ST RUM ENTS

Instruments reserves the right to change or dis· INCORPORATED
continue this product without notice. POST OFFICE BOX"S012 • DALLAS. TEXAS 75222
 TYPE SN74LS362 (TIM9904)
FOUR-PHASE CLOCK GENERATOR/DRIVER

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP+ MAX UNIT
VIH High-level input voltage 2 V
low-level FFD 0.5
Vil V
input voltage OSelN 0.8
VT+-VT- Hysteresis FFD 0.4 0.8 V
VIK Input clamp voltage Vee ~4.75 V, VDD -11.4 V, 11--18mA -1.5 V
High-level ct>1, ct>2,i/>3, ct>4 Vee ~ 4.75 V, 10H ~-100~A VDD-2 VDD-1.5 VDD
VOH V
output voltage Other outputs VDD ~ 11.4 Vto 12.6 V 10H - -400~A 2.7 3.4
ct>1,ct>2,ct>3,ct>4 10l =4 mA 0.25 0.4
low-level
VOL Vee =4.75 V, VDD = 11.4 V 10l -4 mA 0.25 0.4 mA
output voltage Other outputs
10l =8 mA 0.35 0.5
I nput current at FFD VI =7 V 0.1
II Vee = 5.25 V, VDD = 12.6 V mA
maximum input voltage OSelN VI ~ 5.5 V 0.3
High-level t-FD 20
IIH Vee = 5.25 V, VDD = 12.6 V, VI = 2.7 V ~A
input current oselN 60
low-level FFD -0.4
'IL VCC ~ 5.25 V, VDD ~ i2.6 V, VI = 0.4 V mA
input current OSelN -3.2

lOS
Short~circuit

output current+
All except
ct>1, ct>2,ct>3,ct>4
Vee ~ 5.25 V
I
-20 -100 I mA

Vec = 5.25 V, FFD and OSelN at GND,

ICC Supply current from Vce 105 175 mA
Outputs open
Vee = 5.25 V, VDD = 12.6 V,
IDD Supply current from VDD 12 20 mA
FFD and OSCIN at GND, Outputs open

t All typical values are at VCC = 5 V, VDD ~ 12 V, T A = 25°C.

+ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second. Outputs ct>1, ct>2, ct>3,
and ct>4 do not have short-circuit protection.

switching characteristics, TA = 25°C, VCC1 = 5 V, VCC2 = 12 V, fosc = 48 MHz, see figure 1

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f out Output frequency, any ct> or ct> TTL 3 MHz
f out
tc{ct>l
Output frequency, OSeOUT
eycle time, any <I> output
12
333
MHz
ns
I
tr{ct>l Rise time, any ct> output 10 20 ns
tf{ct>l Fall time, any ct> output 10 20 ns
tw{ct>l Pulse width, any ct> output high 40 ns
1<f>ll,ct>2H Delay time, ct>1 low to ct>2 high 0 5 15 ns
1<f>2l,ct>3H Delay time, ct>2 low to ct>3 high 0 5 15 ns
1<f>3l ct>4H Delay time, ct>3 low to ct>4 high 0 5 15 ns
tct>4l,<I>lH Delay time, ct>410w to ct>1 high Output loads: 0 5 15 ns
tct>lH,ct>2H Delay time, <1>1 high to <1>2 high ct>1,<I>3,ct>4: 100pF toGND 70 83 ns
tct>2H, ct>3H Delay time, <1>2 high to ct>3 high ct>2: 200 pF to GND 70 83 ns
1<f>3H,ct>4H Delay time, ct>3 high to ct>4 high Others: Rl = 2 kU, 70 83 ns
tct>4H, ct>lH Delay time, ct>4 high to ct>1 high Cl = 15 pF 70 83 ns
1<f>H,ct>Tl Delay time, <l>n high to ct>n TTL low See Note 2 --8 ns
1<f>l,<I>TH Delay time, ct>n low to ct>n TTL high -19 ns
tct>3l,QH Delay time, <1>3 low to FFQ output high -7 ns
1<f>3l,Ql Delay time"ct>3 low to FFQ output low -12 ns
1<f>l,OSOH Delay time, ct> low to OSeOUT high -5 ns
1<f>H,OSOl Delay time, FFQ high to OSeOUT low -13 ns

NOTE 2: Use load circuit for bi-state totem-pole outputs, page 3-11.

DESIGN GOAL
1076
This page provides tentative information on a
product in the developmental stage, Texas TEXAS INCORPORATED
INSTRUMENTS 7-463
Instruments reserves the right to change or dis-
continue this product without notice. POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 .....
J::,.
CD
-'='"

1/>1 9.4V
~
I"- t l/>1H,1/>2H--IIi
9.4 V :
t~
- I4-- t I/>4H,1/>1H4t
:..pr:4V\
~
."
e-<
C~
::am
.....

0.7 V I4-twl/> 0.7 V i i 0.7 V J \ -acn

trl/>-tojt+ -a./l4-tfl/> r4-trp2H,1/>3H-II>I I I ~----------------
I =z
:. .....
~
~ 9.4 V : I ~-:-trp4L,1/>1H !K9.4V cn~
1/>2 trp1L,1/>2H
- ____~~J
I 1I II II I~ _____________ m~
I+- t I/>3H,1/>4H--+I nW
1/>3 I I
tI/>2L.1/>3H~
1

_ _ _ _ _ _ _.:..1_ _ _1:-,;;0.,;.;.7_V;..."
1
1\.4 V
0.7 V
II
I
I
I1
1
I
II
I 0.7 V
J -\:l=-.;;.;0.~7..:.V_ _ _ __ ."
r-crt
eN
n-
»

~
1/>4
1
I.I
I
I
II trp3L,4H
YDC
1
~94V
. I1
I :.

;0.7 V
I
II
I
1
II
I
I
I
II
IL JJ
»
s:
m
-I
=-=~
C')i:
meD
zeD
[TI I 1 I m
I I mc::::t
><
);-
(J)
z_
q>1 U J ~tl/>L,I/>TH: U JJ
s:
m
~
::a~
:.-
.....
8z
~C/J
0-1
~iC
.2
trpH,I/>TL~

,.
3V
~

UUV i
I,--_ _•...-llf--_ _ _ _ _ _ _ _ _ _ _ _ _......,

W c:
JJ
m
s:m
e
::a
........
c.
-<
::a
~c:
03::
[TI
q>3 \
\.--+1I
: :I I
I
UJi
I
2:
-I
Z
."
m
::a
z I I I I o
-I
C/J Q>4 U· t,/,L
trpH,~SOL-.I!.-:
OSOH~
"1 I
I
II
\
L-.J
r JJ
s:
~
'I' ,T"
o2:
{\ {\ {\~
FFD
INPUT

FFQ
OUTPUT

FIGUFtE 1-SWITCHING CHARACTERISTICS. VOLTAGE WAVEFORMS

oo,J
m
 TYPE SN74LS362 (TIM9904)
FOUR-PHASE CLOCK GENERATOR/DRIVER

APPLICATION INFORMATION
Figure 2 shows the 'LS362 connected to a TMS9900. The oscillator is shown operating with a quartz crystal and an
LC circuit connected to the tank terminals.
For operation of the TMS 9900 microprocessor at 3 MHz, the frequency reference will need a resonant frequency of
48 MHz (16 x 3 MHz). A quartz crystal used as a frequency reference should be made for series-mode operation with a
resistance in the 20~ to 75-ohm range and be capable of a minimum of 2 mW power dissipation. Typical frequency
tolerance is ±O.005%. For 48·MHz o"peration a third-overtone crystal is used. The inductance L connected across the
tank terminals should be 0.47 pH ± 10%, and the capacitance C (including board capacity) should be 22 pF ± 5%. The
LC circuit should be tuned to the third·overtone crystal frequency for best results. A 0.1-pF capacitor can be substi-
tuted for the quartz crystal. With a capacitor rather than a crystal, the LC tuned circuit establishes the operating
frequenCies. LC component values for operation at any frequency can be computed from fosc = 1/(2tryLC) where
fosc is the oscillator frequency, L is the inductance value in henries, and C is the capacitance value in farads.
When the internal oscillator is being used, OSCIN should be connected to VCC through a resistor (1 kSl nominal) and
an LC tank circuit must be connected to the tank inputs. An external oscillator can be uSed by connecting it to OSCIN
and disabling the internal oscillator by connecting the crystal terminals to VCC and leaving the tank inputs open. An
external oscillator must have a frequency four times the desired output clock frequency and a 25% duty cycle. See
Figure 3.

The first iow-ievei externai dock puise wiii preset the divide-by-four counter, allowing the external oscillator signal to
directly drive the phase generator. Figure 3 is a timing diagram illustrating operation with an external oscillator.

Resistors between <1>1, <1>2, <1>3, and <1>4 outputs of the 'LS362 and the corresponding clock input terminals of the TMS
9900 should be in the 10- to 20-ohm range (See Figure 2). Their purpose is to minimize overshoot and undershoot.
The required resistance value"is dependent on circuit layout. Clock signal interconnectionsshould be as short as possible.

The D-type flip-flop associated with pins FFD and FFQ can be used to provide a power-on reset and a manual reset to
the TMS 9900 as shown in Figure 4. A Schmitt-trigger circuit" driving the D input generates a fast-rising waveform when
the input voltage rises to a specific value. At power turn-on, voltage across the 0.1 pF capacitor in Figure 4 will rise
towards VCC. This circuit provides a delay that resets the TMS 9900 after VCC has stabilized. An optional manual
reset switch can be connected to the delay circuit for resetting the TMS 9900 at any time. The TMS 9900 HOLD
signal could alternately be actuated by FFD.
The ground terminals GND1 and GND2 shoulq be connected together and to system ground. I
¢1 R
XTAL1 <1>1

QUARTZ
CRYST AL c:::J XT AL 2 <1>2 R ¢2
'LS362 TMS 9900
TANK 1 (TIM9904) q,3 R q,3 MICROPROCESSOR
CLOCK
DRIVER <t>4 R q,4
TANK2

+5 V +12 V
FIGURE 2-'LS362 CRYSTAL-CONTROLLED OPERATION

1076

TEXAS II'oCORPORATED
INSTRUMENTS 1-465
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPE SN14LS362 (TIM9904)
FOUR-PHASE CLOCK GEN'ERATOR/ORIVER

APPLICATION INFORMATION

OSCIN

q,2 _ _ _ _..J~ ......_ _ _ _ _ _ _ _ ~r

q,3-------------------------------------------J~~_________________________

q,4----------------------------------J~~____________________________
FIGURE 3-EXTERNAL OSCILLATOR TIMING

I
VCC 'LS362
(TIM9904)
TMS 9900
10kn MICROPROCESSOR
100.n
FFQ
D Q 1----+---=-1
RESET

OPTIONAL
MANUAL RESET
SWITCH
FIGURE 4-POWER-ON RESET

1076

7-466 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54LS363, SN54LS364, SN74LS363, SN74LS364
TTL
OCTAL D-TYPE TRANSPARENT LATCHES AND
MSI EDGE-TRIGGERED FLIP-FLOPS
BULLETI N NO. DL-S 7612466, OCTOBER 1976

• High VOH ... 3.65 V Min ( 74LS') SN54LS363 ... J PACKAGE

SN74LS363 ..• J OR N PACKAGE
• Choice of 8 Latches or 8 D-Type Flip-Flops (TOP VIEW)
I n a Single Package
• 3-State Bus-Driving Outputs
• Full Parallel-Access for Loading and Reloading
• Buffered Control Inputs
• Clock/Enable Input Has Hysteresis to Improve
Noise Rejection and P-N-P Inputs To Reduce
D-C Loading
• SN54LS373/SN74LS373 and SN54LS374/
OUTPUT
SN74LS374 Are Similar But Have Standard CONTROL

V OH of 2.4 V Min
logic: see function table
'LS363
FUNCTION TABLE
SN54LS364 •.• J PACKAGE
OUTPUT ENABL.E
D OUTPUT SN74LS364 .•• J OR N PACKAGE
CONTROL G (TOP VIEW)
L H H H
L H L L Vee
L L X 00
H X X Z

'LS364
FUNCTION TABLE

I
. _. I
CLOCK D
I
OUTPUT
CONTROL
L t H H
L t L L
L
H
L
X
X
X
00
Z I
See explanation of function tables on page 3--8.
logic: see function table

description
These 8-bit registers feature totem-pole three-state outputs designed specifically for driving highly-capacitive or
relatively low-impedance loads. The high-impedance third state and increased high-logic-level drive provide these
registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without
need for interface or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
The eight latches of the 'LS363 are transparent D-type latches meaning that while the enable (G) is high the Q outputs
will follow the data (D) inputs. When the enable is taken low the outputs will be latched at the level of the data that
was setup.
The eight flip-flops of the 'LS364 are edge-triggered D-type flip-flops. On the positive transition of the clock the Q
output will be set to the logic state that was setup at the D input. The 'LS363 is particularly useful for interfacing to
MaS logic where a higher than normal VOH level is desirable such as that required by the TMS 8080A microprocessor.
Schmitt-trigger buffered inputs at the enable (,LS363) and clock (,LS364) lines simplify system design as ac and dc
noise rejection is improved by typically 400 mV due to the input hysteresis. A buffered output control input can be
used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the
high-impedance state the outputs neither load nor drive the bus line significantly.

1076 DESIGN GOAL

This page provides tentative information on a TEXAS INS T RUM EN T S 7-467

product in the developmental stage. Texas INCORPORATED
I nstruments reserves the right to change or d is- POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
continue this product without notice.
 TYPES SN54LS363, SN54LS364, SN74LS363, SN74LS364
OCTAL D-TYPE TRANSPARENT LATCHES AND
EDGE-TRIGGERED FLIP-FLOPS
functional block diagram
Same as SN54LS373/SN74LS373 and SN54LS374/SN74LS374

-
schematics of inputs and outputs
EQUIVALENT OF DATA AND
OUTPUT CONTROL INPUTS
VCC
'LS363

EQUIVALENT OF ENABLE INPUT

V C C - - -......- -
TYPICAL OF ALL OUTPUTS

o
Req

INPUT --
INPUT

Data: Req = 20 k!1 NOM

Output control: Req = 18 k!1 NOM

- -
'LS364

EQUIVALENT OF EQUIVALENT OF OUTPUT EQUIVALENT OF TYPICAL OF ALL OUTPUTS

DATA INPUTS CONTROL INPUT CLOCK INPUT

V C C - - -......- -
VCC vcc

a o
30 k!1 NOM 18 k!1 NOM

INPUT -- INPUT -- INPUT OUTPUT

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

I Supply voltage, Vee (see Note 1)

Input voltage
7V
7V
Off-state output voltage 7V
Operating free-air temperature range: SN54LS' _55°C to 125°C
SN74LS' oOe to 70°C
Storage temperature range -65°C to 150°C
NOTE 1: Voltage values are with respect to network ground tarminal.

recommended operating conditions

: -_ _ _S_N_5_4L_S_'_ _ _t -_ _ _S_N_7_4_LS_'_ _ _--1' UNIT I
MIN NOM MAX I MIN NOM MAX I I
Supply voltage, VCC 4.5 5 5.5 4.75 5 5.25 V
High-lell9l output voltage, VOH 5.5 5.5 V
High·level output current, IOH -1 -2.6 mA
High 15 15
Width of clock/enable pulse, tw ns
Low 15 15
'LS363 O.j, O.j,
Data setup time, tsu ns
'LS364 20t 20t
'LS363 10.j, 10.j,
Data hold time, th ns
'LS364 Ot Ot
Operating free-air temperature, T A -55 125 0 70 °c
t.j, The arrow indicates the transition of the clock/enable input used for reference: t for the low-to-high transition, .j, for the high-to-Iow transi
tion.

DESIGN GOAL 1076

7-468
This page provides tentative information on a
product in the developmental stage. Texas
TEXAS INCORPORATED
INSTRUMENTS
Instruments reserves the right to change or dis- POST OFFICE BOX !5012 • DALLAS, TEXAS 75222
continue this product without notice.
 TYPES SN54LS363, SN54LS364, SN74LS363, SN74LS364
OCTAL D-TYPE TRANSPARENT LATCHES AND
EDGE-TRIGGERED FLIP-FLOPS
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS' SN74LS'
PARAMETER TEST CONDITlONSt UNIT
MIN TYP:j: MAX MIN TYP:j: MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
VIK Input clamp voltage Vee = MIN, 11=-18mA -1.5 -1.5 V
VCC = MIN, VIH=2V,
VOH High-level output voltage 3-45 3.65 V
VIL = VI Lmax, IOH = MAX
Vee = MIN, VIH = 2 V, IIOL = 12 rnA 0.25 0.4 0.25 0.4
VOL Low-level output voltage V
VIL = VILmax 1ioL = 24 rnA 0.35 0.5
Off-state output current, Vee = MAX, VIH = 2 V,
IOZH 20 20 p.A
high-level voltage applied Vo = 3.65 V
Off-state output current, Vee = MAX, VIH=2V,
IOZL -20 -20 p.A
low-level voltage applied Vo = 0.4 V
input current at
II Vee = MAX, VI =7 V 0.1 0.1 rnA
maximum input voltage
IIH High-level input current Vee = MAX, VI=2.7V 20 20 p.A
ilL Low-level input current Vee = MAX, VI = 0.4 V -400 -400 p.A
lOS Short·circuit output current§ Vee = MAX -30 -130 -30 -i30 rfiA
lee Supply current Vee= MAX, Output control at 4.5 V 42 70 42 70 rnA

t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at VCC = 5 V, T A = 25°C_
§ Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second.

switching characteristics, Vee = 5 V, T A = 25° C

FROM TO 'LS363 'LS364
PARAMETER TEST CONDITIONS UNIT

•
(INPUT) (OUTPUT) MIN TYP MAX MIN TYP MAX
f max 35 50 MHz
tPLH 15 23
Data Any Q ns
tpHL 18 27
eL=45pF, RL=667n,
tpLH Clock or 19 30 21 33
Any Q See Notes 2 and 3 ns
tpHL enable 24 36 22 34
tPZH Output 16 28 16 28
Any Q ns
tPZL Control 22 36 22 36
tPHZ Output eL=5pF, RL = 667 n, 12 20 10 18
Any Q ns
tPLZ Control See Note 3 16 25 14 24

NOTES: 2. Maximum clock frequency is tested with all outputs loaded.

3. See load circuits and waveforms on page 3-11.

f max == maximum clock frequency

tpLH == propagation delay time, low-to-high-Ievel output
tpH L == propagation delay time, high-to-Iow-Ievel output
tpZH == output enable time to high level
tpZL == output enable time to low level
tpHZ == output disable time from high level
tpLZ == output disable time from low level

DESIGN GOAL
1076
This page provides tentative information on a
product in the developmental stage. Texas
Instruments reserves the right to change or dis-
TEXAS INCORPORATED
INSTRUMENTS 7-469
continue this product without notice. POST OFFICE SOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54LS363, SN54LS364, SN74LS363, SN74LS3~~
OCTAL D-TYPE TRANSPARENT LATCHES AND
EDGE-TRIGGERED FLIP-FLOPS
TYPICAL APPLICATION DATA
IIIDIRECTIONAL BUI DflIVER
OUTPUT
CONTROL 1
~
10 A 10

2D 20
3D 30
BIDIRECTIONAL 0 40 BIDIRECTIONAL
'LS364 DATA BUS 2
DATA BUS 1 SO
I-
I- SO
70 70
0 ~ 80
) CLOCK 2
CLOCK 1
(
'--10 V 10 t--
_20 CK 20 t--

-30 30 t--
'---40
'LS364
40 r----
-SO 50 t - - - - -
SO 60
70 70
80 A 80

Y OUTPUT
CONTROL 2

CLOCK1H5Lr

::HANGEL-j

CLOCK CLOCK 2 H Lr

CLOCK CIRCUIT FORBUS EXCHANGE

II EXPANDABLE ~RD4Y~IT GENERAL REGIITER FILE

SN74LS364

G YO SN74LS364
Y1

A Y2
ENABLE SELECT {
B Y3 SN74LS364

SN74LS364

1/2 SN74LS139

Cusci LS
SELECT CLOCK

1076

7470 TEXAS INCORPORAfED

INSTRUMENTS
POST OFF1CE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54LS373, SN54LS374, SN54S373, SN54S374,
TTL SN74LS373, SN74LS374, SN74S373, SN74S374
MSI OCTAL D-TYPE TRANSPARENT LATCHES AND
EDGE-TRIGGERED FLIP-FLOPS
BULLETIN NO. DL-S 7612350, OCTOBER 1976

• Choice of 8 Latches or 8 D-Type Flip-Flops SN54LS373, SN54S373 ... J PACKAGE

SN74LS373, SN74S373 ••. J OR N PACKAGE
In a Single Package
(TOP VIEW)
• 3-State Bus-Driving Outputs
• Full Parallel-Access for Loading
• Buffered Control Inputs '
• Clock/Enable Input Has Hysteresis to Improve
Noise Rejection
• P-N-P Inputs Reduce D-C Loading on
Data Lines ('S373 and 'S374)
• SN54LS363 and SN74LS364 Are Similar But
Have Higher V OH For MOS Interface

'LS373, 'S373
FUNCTION TABLE logic: see function table

OUTPUT ENABLE
D OUTPUT
CONTROL G
SN54LS374, SN54S374 .•. J PACKAGE
L H H H
SN74LS374, SN74S374 ••• J OR N PACKAGE
L H L L (TOP VIEW)
L L X 00
H X X Z Vee

'LS374, 'S374

•
FUNCTION TABLE

OUTPUT
CLOCK D OUTPUT
CONTROL
L t H H OUTPUT
CONTROL
10

L t L L
L L X 00
H X X Z logic: see function table

See explanation of function tables on page 3-8.

description
These 8-bit registers feature totem-pole three-state outputs designed specifically for driving highly-capacitive or
relatively low-impedance loads. The high-impedance third state and increased high-logic-level drive provide these
registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without
need for interface or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
The eight latches of the 'L8373 and '8373 are transparent O-type latches meaning that while the enable (G) is high the
Q outputs will follow the data (0) inputs. When the enable is taken low the output will be latched at the level of the
data that was setup.

1076 TENTATIVE DATA SHEET

This document provides tentative information TEXAS INSTRUMENTS 7-471
on a new product, Texas Instruments reserves INCORPORATED
the righ.t to change ~ecificatio.ns for this POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
product'" any manner Without notice.
 TYPES SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374
OCTAL D-TYPE TRANSPARENT LATCHES AND
EDGE-TRIGGERED FLIP-FLOPS
description (continued)
The eight flip-flops of the 'LS374 and '5374 are edge-triggered D-type flip-flops. On the positive transition of the clock,
the Q outputs will be set to the logic states that were setup at the D inputs.
Schmitt-trigger buffered inputs at the enable/clock lines simplify system design as ac and dc noise rejection is improved
by typically 400 mV due to the input hysteresis. A buffered output control input can be used to place the eight
outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state
the outputs neither load nor drive the bus lines significantly.
The output control does not affect the internal operation of the latches or flip-flops. That is, the old data can be
retained or new data can be entered even while the outputs are off.

'LS373, 'S373 'LS374, 'S374

TRANSPARENT LATCHES POSITIVE-EDGE-TRIGGERED FLIP-FLOPS

OUTPUT _(_1_)______~~ (1_)______~n

OUTPUT __
CONTROL CONTROL

10 (3)

20 (4)

(7)
3D ---'-----1----1 3D -------+----4

• 40

50
(8)
-------+----4

(13)
-------+----4
40 - - - - - 1 - - - 1

50 -----I--~

50
(14)
60 --------1---1 60 -----I--~

60 60
(17)
70 --------1----4 70 -------~-

70 70

80 (18)

CLOCK

1076

7-472 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54LS373, SN54LS374, SN74LS373, SN74LS374
OCTAL D-TYPE TRANSPARENT LATCHES AND
EDGE-TRIGGERED FLIP-FLOPS

-
schematic of inputs and outputs
EQUIVALENT OF DATA AND
OUTPUT CONTROL INPUTS

vcc
'LS373

EQUIVALENT OF ENABLE INPUT

Vcc---......- -
TYPICAL OF ALL OUTPUTS

- - - -......--Vcc

o
Req

INPUT --
INPUT

Data: Req = 20 kn NOM

Output control: Req = 18 kn NOM

'LS374
EQUIVALENT OF EQUIVALENT OF OUTPUT EQUIVALENT OF TYPICAL OF ALL OUTPUTS
DATA INPUTS CONTROL INPUT CLOCK INPUT
- - - -......--VCC

VCC~NOM
,NPUT w--
absoiute maximum ratings over operating free-air temperature range (unless otherwise noted)

•
Supply voltage, vee (see Note 1) 7V
Input voltage 7V
Off-state output voltage .7V
Operating free-air temperature range: SN54LS' _55°C to 125°C
SN74LS' aOe to 7aoe
Storage temperature range _65°C to 15aoe
NOTE 1: Voltage values are with raspect to network ground terminal.

recommended operating conditions

SN54LS' SN74LS'
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, VCC 4.5 5 5.5 4.75 5 5.25 V
High-level output voltage, VOH 5.5 5.5 V
High-level output current, IOH -1 -2.6 rnA
High 15 15
Width of clock/enable pulse, tw ns
Low 1.5 15
'LS373 O.j. O.j.
Data setup time, tsu ns
'LS374 20t 20t
'LS373 10.j. 10.j.
Data hold time, th ns
'LS374 Ot Ot
Operating free-air temperature, T A I --55 125 0 70 °c
t.j. The arrow indicates the transition of the clock/enable input used for reference: t for the low-to-high transition, .j. for the high-to-Iow transi-
tion.

1076 DESIGN GOAL

This page provides tentative information on a
product in the developmental stage. Texas TEXAS ',",CORPORATED
INSTRUMENTS 7-473
Instruments reserves the right to change or dis-
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
continue this product without notice.
 TYPES SN54LS373. SN54LS374. SN74LS373. SN74LS374
OCTAL D-TYPE TRANSPARENT LATCHES AND
EDGE-TRIGGERED FLIP-FLOPS
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS' SN74LS'
PARAMETER TEST CONDITIONSt UNIT
MIN TYP:j: MAX MIN TYP:j: MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0_7 0.8 V
VIK Input clamp voltage Vee; MIN, 11;-18mA -1.5 -1.5 V
Vce - MIN, VIH - 2 V,
VOH High-level output voltage I Vil ;VILmax,IOH; MAX
2.4 3.4 2.4 3.1 V

Vce; MIN, VIH;2V, I10l; 12 mA 0.25 0.4 0.25 0.4

VOL Low-level output voltage V
VIL; VILmax I10l; 24 mA 0.35 0.5
Off-state output current, Vee; MAX, VIH;2V,
10ZH I 20 20 p.A
high-level voltage applied VO;2.7V
Off-state output current, Vee; MAX, VIH; 2 V,
10ZL -20 -20 p.A
low-level voltage applied Va; 0.4 V
Input current at I
II Vee; MAX, VI; 7 V 0.1 0.1 mA
maximum input voltage
IIH High-level input current Vee ;MAX, VI; 2.7 V 20 20 p.A
IlL Low-level input current Vce; MAX, VI; 0.4 V -0.4 -0.4 mA
lOS Short-circuit output current§ Vee; MAX -30 -130 -30 -130 mA
Vec; MAX, !'lS373 24 40 24 40
ICC Supply current mA
Output control at 4.5 V I'LS374 27 45 27 45

t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at VCC ; 5 V, T A; 25°C.
§ Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second.

switching characteristics, Vee = 5 V, TA = 25° C

FROM TO 'LS373 'LS374
PARAMETER TEST CONDITIONS UNIT

•
ItNPUT) (OUTPUT) MIN TYP MAX MIN TYP MAX
f max 35 50 MHz
tpLH 10 18
Data Any Q ns
tpHl 18 27
el ;45 pF, RL; 667 n,
tPlH Clock or 14 25 16 28
Any Q See Notes 2 and 3 ns
lPHL enable 24 36 22 34 !
I tpZH Output 16 28[ 16 28
Any Q ns
tPZL Control 22 36 22 36
tpHZ Output el;5pF, RL; 667 n, 12 20 10 18
Any Q ns
tPLZ Control See Note 3 16 25 14 24

NOTES: 2. Maximum clock frequency is tested with all outputs loaded.

3. See load circuits and waveforms on page 3-11.

f max == maximum clock frequency

tpLH == propagation delay time, low-to-high-Ievel output
tpH L == propagation delay time, high-to-Iow-Ievel output
tpZH == output enable time to high level
tpZL == output enable time to low level
tpHZ == output disable time from high level
tpLZ == output disable time from low level

DESIGN GOAL 1076

7-474
This page provides tentative information on a
product in the developmental stage. Texas
TEXAS INCORPORATED
INSTRUMENTS
I nstruments reserves the right to change or dis- POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
continue this product without notice.
 TYPES SN54S373, SN54S374, SN74S373, SN74S374
OCTAL D-TYPE TRANSPARENT LATCHES AND
EDGE-TRIGGERED fLIP-fLOPS
schematic of inputs and outputs

EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS

------------~-----Vee
50n
NOM
Vee--------------~------

2.8 kn
NOM

INPUT ---41-....- . . OUTPUT

m II f V

~- - - - - - - - - - - - - - - ~I ~ ~ ~ ~ _________-_-
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
__ __

•
Supply voltage, Vee (see Note 1) 7V
Input voltage 5.5 V
Off-state output voltage 5.5 V
Operating free-air temperature range: SN54S' -55°e to 125°e
SN74S' aOe to 7aoe
Storage temperature range -65°e to 15aoe
NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54S' SN74S'
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output voltage, VOH 5.5 5.5 V
High-level output current, IOH -2 -6.5 rnA
High 6 6
Width of clock/enable pulse, tw ns
Low 7.3 7.3
'S373 O.j, O.j,
Data setup time, tsu ns
'S374 5t 51'
'S373 10.j, 10.j,
Data hold time, th ns
'S374 21' 2t
Operating free-air temperature, T A -55 125 0 70 °e

1'.j, The arrow indicates the transition of the clock/enable input used for reference: l' for the low-to-high transition, .j, for the high-to-Iow transi-
tion.

TENTATIVE DATA
1076
This page provides tentative information on a
new product. Texas Instruments reserves the TEXAS INCORPORATED
INSTRUMENTS 7-475
right to change specifications for this product
in any manner without notice. POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54S373, SN54S374, SN74S373, SN74S374
O-C-TAL D-TYPE TRANSPARENT LATCHES AND
EDGE-TRIGGERED fLIP-fLOPS

electrical character~stics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONSt MIN TYpt MAX UNIT
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
VIK Input clamp voltage VCC= MIN, 1,=-18mA -1.2 V

VOH High-level output voltage I SN54S' VCC= MIN, VIH=2V, 2.4 3.4
V
I SN74S' VIL = 0.8 V, IOH = MAX 2.4 3.1
VCC= MIN, VIH=2V,
VOL Low-level output voltage 0.5 V
VIL = 0.8 V, IOL = 20mA
Off-state output current, VCC = MAX, VIH=2V,
IOZH 50 IlA
high-level voltage applied VO= 2.4 V
Off-state output current, VCC= MAX, VIH=2V,
IOZL -50 IlA
low-level voltage applied Vo =0.5 V
II Input current at maximum input voltage VCC= MAX, VI=5.5V 1 mA
IIH High-level input current VCC = MAX, VI = 2.7 V 50 IlA
IlL Low-level input current VCC= MAX, VI =0.5V -250 IlA
lOS Short-circuit output current!l VCC= MAX -40 -100 mA

ICC Supply current VCC= MAX

I 'S373 105 160
mA
I 'S374 90 140
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAli typical values are at Vee = 5 V, TA = 25°C.
§ Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second.

switching characteristics, Vee == 5 V, T A = 25°e

PARAMETER
FROM TO
TEST CONDITIONS
'5373 I '5374
UNIT
(INPUT) (OUTPUT) MIN TYP MAX IMIN TYP MAX
f max I 75 100 MHz

•
tpLH 5 9;
Data AnyQ ns
tpHL 9 13 i
CL=15pF, RL=280n,
tpLH Clock or 7 14 i 8 15
Any Q See Notes 2 and 4 ns
tpHL enable 12 18 i 11 17
tpZH Output
Any Q
8 15 I 8 15 ,
ns
tP2;L- Control 11 18 I 11 18 I
tpHZ Output CL = 5 pF, RL = 280 n, 6 91 5 9
Any Q ns
tpLZ Control See Note 3 8 12 1 7 12

NOTES: 2. Maximum clock frequency is tested with all outputs loaded.

4. See load circuits and waveforms on page 3·10.

f max "" maximum clock frequency

tpLH "'" propagation delay time, low-to-high-Ievel output
tpHL == propagation delay time, high-to-Iow-Ievel output
tpZH "'" output enable time to high level
tpZL == output enable time to low level
tpHZ == output disable time from high level
tpLZ "'" output disable time from low level

TENTATIVE DATA 1076

This page provides tentative information on a
7-476 new product. Texas Instruments reserves the TEXAS INSTRUMENTS
INCORPORATED
right to change specifications for this product
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
. in any manner without notice.
 TYPES SN54LS374, SN54S374, SN74LS374, SN74S374
OCTAL D-TYPE TRANSPARENT LATCHES AND
EDGE-TRIGGERED FLIP-FLOPS
TYPICAL APPLICATION DATA
BIDIRECTIONAL lUI DRIVER
OUTPUT
CONTROL 1
A
1D A 10

2D 2Q

3D 3Q

BIDIRECTIONAL
DATA flUS 1
-
r-
'LS374
OR
40
ISO
BIOI RECTIONAL
OATABUS2
'S374
1- 10
7D 70
5'{ 80

CLOCK 1
) i CLOCK 2
(
10 \( 10
1

lUI CLOCK 1

EXCHANGELr
H =c?- '----J
CLOCK --, I
CLOCK 2 H --L-,J- L-...J

•
CLOCK CIRCUIT FOR lUI EXCHANGE

EXPANDABLE ~RD"Y""IT GENERAL REGIITER FILE

1/2 SN74LSl39
OR SN74S139

G YO
Y1

A Y2
ENABLE SELECT {
B Y3

1/2 SN74LSl39
OR SN74S139

~ L..S
SELECT
CLOCK

1076

TEXAS INCORPORATED
INSTRUMENTS 7477
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TTL TYPES SN54LS375, SN74LS375
MSI 4-BIT BISTABLE LATCHES
BULLETIN NO. DL-S 7612131, OCTOBER 1976

• Supply Voltage and Ground on Corner SN54LS375 ••• J OR W PACKAGE

Pins To Simplify P-C Board Layout SN74LS375 •.. J OR N PACKAGE
(TOP VIEW)
logic
FUNCTION TABLE ENABLE
(EACH LATCH) vce 40 40 3-4 30 3D

INPUTS OUTPUTS
0 G Q Q
L H L H
H H H L
X L Co 00
H = high level, L = low level, X = irrelevant
00 = the level of a before the high-to-Iow transition of G.

functional block diagram (each latch)

mo,","
Dm~ ~
10 10 10 ENABLE 20 2Q 20 GNO
LATCH 1·2

ENABLE logic: see function table

description
The SN54lS375 and SN74LS375 bistable latches are
electrically and functionally identical to the
SN54lS75 and SN74lS75, respectively. Only the schematics of inputs and outputs
arrangement of the terminals has been changed in the
SN54lS375 and SN74lS375.
EQUIVALENT OF
EACH INPUT TYPICAL OF ALL OUTPUTS
r------------.
These latches are ideally suited for use as temporary
storage for binary information between processing Vee

~
units and input/output or indicator units. Informa-

•
q
tion present at a data (D) input is transferred to the Q IRe
output when the enable (G) is high and the Q output INPUT --
will follow the data input as long as the enable "
remains high. When the enable goes low, the informa- ~
tion (that was present at the data input at the time ~~ U
the transition occurred) is retained at the Q output
until the enable goes high. 111

These circu,its are completely compatible with all

popular TIL or DTl families. All inputs are diode·
clamped to minimize transmission-line effects and Data: Req = 17 kn
simplify system design. The SN54lS375 is character· Enable: Req = 4.2 kn
ized for operation over the full military temperature
range of -55°C to 125°C; SN74LS375 is character-
ized for operation from 0° C to 70° C.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1) . . . . . . . 7V
Input voltage . . . . . . . . . . . . . . 7V
Operating free-air temperature range: SN54LS375 -55°C to 125°C
SN74lS375 . O°C to 70°C
Storage temperature range -65°C to 150°C
NOTE1: Voltage values are with respect to network ground terminal.

recommended operating conditions, electrical characteristics, and switching characteristics

Same as SN54LS75 and SN74LS75, see page 7-39.

1076

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TTL TYPES SN54376. SN74376
MSI QUADRUPLE J-K FLIP-FLOPS
BULLETIN NO. DL-S 7612461, OCTOBER 1976

SN54376 .•. J OR W PACKAGE

SN74376 ... J OR N PACKAGE
• Four J-j( Flip-Flops in a Single Package ... (TOP VIEW)
Can Reduce FF Package Count by 50%
• Common Positive-Edge-Triggered Clocks Vcc 4J 4K 4Q 3Q 3K 3J CLOCK
with Hysteresis ... Typically 200 mV
• Fully Buffered Outputs
• Typical Clock Input Frequency ... 45 MHz

description
These quadrup!e TTL J-j( flip-f!ops incorporate a
. '~umber of third-generation IC features that can
simpltfy system design and reduce flip-flop package
count by as much as 50"k. They feature hysteresis at CLEAR 1J 11<: 1Q 2Q 2J GND

the clock input, fully buffered outputs, and direct

clear capability. The positive-edge-triggered SN54376 logic: see function table
and SN74376 are directly compatible with most
Series 54/74 MSI registers. schematics of inputs and outputs
The SN54376 is characterized for operation over the EQUIVALENT OF TYPICAL OF ALL
EACH INPUT OUTPUTS
full military temperature range of -55°C to 125°C;
the SN74376 is characterized for operation from O°C
to 70°C. VCC--....- - -

FUNCTION TABLE (EACH FLIP-FLOP)

•
Q
COMMON INPUTS INPUTS OUTPUT
CLEAR CLOCK J K Q
L X X X L
H t L H Qo
H t H H H
H t L L L
Clear, J, K: Req: 4 kn NOM
H t H L TOGGLE
Clock: Req: 11.6 kn NOM
H L X X QO
See explanation of function tables on page 3-8. Resistor values shown are nominal and in ohms

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, Vec (see Note 1) .... . . .... 7 V

Input voltage . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range: . SN54376 -55°C to 125°e
SN74376 O°C to 70°C
Storage temperature range -65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

1076

TEXAS INCORPORATED
INSTRUMENTS 7-479
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54376, SN74376
QUADRUPLE J-K FLIP-FLOPS

recommended operating conditions

SN54376 SN74376
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -SOO -SOO p.A
Low-level output current, 10L 16 16 mA
Clock frequency 0 30 0 30 MHz
Clock high 22 22
Pulse width, tw Clock low 12 12 ns
Preset or clear low 12 12
J, K inputs Ot Ot
Setup time, 1:su ns
Clear inactive state lOt lOt
Input hold time, lh 20t 20t I ns
Operating free-air temperature, T A 55 125 0 70 °e

t.j, The arrow indicates the edge of the clock pulse used for reference: t for the rising edge, .j. for the falling edge.

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONSt MIN TYP; MAX UNIT

VIH High-level input voltage 2 V
VIL Low-level input voltage O.S V
VIK Input clamp voltage Vee; MIN, 11;-12mA -1.5 V
Vee; MIN, VIH;2 V,
VOH High-level output voltage 2.4 3.4 V
VIL; O.S V, 10H ;-Soop.A
Vee; MIN, VIH; 2 V,
VOL Low-level output voltage 0.2 0.4 V
VIL; O.S V, IOL=16mA
Input current at maximum input voltage VI; 5.5 V

•
II Vee; MAX, 1 mA
IIH High-level input current Vee = MAX, VI = 2.4 V 40 p.A
IlL Low-level input current Vee - MAX, VI; 0.4 V -1.6 mA
lOS Short-i:ircuit output current!? Vee = MAX -30 -S5 mA
ICC Supply current Vee = MAX 52 74 mA

t For conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions.
;AII typical values are at Vee = 5 V, T A = 25°e.
§Not more than one output should be shorted at 8 time.

switching characteristics, Vee = 5 V, TA = 25°e

PARAMETER TEST CONDITIONS MIN TVP MAX UNIT
fmax Maximum clock frequency 30 45 MHz
eL;15pF,
tpHL Propagation delay time, high-to-Iow-Ievel output from clear· 17 30 ns
RL = 400n,
tpLH Propagation delay time, low-to-hi!tl-Ievel output from clock 22 35 ns
See Note 2
tpHL Propagation delay time, high-to-low-level output from clock 24 35 ns

NOTE 2: Load circuit and voltage waveforms are sh own on page 3'10.

1076

7-480 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54LS377, SN54LS378, SN54LS379,
SN74LS377, SN74LS378, SN74LS379
OCTAL, HEX, AND QUAD D-TYPE FLIP-FLOPS WITH ENABLE
BULLETIN NO. DL-S 7612474, OCTOBER 1976

SN54LS377 •.• J PACKAGE

SN74LS377 ... J OR N PACKAGE
• 'LS377 and 'LS378 Contain Eight and (TOP VIEW)
Six Flip-Flops, Respectively, with Single-
Rail Outputs 80 8D 7D 70 6Q 6D SD sa CLDCK

• 'LS379 Contains Four Flip-Flops with

Double-Rail Outputs
• Individual Data Input to Each Flip-Flop
• Applications Include:
Buffer/Storage Registers
Shift Registers
Pattern Generators

description ENABLE 10 1D 2D 20 30 3D 4D 40 GND

G

These monolithic, positive-edge-triggered flip-flops

utilize TTL circuitry to implement D-type flip-flop logic: see function table

logic with an enable input. The 'LS377, 'LS378, and SN54LS378 ... J OR W PACKAGE
'LS379 devices are similar to 'LS273, 'LS174, and SN74LS378 ... J OR N PACKAGE
'LS175, respectively, but feature a common enable (TOP VIEW)
instead of a common clear.
Vee 6Q 6D 50 sa 4D 40 CLOCK
Information at the D inputs meeting the setup time
requirements is transferred to the Q outputs on the
positive-going edge of the clock pulse if the enable
input G is low. Clock triggering occurs at a particular
voltage level and is not directly related to the
transition time of the positive-going pulse. When the
clock input is at either the high or low level, the D
input signal has no effect at the output. The circuits

•
are designed to prevent false clocking by transitions
at the G input.
ENABLE 10 1D 2D 20 3D 30 GND
G
These flip-flops are guaranteed to respond to clock
frequencies ranging from 0 to 30 MHz while
logic: see function table
maximum clock frequency is typically 40 megahertz.
Typical power dissipation is 10 milliwatts per SN54LS379 •.• J OR W PACKAGE
flip-flop. SN74LS379 ... J OR N PACKAGE
(TOP VIEW)

vce 40 40- 4D 3D 35 30 CLOCK

FUNCTION TABLE
(EACH FLIP-FLOP)
INPUlS OUTPUTS
G CLOCK DATA a a
H x X 00 00
L t H H L
L t L L H
X L X 00 DD
See explanation of function tables on page 3-8.

ENABLE 10 115 10
G

logic: see function table

076

TEXASINCORPORATED
INSTRUMENTS 7-481
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54LS311, SN54LS318, SN54LS319,
SN14LS311, SN14LS318, SN14LS319
OCTAL, HEX, AND QUAD D-TYPE FLIP-FLOPS WITH ENABLE
functional block diagram

CLOCK - - - - - t

D
CK TO 7 ('LS377J
5 ('LS378)
3 ('LS379)
OTHER FLIP-FLOPS
a. Q

ENABLE
G --~L_~_""

a. Q
('LS379
ONLY)

schematics of inputs and outputs

EQUIVALENT OF DATA EQUIVALENT OF CLOCK OR TYPICAL OF ALL OUTPUTS

INPUT ENABLE INPUT
------4I~-VCC

vcc-----.....- vcc--......- -
25 kO
20 kO NOM
INPUT_~---,tI....- .... NOM

I NPUT-..,........- .......
' - - - + - OUTPUT

• absolute maximum rating over operating free-ai-r temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) .... . . . . . . 7V
Input voltage . . . . . . . . . . . . . . . . . . 7V
Operating free-air temperature range: SN54LS' · _55°C to 125°C
SN74LS' · . oOe to 70°C
Storage temperature range · -65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.

10

7-482 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54LS377, SN54LS378, SN54LS379,
SN74LS377, SN74LS378, SN74LS379
OCTAL, HEX, AND QUAD D-TYPE FLIP-FLOPS WITH ENABLE
recommended operating conditions
SN54LS' SN74LS'
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, IOH -400 -400 /LA
Low-level output current, IOH 4 8 mA
Clock frequency, fclock 0 30 0 30 MHz
Width of clock or clear pulse, tw 20 20 ns
Data input 20t 20t
Setup time, tsu Enable active-state 25t 25t ns
Enable inactive-state 10t 10t
Hold time, "th Data and enable 5t 5t ns
Operating free-air temperature, T A -55 125 0 70 °c

t The arrow indicates that the rising edge of the clock pu Ise is used for reference.

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

SN54LS' SN74LS'
PARAMETER TEST COND!T!ONSt UNIT
MIN TYp:j: MAX MIN TYp:j: MAX
V,H High-level input voltage 2 2 V
VIL Low-level input voltage 0,7 0.8 V
VIK Input clamp voltage Vee = MIN /I =-18mA -1.5 -1.5 V
Vec- MIN, VIH - 2 V,
VOH High-level output voltage 2.5 3.5 2.7 3.5 V
VIL = VIL max, IOH =-400/LA
Vee = MIN, VIH = 2 V, 1I0L=4mA 0.25 0.4 0.25 0.4
VOL Low-level output voltage V
Vil =Vll max tlOl =8 mA 0.35 0.5
Input current at I ~ .1 ~ .1 I
f; Vee = MAX, Vi =7V U.I U.I mA I
maximum input voltage I
IIH High-level input current VCC= MAX, VI = 2.7 V 20 20 p,A

•
IlL low-level input current VCC = MAX, VI = 0.4 V -0.4 )
-0.4 mA
lOS Short·circuit output current§ Vec= MAX -20 -100 -20 -100 mA
l'lS377 17 28 17 28 mA
Ice Supply current VCC = MAX, See Note 2 l'lS378 13 22 13 22 mA
l'lS379 9 15 9 15 mA

t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j: All typical values are at V CC = 5 V, T A = 25° C.
§ Note more than one input should be shorted at a time, and duration of the short-circuit should not exceed one second.
NOTE 2: With all outputs open and ground applied to all data and enable inputs, ICC is measured after a momentary ground,
then 4.5 V, is applied to clock.

switching characteristics, Vee =5 V, TA = 25°e

PARAMETER TEST CONDITIONS MIN TVP MAX UNIT
f max Maximum clock freq'uency CL = 15 pF, 30 40 MHz
tPlH Propagation delay time, low-to-high-level output from clock RL = 2 kU 17 27 ns
tpHl Propagation delay time, high-to-low-Ievel output from clock See Note 3 18 27 ns

NOTE 3: Load circuit and voltage waveforms are shown on page 3-11.

1076

TEXAS INCORPORATED
INSTRUMENTS 7-483
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TTL TYPES SN 54S381, SN74$381
MSI ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR
BULLETIN NO. DL-S 7612124, MARCH 1974 - REVISED OCTOBER 1976

SN54S381 ..• J PACKAGE

PIN DESIGNATIONS SN74S381 .•• J OR N PACKAGE
{TOP VIEW)
DESIGNATION PIN NOS. FUNCTION
A3, A2, Al, AO 17,19,1,3 WORD A INPUTS
B3, B2, B1, BO 16,18,2,4 WORD B INPUTS
FUNCTION-SELECT
S2, Sl, SO 7,6,5
INPUTS
CARRY INPUT FOR
ADDITION,INVERTED\
Cn 15
\ CARRY INPUT FOR
SUBTRACTION
F3, F2, Fl, FO 12,11,9,8 FUNCTION OUTPUTS
INVERTED CARRY
P 14
PROPAGATE OUTPUT
INVERTED CARRY
G 13
GENERATE OUTPUT
VCC 20 SUPPLY VOLTAGE
GND 10 GROUND logic: see function table

• A Fully Parallel 4-Bit ALU in 20-Pin

Package for 0.300-1 nch Row Spacing
• Ideally Suited for High-Density
Economical Processors
FUNCTION TABLE
• Parallel Inputs and Outputs and Full
Look-Ahead Provide System Flexibility SELECTION ARITHMETIC/LOGIC
S2 S1 SO OPERATION
• Arithmetic and Logic Operations L L L CLEAR
Selected Specifically to Simplify System L L H B MINUSA
Implementation: L H L A MINUSB
A MinusB L H H A PLUS B
B Minus A
I
H L L AGB
A Plus B H L H A + B
and Five Other Functions H H L AB
H H H PRESET
• Schottky-Clamped for Hi~ Performance
H ~ high level. L ; low level
i 6-Bit Add Time ... 26 ns Typ Using
Look-Ahead
32-Bit Add Time ... 34 ns Typ Using
Look-Ahead

description

The 'S381 is a Schottky TTL arithmetic logic unit (ALU)/function generator that performs eight binary arithmetic/
logic operations on two 4·bit words as shown in the function table. These operations are selected by the three
function-select lines (SO, S1, S2). A full carry look·ahead circuit is provided for fast, simultaneous carry generation
by means of two cascade outputs (p and G) for the four bits in the package. The method of cascading SN54182/
SN74182 or SN54S182/SN74S182 look·ahead carry generators with these ALU's to provide multi-level full carry
look·ahead is illustrated under typical applications data for the '182 and 'S182. The typical addition times shown
above illustrate the short delay time required for addition of longer words when full look-ahead is employed. The
exciusive·OR, AND, or OR function of two Boolean variables is provided without the use of external circuitry. Also,
the outputs can be either cleared (low) or preset (high) as desired.

1076

7-484 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN 54S381, SN74S381
ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR
REVISED OCTOBER 1976

functional block diagram and schematics of inputs and outputs

EQUIVALENT OF EACH INPUT

VCC-----4I--_ _

INPUT

Any A or B: Req = 1 kn
Cn: Req = 800 n
Any S: Req = 6 kn

TYPICAL OF ALL OUTPUTS

- - - -.......-VCC

~---41--- OUTPUT

1076

TEXAS INCORPORATED
INSTRUMENTS 7-485
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54S381, SN74S381
ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS
REVISED OCTOBER 1976

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see !\I0te 1) . 7V
Input voltage . . . . . . . . . . . . . . 5.5 V
Interemitter voltage (see Note 2) .••..• 5.5 V
Operating free-air temperature range: SN54S381 -55°C to 125°C
SN74S381 oOe to 70°C
Storage free-air temperature range _65°C to 150°C
NOTES: 1. Voltage values, except interemitter voltage, are with respect to network ground terminal.
2. This is the voltage between two emitters of a multiple-emitter transistor. For this circuit, this rating applies to each A input in
conjunction with its respective B input; for example AO with BO, etc.
recommended operating conditions
SN54S381 SN74S381
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High·level output current, 10H -1 -1 mA
Low-level output current, 10L 20 20 mA
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONSt MIN TYPt MAX UNIT
VIH High·level input voltage 2 V
VIL Low·level input voltage 0.8 V
VIK Input clamp voltage Vee= MIN, II = -18mA -1.2 V
SN54S381 Vee - MIN, VIH - 2 V, 2.4 3.4
VOH High·level output voltage V
SN74S381 VIL = 0.8 V, 10H = -1 mA 2.7 3.4
Vee = MIN, VIH =2V,
VOL Low-level output voltage 0.5 V
VIL = 0.8 V, 10L =20mA
II Input current at maximum input voltage Vee = MAX, VI = 5.5 V 1 mA
Any S input 50
IIH High-level input current en Vee = MAX, VI = 2.7 V 250 ~A
All others 200

• IlL

lOS
lec
Low-level input current

Short-circuit output current§

Supply current

tAli typical values are at VCC = 5 V, TA = 25°C.

§ Not more than one output should be shorted at a time.
Any S inpu
en
All others
Vee = MAX,

Vee = MAX
Vee= MAX
--
VI = 0.5 V

tFor conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions.
-40
105
-100
160
-2
-8
-6

mA
mA

mA

switching characteristics, Vee = 5 V, TA = 25°e

FROM TO
PARAMETER. TEST CONDITIONS MIN TYP MAX UNIT
(INPUT) (OUTPUT)
tPLH 10 17
Cn Any F ns
tpHL 10 17
tpLH - 12 20
Any A or B G ns
tpHL 12 20
tPLH - CL=15pF, RL = 280 n, 11 18
Any A or B P ns
tPHL See Note 3 11 18
tpLH 18 27
AiorBi Fi ns
tpHL 16 25
tpLH 18 30
Any S Any ns
tpHL 18 30
.tPLH == propagation delay time, low-to-high-Ievel output
tpHL == propagation delay time, high-to-Iow-Ievel output
NOTE 3: Load circuit and voltage waveforms are shown on page 3-10.

1076

1-486 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TIL TYPES SN54LS386, SN74LS386
MSI QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
BULLETIN NO. DL-S 7612118, MARCH 1974-REVISED OCTOBER 1976

SN54LS386 ••. J OR W PACKAGE

SN74LS386 .•• J OR N PACKAGE
(TOP VIEW)

Vee 4B 4A 4Y 3Y 3B 3A

• Electrically Identical to
SN54LS86/SN74 LS86
• Mechanically Identical to
SN54L86/SN74L86
• Total Average Propagation Delay
Times ... 10 ns
• Typical Total Power
Dissipation ... 30.5 mW
lA lB lY 2Y 2A 2B GND

positive logic: Y = A <±> B = AB + AS

FUNCTION TABLE
(EACH GATE)

INPUTS
OUTPUT
A B
L L L
L H H
H L H

•
H H L

H = high level
L = low level
schematics of inputs and outputs

EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS

-----------4~---Vcc

vcc-------e------

12.5 kn NOM

I NPUT·--. . . . . .--4II---__
......- ......--OUTPUT

1076

TEXAS INSTRUMENTS 7-487

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54LS386, SN74LS386
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
REVISED OCTOBER 1976

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, Vee (see Note 1) ..... . 7V

Input voltage . . . . . . . ..... . 7V
Operating free-air temperature range: SN54LS386 -55°C to 125°C
SN74LS386 O°C to 70°C
Storage temperature range -65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54 LS386 SN74LS386
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -400 -400 /loA
Low-level output current, 10L 4 8 mA
Operating free-air temperature, T A -55 125 0 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS386 SN74 LS386
PARAMETER TEST CONDITIONSt UNIT
MIN TVPt MAX MIN TVPt MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
VIK I nput clamp voltage Vee= MIN, II = -18 mA -1.5 -1.5 V
Vec= MIN, VIH=2V,
VOH High-level output voltage 2.5 3.4 2.7 3.4 V
VIL = VIL max, 10H = -400/loA

VOL Low-level output voltage

Vee = MIN.
VIH=2V, I 10L = 4 mA 0.25 0.4 0.25 0.4
V

•
VIL = VIL mad 10L = 8 mA 0.35 0.5

II Input current at maximum input voltage Vee - MAX, VI-7 V 0.2 0.2 mA
IIH High-level input current Vee = MAX, VI - 2.7 V 40 40 /loA
IlL Low-level input current Vee = MAX, VI = 0.4 V -0.8 -0.8 mA
lOS Short-circuit output current§ Vee = MAX -6 -40 -5 -42 mA
lee Supplv current Vee- MAX, See Note 2 6.1 10 6.1 10 mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
t All typical values are at V CC = 5 V, T A = 25° C.
§ Not more than 0 ne output shou Id be shorted at a time.
NOTE 2: ICC is measured with the inputs grounded and the outputs open.

switching characteristics, Vee =5 V, TA = 25°C

FROM
PARAMETERlI TEST CONDITIONS MIN TVP MAX UNIT
(INPUT)
tpLH 12 23
AorB Other input low eL = 15 pF, ns
tpHL 10 17
RL = 2 kn,
tpLH 20 30
AorB Other input high See Note 3 ns
tpHL 13 22

lItPLH '" propagation delay time, low-to-high-Ievel output

tpHL '" propagation delay time, high-to-Iow-Ievel output
NOTE 3: Load circuit and VOltage waveforms are shown on page 3-11.

1071

7-488 TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54390, SN54LS390,. SN54393, SN54LS393,
TTL SN14390, SN14LS390, SN14393, SN14LS393
DUAL 4-BIT DECADE, AND BINA.RY COUNTERS
BUL OCTOBER 1976

SN54390, SN54LS390 .•. J OR W PACKAGE

• Dual Versions of the Popular '90A, 'LS90 SN74390, SN74LS390 .•• J OR N PACKAGE
and '93A, 'LS93 (TOP VIEW)

• '390, 'LS390 .. .Individual Clocks for A and B

Flip-Flops Provide Dual +2 and +5 Counters VCC 2A CLEAR
2 OUTPUT
2QA 2B~
OUTPUTS

• '393, 'LS393 ...Dual 4-Bit Binary Counter

with Individual Clocks
• All Have Direct Clear for Each
4-Bit Counter
• Dual4-Bit Versions Can Significantly Improve

e
System Densities by Reducing Counter Package
Count by 50%
Typical Maximum Count Fiequency ... 35 MHz I r-l~~"
I I¥ e ~ ~
I I
Qo
I

• Buffered Outputs Reduce Possibility of Collector 1A CL~AR OJ~~UT 1B ~ GND

Commutation OUTPUTS

positive logic: High input to clear resets all four

outputs low
description

SN54393, SN54LS393 •.. J OR W PACKAGE

Each of these monolithic circuits contains eight SN74393, SN54LS393 ... J OR N PACKAGE
master-slave flip-flops and additional gating to imple· (TOP VIEW)
ment two individual four-bit counters in a single OUTPUTS
package. The '390 and 'LS390 incorporate dual
divide-by-two and divide-by-five counters, which can
be used to implement cycle lengths equal to any

•
whole and/or cumulative multiples of 2 and/or 5 up
to divide-by-100. When connected as a bi-quinary
counter, the separate divide-by-two circuit can be
used to provide symmetry (a square wave) at the final
output stage. The '393 and 'LS393 each comprise
two independent four-bit binary counters each having
a clear and a clock input. N-bit binary counters can
be implemented with each package providing the
capability of divide-by-256. The '390, 'LS390, '393,
and 'LS393 have parallel outputs from each counter
stage so that any submultiple of the input count
frequency is available for system-timing signals.
Series 54 and Series 54LS circuits are characterized
for operation over the full military temperature range
positive logic: High input to clear resets all four
of -55°C to 125°C; Series 74 and Series 74LS outputs low
circuits are characterized for operation from O°C
to 70°C.

1076

TEXAS INSTRUMENTS 7-489

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN64390, SN64LS390. SN64393, SN54LS393.
SN74390. SN74LS390. SN74393. SN74LS393
DUAL 4-BIT DECADE AND BINARY COUNTERS

FUNCTION TABLES
'390, 'LS390 '390, 'LS390
BCO COUNT SEQUENCE BI·QUINARY (5·2) '393, 'LS393
(EACH COUNTER) (EACH COUNTER) COUNT SEQUENCE
(See Note A) (See Note B) (EACH COUNTER)
OUTPUT OUTPUT OUTPUT
COUNT COUNT COUNT
QO QC QB QA QA QO QC QB QO Oc QB QA
0 L L L L 0 L L L L 0 L L L L
1 L L L H 1 L L L H 1 L L L H
2 L L H L 2 L L H L 2 L L H L
3 L L H H 3 L L H H 3 L L H H
4 L H L L 4 L H L L 4 L H L L
5 L H L H 5 H L L L 5 L H L H
6 L H H L 6 H L L H 6 L H H L
7 L H H H 7 H L H L 7 L H H H
8 H L L L 8 H L H H 8 H L L L
9 H L L H 9 H H L L 9 H L L H
10 H L H L
NOTES: A. Output QA is connected to Input B for BCD count.
B. Output QD is connected to input A for bi-quinary 11 H L H H
count. 12 H H L L
C. H = high level. L = low level.
13 H H L H
14 H H H L
15 H H H H

functional block diagrams

OUTPUT
aA
(1,151

•
INPUT A

aA

OUTPUT
(4,12) Os
!NPUTlJ

OUTPUT
Oc

OUTPUT
aD

(2,
CLEAR 14)
INPUT

'390, 'LS390 '393, 'LS393

1076

7-490 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54390. SN54LS390. SN54393, SN54LS393.
SN14390, SN14LS390. SN14393. SN14LS393
DUAL 4-BIT DECADE AND BINARY COUNTERS
schematics of inputs and outputs

'390, '393
EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS

VCC3--
INPUT
Req

--

INPUT Req NOM

A ('390)...... 3 kn
B ('390) ...... 1.5 kn
A ('393)...... 3 kn
Any clear . . . . .. 8 kn

-
'LS390, 'LS393
EQUIVALENT OF EACH EQUIVALENT OF EACH
TYPICAL OF ALL OUTPUTS
AAND B INPUT CLEAR INPUT
VCC
VCC~--
INPUT
A
~
Req

-- INPUT
18 kn NOM

~
--

•
INPUT Req NOM
A ('LS390l. ........ 4.3 kn
B ('LS390). ........ 2.7 kn
A ('LS393l. ....... .4.3 kn

076

TEXAS INCORPORATED
INSTRUMENTS 7-491
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54390. SN54393. SN74390. SN74393
DUAL 4-BI1 DECADE AND BINARY COUNTERS

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . 7V
Input voltage . . . . . . . . . . . . . 5.5V
Operating free·air temperature range: SN54390, SN54393 -55°C to 125°C
SN74390, SN74393 oOe to 70°C
Storage temperature range -65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54390 SN74390
SN54393 SN74393 UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, V CC 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -800 -800 J.l.A
Low-level output current, 10L 16 16 mA
A input 0 25 0 25
Count frequency, fcount MHz
B input 0 20 0 20
A input high or low 20 20
Pulse width, tw B input high or low 25 25 ns
Clear high 20 20
Clear" inactive-state setup time, tsu 25-1- 25+ ns
Operating free-air temperature, T A -55 125 0 70 °c

+The arrow indicates that the falling edge of the clock pulse is used for reference.

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
'390 '393
PARAMETER TEST CONDITIONSt UNIT
MIN TYP+ MAX MIN TYP+ MAX
VIH High·level input voltage 2 2 V

•
VIL Low-level input voltage 0.8 0.8 V
VIK Input clamp voltage VCC = MIN, 11=-12mA -1.5 -1.5 V
VCC= MIN, VIH=2V,
VOH High-level output voltage 2.4 3.4 2.4 3.4 V
VIL = 0.8 V, 10H = -800J.l.A
VCC = MIN, VIH=2V,
VOL Low-level output voltage 0.2 0.4 0.2 0.4 V
,VIL =0.8V, 10L = 16mA'
Input current at
II VCC = MAX, VI = 5.5 V 1 1 mA
maximum input voltage
Clear 40 40
IIH High-level input current 'Input A VCC = MAX, VI = 2.4 V 80 80 J.l.A
r---
Input B 120

Low-level input current

Clear
'Input A
i -1
-3.2
I -1
-3.2
i I
IlL VCC = MAX, VI = 0.4 V mA
'Input B -4.8
ISN54' -20 -57 -20 -57
lOS Short-circuit output current § VCC = MAX mA
ISN74' -18 -57 -18 -57
ICC Supply current VCC = MAX, See Note 2 42 69 38 64 mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAli typical values are at V CC = 5 V, T A = 25°C.
, The QA outputs of the '390 are tested at IOL = 16 mA plus the limit value for IlL for the B input. This permits driving the B input while
maintaining full fan·out capability.
§Not more than one output should be shorted at a time.
NOTE 2: ICC is measured with all outputs open, both clear inputs grounded following momentary connection to 4.5 V, and all other inputs
grounded.

107€

7-492 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54390, SN54393, SN74390, SN74393
DUAL 4-BI1 DECADE AND BINARY COUNTERS

switching characteristics, Vee = 5 V, TA = 25°e

FROM TO '390 '393
PARAMETER~ TEST CONDITIONS UNIT
(INPUT) (OUTPUT) MIN TYP MAX MIN TYP MAX
A QA 25 35 25 35
f max MHz
B QB 20 30
tPLH 12 20 12 20
A QA ns
tpHL 13 20 13 20
tPLH QC of '390 CL = 15 pF, 37 60 40 60
A ns
tpHL QD of '393 RL=400n, 39 60 40 60
tPLH See Note 3 13 21
B QB ns
tPHL and 14 21
tPLH Figure 1 24 39
B QC ns
tpHL 26 39
tpLH 13 21
B QD ns
tpHL 14 21
Clear Any 24 39 24 39 ns

~fmax = maximum count frequency

tpLH = propagation delay time, low-to-high-Ievel output
tpH L = propagation delay time, high-to-Iow-Ievel output
NOTE 3: Load circuit is shown on page 3-10.

PARAMETER MEASUREMENT INFORMATION

\~~ r"i
~::----~,-----------~,---------::
~ tsu ~ I- -, tw(clock)

~
I ~----3V
IN~UT:

•
.1_SV 'l.SV 1.SV 1.SV
, I I ov
I ~LH-Measure ~ Ii>HL-Measure I
~tPHL I at tn+l I 'I at tn+2 I
OUTPUTQA~I~.
.==~
INPUT
I
:
,1.5V
-
t~rf
-
1.SV
~.
l\1.5V
I -
/
-
r~----VOH
I 1.SV
I I VOL
r-----:-tpHL M tpLH-Measure at tn+2 I r------rtpHL -Measure at tn+4
- -- ~I I f f - I - -VOH
OUTPUTQB I ~l.SV : !1.5V : X- 1 .5V
,\ H · \:.VOL
htpHL ,_ ~} tpLH-Measureat tn+4 :_ RtPHL-Measureat tn+8

- - --,,\, I /1 {f-I--voH
OUTPUTQc ,I +\l.SV I I lSV I I ~l.SV
--...:...-.....Ji-----------4rS-s--..:I--;.I-J . I I \:.VOL
~tpHL ,I _ b tpLH-Measure at tn+8 I \4-=-=t\. tpHL -Measure at t n +l0 for '390
, ----tf ,- ~
OUTPUT QD
- - - "\, -\-l.S V
l'----oIHlf--.....;.....;--"""'\:i
1.S V
VOH
1.5 V
ortn+lsfor'393

----------~\~------------~J,~S-------------'· VOL
VOLTAGE WAVEFORMS

NOTE A: Input pulses are supplied by a generator having the following characteristics tr';; 5 ns, tf';; 5 ns, PRR =1 MHz, duty cycle = 50%,
Zout '" 50 ohms_

FIGURE 1

1076

TEXAS INCORPORATED
INSTRUMENTS 7-493
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54LS390, SN54LS393, SN74LS390, SN74LS393
DUAL 4-BIT DECADE AND BINARY COUNTERS

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1) . 7V
Clear input voltage . . . . . . . 7V
Any A or B clock input voltage 5.5V
Operating free-air temperature range: SN54LS390, SN54LS393 _55°C to 125°C
SN74LS390,SN74LS393 O°C to 70°C
Storage temperature range _65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54LS390 SN74LS390
SN54LS393 SN74LS393 UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, V CC 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -400 -400 p,A
Low-level output current, 10L 4 S rnA
A input 0 25 0 25
Count frequency, fcount MHz
B input 0 20 0 20
A input high or low 20 20
Pulse width, tw B input high or low 25 25 ns
Clear high 20 20
Clear"inactive·state setup time, tsu 25. 25. ns
Operating free-air temperature, T A -55 125 0 70 °c
.j. The arrow indicates that the falling edge of the clock pulse is used for reference.

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS' SN74LS'
PARAMETER TEST CONDITIONSt UNIT
MIN TYP:!: MAX MIN TYP:!: MAX
VIH High·level input voltage 2 2 V
VIL Low-level input voltage 0.7 O.S V

•
VIK Input clamp voltage VCC= MIN, II = -lS rnA -1.5 -1.5 V
VCC= MIN, VIH=2V,
VOH High-level output voltage 2.5 3.4 2.7 3.4 V
VIL = VI Lrnax, VOH = -400p,A
VCC= MIN, VIH=2V, IOL=4mA. 0.25 0.4 0.25 0.4
VOL Low-level output voltage V
VIL = O.S V, 10L=SmA~ 0.35 0.5
Clear VI =7 V 0.1, 0.1 ,
Input current at I---
0.2 0.2
II
maximum input voltage ~ VCC= MAX
VI=5.5V rnA
Input B 0.4 0.4
Clear 20 20
r--
IIH High-level input current [Input A VCC = MAX, VI = 2.7 V 40 40 p,A
Input B SO SO
Clear -0.4 -0.4 .
f---
Low-level input current Input A Vce= MAX, VI=0.4V -1.6 -1.6 rnA
I
IlL
,.......--
Input B -2.4 -2.4
lOS Short-circuit output current§ Vec = MAX -20 -100 -20 -100 rnA
Vee = MAX, 'LS390 15 26 15 26
ICC Supply current rnA
See Note 2 'LS393 15 26 15 26

t For conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions.
:!:AII typical values are at Vee = 5 V, T A = 25°e .
• The QA outputs of the 'LS390 are tested at 10L = MAX plus the limit value for IlL for the clock B input. This permits driving the clock B
input while maintaining full fan-out capability.
§ Not more than one output should be shorted at a time,and duration of the short-circuit should not exceed one second.
NOTE 2: lee is measured with a!l outputs open, both clear inputs grounded following momentary connection to 4.5 V, and all other inputs
grounded.

TENTATIVE DATA 1076

This page provides tentative information on a
7-494 new product. Texas Instruments reserves the TEXAS INSTRUMENTS
INCORPORATED
right to change specifications for this product POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
in any manner without notice.
 TYPES SN54LS390, SN54LS393, SN74LS390, SN74LS393
DUAL 4-BIT DECADE AND BINARY COUNTERS

switch ing characteristics, Vee = 5 V, T A = 25' C

FROM TO 'LS390 'L.s393
PARAMETER' TEST CONDITIONS UNIT
(INPUT) (OUTPUT) MIN TYP MAX MIN TYP MAX
A QA 25 35 25 35
f max MHz
B QB 20 30
tPLH 12 20 12 20
A QA ns
tpHL 13 20 13 20
tPLH Oc of 'LS390 CL = 15 pF, 37 60 40 60
A ns
tPHL QD of 'LS393 RL = 2 kn, 39 60 40 60
tPLH See Note 4 and Figure 2 13 21
B QB ns
tPHL 14 21
tPLH 24 39
B QC ns
tPHL 26 39
tPLH 13 21
B QD ns
tPHL 14 21
tpHL Clear Any 24 39 24 39 ns

, f max == max imu m cou nt freq uency

tpLH == propagation delay time, low-to-high-Ievel output
tpH L == propagation delay time, high-to-Iow-Ievel·output
NOTE 4: Load circuit is shown on page 3-11.

PARAMETER MEASUREMENT INFORMATION

~~~ (" ~~;;----~,-----------~,---------

!• •I
I I+- ~

J
tsu tw(clock)

IN~UT: ~1.3V ~1.3V / \ ~::-- 3V

~ r\:,;....1 . -- ~ ~ I ov

•
~ ~PLH-Measure ~tPLH-Measure I
OUTPUT QA -..;........,.,

'L::!
1-

l
-I
'i.~
,1.3 V
tPHL

t
I
~rf
1 3V
.
attn+1 I I
\_
l\13V
attn+2

I
r~-
I

I ~
-- -VOH

B INPUT I 1 I' VOL

~tPHL ~tPLH-MeaSUreattn+2 I r----rtpHL-Measureat tn+4

- -- ~ I ff-I-
\1.3
-VOH

OUTPUTQB ! V : !1.3V I '\::V

I H I~ I VOL
r----r-tPHL ,_ _I} tpLH-Measureattn+4 I_ R}'PHL-Measureat tn+8

OUTPUTOc
----"'\1
I + 1.3 V I
II (I 13V
ff-'--v
I I ~1.3V OH
: \ rs I ~ I I L.VOL

~tPHL ,_ ~tPLH-Measureattn+8 ~_ ~} tpHL-Measureattn+10for'LS390

- - - ~ 1.3 V /1.3 V If ~ l~:OH or 'n+16 for 'LS393

\ IS· \:.VOL

VOLTAGE WAVEFORMS

NOTE A: Input pulses are supplied by a generator having the following characteristics tr';; 15 ns, tf .;; 6 ns, PR R =1 MHz, duty cycle = 50%,
Zout "" 50 ohms_

1076
TENTATIVE DATA
This page provides tentative information on a TEXAS INSTRUM ENTS 1-495
new product. Texas Instruments reserves the INCORPORATED
right to change specifications for th is product POST OFFICE BOX 5012 • DALLAS. TEXAS 75222

in any manner without notice.

 TTL TYPES SN54LS395A. SN74LS395A
MSI 4-BI1 CASCADABLE SHIFT REGISTERS WITH 3-STATE OUTPUTS
BULLETIN NO. OL-S 7612114, OCTOBER 1976

SN54LS395A ..• J OR W PACKAGE

• Three-State, 4 Bit, Cascadable, SN74LS395A ••• J OR N PACKAGE
Parallel-In, Parallel-Out Registers (TOP VIEW)

• 'LS395A Offers Three Times the

Sink-Current Capability of 'LS395 .
OUTPUTS

• Low Power Dissipation ... 75 mW Typical

(Enabled)
• Applications:
N-Bit Serial-To-Parallel Converter
N-B it Parallel-To-Serial Converter
N-Bit Storage Register
description

These 4-bit registers feature parallel inputs, parallel

outputs, and clock, serial, load/shift, output control
and direct overriding clear inputs.
PARALLh INPUTS
Shifting is accomplished when the load/shift control
is low. Parallel loading is accomplished by applying logic; see functional table
the four bits of data and taking the load/shift control
input high. The data is loaded into the associated flip-flops and appears at the outputs after the high-to-Iow transition
of the clock input. During parallel loading, the entry of serial data is inhibited.

When the output control is low, the normal logic levels of the four outputs are available for driving the loads or bus
lines. The outputs are disabled independently from the level of the clock by a high logic level at the output control
input. The outputs then present a high impedance and neither load nor drive the bus line; however, sequential operation
of the registers is not affected. During the high-impedance mode, the output at GO' is still available for cascading.

FUNCTION TABLE

• ,
CLEAR

L
H
H
H
LOAD/SHIFT
CONTROL
X
H
H
L
INPUTS

CLOCK SERIAL

X
H
~

H
X
X
X
X
PARALLEL
A B C 0
X X X X L L
3-STA TE OUTPUTS

°A

L
°B

L
,X X X X OAO 0BO OCO 0DO
a b c d a b c d
X X X X 0AO 0BO 0CO 0DO
Oc 00
CASCADE
OUTPUT
aD'
L
°DO
d
°DO
H L ~ H X X X X H 0An 0Bn 0Cn °Cn
H L ~ I.,. X X X X L 0An 0Bn 0Cn OCn

When the output control is high, the 3-state outputs are disabled to the high-impedance state;
however, sequential operation of the registers and the output at QO' .are not affected_

See explanation of function tables on page 3-8.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, Vee (see Note 1) ...... . 7V

Input voltage . . . . . . . . . . . . . . . 7V
Operating free-air temperature range: SN54LS395A -55°C to 125°C
SN74LS395A oOe to 70°C
Storage temperature range -65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.

DESIGN GOAL 1076

7·496
This page provides tentative information on a
product in the developmental stage. Texas TEXAS INCORPORATED
INSTRUMENTS
Instruments reserves the right to change or dis-
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
continue this product without notice.
 TYPES SN54LS395A. SN74LS395A
4-BIT CASCADABLE SHIFT REGISTERS WITH 3-STATE OUTPUTS

recommended operating conditions

SN54LS395A SN74LS395A
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, VCC 4.5 5 5.5 4.75 5 5.25 V
QA,QB,Qc,QD -1 -2.6 mA
High-level output current, IOH
QD' -400 -400 J.lA
QA,QB, Qc,QD 12 24 mA
Low-level output current, IOL
QD' 4 8 mA
Clock frequency, fclock 0 25 0 25 MHz
Width of clock pulse, tw(clock) 25 25 ns
Setup time, high-level or low-level data, tsu 20 20 ns
Hold time, high-level or low-level data, th 10 10 ns
Operating free-air temperature, T A -55 125 0 70 °c

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS395A SN74LS395A
FARAiv1EiER iESi COr~DiTioNst Ui~ii
MIN TYPt MAX MIN TYpt MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
VIK Input clamp voltage VCC= MIN, II =-18mA -1.5 -1.5 V
QA,QB,
VCC = MIN, VIH = 2 V, 2.4 3.4 2.4 3.1 V
VOH High-level output voltage Qc,QD
VIL = VIL max, IOH = MAX
QD' 2.5 3.4 2.7 3.4 V
QA,QB, IOL = 12mA 0.25 0.4 0.25 0.4
VCC= MIN, V
Qc,QD IOL - 24 mA I 0.35 0.5 I I
VOL Low-ievei output voitage VIL = VIL max,
IOL -4 mA 0.25 0.4 0.25 0.4
VIH = 2 V QD V
0.35 0.5

•
IOL=8mA
Off-state output current, VCC= MAX, VIH=2V, QA,QB,
IOZH 20 20 J.lA
high-level voltage applied VO=2.7V Qc,QD
Off-state output current, VCC = MAX, VIH-2V, QA,QB,
IOZL -20 -20 J.lA
low-level voltage applied VO=0.4 V Qc,QD
Input current at
II VCC = MAX, VI =7V 0.1 0.1 mA
maximum input voltage
IIH High-level input current VCC= MAX, VI = 2.7 V 20 20 J.lA
IlL Low-level input current VCC = MAX, VI = 0.4 V -0.4 -0.4 mA
QA,QB,
-30 -130 -30 -130 mA
lOS Short-circuit output current§ VCC= MAX Qc,QD
QD -20 -100 -20 -100 mA
Condition A 18 29 18 29
ICC Supply current VCC= MAX, See Note 2 mA
Condition B 15 25 15 25

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAli typical values are at Vee = 5 V. T A = 25°e.
§ Not more than one output should be shorted at a time,and duration of the short-circuit should not exceed one second.
NOTE 2: lee is measured with the outputs open, the serial input and mode control at 4.5 V, and the data inputs grounded under the following
conditions:
A. Output control at 4.5 V and a momentary 3 V, then ground, applied to clock input.
. B. Output control and clock input grounded.

1076 DESIGN GOAL

This page provides tentative information on a
product in the developmental stage. Texas
TEXAS INCORPORATED
INSTRUMENTS 7-497
1nstruments reserves the right to change or d is- POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
continue this product without notice.
 TYPES SN54LS395A, SN74LS395A
4-BIT CASCADABLE SHIFT REGISTERS WITH 3-STATE OUTPUTS

switching characteristics, Vee = 5 V, TA = 25°e

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f max Maximum clock frequency 25 35 MHz
See Note 3,
tPHL Propagation delay time, high-to-Iow-Ievel output from clear 23 35 ns
QA, QB, Oc, QD outputs:
tpLH Propagation delay time, low-to-high-Ievel output 23 35 ns
RL = 667 n, CL = 45 pF
tPHL Propagation delay time, high-to-low-Ievel output 20 30 ns
QD' output:
tpZH Output enable time to high level 13 20 ns
RL =2 kn,CL = 15pF
tpZL Output enable time to low level 24 36 ns
tpHZ Output disable time from high level CL =5 pF, 11 17 ns
tpLZ Output disable time from low level See Note 3 15 23 ns

NOTE 3: Load circuit and voltage waveforms are shown on page 3-11.

functional block diagram

DATA INPUTS

A B C o
(3) (4) (5) (6)

•
(14) (13) (12) (11)
Os ac aD
I
v 00'
3-STATE OUTPUTS
CASCADE
OUTPUT

schematics of inputs and outputs

EQUIVALENT OF SERIAL
AND DATA INPUTS

Vee --~fr--Req-

"PUT_q--
-
EQUIVALENT OF
OTHER INPUTS

vee
20k r1 NOM
TYPICAL OF QA, QS. Oc. QD
OUTPUTS

------vee
TYPICAL OF QD' OUTPUTS

- - -......--vee

Serial: Req
A, B, C, D: Req
= 30 kn
= 20 kn NOM
NOM
INPUT-

o --

OUTPUT OUTPUT

DESIGN GOAL 1076

7-498
This page provides tentative information on a
product in the developmental stage. Texas
TEXAS I N STRUM ENTS
INCORPORATED
I nstruments reserves the right to change or dis~ POST OFFICE BOX 5012 • CALLAS, TEXAS 75222
continue this product without notice.
 TYPES SN54LS398, SN54LS399
TTL SN74LS398, SN74LS399
MSI QUADRUPLE 2-INPUT MULTIPLEXERS WITH STORAGE
BULLETIN NO. DL-S 7612465, OCTOBER 1976

SN54LS398 ••• J OR W PACKAGE

• Double-Rail Outputs on 'LS398 SN74LS398 ••• J OR N PACKAGE

• Single-Rail Outputs on 'LS399 (TOP VIEW)

• 'LS398 is Similar to 'LS298,

Which Has Inverted Clock
• Selects One of Two 4-Bit Data Sources
and Stores Data Synchronously with System Clock
• Applications:
Dual Source for Operands and Constants
in Arithmetic Processor; Can Release
Processor Register Files for Acquiring
New Data
Implement Separate Registers Capable of
Parallel Exchange of Contents Yet Retain
logic: see function table
External Load Capability
Universal Type Register for Implementing
Various Shift Patterns; Even Has Compound
Left-Right Capabilities SN54LS399 •.. J OR W PACKAGE
SN74LS399 .•• J OR N PACKAGE
(TOP VIEW)

Vcc Co 01 02 C2 Cl Clc CLOCK

~
description

These mono!!thic quadruple t'No-input multiplexers

with storage provide essentially the equivalent func- ws
tional capabilities of two separate MSI functions
(SN54LS157/SN74LS157 and SN54LS175/
SN74LS175) in a single 16-pin or 20-pin package.

When the word-select input is low, word 1 (A1, 81,

II
C1, 01) is applied to the flip-flops. A high input to
word select will cause the selection of word 2 (A2,
logic: see function table
82, C2, 02). The selected word is clocked to the
output terminals on the positive-going edge of the
clock pulse.

Typical power dissipation is 37 milliwatts. FUNCTION TABLE

SN54LS398 and SN54LS399 are characterized for INPUTS OUTPUTS
operation over the full military range of -55°C to WORD
125°C, SN74LS398 and SN74LS399 are character- SELECT
CLOCK aA aB Dc aD
izea for operation from O°C to 70°C.
L t a1 b1 c1 d1
H t a2 b2 c2 d2
X L QAO QBO Qeo QDO

See explanation of function tables on page 3-8.

1076

TEXAS INSTRUMENTS 7-499

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54LS398, SN54LS399, SN74LS398, SN74LS399
QUADRUPLE 2-INPUT MULTIPLEXERS WITH STORAGE

functional block diagram

A1-------,-........,
WORD
SELECT

A2---+--+-+-L-"';

B1-----+-~r-........,

B2-----f--+-IL-.../

C1-----+-+-r--........,

C2-----f--f--L-J

D1-----r--t---i,--.......

QD

'00

•
CLOCK -----------1 ~D_--------'

I
--<l> . . . . Dynam ic input activated by a transition from a high level to a low level
I
. . . . 'LS398 Only

schematics of inputs and outputs

EQUIVALENT OF EQUIVALENT OF TYPICAL OF ALL OUTPUTS

EACH DATA INPUT OTHER INPUTS
------411..... Vee
VCC
Vee ,
Req
30kn
NOM
INPUT
C.
...s--. -
INPUT .............- + - OUTPUT

~,
~~
~~
/)7

Clock: Req = 17 kn NOM

Word select: Req = 25 kn NOM

1076

7·500 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54LS398, SN54LS399, SN74LS398, SN14LS399
QUADRUPLE 2-INPUT MULTIPLEXERS WITH STORAGE

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ..... 7 V
Input voltage . . . . . . . .... . . . . . . 7V
Operating free·air temperature range: SN54LS' -55°C to 125°C
SN74LS' oOe to 70°C
Storage temperature range -65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54lS' SN74lS'
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -400 -400 /.LA
Low-ievei output current, 10l 4 8 mA
Width of clock pulse, high or low level, tw 20 20 ns
C" ....... _ .... : _ _
uCl.u ..... 1..IIIn::;,
....
"'su I Data 20 20
ns
25 25

Hold time, th
o o
o o
Operating free-air temperature, T A -55 125 o 70

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54lS' SN74lS'
PARAMETER TEST CONDITIONSt UNIT
MIN TYP+ MAX MIN TYP+ MAX
VIH High·level input voltage 2' 2 V
ViL Lovv-Iavel input voltage 0.7 0.8 V
VIK Input clamp voltage Vee - MIN, II - -18 mA -1.5 -1.5 V
Vee= MIN, VIH = 2 V,
VOH High-level output voltage 2.5 304 2.7 304 V
Vil = VILmax 10H = -400 /.LA

VOL Low-level output voltage

Input current at
Vee - MIN,
Vil = VILmax
VIH - 2 V, llOL - 4 mA
I 10L -8 mA
0.25 004 0.25
0.35
004
0.5
V II
II Vee = MAX, VI =7 V 0.1 0.1 mA
maximum input voltage
IIH High-level input current Vee = MAX, VI - 2.7 V 20 20 /.LA
IlL low-level input current Vee - MAX, VI-OAV -004 -004 mA
lOS Short-circuit output current§ Vee = MAX -20 -100 -20 -100 mA
lee Supply current Vee = MAX, See Note 2 7.3 13 7.3 13 mA

t For conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at Vee = 5 V, T A = 25°C.
§ Not more than one output should be shorted at a time, duration of the short-circuit should not exceed one second
NOTE 2: With all outputs open and all inputs except clock low, ICC is measured after applying a momentary 4.5 V, followed by ground, to
the clock input.

switching characteristics, Vee = 5 V, TA = 25°e

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tpLH Propagation delay time, low·to-high·level output eL = 15pF, RL = 2 kn, 18 27
ns
tPHL Propagation delay time, high-to-Iow-Ievel output See Note 3 21 32

NOTE 3: Load circuit and waveforms are shown on page 3-11.

1076

TEXAS INCORPORATED
INSTRUMENTS 7-501
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TTL TYPES SN54S412, SN74S412 (TIM8212)
MSI MULTI-MODE BUFFERED LATCHES
BULLETIN NO. DL-S 7512351, OCTOBER 1975

• P-N-P Inputs and 3-State Outputs Maximize SN54S412 _•• J PACKAGE

SN74S412 ••• J OR N PACKAGE
I/O and Data Bus Capabilities (TOP VIEW)
• Data Latch Transparency Permits OAT A INPUTS AND OUTPUTS

Asynchronous or Latched Receiver Modes

• Mode and Select Inputs Permit Storing
With Outputs Enabled or Disabled
• Strobe-Controlled Flag Flip-Flop Indicates
Status or Interrupt
• Asynchronous Clear Sets All Eight Data
Lines Low and Initializes Status Flag
• High-Level Output Voltage, Typically 4 V,
Drives Most MOS Functions Directly
• Direct Replacement for Intel 3212
or 8212 logic: see function table

description

This high-performance eight-bit parallel expandable buffer register incorporates package and mode selection inputs and
an edge-triggered status flip-flop designed specifically for implementing bus-organized input/output ports. The
three-state data outputs can be connected to a common data bus and controlled from the appropriate select inputs to
receive or transmit data. An integral status fl ip-flop provides package busy or request interrupt commands. The outputs,
with a 4-volt typical high-level Voltage, are compatible for driving low-threshold MOS directly.

DATA LATCHES

The eight data latches are fully transparent when the internal gate enable, G, input is high and the outputs are enabled

II
(OE = H). Latch transparency is selected by the mode control (M), select (Sl and S2), and the strobe (STB) inputs and
during transparency each data output (DOi) follows its respective data input (Dli)' This mode of operation can be
terminated by clearing, de-selecting, or holding the data latches. See data latches function table.

MODE SELECTION

An input mode or an output mode is selectable from this single input line. In the input mode, MD = L, the eight data
latch inputs are enabled when the strobe is high regardless of device selection. If selected during an input mode, the
outputs will follow the data inputs. When the strobe input is taken low, the latches will store the most-recently setup
data.

In the output mode, M = H, the output buffers are enabled regardless of any other control input. During the output
mode the content of the register is under control of the select ($1 and S2) inputs. See data latches function table.

STATUS FLIP-FLOP

The status flip-flop provides a low-level output Signal when:

a. the packagj is selected

b. a strobe input is received.

This status signal can be used to indicate that the register is busy or to initiate an interrupt type command.

TENTATIVE DATA SHEET 1076

This document provides tentative information TEXAS IN ST RU M ENTS
7-502 n arr:-w product. Texas 1~~tlfrO-r ~
0tha INCORPORATED
itht to change specifications thiS POST OFFICE BOX 5012 • DALLAS TEXAS 75222
product in any manner without 1'IOtic:e. .
 TYPES SN54S412_. SN74S412 (TIM8212)
MULTI-MODE BUFFERED LATCHES

functional block diagram

r---- - - -- ----- - - ---- -----,
I
I
PRESET I
o Q

STB (11)
(2)
M

51 """-~~.........
S2 I----~~=O"'-_+_......._L - j 7<>-+-- iNT
L-------~--~-L_/

011 (3)

J:---+--+-~D02
012 (5)

013 (7)

014 19) 1101

I-+--+~ >--+-....:..:..::.~ DO 4

DIS 118)
115) DOS

016 lIS)
,>-...!...-..:..:ll.:.,:.7)_ DO 6

017 120)
I 119) 007

DIS 122)
121) DOS
I
I
CUi 114)
I
L ________________________ --.J

schematics of inputs and outputs

EQUIVALENT OF CLEAR, STROBE, EQUIVALENT OF EACH 01 INPUT TYPICAL OF ALL OUTPUTS
MODE, S1, AND S21NPUTS
vcc-------------.--------~
------....---vcc
vcc----__.-__4 -

OUTPUT
INPUT

I NPUT---.-:IiI.....--I

1076

TEXAS INCORPORATED
INSTRUMENTS 7-503
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54S412, SN~4S412 (TIM8212)
MULTI-MODE BUFFERED LATCHES

DATA LATCHES FUNCTION TABLE

FUNCTION CLEAR M S1 S2 STB DATA IN DATA OUT

L H H X X X L
Clear
L L L H L X L
X L X L X X Z
De-select
X L H X X X Z
H H H L X X 00
Hold
H L L H L X 0.0
H H L H X L L
Data Bus
H H L H X H H
H L L H H L L
Data Bus
H L L H H H H

STATUS FLIP-FLOP FUNCTION TABLE

CLEAR S1 S2 STB
-INT
L H X X H
L X L X H
H X X -l- L
H L H X L

H == high level (steady state)

L == low level (steady state)
X ==irrelevant (any input, including transitions)
Z == high impedance (off)
-l- ==transition from low to high level

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) .... 7 V
Input voltage . 5.5 V
Operating free-air temperature range: SN54S412 · -55°C to 125°C
· . oOe to 70°C
I Storage temperature range. .
SN74S412

NOTE 1: Voltage values are with respect to network ground terminal.

· -65°C to 150°C

recommended operating conditions

SN54S412 SN74S412
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, VCC 4.5 5 5.5 4.75 5 5.25 V
Pulse width, tw I STB or S"1 • S2 25 25
ns
(see Figures 1,2, and 41 I Clear low 25 25 I
Setup time, tsu (see Figure 3) 15-l- 15-l- ns
Hold time, th (see Figures 1 and 3) 20-l- 20-l- ns
Operating free-air temperature, T A -55 125 0 70 °c
-l- The arrow indicates that the falling edge of the clock pulse is used for reference.

1075

7-504 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54S412, SN74S412 (TIM8212)
MULTI-MODE BUFFERED LATCHES

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54S412 SN74S412
PARAMETER TEST CONDITIONSt UNIT
MIN Typf MAX MIN Typf MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.85 0.85 V
VIK Input clamp voltage Vee = MIN; II = -18mA -1.2 -1.2 V
Vee=MIN, VIH = 2 V,
VOH High-level output voltage 3.65 4 3.65 4 V
VIL = 0.8 V, 10H= -1 rnA
Vee=MIN, I 10L = 15mA 0.45 0.45
VOL Low-level output voltage VIH=2V, V
IIOL -20mA 0.5 0.5
VIL = 0.8 V
Off-state output current, DO 1 thru
10ZH Vee = MAX, Vo =2.4 V 50 50 IJ.A
high-level voltage applied 008
Off-state ou tput cu rrent, DO 1 thru
10ZL Vee = MAX, Vo =0.5 V -50 -50 IJ.A
low-level voltage applied 008
Input current at
II Vee = MAX, V! = 5.5 V 1 1 ~I\

maximum input voitage

IIH High-level input current Vr.C=MAX, V! =5.25 V 20 10 p..A
81 -1 -1
IlL Low-level input current M Vee= MAX, VI =0.4 V -0.75 -0.75
rnA
All others -0.25 -0.25
lOS Short-circuit output current § Vee = MAX -20 -65 -20 -65 rnA
ICC Supply current Vee = MAX, see Note 2 82 82 130 rnA

t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
TAli tYpical values are at Vee = 5 V, T A = 25°e.
§Not more than one output should be shorted at a time.
NOTE 2: iee is measured with ail outputs open, ciear input at 4.5 V. and all other inputs grounded.

switching characteristics, Vee = 5 V, TA = 25°e

PARAMETER
tpLH
FROM

STB, 51, or S2
TO
Any
FIGURE

1
TEST CONDITIONS MIN TYP
18
MAX
27
UNIT

ns
I
tpHL DO 15 25
eL =30pF,
tpHL eLR Any DO 2 18 27 ns
See Note 3
tpLH 12 20
Dli DOi 3 ns
tpHL 10 20
tPLH S10rS2 INT 4 eL =30pF, 12 20
ns
tPHL STB INT 4 See Note 3 16 25
tZH eL=30pF, 21 35
51,S2,orM Any DO 5 ns
tZL See Note 3 25 40
tHZ eL = 5 pF, 9 20
51,S2,orM Any DO 5 ns
tLZ See Note 3 12 20

tpLH ==propagation delay time, low-to-high-Ievel output

tpHL == propagation delay time, high-to-Iow-Ievel output
tZH ==output enable time to high levlli
tZL ==output enable time to low level
tHZ ==output disable time from high level
tLZ == output disable time from low level
NOTE 3: Load circuit and voltage waveforms are shown on page 3-10.

1076

TEXAS INSTRUMENTS 7-505

INCORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPE5 5N545412. 5N145412 (TIM8212)
MULTI-MODE BUFFERED LATCHE5

PARAMETER MEASUREMENT INFORMATION

DATA INPUT ___ ~.~V)(------- - ,~.~ __ ::V

~ tw -:r---~~--- 2.5 V
STB OR 5'·S2 ,.5V! \,.5 V
_ _ _ _ _ _. J !+tPHL ~ '------- OV

- - - - - - - --I~;------
VOH
DATA OUTPUT
VOL
FIGURE' - S"rROBE OR SELECT TO DATA OUTPUT

CLEAR INPUT
- _ _ _ _ _ _...... ~ !wIeld

,.
5V
k ...j
t..5~
~______

_ _ _ _ _ _ _..:........_---.:..tp.:..:.H;;:...L~ _ _ _ _ _ _
_____
2.5 V

OV

VOH
DATA OUTPUT \,.5V

FIGURE 2 - CLEAR INPUT TO DATA OUTPUT

DATA INPUT '.5V X- - ---- - - ~.5V

2.5 V

- - - -..../ I4-- t SU" th~'- - - - - ov

STBOR 8'·S2
I . {,~ ;- - - - - - - - 2.5 V

L- --I OV
~tPHL
-----....:......-~;--------- VOH
DATA OUTPUT
-------/ . VOL
FIGURE 3 - DATA INPUT TO DATA OUTPUT

2.5 V
STROBE
OV

I I ~
2.5 V

_______....!I__ !w(sell I.. .'J:;;I -;P~H 0V

V- VOH
INTERRUPT OUTPUT I \ j-,_.5.5_'V
~~tp-H-L-------~ VOL

FIGURE 4 - STROBE OR SELECT TO INTERRUPT OUTPUT

_ _---J
/'V
I
\~,~
I
--- ::v
---I tZH I-- ---! tHZ r C 0.5 V

DATA OUTPUT ! l,------~,--""'~

IHIGHSTORED) _ _ _ -----=-:_-.J - ' : : V : t
--t tZL I.- --l
I
DATA OUTPUT
(LOW STORED)
- - - - - - - - . , , - - - - • 45 V
.,.5V F CO. 5V

~-----------~ +
FIGURE 5 - SELECT TO DATA OUTPUT

1075

7-506 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TTL TYPE SN74LS424 (TIM8224)
MSI TWO-PHASE CLOCK GENERATOR/DRIVER
BULLETIN NO. DL-S 7612475, OCTOBER 1976

• Designed to be Interchangeable With Intel 8224

• Single-Chip Clock Driver With
Self-Contained Oscillator J OR N PACKAGE
(TOP VIEW)
• Specifically Designed to Drive
All 8080A Microprocessors
XTAL XTAL TANK QSC 61 02

description

This clock generator is capable of driving 12-volt

lines. It contains a crystal-controlled oscillator, a
divide-by-nine clock phase generator, two high-level
drivers, and auxiliary circuitry. RESET

The internal oscillator is designed to operate with

fundamental-mode crystals, or with overtone-mode
crystals when using a parallel-tuned circuit connected
..1.. . . . . . . . . L._ 1...
.&. _ _ 1
.&. _ _ _ : _ _ ..... :_ 1') T ..... _ ..... __ :11 ... + __ ...... + ........ +
I.U Lilt: lalll'- LeIIIIlIIOI, 1-1111 Iv. Ille V;, .... IIIQlVI VUq.JUl

appears on pin 12 and drives the divide-by-nine RESET RESIN RDYIN READY SYNC 62 STSTS GND
OUT iNPUT TTL OUT
counter. The 79 clock phase generator output
consists of phases cf>2 for driving MOS inputs and
cf>2 TTL for driving TTL. Three other TTL outputs,
status strobe, reset, and ready, are coupled to the trigger. A rising voltage waveform is triggered at a
divide-by-nine counter. A sync input from the SOSOA particular voltage. A synchronized ready output is
is AND'ed with cf>1A to produce the status strobe. obtained by clocking with a cf>2 signal.
The power-on reset also generates the status strobe
signal through an output NOR gate. The reset input The SN74LS424 is characterized for operation over
works on a voltage-level basis by use of a Schmitt the temperature range of DoC to 70°C.

functional block diagram

•
(15)
XTAL 1
(12) OSC

XTAL 2

TANK -,-I1_3,-)_ _ _.......

(11) qil
79
CLOCK
PHASE (10) <b2
GEN
>-___....:.(6;:.:.)_qi2TTL
qi2D qilA

STATUS
~~~JT-(~5~)-----+------~__~ STROBE
STSTB
RESET
INPUT
RESIN

>-__----(;...1.;...) RESET

READY
INPUT ~---~(~4)~READY
RDYIN

1076

TEXAS INSTRUMENTS 7-507

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPE SN74LS424 (TIM8224)
TWO-PHASE CLOCK GENERATOR/DRIVER

schematics of inputs and outputs

EQUIVALENT OF RESET EQUIVALENT OF XTAL 1 AND TYPICAL OF <P1. <P2 OUTPUTS

AND SYNC INPUTS XTAL 2 NODES
-.-----------.--.--VDD
Vee Vee-----~~~.-
Skn
NOM r;RESET
---t~--,
\oJ I

SYNC I NPUT-------

INPUT

~--...~._ OUTPUT

EQUIVALENT OF READY INPUT EQUIVALENT OF TANK INPUT TYPICAL OF ALL OUTPUTS

EXCEPT <P1. <P2

Vee
V e e - -- - -+---- V e e - - - t - -.....
S kn 200n
NOM NOM
INPUT-"';"'---4I~-I

•
INPUT OUTPUT

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . 7V
Supply voltage, VDD . . . . . 17 V
Input voltages (sync, reset, ready) . 7V
Operating free·air temperature range, T A oOe to 70°C
Storage temperature range . . . . . -65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.

1076

7-508 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPE SN74LS424 (TIM8224)
TWO-PHASE CLOCK GENERATOR/DRIVER

recommended operating conditions

MIN NOM MAX UNIT
Supply voltage, Vee 4.75 5 5.25 V
Supply voltage, VOO 11.4 12 12.6 V

Ready input se.tup time, tsu(ROYIN) 50-~ ns

Ready input hold time, th(ROYIN) ~ ns

9
Operating free-air temperature range, T A 0 25 70 °e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP* MAX UNIT

Reset input 2.6
VIH High-level input voltage V
Ali others 2
Vil low-level input voltage 0.8 V
VT+-VT- Hysteresis Reset input 0.25 V
11- -5 mA -1
VIK Input clamp voltage Vee: 4.75 V, VOO:11.4V V
li--1SmA -1.5
t/>1,t/>2 9.4 10.4
10H: -100.uA
VOH High-level output voltage Ready, reset Vee: 4.75 V, VOO:11.6V 3.6 3.9 V
Others IOH--1mA 2.4 3.1
t/>1, t/>2, reset,
10l :2.5mA 0.2 0.45
Val low-level output voltage status strobe Vee: 4.75 V, VOO: 11.4 V V
<P2 TTL, osc 10l: 15mA 025 0.45
Input current at
II Vee: 5.25 V, VOO = 12.6V, VI = 7V 100 !-LA
maximum input voltage
ilH High-level input current Vee: 5.25 V, VOO = 12.6 V. VI = 5.25 V 10 .u A
III low-level input current Vee = 5.25 V, VOO=12.6V. VI:O.4V -0.25 mA
Short-circuit All except
lOS Vee: 5 V. VOO:12V -10 -60 mA

I
ci rcu it cu rrent § t/>1, t/>2
ICC Supply current from Vee Vee: 5.25 V, VOO:12V 70 115 mA
100 Supply current from VOO VOO = 12.6 V. Vee = 5 V, See Note 2 6 12 mA
Vee: 5 V. VOO: 12 V, VI = 2.5 V.
ei Input capacitance 8 pF
f = 1 MHz, See Note 2

*AII typical values are at Vee: 5 V. Voo = 12 V. T A: 25°C.

§ Not more than one output should be shorted at a time. t/>1 and t/>2 do not have short-circuit protection.
NOTE 2: ICC and 100 are measured with outputs disabled and open.

1076

TEXAS INCORPORATED
INSTRUMENTS 7-509
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPE SN74LS424 (TIM8224)
TWO-PHASE CLOCK GENERATOR/DRIVER

switching characteristics, Vee = 5 V, V DD = 12 V, T A = 25°e, see figure 1

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f max Maximum oscillator frequency 27 MHz
ns
tc(osc) Oscillator cycle time .!2:
9
tw(cp1) Pulse width, cp1 high 2tc _ 20 ns
cp1 and cp2: 9

t w (cp2) Pulse width, cp2 high CL = 20 pF to 110 pF, ~-35 ns

See Figure 2 9

tw(SS) Pulse width, status strobe low .!£.- 15 ns

cp2TTL: 9
Rise time, clock outputs CL = 30 pF, R1 = 300 n, 20 ns
tr(cp)
Fall time, clock outputs R2 = 600 n, See Figure 3 20 ns
tf(cp)
tcp1L,cp2H Delay time, cp1 low to cp2 high 0 ns
Status Strobe:
tcp2L,cp1H Delay time, cp2 low to cp1 high 2tc _ 14 ns
CL=15pF, R1=2kn,
9
R2=4kn, See Figure 3
t¢lH,q,2H Delay time, q,1 high to q,2 high ~ 2tc + 20 ns
9 9
OSC, Ready, Reset:
tq,2,cp2T Delay time, cp2 to cp2 TTL CL=10pF, R1 = 2 kn, -5 15 ns
R2=4kn, See Figure 3

tq,2H,SSL
Delay time, q,2 high to ~-30 6t c ns
status strobe low 9 S-
Delay time, ready or reset
tRV, q,2L ~-25 ns
output valid to phase 2 low 9

EXAMPLE: switching times for fosc = 20 MHz (tc(¢1) = tc(¢2} = 450 ns)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fosc Oscillator frequency 20 MHz
tc(osc) Oscillator cycle time 50 ns
tw(¢l) Pulse width, q,1 high 80 ns

I t w (q,2)

tw(SS)
Pulse width, cp2 high

Pulse width, status strobe

215

35
ns

ns

t<1>lL,cp2H Delay time, <1>1 low to <1>2 high Same as above I 0 ns

tq,2L,q,lH Delay time, q,2 low to q,1 high 86 ns
tcp1H,q,2H Delay time, q,1 high to q,2 high 100 120 ns
Delay time, q,2 high to
tcp2H,SSL 270 300 ns
status strobe low
Delay time, ready or reset
tRV,cp2L 175 ns
output valid to cp2 low

1076

7-510 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPE SN74LS424 (TIM8224)
TWO-PHASE CLOCK GENERATOR/DRIVER

PARAMETER MEASUREMENT INFORMATION

tc(OSCl-r----1

OSC

ct>2TTL _ _ _ _ _ _ _ _ _ _-+l if 1.5 V I \"'_1.5_V

_ _ _ _ _ _ _ _ _ __

! I
SYNC
(FROM 8080A)
\
\
i /
I'
1I ~~~~
~tw(SS) I_ tct>2H,SSL I -, I
I I 1 1,_----
STATUS
STROBE
~'.5V '.5V~'.5V
--.ll.-tsu(RDYINl I
READY It- th(RDYINl -I I
-~5~±- _ _ _ _ _ _ _ _ _ 1l.;V---
~
-r
- _
..:J!,;;._ _ _ _ _ - -- - ---- ------_
-+I______________
RESET
INPUT r tRV ,ct>2L----1
- - - -- - - - - - - -- - ~~------+I---------------
READY OUTPUT _ _ _ _ _ _ _ _ _ _ _ _ _ _'_.5_V....'l.. _____ +-____________ _

I'---tRV, ct>2L---!
RESET OUTPUT ---------------~~~I_,~.5_V_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

NOTE: Transistion times, pulse widths, and interpulse relationships are distorted in this diagram in order to define various intervals, See Figure 5
I
for correct relative relationships,

VOLTAGE WAVEFORMS

FIGURE 1

Vcc

~
OUTPUT
Rl
UNDER
TEST
CL R2

LOAD CIRCUIT LOAD CIRCUIT

FIGURE 2 FIGURE 3

1076

TEXASINCORPORATED
INSTRUMENTS 7-511
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPE SN74LS424 (TIM8224)
TWO-PHASE CLOCK GENERATOR/DRIVER

TYPICAL APPLICATION DATA

The 'LS424 is a single-chip clock generator/driver for 8080A CPU's, furnishing three clocks (</>1, </>2 and </>2 TTLl. status
strobe, reset, and ready signals. The 'LS424 contains a crystal-controlled oscillator, a divide-by-nine counter, two
high-level drivers, and several auxiliary logic functions. Figure 4 is a functional block diagram of the SN74LS424.
Figure 5 shows the relationship between </>1, </>2, and the oscillator frequency period.

oscillator
A high order of clock frequency stability is provided by use of an external quartz crystal to set the oscillator frequency
which is nine times the operating frequency of the 8080A. The quartz crystal is operated in a series·resonant mode. A
fundamental-mode crystal requires no auxiliary circuitry, but an overtone-mode crystal requires an ac-coupled
parallel-resonant circuit to be connected to the tank connection (pin 13). The "parallel-resonant circuit, tuned to the
oscillator frequency, compensates for the lower Q of the overtone"-mode crystal. The required size of the circuit
components can be calculated from f = 1/2rrv'LC where f is the oscillator frequency, L is inductance value, and C is
capacitance value. Figure 6 shows an ac-coupled parallel-tuned circuit used with the SN74 LS424.

clock phase generator

The divide-by-nine clock phase generator contains a divide-by-nine counter, logic required to shape the clock pulses as
shown under parameter measurement information, gates and flip-flops to generate auxiliary signals, and output drivers.
The divide-by-nine counter waveforms are combined with gates to form a </>1 pulse with a width of two periods of the
oscillator frequency, repeating at intervals of nine oscillator periods. Similarly, the </>2 pulse, having a width of five
oscillator frequency periods, is formed lagging the </>1 pulse by two oscillator periods.
</>1 and </>2 outputs are provided by high-level drivers for direct connection to the 8080A CPU. </>2 TTL is derived in a
manner similar to </>1 and </>2, but the output driver output is at TTL voltage levels. The </>2 TTL pulse width is the same
as </>2. A </>2 TTL application is clocking in direct memory access activities. Figure shows the 'LS424 connected to an
8080A, quartz crystal, and LC circuits.

status strobe
The 8080A CPU puts status information on its data bus at the beginning of each machine cycle that defines the nature
of the machine operation for that cycle. A sync signal from the 8080A is gated by an internal timing signal (</>lA) and
becomes a status strobe to notify system components that the status data is present on 8080A status output lines. The
status strobe signal connects directly to the 'S428 system controller.
I The status strobe signal is alternatively generated by the reset input. An external RC series network connected to VCC
and the reset input will provide a rising voltage waveform when VCC is turned on. An internal Schmitt trigger circuit
generates a sharp, fast-rising waveform when the reset input reaches a particular voltage value. The Schmitt trigger is
connected to the D input of a flip-flop clocked by </>2D. When power is turned on, the combination of internal and
external circuitry will produce a status strobe signal. A manual reset switch can be connected as in figure 6 to the RC
network to produce reset and status strobe signals for the 8080A.
The ready signal indicates to the 8080A that an external device has completed transfer of data to or from the data bus.
A ready signal input to the 'LS424 drives the D input of a flip-flop clocked by an internal </>2D signal. Timing
requirements of the 8080A machine cycle are met by the synchronization with the system clocks provided by the
flip-flop. This implementation saves about 200 ns of system time during memory cycles (as contrasted with generating a
"wait request" within the 8080A's MOS logic) since the bipolar logic of the 'LS424 has much less delay,

1076

7·512 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPE SN74LS424 (TIM8224)
TWO-PHASE CLOCK GENERATOR/DRIVER

TYPICAL APPLICATION DATA

Qil

Qi2 1
1 UNIT=-
qi2TTL fosc
cp1

STATUS
STROBE cp2
STSTB

Example: 8080A cycle = 450 ns

fosc: 20 MHz (unit = 50 ns)
(1)
RESET tw\qjij = 100~:; (2 X 50 :--::;)
t w (cp2) = 250 ns (5 X 50 ns)
(4)
READY
tcp2L,cp1 H = 100 ns (2 X 50 ns)

FIGURE 4 FIGURE 5

QUARTZ

r-- -- --,
I L:
0 CRYSTAL

I
I
ICs'X'
C

I
XTAL2 XTAL 1
(14) (15)
I
IL C~C
_ _ _ _ _ _ ..JI (11) ¢1
(12)
OSC (10) ¢2 (15)
(6)
¢2TTL
(4) READY
READY (3)
(23)
(RDYIN) 'LS424 8080A
CPU
VCC
(1) RESET(12)
R

r
MANUAL::::r::;
SWITCH RESET (2) (5) SYNC (19)
(RESIN)

l' (7) STATUS

STROBE
(STSTB)

FIGURE 6

1076

TEXASINCORPORATED
INSTRUMENTS 7-513
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TTL TYPES SN74S42B(TIMB22B). SN74S43B(TIMB23B)
LSI CONTROLLER AND BUS DRIVER FOR BOBOA SYSTEMS
BULLETIN NO. DL-S 7612468, OCTOBER 1976

N PACKAGE
• Designed to Be Interchangeable with Intel 8228 (TOP VIEW)
and 8238
PIN DESIGNATIONS

DESIGNATION PIN NOS. FUNCTION

15, 17, 12, 10, BIDIRECTIONAL DATA PORT
DO thru D7
6, 19.21,8 (TO TMS 8080A)
13. 16. 11.9. BIDIRECTIONAL DATA PORT
DBO thru DB7
5, 18. 20, 7 (TO SYSTEM BUS)
READ OUTPUT TO I/O
I/OR 25
(ACTIVE LOW)
WRITE OUTPUT TO I/O V
10/w 27 BIDIRECTlONA.L DATA PORTS
(ACTIVE LOW)
READ OUTPUT TO MEMORY logic: see description
MEMR 24
(ACTIVE LOW)
WRITE OUTPUT TO MEMORY
MEMW 26 functional block diagram
(ACTIVE LOW)
INPUT TO INDICATE
DBIN 4 TMS 8080A IS IN INPUT

~
DO

DB~
MODE (ACTIVE HIGH) Dl DBl
INTERRUPT ACKNOWLEDGE D2 DB2
INTA 23 i
OUTPUT (ACTIVE LOW) TM~/~080A D3 DB3 SY~JoEM
HOLD ACKNOWLEDGE DATA PORT D4 DB4 DATA PORT
D5 DB5
HLDA 2 INPUT (ACTIVE HIGH) D6 DB6
FROM TMS 8080A D7 DB7

INPUT TO INDICATE
WR 3 TMS 8080A IS IN WRITE
STATUS (1)
MODE (ACTIVE LOW) STROBE
INPUT
SYSTEM DATA PORT
BUS EN 22 ENABLE INPUT (ACTIVE
LOW)

I STsTB 1
SYNCHRONIZING STATUS
STROBE INPUT FROM
SN74LS424 (TIM8224)
VCC 28 SUPPLY VOLTAGE (5 V)
I GND 14 IGROUND vcc = PIN (281. GND = PIN (14)

description

These monolithic Schottky-clamped TTL system controllers are designed specifically to provide bus-driving and
peripheral-control capabilities for interfacing memory and I/O devices with the 8080A in small to medium-large micro-
computer systems.

A bidirectional eight-bit parallel bus driver is provided that isolates the 8080A bus from the memory and I/O data bus
allowing the system designed to utilize cost-effective memory and peripheral devices while obtaining the maximum
efficiency from the microprocessor. The TTL system drivers also provide increased fan-out with a lower impedance
that enhances noise margins on the system bus.

Implementation of the status latches and control decoding array of the SN74S428/SN74S438 provides for using
either a single-level interrupt vector RST7 for small systems, or multiple-byte call instructions for systems needing
unlimited interrupt levels.

TENTATIVE DATA SHEET

This document provides tentative information T I 1076

7·514 on a new product. Texas Instruments reserves EXAS N STRUM ENTS

the right to change specifications for this INCORPORATED
product in any manner without notice. POST OFFICE BOX 5012 • OALLAS, TEXAS 75222
 TYPES SN74S428(TIM8228), SN74S438(TIM8238)
CONTROLLER AND BUS DRIVER FOR 8D8DA SYSTEMS

description (continued)

With respect to the system clocks, the SN74S438 is configured to generate an advanced response for I/O or memory
write output signals to further simplify peripheral control implementation of complex systems. See Figure 3.

8-bit parrallel bus transceiver

The 8-bit parallel bus transceiver buffers the 8080A data bus from the memory and I/O system bus by providing
one port (DO through 07) to interface with the 8080A and another port (DBO through DB7) to interface with the
system devices. The 8080A side of the transceiver is designed specifically to interface with the microprocessor data
bus ensuring not only that the processor output drive capabilities are adequate, but also that the inputs are driven
with enhanced noise margins. The system bus side features high fan-out buffers designed to drive a number of system
devices simultaneously and directly. The system port is rated to sink ten milliamperes of current and to source one
milliampere of current at standard low-threshold voltage levels.

Status lines from the 8080A instruction-status decoder and the system bus enable input (BUSEN) provide complete
transceiver directional and enable control to ensure integrity of both the processor data and the system bus data.

status latches

During the beginning of each machine cycle, the six status latches receive status information from the 8080A data
bus indicating the type of operation that will be performed. When the STsTB input goes low, the latches store the
status data and generate the signals needed to enable and sequence the memory and I/O control outputs. The status
words and types of machine cycles are enumerated in Table A.

TABLE A - STATUS WORDS

80SOA 'S4281'S438
STATUS TV!>E OF
STATUS OUTPUT COMMAND
WORD MACHINE CYCLE
DO 01 02 03 D4 05 D6 07 GENERATED
1 L H L L L H L H I nstruction fetch MEMR
2 L H L L L L L H Memory read MEMR
3
4
L
L
L
H
L
H L
L L
L
L
L
L
L
L
H
Memory write
Stack read
MEMW
MEMR
I
5 L L H L L L L L Stack write riiiEii.1W
6 L H L L L L H L Input read IIOR
7 L L L L H L L L Output write I/OW
8 H H L L L H L L Interrupt acknowledge iNTA
9 L H L H L L L H Halt acknowledge NONE
10 H H L H L H L L Interrupt acknowledge at halt INTA
« ::.: «
~
f- 0.. c:
f- U f- :;) i ~ :2
~ ~
-l 0 W
J: :2
CIl

STATUS INFORMATION

decoding array

The decoding array receives enabling commands from the status latches and sequencing commands from the 8080A
and generates memory and I/O read/write commands and an interrupt acknowledgement.

1076

TEXAS INCORPORATED
INSTRUMENTS 1-515
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN74S428(TIM8228), SN74S438(TIM8238)
CONTROLLER AND BUS DRIVER FOR 8080A SYSTEMS

description (continued)

The read commands (MEM"R, I/OR) and the interrupt acknowledgement (lNTA) are derived from the status bit(s)
and the data bus input mode (DBIN) signal. The write commands (M"EMW, i/OW) are derived from the status bit(s)
and the write mode (WR) signal. (See Table A.) All control commands are active low to simplify interfacing with
memory and I/O controllers.

The interrupt acknowledgement (lNTA) command output is actually a dual function pin. As an output, its function
is to provide the ii\i'TA command to the memory and I/O peripherals as decoded from the status inputs and latches.
When CALL is used as an interrupt instruction, the SN74S428/SN74S428 generates the proper sequence of control
signals. Additionally, the terminal includes high·threshold decoding logic that permits it to be biased through a one-
kilohm series resistor to the 12-volt supply to implement an interrupt structure that automatically inserts an RST7
instruction on the bus when the DBIN input is active and an interrupt is acknowledged. This capability provides a
single·level interrupt vector with minimal hardware.

The asynchronous bus enable (BUSEN) input to the decoding array is a control signal that protects the system bus.
The system bus can be accessed and driven·from the SN74S428/SN74S428 controller only when the BOSEN'input
is at a low voltage level.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, VCC (see Note 1) ... 7 V

Input voltage . . . . . . . . 7V
Operating free·air temperature range O°C to 70°C
Storage temperature range -65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

MIN NOM MAX UNIT
Supply voltage, Vee 4.75 5 5.25 V

I High·level output current, IOH

DO thru 07
All othel1i
DO thru 07
-10
-1
2
jlA
rnA

Low-level output current, IOL rnA

All othel1i 10
Status strobe pulse width, tw(STSTBi (see Figure 3; , 22 ns
Status inputs DO thru 07 8
Setup time, tsu (see Figure 3) ns
System bus inputs to HLOA 10
Status inputs DO thru 07 5
Hold time, th (see Figure 3) ns
System bus inputs to HLOA 20
Operating free-air temperature, T A 0 70 °e

1076

7-516 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN74S428(TIM8228), SN74S438(TIM8238)
CONTROLLER AND BUS DRIVER FOR 8080A SYSTEMS

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP:j: MAX UNIT
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
VIK Input clamp voltage VCC =MIN, II = -5 rnA -1 V
00 thru 07 VCC =MIN, VIH-2V, 3.6 4
VOH High-level output voltage V
All other outputs VIL = 0.8 V, 10H = MAX 2.4
VCC = MIN, VIH=2V,
VOL Low-level output voltage 0.45 V
VIL = 0.8 V, 10L = MAX
Off-51:ate output current,
10ZH VCC =MAX, Vo =5.25 V 100 IJA
high-level voltage applied
Off~te output current,
10ZL VCC =MAX, Vo = 0.45 V -100 JJA
low-level voltage applied
INTA Vee= MIN, See Figure 1 5 rnA
IIH High-level input current 00 thru 07 20
VCC = MAX, VI =5.25 V JJA
All other inputs 100
I u2 or u6 -/bU

IlL Low-level input current STSTB IVCC = MAX, VI =0.45 V -500 JJA I
I Short·drcuit output current§
All other inputs
VCC = MAX -15
-250
-90 rnA
lOS
ICC Supply current VCC =MAX 140 190 rnA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at Vee = 5 V, T A = 25°e.
§ Not more than one output should be shorted at a time.

switching characteristics, Vee =5 V, TA =25°e, see figure 3

FROM

•
TO
PARAMETER1I TEST CONDITIONS MIN TYP MAX UNIT
(INPUT) (OUTPUT)
tpo DO thru 07 DBO thru OB7 CL = 100 pF, See Figure 2 5 40 ns
tPD DBO thru DB7 DO thru D7 CL = 25pF, See Figure 2 30 ns
INTA, '"i7(5R, MEMR,
tPHL STSTB 20 60 ns
mJiJ, MEiiiiW
tpo WR 1f(YoN,MEMW CL = 100pF, See Figure 2 5 45 ns
tpLH DBIN INTA, i70R, MEMR 30 ns
tpLH HLDA INTA, i7QR, MEMR 25 ns
tpZX DBIN DO thru D7 45 ns
CL=25pF, See Figure 2
tpxz DBIN DO thru D7 45 ns
tpZX STSTB, BOSEfij DBO thru DB7 30 ns
CL = 100pF, See Figure 2
tpXZ i3Om'l DBO thru DB7 30 ns

11 tp 0 == propagation delay time

tpH L == propagation delay time, hiltJ-to-low-level output
tpLH == propagation delay time, low-to-high-Ievel output
tpZX == output enable time from hiltJ-impedance state
tpXZ == output disable time to high-impedance state

1076

TEXAS INCORPORATED
INSTRUMENTS 7-517
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN74S428(TIM8228), SN74S438{TIM8238)
CONTROLLER AND BUS DRIVER FOR 8080A SYSTEMS

PARAMETER MEASUREMENT INFORMATION

Vee

!::
TO INTA--.J
OUTPUT . - -
II

FIGURE 1-iN"i'A INPUT CURRENT

'iV'kn
OUTPUT

UNDER TEST

FIGURE 2-SWITCHING CHARACTERISTICS

11Tel

-=- i
R2

S2

TEST CIRCUIT LOAD CI RCUIT

C~::e~I{¢' ¢2
-
- -
_-_-_
-_' _----,.Je-tw--lr-_ _ _ _ _ _ _ _ _ _ _ _ _ ~

STsTa 'i H vJ{

INPUT .... ..J.--..t6~t~-t
~------------------
ST~~,~~TS ~'.5 ~
TMS8080A I : I I

DO'h", 07
ill '1..u. V
'--------------------
.1r-----"""'~
OBIN
INPUT
mTA,mlR,~--------~I~-~I----J:
! I
I I
r.,.5V 1\1.5 V
i~~-l-H~-,------------

OUTPUTS : ~.5Y I I f1.5V

•
1.-1 I t--------------
1
HLDA INPUT

: 1
'PHL...l
: I I
:
,. 5v t!~~LH
r1

mTA,mlR,MEMR--------~lh\ I I , I ...1r=~----------
OURINGHLOA I I : i I T,·5V

I - - I - - j - - =I I ]-
SVSTEMBUS I N P U T - - - - - - - - I
' '... -=iiI4'I'h
I ....
~-------------
DU~'NG~EAD l' I 1.5 V ! ~
D80tb",OB1 ---------t--+- . i.=::=::ii~0:· ------------
TMS BOBOA BUS OUTPUT I I I 3V I l V
O~':~u':,;AD --------t--r----I 'O.8V '.5V I 0.8 vi ------------
! I ~zx-
iVA INPUT ~HL--4--.t l ,:svt
:I ~~O
('S428onlYl ~ ..-::,'' ' PO''--_ __
1.5~-I~-=Y~~~--- , ....
I/C1#/ORMEMW
OUTPUT
'5_V_ _ _ _....Jf'·5V
I
TMS 8080A BUS INPUT I V
DU:::';r:~~TE __________ -1. ~'.5V
SYSTEM BUS OUTPUT

Dg~~:~~~E - -
,pzx~ ; ; V

- - - - - - - - - ' ' . j . . - ' ' 0..:...8V'--_ _ _ _ --'*. .

_ _ _ -,''"''PO::....-_ _ _ _ _ _ _ _ _ __

'.5_V_ _ _ _ _ _ _ _ _ _ __

iiUsEN 1.,.5 V .J,.5V

INPUT I .... -----J~
SYSTEM BUS _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ L _ ; t l V I 3Vt,_ _ _ _ _ _ _ _ _ _ _ _ _
OUTPUTS I ~0.8 v I 0.8 v-JL
OBO 'hno OB7 I--tpzx-, F=t!--tpxz

NOTE A: Advanced response of I/OW or MEMW for the SN74S438 is indicated by the dashed line.

FIGURE 3-VOL TAGE WAVEFORMS

1076

7-518 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALL.AS. TEXAS 75222
 TYPES SN74S428(TIM8228), SN74S438(TIM8238)
CONTROLLER AND BUS DRIVER FOR 8080A SYSTEMS

TYPICAL APPLICATION DATA

VOO (12V)

VCC (5V)
-
V BB (-5 V)

VCC
(16)
VOO
(9) 1(11)
V BB
L
VCC
(28)
VOO
I,~,
VCC

~
(11)
. .
~:J
SN74LS424 (22) ;;1 DO (10) (15) (13)
4;1 DO '54281'5438 DBO ....-
(9) ~ .. (17)
~
%) XT AL (TIM8224)

4>2
(10) (15)
4>2
8080A
CPU
01
02
(8) (12)
01
02
(TlM82281
TIM8238)
OBl (16)
OB2 ... --.. OB~l
(:~)
(7) (10)
, ....... 03 03 I~\
041'~': : .u, 104 OB4r'u,-r--:-~~lf3 0:.1:
,? r
'e' BIDIRECTIONAL DB3 ~

TANK-----..9 TANK CLOCK

05 (4) (19)05 OB5 (18) OB5
USC ~IOSC GE~i;~~~OR D6 (5) ..... (21) 06 DB'; (20).... ~ DB6
07 (6) ~ : (8) 07 OBl (7) .... ~ OB7
~
(5) (19)
oi>2TTL q,2TTL SYNC ~ SYNC f.--------
CONTROL

RESIN --A RESIN RESET

(1) (12)
RESET OBIN (17) «43:»_ OBIN
~
D~~':~G MEMR
INTA (23) - }

ROYIN ~ ROYIN READY

(4) .. (23)
READY
- (18)
HL:: i"'(21) r (2)- :~OA
IV (24)
~(~26~).....- - :~::
INTA
CONTROL

~
22) BUSEN M~ '""(25) I/OR BUS
J!lr, __ I/OR U'"(27)-r
STSTB
~, ~ WAIT
BUSEN :---v STSTB I/OW "" I/OR
GNO GNO
J¥) ~4)
(25)
AO AO
(26) ..
Al Al
(27) ::
A2

•
A2
(13) (29) ::
SYSTEM OMA REQUEST---+--+"":':'::, HOLD A3 A3
(30) ..
(14)
SYSTEM INTERRUPT REQUEST---+-....-'-'-"I INT
.. AS
A4
(31)
(32) ::
A4
AS
A6 A6
(16) (33) ::
INTERRUPT ENABLE---+-. . ....!.!.::!.f INTE ~ A7 A7 ADDRESS
(34)
A8 A8 BUS
(35) ..
A9 A9
(1) ..
Al0 Al0
(40) .. All
All
(37)
A12 A12
(38) ..
A13 A13
(39)
A14 A14
(38)
A15 A15

Vss

~)

FIGURE 4-SYSTEM tNTERFACING WITH CENTRAL PROCESSING UNIT

1076

TEXAS INCORPORATED
INSTRUMENTS 7-519
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TTL TYPES SN54490, SN54LS490, SN14490, SN14LS490
MSI DUAL 4-81T DECADE COUNTERS
BULLETIN NO. DL-S 7612089, OCTOBER 1976

SN54490 ... J OR W PACKAGE

• Dual Versions of Popular SN5490A, SN54LS90,
SN74490 •.. J OR N PACKAGE
SN7490A, and SN74LS90 Counters
(TOP VIEW)

• Individual Clock, Direct Clear, and Set-to-9

20A 2 OUTPUTS
I nputs for Each Decade Counter
~~~9~
2 2 OUT·
CLOCK CLEAR PUT

• Dual Counters Can Significantly Improve

System Densities as Package Count Can
Be Reduced by 50%

• Maximum Count Frequency •.. 35 MHz

Typical

• Buffered Outputs Reduce Possibility of

Collector Commutation

1 1 10A
CLOCK CLEAR OUT·
PUT
description
positive logic: High input to clear resets all fqur outputs low;
Each of these monolithic circuits contains eight
high input to set-to-9 sets 0A and 00 high, Os
master-slave flip-flops and additional gating to imple- and 0c low.
ment two individual 4-bit decade counters in a single
package. Each decade counter has individual clock,
clear, and set-to-9 inputs. BCD count sequences of any length up to divide-by-l00 may be implemented with a single
'490 or 'LS490. Buffering on each output is provided to ensure that susceptibility to collector cummutation is
reduced significantly. All inputs are diode-clamped to reduce the effects of line ringing. The counters have
parallel outputs from each counter stage so that submultiples of the input count frequency are available for system
timing signals.

•
The SN54490 and SN54LS490 are characterized for operation over the full military temperature range of _55°C to
125°C; the SN74490 and SN74LS490 are characterized for use in industrial systems operating from O°C to 70°C .

BCD COUNT SEQUENCE

(EACH COUNTER)
OUTPUT CLEARISET-TO·9
COUNT
Qo Qc Qs QA FUNCTION TABLE
0 L L L L (EACH COUNTER)
1 L L L H INPUTS OUTPUTS
2 I L L H LI CLEAR SET-TQ-9 QA QB Oc QD
3 L L H H H L L L L L
4 L .H L L L H H L L H
5 L H L H L L COUNT
6 L H H L H = high level, L = low level
7 L H H H
8 H L L L
9 H L L H

1076

7-520
TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX !5012 • DALLAS. TEXAS 75222
 TYPES SN54490, SN54LS490, SN74490, SN74LS90
DUAL 4-81T DECADE COUNTERS

schematics of inputs and outputs

EQUIVALENT OF EACH INPUT

vee - '490

TYPICAL OF ALL OUTPUTS

--_-vee

o
Req

INPUT --

OUTPUT

INPUT Req NOM

CLOCK 3 kH
CLEAR, SET -TO-S 8 k1!

'LS490

EQUIVALENT OF EACH EQUIVALENT OF EACH TYPICAL OF ALL OUTPUTS

CLOCK INPUT CLEAR AND SET-TO-NINE INPUT ----_vee

t--
v e e - -......
18kHNOM

functional block diagram (each counter)

I
(5,11) OUTPUT
DB

(6,10) OUTPUT
Oc

OUTPUT
DD

1076

TEXAS INCORPORATED
INSTRUMENTS 7-521
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54490, SN74490
DUAL 4-81T DECADE COUNTERS

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, Vee (see Note 1) ..... . . . . . 7V

Input voltage . . . . . . . . . . . . . . . . . 5.5V
Operating free-air temperature range: SN54490 -55°C to 125°C
SN74490 oOe to 70°C
Storage temperature range -65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54490 SN74490
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, VCC 4.5 5 5.5 4.75 5 5.25 V
High-level output current, 10H -800 -800 J1.A
Low-level output current, 10L 16 16 mA
Count frequency, f count 0 25 0 25 MHz

Pulse width, tw (any input) 20 20 ns

Clear or set-to-9 inactive-state setup time, tsu 25~ 25~ ns

Operating free-air temperature, T A -55 125 0 70 °c

~ The arrow indicates that the falling edge of the clock pulse is used for reference.

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONSt MIN TYP:j: MAX UNIT
VIH High-level input voltage 2 V

I VIL
VIK
Low-level input voltage
I nput clamp voltage Vee; MIN,
VCC - MIN,
II; -12mA
VIH - 2V,
0.8
-1.5
V
V

VOH High-level output voltage 2.4 3.4 V

,VIL;0.8V, 10H ; -800 J.lA !
VOL Low-level output voltage
Vee; MIN, VIH; 2 V, I 0.2 0.4 V
VIL;0.8V IOL; 16mA
II Input current at maximum input voltage Vce; MAX, VI; 5.5 V 1 mA
Clear, set-to-9 40
IIH High-level input current Vce; MAX, VI = 2.4 V J1.A
Clock 80
Clear, set-to-9 -1
IlL Low-level input current Vce; MAX, VI = 0.4 V mA
Clock -3.2
ISN54490 -20 -57
lOS Short-circuit output current§ Vee = MAX ISN74490 mA
-18 -57
ICC Supply current Vee = MAX. See Note 2 45 70 mA

tFor conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at Vee; 5 V, T A ; 25°C.
§Not more than one output should be shorted at a time.
NOTE 2: ICC is measured with all outputs open, both clear inputs grounded following momentary connection to 4.5 V, and all other inputs
grounded.

1076

7-522 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54490, SN74490
DUAL 4-81T DECADE COUNTERS

switching characteristics, Vee = 5 V, TA =25°e

FROM TO
PARAMETER~ TEST CONDITIONS MIN TYP MAX UNIT
(INPUT) (OUTPUT)
f max Clock °A 25 35 MHz
tpLH 12 20
Clock °A ns
tpHL 13 20
tPLH 24 39
Clock °8,°0 ns
tpHL CL=15pF, RL = 400 n, 26 39
tpLH See Figure 1 and Note 3 32 54
Clock °c ns
tPHL 36 54
tpHL Clear Any 24 39 ns
tpLH °A,OO 24 39
Set-to-9 ns
tpHL °8,OC 20 36

~fmax == maximum count frequency

tpLH == propagation delay time, low-to-high-Ievel output
tpHL == propagation delay time, high-to-Iow-Ievel output
NOTE 3: Load circuit is shown on page 3-10.

S~~~~~9 ~~;---------~s---- - - ~S- - - - - - - - - : :

~ tsu _I
CLEAR F\l-:V---!-------------------- 3V
INPUT
_..;...____....J: I I S\ H ov
I I+- tsu -+J ~twlcIOCkl.,

CLOCK i
I
: ~I
1.5V 1.5V
~----3\1
1.5V
INPUT __~_ _ _ _ _~I_ _ __ J I 1 ov
I+-+t- tPLH ~ ~
1 I
:
~tPHL pi tPLH-Meosure
I I
tpHL -Measure

Ir -
r attn+l attn+2

OUTPUTQA
jJ
I
l

I
,.-_......:_-"
I 1.5V :
I
' \ 1.5V
I ,
1.5V :
I
\i.I 1.5V
~"'f----..;..--1
~ tpHL -Measure
VvOoHL
II
~tPHL
~ tPHL tPLH-Meosure~ I I ottn+4

--:-': -,-, I ottn+2 I J.ri - VOH

OUTPUTQB I
I
\- 1.5V
\ I \1.5V H i /1.SV ! ~ VOL

: . . - - . : - tPHL I~tPHL --J...-...., ~I tpHL -Measure at tn+8

I 1
--1-' 1 -1"---'1
tPLH-Meosure
attn+4 I r' I I
-- VOH
OUTPUTOc ~ \1.5V I *-1.5V 1 (1.5V : ~
I : \ if I I VOL
~tPLH 4 t PHL tpLH-Measureatt n +8 ~ ~ tpHL-Measureatt n +10

OUTPUTQO
1"'------'
11.5v ' \ 1.5V
r
l
/ ' 1.5V
~---
1.5V
VOH

---1' \..--------~5t-f---------' VOL

VOLTAGE WAVEFORMS
NOTES: A. Input pulses are supplied by a generator having the following characteristics: tr .;;; 5 ns, tf .;;; 5 ns, PRR = 1 MHz, duty cycle
= 50%, Zout "" 50 ohms.

FIGURE 1

1076

TEXAS INSTRUMENTS 7-523

INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54LS490 SN74LS490
DUAL 4-81T DECADE COUNTERS

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, Vcc (see Note 1) . 7V

Clear and set-to-9 input voltage . 7V
Clock input voltage . . . . . . 5.5 V
Operating free-air temperature range: SN54LS490 -55°C to 125°C
SN74LS490 O°C to 70°C
Storage temperature range -65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

SN54LS490 SN74LS490
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, V CC 4.5 5 5.5 4.75 5 5.25 V
High-Ie\lel output current, 10H -400 -400 IJA
low-Ie\lel output current, 10l 4 8 mA
Count frequency, fcount 0 25 0 25 MHz

Pulse width, tw (any input I 20 20 ns

Clear or set-t0-9 inactive-state setup time, tsu 25. 25. ns

Operating free-air temperature, T A -55 125 0 70 °c

• The arrow indicates that the falling edge of the clock pulse is used for reference.

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54lS490 SN74LS490
PARAMETER TEST CONDITIONSt UNIT
MIN TYPt MAX MIN TYPt MAX
VIH High-level input voltage 2 2 V
Vil low-level input voltage 0.7 0.8 V

II VIK

VOH
Input clamp voltage

High-level output voltage

VCC =MIN,
VCC = MIN,
Vil = Vilmax
II =-1 mA
VIH = 2 V,
2.5 3.4
-1.5

2.7 3.4
-1.5 V

VCC = MIN, 1101.>4 mA 0.25 0.4 I 0.25 OA

VOL Low-level output vOltage VIH = 2 V, V
VIL = VILmax IQ1. =8 mA 0.35 0.5
Clear,
I nput current at VI =7 V 0.1 0.1
II set-to-9 VCC = MAX, mA
maximum input voltage I - - -
Clock VI = 5.5 V 0.2 0.2
Clear,
20
IIH High-level input current set-to-9 VCC = MAX, VI=2.7V
20
IJA I
I Clock 40 40
Clear,
-0.4 -0.4
IlL Low-level input current set-to-9 VCC =MAX, VI=O.4V mA
I---
Clock -1.6 -1.6
lOS Short-circuit output current§ VCC = MAX -20 -100 -20 -100 rnA
ICC Supply current VCC = MAX, See Note 2 15 26 15 26 rnA

tFor conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions.
fAil typical values are at Vee = 5 V, T A = 25°C.
§ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
NOTE 2: ICC is measured with all outputs open, both clear inputs grounded following momentary connection to 4.5 V. and all other inputs
grounded.

1076
TENTATIVE DATA

7-524 This page provides tentative information on a TEXAS INSTRUMENTS

new product. Texas Instruments reserves the INCORPORATED
right to change specifications for this product POST OFFICE BOX 5012 • OALLAS. TEXAS 75222
in any manner without notice.
 TYPES SN54LS490, SN74LS490
DUAL 4-81T DECADE COUNTERS

switching characteristics, Vee =5 V, TA =25°e

FROM TO
PARAMETER~ TEST CONDITIONS MIN TYP MAX UNIT
(INPUT) (OUTPUT)
f max Clock QA 25 35 MHz
tPLH 12 20
Clock QA ns
tpHL 13 20
tPLH 24 39
Clock QS,QD ns
tpHL CL=15pF, RL = 2 kn 26 39
tpLH See Figure 2 and Note 4 32 54
Clock QC ns
tpHL 36 54
tPHL Clear Any 24 39 ns
tPLH QA,QD 24 39
Set-to-9 ns
tpHL QS,QC 20 36

~ f max == maximum count frequency

tpLH == propagation delay time, low-to-high-Ievel output
tpH L == propagation delay time, high-to-Iow-Ievel output
NOTE 4: Load circuit is shown on page 3-11.

SET-TO-9 ~~3~-------- -~\- -- - - - ~s - - - - - - - --::

INPUT

: ~ tsu .1
CLEAR
! F\1~V---!-------------------- 3V

INPUT
I I I 5\ IS 0v
I ~ tsu -, ~tWICIOCkl"

CLOCK
INPUT ,-____~!:__---J/~J~~~v~- - ::
_..;I.--..r- tPLH : ~ tPLH-M:~sure ~ tpHL -Measure I
I I ,--_ _...;1'-
• .....,.1 f I I 1

Pv \.;v :I.----.t--
tPHL a n+1 at tn+2 VOH

OUTPUTQA
JJ1.3V

I
i '\ C
I
1.3V VOL

tPH L -Measure
II
~tPHL
...J~ tPHL tPLH-:~:s~;e ~~1 ~ tn+4
OUTPUTQS
--:-':
I \-- 1.3 V - : - ' \ 1.3 V I 1.3V
I
:
I
'{ ::- OH
I \ I \ i f . L- VOL

r-----r-
I I
tPHL \.----.t--
I
tPHL tPLH-Measure~
I I
~ tPHL-Measure attn+8

--1-'1 -.-'1 attn+4 I FI l' -- VOH

OUTPUTOc ! 4-1.3V- I + 1.3 V 1 1.3 V : ~1.3V
t"\ : \ If I I ~ VOL

~tPLH 4 t
PHL tpLH-Measureatt n +8 ~ ~ tpHL-Measureatt n +10

1,--------,. ~I ~--- VOH

OUTPUTQO 11.3 V ' \ . 1.3 V / ' 1.3 V 1.3 V

~ ~-----------------~§rf------------J VOL

VOLTAGE WAVEFORMS
NOTES: A. Input pulses are supplied by a generator having the following characteristics: tr .;; 15 ns, tf';;; 6 ns, PRR = 1 MHz, duty cycle
= 50%, Zout '" 50 ohms.

FIGURE 2

1076 TENTATIVE DATA

This page provides tentative information on a TEXAS INCORPORATED
INSTRUMENTS 7-525
new product_ Texas Instruments reserves the
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
right to change specifications for this product
in any manner without notice_
 TTL TYPES SN54LS670, SN74LS670
MSI 4-8Y-4 REGISTER FILES WITH 3-STATE OUTPUTS
BULLETIN NO. DL-S 7612122, MARCH 1974-:-REVISED OCTOBER 1976

SN54LS670 ••. J OR W PACKAGE

• Separate Read/Write Addressing Permits SN74LS670 •.• J OR N PACKAGE
(TOP VIEW)
Simultaneous Reading and Writing
WRITE SELECT ENABLE OUTPUTS
• Fast Access Times ... Typically 20 ns Vcc D~~A 'W";"'W';" WRITE READ "Ci'i"'Cii'
• Organized as 4 Words of 4 Bits
• Expandable to 512 Words of n-Bits
D1 01
• For Use as:
Scratch-Pad Memory D2 02

Buffer Storage between Processors

Bit Storage in Fast Multiplication Designs
• 3-State Outputs
• SN54LS170 and SN74LS170 Are Similar
But Have Open-Collector Outputs
positive logic: see description
description

The SN54LS670 and SN74LS670 MSI 16-bit TTL register files incorporate the equivalent of 98 gates. The register file
is organized as 4 words of 4 bits each and separate on-chip decoding is provided for addressing the four word locations
to either write-in or retrieve data. This permits simultaneous writing into one location and reading from another word
location.

Four data inputs are available which are used to supply the 4-bit word to be stored. Location of the word is determined
by the write-address inputs A and B in conjunction with a write-enable signal. Data applied at the inputs should be in its
true form. That is, if a high-level signal is desired from the output, a high-level is applied at the data input for that
particular bit location. The latch inputs are arranged so that new data will be accepted only if both internal address gate
inputs are high. When this condition exists, data at the D input is transferred to the latch output. When the write-enable
input, GW, is high, the data inputs are inhibited and their levels can cause no change in the information stored in the
internal latches. When the read-enable input, GR, is high, the data outputs are inhibited and go into the high-impedance
I state,

The individual address lines permit direct acquisition of data stored in any four of the latches. Four individual decoding
gates are used to complete the address for reading a word. When the read address is made in conjunction with the
read-enable signal, the word appears at the four outputs.

This arrangement-data-entry addressing separate from data-read addressing and individual sense line-eliminates
recovery times, permits simultaneous reading and writing, and is limited in speed only by the write time
(27 nanoseconds typical) and the read time (24 nanoseconds typical). The register file has a nondestructive readout in
that data is not lost when addressed.

All inputs except read enable and write enable are buffered to lower the drive requirements to one Series 54LS/74LS
standard load, and input-clamping diodes minimize switching transients to simplify system design. High-speed,
double-ended AND-OR-INVERT gates are employed for the read-address function and have high-sink-current,
three-state outputs. Up to 12L of these outputs may be wire-AND connected for increasing the capacity up to 512
words. Any number of these registers may be paralleled to provide n-bit word length.

The SN54LS670 characterized for operation over the full military temperature range of -55°C to 125°C; the
SN74LS670 is characterized for operation from O°C to 70°C.

1076

7-526 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54LS670, SN74LS670
4-8Y-4 REGISTER FILES WITH 3-STATE OUTPUTS
REVISED OCTOBER 1976

logic
WRITE FUNCTION TABLE (SEE NOTES A, B, AND CI READ FUNCTION TABLE (SEE NOTES A AND DI

WRITE INPUTS WORD READ INPUTS OUTPUTS

WB WA GW 0 1 2 3 RB RA GR Q1 Q2 Q3 Q4
L L L Q=D QO QO QO L L L WOB1 WOB2 WOB3 WOB4
L H L QO Q=O QO QO L H L W1B1 W1B2 W1B3 W1B4
H L L QO QO Q=O QO H L L W2B1 W2B2 W2B3 W2B4
H H L QO QO QO Q=O H H L W3B1 W3B2 W3B3 W3B4
X X H QO QO QO QO X X H Z Z Z Z

NOTES: A. H = high level, L = low level, X = irrelevant, Z = high impedance (off)

B. (a = D) = The four selected internal flip·flop outputs will assume the states applied to the four external data inputs.
C. aO = the level of a before the indicated input conditions were established.
D. WOB1 = The first bit of word 0, etc.

functional block diagram

DATA
INPUTS
OUTPUTS

1076

TEXAS INCORPORATED
INSTRUMENTS 7-527
POST OFFICE BOX 5012 • DALLAS, TEXAS 75222
 TYPES SN54LS670, SN74LS670
4-8Y-4 REGISTER FILES WITH 3-STATE OUTPUTS

schematics of inputs and outputs

EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS

Vee - - - -....- - - - -------4. . . -- vee

INPUT - . .-W......- -. .-

'----4......- - OUTPUT

Any D, R, or W: Req = 20 kn NOM

GR: Req = 6.67 kn NOM
GW: Req = 10 kn NOM

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) 7V
Input voltage . . . . . . . . 7V
Off-state output voltage 5.5 V
Operating free-air temperature range: SN54LS670 -55°C to 125°C
SN74LS670 oOe to 70°C
Storage temperature range -65°C to 150°C

•
recommended operating conditions
SN54LS670 SN74LS670
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, Vee 4.5 5 5.5 4.75 5 5.25 V
High-level output current, IOH -1 i -2.6 ! rnA i
Low-level output current, IOL 41 81 rnA
I
Width of write-enable or read-enable pulse, tw 25 25 I ns
Data input with respect to
10 10 ns
Setup times, high- or low-level data write enable, tsu(D)
i
(see Figure 2) Write select with respect to
15 15 ns
write enable, tsu(W) I
Data input with respect to I
15 15 ns
Hold times, high- or low-level data write enable, th(W)
(see Note 2 and Figure 2) Write select with respect to
5 5 ns
write enable, th(O)
Latch time for new data, tlatch (see Note 3) 25 25 ns
Operating free-air temperature range, T A -55 125 0 70 °c
NOTES: 1. Voltage values are with respect to network ground terminal.
2. Write-select setup time will protect the data written into the previous address. If protection of data in the previous address is not
required, tsu(W) can be ignored as any address selection sustained for the final 30 ns of the write-enable pulse and during th(W)
will result in data being written into that location. Depending on the duration of the input conditions. one or a number of
previous addresses may have been written into.
3. Latch time is the time allowed for tl'le internal output of the latch to assume the state of new data. See Figure 2. This is important
only when attempting to read from a location immediately after that location has received new data.

1076

7-528 TEXAS INSTRUMENTS

INCORPORATED
POST OFFICE BOX 5012 • OALLAS, TEXAS 75222
 TYPES SN54LS670. SN74LS670
4-8Y-4 REGISTER FILES WITH 3-STATE OUTPUTS
REVISED OCTOBER 1976

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS670 SN74LS670
PARAMETER TEST CONDITIONSt UNIT
MIN TYP:j: MAX MIN TYP:j: MAX
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
VIK Input clamp voltage Vee= MIN, II = -18 mA -1.5 -1.5 V
Vee- MIN, VIH-2V, 10H =-1 mA 2.4 3.4
VOH High-level output voltage V
VIL = VIL max 10H =-2.6mA 2.4 3.1
Vee- MIN, VIH - 2V, 10L -4mA 0.25 0.4 0.25 0.4
VOL Low-level output voltage V
VIL = VIL max 10L =8 mA 0.35 0.5
Off-state output current,
Vee = MAX, VIH = 2V, Vo = 2.7 V 20 20 p.A
10ZH high-level voltage applied
Off-state output current,
Vee = MAX, VIH=2V, Vo = 0.4 V
I -20 -20 p.A
10ZL low-level voltage applied

Input current at Vee = MAX,

I Any D, R, crW 0.1 0.1

maximum input voltage VI = 7V

I GW 0.2 0.2 mA
I GR 0.3 0.3
I"
I Vee= MAX,
I ..
Any D, R, or W
~G-,.~'~~--------------~-----------4-0~------------4-0~
20 20 I I
... Hioh-Ievel
-- input current
VI =2.7V
uA

GR 60 60
Any D, R,orW -0.4 -0.4
IlL Low-level input current Vee= MAX GW -0.8 -0.8 mA
GR -1.2 -1.2
lOS Short-circuit output current§ Vee= MAX -30 -130 -30 -130 mA
ICC Supply current Vee= MAX, See Note 4 30 50 30 50 mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at VCC = 5 V, TA = 25°C.
§ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
NOTE 4: Maximum ICC is guaranteed for the following worst·case conditions: 4.5 V is applied to all data inputs and both enable inputs, all
address inputs are grounded and all outputs are open.

switching characteristics, Vee = 5 V, TA = 25°e

PARAMETER~

tPLH
tpHL
tpLH
FROM
(INPUT)

Read select

Write enable
TO
(OUTPUT)

AnyQ

AnyQ
TEST CONDITIONS

eL = 15 pF, RL=2kn.
See Figures 1 and 2
MIN TYP

23
25
26
MAX UNIT

40
45
45
ns

ns
•
tpHL eL = 15 pF, RL = 2 kn, 28 50
tpLH See Figures 1 and 3 25 45
Data AnyQ ns
tPHL 23 40
tZH 15 35
ns
tZL eL=5pF, RL = 2 kn, 22 40
Read enable AnyQ
tHZ See Figures 1 and 4 30 50 i
ns
tLZ 16 35

~tpLH = propagation delay time, low·to-high·level output

=
tpHL propagation delay time, high-to·low·level output
tZH = output enable time to high level
tZL = output enable time to low level
=
tHZ output disable time from high level
tLZ = output disable time from low level

)76

TEXAS INCORPORATED
INSTRUMENTS 1-529
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54LS670, SN74LS670
4-8Y-4 REGISTER FILES WITH 3-STATE OUTPUTS

PARAMETER MEASUREMENT INFORMATION

TEST
POINT

Sl
FROM OUTPUT
UNDER TEST - ......- - - - 4................
(See Note B)

NOTES: A. CL includes probe and jig capacitance.

B. All diodes are 1N916 or 1N3064.
LOAD CI RCUIT

FIGURE 1

WRITE-SELECT
INPUTWAorWB
(See Note A)
~
I
1.3V
\-----------3V
11.3V
\.._______________ 0 V
-.j ~ tsu(W) I
-----il-""\ . --I t-- th{W) 3V

\.3V /.~"-
OATt' INPUT
01,02,03, or 04
(See Note A) 1 ________ ov
I 1---1- tsu(D)

•
I ~th(O)
- - -.. . t-- tw ---I
I ~~ _________ -ov
3V

~~~:~~ABLE 11.3v
\ . - - tlatch - - ,

______--J,)'..3 V \l~V --
- _ _ 3V
READ-SELECT
INPUT RA or RS
(See Note S) I \..._ _ _ _ _ _ 0 V
I
I !+tPLH ,
!+-tPHL-!

OUTPUT
01,02,03, or 04
\1."-___
3V -It":. _- I VOH

VOL

VOLTAGE WAVEFORMS (S1 AND S2 ARE CLOSED)

NOTES: A. High-level input pulses at the select and data inputs are illustrated; however, times associated with low-level pulses are measured
from the same reference points.
B. When measuring delay times from a read-select input, the read-enable input is low.
C. Input waveforms are supplied by generators having the following characteristics: PRR .;; 2 MHz, Zout '" 50 51, duty cycle';; 50%,
tr .;; 15 ns, tr .;; 6 ns.
FIGURE 2

107;

7-530 TEXAS INCORPORATED

INSTRUMENTS
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
 TYPES SN54LS670, SN74LS670
4-BY-4 REGISTER FILES WITH 3-STATE OUTPUTS

PARAMETER MEASUREMENT INFORMATION

,DATA INPUT \ - - - - - - - - - - - - 3V
D1, D2, D3, or D4
. OV

WRITE-ENABLE
INPUTGW

OUTPUT
01,02,03, or 04

VOLTAGE WAVEFORM 1 (S1 AND S2 ARE CLOSED)

DATA INPUT
D1, D2, D3, or D4 ~.3V-----....J
I ........
1 - - - - - - - - - - - - ov
3v

WRITE-ENABLE
INPUTGW _ _--:1_ _ _ _ ---'1 \;~ ~ ----- ::
I------i-tpH L
tpLH 3V
r - - - + I

----\1I
OUTPUT
01,02,03, or 04
_____\\..._3_V____________ ---Jl,·: ___ ov

NOTES:
VOLTAGE WAVEFORM 2 (S1 AND S2 ARE CLOSED)
A. Each select address is tested. Prior to the start of each of the above tests both write and read address inputs are stabilized with
WA = RA and WB = RB' During the test GR is low.
B. Input waveforms are supplied by generators having the following characteristics: PRR .;; 1 MHz, Zout '" 50 n, duty cycle';; 50%,
tr .;; 15 ns, tr .;; 6 ns.

READ~ 1.3V
FIGURE 3

~3V
•
ENABLE l\:
I '-------------- ----li=~.>-.:'-------- 0 V
I---tZL----., I--tLZ--j
I I Sl and
: -t----""4.5V
WAVEFORM 1 I Sl closed, 1.3 V : I S2 closed
(See Note A) : S2 open I
:
1---1.. ,----VOL
'" 1.5 V

I----tZH -----l r-tHZ-\ 0.5 VO.5 V

I - - - - - . . . : ' -*-----VOH
WAVEFORM 2 Sl open, lr-- ,... "'1.5V
(See Note A) S2 closed / " 1.3 V "" 0 V S1 and
S2 closed

VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, THREE-STATE OUTPUTS
NOTES: A. Waveforms 1 is for an output with internal conditions such that the output is low except when disabled by the read-enable input.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the read-enable input.
B. When measuring delay times from the read-enable input, both read-select inputs have been established at steady states.
C. Input waveforms are supplied by generators having the following characteristics: PRR .;; 1 MHz, Zout '" 50 n, duty cycle';; 50%,
tr .;; 15 ns, tr .;; 6 ns.
FIGURE 4

374

TEXAS INCORPORATED
INSTRUMENTS 7-531
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222
•

7-532