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SEMICONDUCTOR TECHNICAL DATA by MTD1N80E/D

   
 


  
 Motorola Preferred Device

!
  
      TMOS POWER FET
N–Channel Enhancement–Mode Silicon Gate 1.0 AMPERES
800 VOLTS
This high voltage MOSFET uses an advanced termination RDS(on) = 12 OHM
scheme to provide enhanced voltage–blocking capability without
degrading performance over time. In addition this advanced TMOS
E–FET is designed to withstand high energy in the avalanche and
commutation modes. The new energy efficient design also offers a 
drain–to–source diode with a fast recovery time. Designed for high
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
D
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.
• Robust High Voltage Termination
G
• Avalanche Energy Specified
CASE 369A–13, Style 2
• Source–to–Drain Diode Recovery Time Comparable to a Discrete
DPAK
Fast Recovery Diode S
• Diode is Characterized for Use in Bridge Circuits
• IDSS and VDS(on) Specified at Elevated Temperature
• Surface Mount Package Available in 16 mm, 13–inch/2500
Unit Tape & Reel, Add T4 Suffix to Part Number

MAXIMUM RATINGS (TC = 25°C unless otherwise noted)

Rating Symbol Value Unit
Drain–to–Source Voltage VDSS 800 Vdc
Drain–to–Gate Voltage (RGS = 1.0 MΩ) VDGR 800 Vdc
Gate–to–Source Voltage — Continuous VGS ± 20 Vdc
Gate–to–Source Voltage — Non–Repetitive (tp ≤ 10 ms) VGSM ± 40 Vpk
Drain Current — Continuous ID 1.0 Adc
Drain Current — Continuous @ 100°C ID 0.8
Drain Current — Single Pulse (tp ≤ 10 µs) IDM 3.0 Apk
Total Power Dissipation PD 48 Watts
Derate above 25°C 0.38 W/°C
Total Power Dissipation @ TA = 25°C, when mounted to minimum recommended pad size 1.75 Watts
Operating and Storage Temperature Range TJ, Tstg – 55 to 150 °C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C EAS mJ
(VDD = 100 Vdc, VGS = 10 Vdc, IL = 2.0 Apk, L = 10 mH, RG = 25 Ω) 20
Thermal Resistance — Junction to Case RθJC 2.6 °C/W
Thermal Resistance — Junction to Ambient RθJA 100
Thermal Resistance — Junction to Ambient, when mounted to minimum recommended pad size RθJA 71.4
Maximum Temperature for Soldering Purposes, 1/8″ from case for 10 seconds TL 260 °C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

 Motorola TMOS
Motorola, Inc. 1995 Power MOSFET Transistor Device Data 1
MTD1N80E
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage V(BR)DSS Vdc
(VGS = 0 Vdc, ID = 0.250 µAdc) 800 — —
Temperature Coefficient (Positive) — 981 — mV/°C
Zero Gate Voltage Drain Current IDSS µAdc
(VDS = 800 Vdc, VGS = 0 Vdc) — — 10
(VDS = 800 Vdc, VGS = 0 Vdc, TJ = 125°C) — — 100
Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0 Vdc) IGSS — — 100 nAdc
ON CHARACTERISTICS (1)
Gate Threshold Voltage VGS(th) Vdc
(VDS = VGS, ID = 250 µAdc) 2.0 3.3 4.0
Temperature Coefficient (Negative) — 6.3 — mV/°C
Static Drain–to–Source On–Resistance (VGS = 10 Vdc, ID = 0.5 Adc) RDS(on) — 10.3 12 Ohm
Drain–to–Source On–Voltage VDS(on) Vdc
(VGS = 10 Vdc, ID = 1.0 Adc) — 11 14.4
(VGS = 10 Vdc, ID = 0.5 Adc, TJ = 125°C) — — 12.6
Forward Transconductance (VDS = 15 Vdc, ID = 0.5 Adc) gFS 0.4 0.985 — mhos
DYNAMIC CHARACTERISTICS
Input Capacitance Ciss — 297 420 pF
Output Capacitance (VDS = 25 Vdc, VGS = 0 Vdc,
Coss — 29 40
f = 1.0 MHz)
Reverse Transfer Capacitance Crss — 6.0 10

SWITCHING CHARACTERISTICS (2)

Turn–On Delay Time td(on) — 9.0 20 ns
Rise Time (VDD = 400 Vdc, ID = 1.0 Adc, tr — 10 20
VGS = 10 Vdc,
Turn–Off Delay Time RG = 9.1 Ω) td(off) — 20 40
Fall Time tf — 27 55
Gate Charge QT — 9.6 20 nC

(VDS = 400 Vdc, ID = 1.0 Adc, Q1 — 2.1 —

VGS = 10 Vdc) Q2 — 4.2 —
Q3 — 4.7 —
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage (1) VSD Vdc
(IS = 1.0 Adc, VGS = 0 Vdc)
— 0.82 1.2
(IS = 1.0 Adc, VGS = 0 Vdc, TJ = 125°C)
— 0.7 —
Reverse Recovery Time trr — 317 — ns

(IS = 1.0 Adc, VGS = 0 Vdc, ta — 56 —

dIS/dt = 100 A/µs) tb — 261 —
Reverse Recovery Stored Charge QRR — 0.93 — µC
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance LD nH
(Measured from the drain lead 0.25″ from package to center of die) — 4.5 —

Internal Source Inductance LS nH

(Measured from the source lead 0.25″ from package to source bond pad) — 7.5 —
(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.

2 Motorola TMOS Power MOSFET Transistor Device Data

 MTD1N80E
TYPICAL ELECTRICAL CHARACTERISTICS

2.0 TJ = 25°C 2.0

VDS ≥ 10 V
ID , DRAIN CURRENT (AMPS)

ID , DRAIN CURRENT (AMPS)

1.6 VGS = 10 V 1.6

6V
1.2 8V 1.2

0.8 0.8
5V
TJ = 100°C
0.4 0.4 25°C
4V
–55°C
0 0
0 5 10 15 20 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)

Figure 1. On–Region Characteristics Figure 2. Transfer Characteristics

RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)

RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)

18 16
VGS = 10 V TJ = 25°C
15 100°C 15

14
12

TJ = 25°C 13
9
12 VGS = 10 V
6
–55°C 11
15 V
3
10

0 9
0 0.25 0.50 0.75 1.0 1.25 1.50 1.75 2.0 0 0.4 0.8 1.2 1.6 2.0
ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS)

Figure 3. On–Resistance versus Drain Current Figure 4. On–Resistance versus Drain Current
and Temperature and Gate Voltage

2.5 1000
RDS(on) , DRAIN–TO–SOURCE RESISTANCE

VGS = 10 V VGS = 0 V
ID = 0.5 A
2 TJ = 125°C
100 100°C
I DSS , LEAKAGE (nA)
(NORMALIZED)

1.5

10
1
25°C
1
0.5

0 0.1
– 50 – 25 0 25 50 75 100 125 150 0 100 200 300 400 500 600 700 800
TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

Figure 5. On–Resistance Variation with Figure 6. Drain–To–Source Leakage

Temperature Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data 3

MTD1N80E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted The capacitance (Ciss) is read from the capacitance curve at
by recognizing that the power MOSFET is charge controlled. a voltage corresponding to the off–state condition when cal-
The lengths of various switching intervals (∆t) are deter- culating td(on) and is read at a voltage corresponding to the
mined by how fast the FET input capacitance can be charged on–state when calculating td(off).
by current from the generator.
The published capacitance data is difficult to use for calculat- At high switching speeds, parasitic circuit elements com-
ing rise and fall because drain–gate capacitance varies plicate the analysis. The inductance of the MOSFET source
greatly with applied voltage. Accordingly, gate charge data is lead, inside the package and in the circuit wiring which is
used. In most cases, a satisfactory estimate of average input common to both the drain and gate current paths, produces a
current (IG(AV)) can be made from a rudimentary analysis of voltage at the source which reduces the gate drive current.
the drive circuit so that The voltage is determined by Ldi/dt, but since di/dt is a func-
t = Q/IG(AV) tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
During the rise and fall time interval when switching a resis-
mathematics. And finally, MOSFETs have finite internal gate
tive load, VGS remains virtually constant at a level known as
resistance which effectively adds to the resistance of the
the plateau voltage, VSGP. Therefore, rise and fall times may
driving source, but the internal resistance is difficult to mea-
be approximated by the following:
sure and, consequently, is not specified.
tr = Q2 x RG/(VGG – VGSP) The resistive switching time variation versus gate resis-
tf = Q2 x RG/VGSP tance (Figure 9) shows how typical switching performance is
where affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
VGG = the gate drive voltage, which varies from zero to VGG value of unity regardless of the switching speed. The circuit
RG = the gate drive resistance used to obtain the data is constructed to minimize common
and Q2 and VGSP are read from the gate charge curve. inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
During the turn–on and turn–off delay times, gate current is
power electronic loads are inductive; the data in the figure is
not constant. The simplest calculation uses appropriate val-
taken with a resistive load, which approximates an optimally
ues from the capacitance curves in a standard equation for
snubbed inductive load. Power MOSFETs may be safely op-
voltage change in an RC network. The equations are:
erated into an inductive load; however, snubbing reduces
td(on) = RG Ciss In [VGG/(VGG – VGSP)] switching losses.
td(off) = RG Ciss In (VGG/VGSP)

700 1000
TJ = 25°C TJ = 25°C
VGS = 0 V VGS = 0 Ciss
600
C, CAPACITANCE (pF)

500
C, CAPACITANCE (pF)

100
400
Ciss
Coss
300
10
200
Coss Crss
100
Crss
0 1
0 5 10 15 20 25 10 100 1000
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS) VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

Figure 7a. Capacitance Variation Figure 7b. High Voltage Capacitance Variation

4 Motorola TMOS Power MOSFET Transistor Device Data

 MTD1N80E
12 400 100

VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)

VDS , DRAIN–TO–SOURCE VOLTAGE (VOLTS)

VDD = 400 V
QT ID = 1 A
10
VGS = 10 V
VGS 300 TJ = 25°C tf
8

t, TIME (ns)
td(off)

6 200 10 td(on)
tr
Q1 Q2
4
ID = 1 A 100
2 TJ = 25°C

Q3 VDS
0 0 1
0 2 4 6 8 10 1 10 100
QT, TOTAL CHARGE (nC) RG, GATE RESISTANCE (OHMS)

Figure 8. Gate–To–Source and Drain–To–Source Figure 9. Resistive Switching Time

Voltage versus Total Charge Variation versus Gate Resistance

DRAIN–TO–SOURCE DIODE CHARACTERISTICS

1.0
VGS = 0 V
TJ = 25°C
I S , SOURCE CURRENT (AMPS)

0.8

0.6

0.4

0.2

0
0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85
VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define able operation, the stored energy from circuit inductance dis-
the maximum simultaneous drain–to–source voltage and sipated in the transistor while in avalanche must be less than
drain current that a transistor can handle safely when it is for- the rated limit and adjusted for operating conditions differing
ward biased. Curves are based upon maximum peak junc- from those specified. Although industry practice is to rate in
tion temperature and a case temperature (TC) of 25°C. Peak terms of energy, avalanche energy capability is not a con-
repetitive pulsed power limits are determined by using the stant. The energy rating decreases non–linearly with an in-
thermal response data in conjunction with the procedures crease of peak current in avalanche and peak junction
discussed in AN569, “Transient Thermal Resistance–Gener-
temperature.
al Data and Its Use.”
Although many E–FETs can withstand the stress of drain–
Switching between the off–state and the on–state may tra-
verse any load line provided neither rated peak current (IDM) to–source avalanche at currents up to rated pulsed current
nor rated voltage (VDSS) is exceeded and the transition time (IDM), the energy rating is specified at rated continuous cur-
(tr,tf) do not exceed 10 µs. In addition the total power aver- rent (ID), in accordance with industry custom. The energy rat-
aged over a complete switching cycle must not exceed ing must be derated for temperature as shown in the
(TJ(MAX) – TC)/(RθJC). accompanying graph (Figure 12). Maximum energy at cur-
A Power MOSFET designated E–FET can be safely used rents below rated continuous ID can safely be assumed to
in switching circuits with unclamped inductive loads. For reli- equal the values indicated.

Motorola TMOS Power MOSFET Transistor Device Data 5

MTD1N80E
SAFE OPERATING AREA

10 20

EAS, SINGLE PULSE DRAIN–TO–SOURCE

VGS = 20 V
10 µs ID = 1 A
SINGLE PULSE
I D , DRAIN CURRENT (AMPS)

TC = 25°C

AVALANCHE ENERGY (mJ)

15
1
100 µs
10
1 ms
10 ms
0.1
dc
5
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.01 0
0.1 1 10 100 1000 25 50 75 100 125 150
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) TJ, STARTING JUNCTION TEMPERATURE (°C)

Figure 11. Maximum Rated Forward Biased Figure 12. Maximum Avalanche Energy versus
Safe Operating Area Starting Junction Temperature
r (t), EFFECTIVE TRANSIENT THERMAL RESISTANCE

D = 0.5

0.2
(NORMALIZED)

0.1
0.1 0.05 P(pk)
RθJC(t) = r(t) RθJC
0.02 D CURVES APPLY FOR POWER
0.01 PULSE TRAIN SHOWN
SINGLE PULSE t1 READ TIME AT t1
t2 TJ(pk) – TC = P(pk) RθJC(t)
DUTY CYCLE, D = t1/t2
0.01
0.00001 0.0001 0.001 0.01 0.1 1 10
t, TIME (SECONDS)
Figure 13. Thermal Response

di/dt
IS
trr
ta tb
TIME

tp 0.25 IS

IS

Figure 14. Diode Reverse Recovery Waveform

6 Motorola TMOS Power MOSFET Transistor Device Data

 MTD1N80E
INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE

RECOMMENDED FOOTPRINTS FOR SURFACE MOUNTED APPLICATIONS

Surface mount board layout is a critical portion of the total between the board and the package. With the correct pad
design. The footprint for the semiconductor packages must be geometry, the packages will self align when subjected to a
the correct size to ensure proper solder connection interface solder reflow process.

0.165 0.118
4.191 3.0
0.100
2.54
0.063
1.6
0.190 0.243
4.826 6.172

inches
mm

POWER DISSIPATION FOR A SURFACE MOUNT DEVICE

The power dissipation for a surface mount device is a dissipation can be increased. Although one can almost double
function of the drain pad size. These can vary from the the power dissipation with this method, one will be giving up
minimum pad size for soldering to a pad size given for area on the printed circuit board which can defeat the purpose
maximum power dissipation. Power dissipation for a surface of using surface mount technology. For example, a graph of
mount device is determined by TJ(max), the maximum rated RθJA versus drain pad area is shown in Figure 15.
junction temperature of the die, RθJA, the thermal resistance
from the device junction to ambient, and the operating 100
RθJA , THERMAL RESISTANCE, JUNCTION

temperature, TA. Using the values provided on the data sheet, Board Material = 0.0625″
PD can be calculated as follows: G–10/FR–4, 2 oz Copper
1.75 Watts
80
TO AMBIENT (°C/W)

TJ(max) – TA TA = 25°C
PD =
RθJA
60
The values for the equation are found in the maximum 3.0 Watts
ratings table on the data sheet. Substituting these values into
the equation for an ambient temperature TA of 25°C, one can 40
calculate the power dissipation of the device. For a DPAK 5.0 Watts
device, PD is calculated as follows.
20
0 2 4 6 8 10
PD = 150°C – 25°C = 1.75 Watts A, AREA (SQUARE INCHES)
71.4°C/W
Figure 15. Thermal Resistance versus Drain Pad
The 71.4°C/W for the DPAK package assumes the use of Area for the DPAK Package (Typical)
the recommended footprint on a glass epoxy printed circuit Another alternative would be to use a ceramic substrate or
board to achieve a power dissipation of 1.75 Watts. There are an aluminum core board such as Thermal Clad. Using a
other alternatives to achieving higher power dissipation from board material such as Thermal Clad, an aluminum core
the surface mount packages. One is to increase the area of the board, the power dissipation can be doubled using the same
drain pad. By increasing the area of the drain pad, the power footprint.

Motorola TMOS Power MOSFET Transistor Device Data 7

MTD1N80E
SOLDER STENCIL GUIDELINES
Prior to placing surface mount components onto a printed
ÇÇÇÇÇÇÇÇ ÇÇ
ÇÇÇÇÇÇÇÇ ÇÇ
circuit board, solder paste must be applied to the pads. Solder

ÇÇÇÇÇÇÇÇ ÇÇ
stencils are used to screen the optimum amount. These
stencils are typically 0.008 inches thick and may be made of

ÇÇÇÇÇÇÇÇ ÇÇ
brass or stainless steel. For packages such as the SC–59, SOLDER PASTE

ÇÇÇÇÇÇÇÇ
SC–70/SOT–323, SOD–123, SOT–23, SOT–143, SOT–223, OPENINGS
SO–8, SO–14, SO–16, and SMB/SMC diode packages, the
stencil opening should be the same as the pad size or a 1:1
ÇÇÇÇÇÇÇÇ
ÇÇÇÇÇÇ
registration. This is not the case with the DPAK and D2PAK STENCIL
packages. If one uses a 1:1 opening to screen solder onto the
drain pad, misalignment and/or “tombstoning” may occur due
to an excess of solder. For these two packages, the opening Figure 16. Typical Stencil for DPAK and
in the stencil for the paste should be approximately 50% of the D2PAK Packages
tab area. The opening for the leads is still a 1:1 registration.
Figure 16 shows a typical stencil for the DPAK and D2PAK
packages. The pattern of the opening in the stencil for the
drain pad is not critical as long as it allows approximately 50%
of the pad to be covered with paste.

SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated • When shifting from preheating to soldering, the maximum
temperature of the device. When the entire device is heated temperature gradient shall be 5°C or less.
to a high temperature, failure to complete soldering within a • After soldering has been completed, the device should be
short time could result in device failure. Therefore, the allowed to cool naturally for at least three minutes.
following items should always be observed in order to Gradual cooling should be used as the use of forced
minimize the thermal stress to which the devices are cooling will increase the temperature gradient and result
subjected. in latent failure due to mechanical stress.
• Always preheat the device. • Mechanical stress or shock should not be applied during
• The delta temperature between the preheat and soldering cooling.
should be 100°C or less.*
• When preheating and soldering, the temperature of the * Soldering a device without preheating can cause excessive
leads and the case must not exceed the maximum thermal shock and stress which can result in damage to the
temperature ratings as shown on the data sheet. When device.
using infrared heating with the reflow soldering method,
the difference shall be a maximum of 10°C. * Due to shadowing and the inability to set the wave height to
• The soldering temperature and time shall not exceed incorporate other surface mount components, the D2PAK is
260°C for more than 10 seconds. not recommended for wave soldering.

8 Motorola TMOS Power MOSFET Transistor Device Data

 MTD1N80E
TYPICAL SOLDER HEATING PROFILE
For any given circuit board, there will be a group of control line on the graph shows the actual temperature that might be
settings that will give the desired heat pattern. The operator experienced on the surface of a test board at or near a central
must set temperatures for several heating zones, and a figure solder joint. The two profiles are based on a high density and
for belt speed. Taken together, these control settings make up a low density board. The Vitronics SMD310 convection/in-
a heating “profile” for that particular circuit board. On frared reflow soldering system was used to generate this
machines controlled by a computer, the computer remembers profile. The type of solder used was 62/36/2 Tin Lead Silver
these profiles from one operating session to the next. Figure with a melting point between 177 –189°C. When this type of
17 shows a typical heating profile for use when soldering a furnace is used for solder reflow work, the circuit boards and
surface mount device to a printed circuit board. This profile will solder joints tend to heat first. The components on the board
vary among soldering systems but it is a good starting point. are then heated by conduction. The circuit board, because it
Factors that can affect the profile include the type of soldering has a large surface area, absorbs the thermal energy more
system in use, density and types of components on the board, efficiently, then distributes this energy to the components.
type of solder used, and the type of board or substrate material Because of this effect, the main body of a component may be
being used. This profile shows temperature versus time. The up to 30 degrees cooler than the adjacent solder joints.

STEP 1 STEP 2 STEP 3 STEP 4 STEP 5 STEP 6 STEP 7

PREHEAT VENT HEATING HEATING HEATING VENT COOLING
ZONE 1 “SOAK” ZONES 2 & 5 ZONES 3 & 6 ZONES 4 & 7
“RAMP” “RAMP” “SOAK” “SPIKE” 205° TO 219°C
200°C 170°C PEAK AT
DESIRED CURVE FOR HIGH SOLDER JOINT
MASS ASSEMBLIES 160°C

150°C
150°C
SOLDER IS LIQUID FOR
40 TO 80 SECONDS
100°C 140°C (DEPENDING ON
100°C MASS OF ASSEMBLY)

DESIRED CURVE FOR LOW

MASS ASSEMBLIES
50°C

TIME (3 TO 7 MINUTES TOTAL) TMAX

Figure 17. Typical Solder Heating Profile

Motorola TMOS Power MOSFET Transistor Device Data 9

MTD1N80E
PACKAGE DIMENSIONS

NOTES:
–T– SEATING 1. DIMENSIONING AND TOLERANCING PER ANSI
PLANE Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
B C
INCHES MILLIMETERS
V R E DIM MIN MAX MIN MAX
A 0.235 0.250 5.97 6.35
B 0.250 0.265 6.35 6.73
C 0.086 0.094 2.19 2.38
Z D 0.027 0.035 0.69 0.88
A E 0.033 0.040 0.84 1.01
S F 0.037 0.047 0.94 1.19
G 0.180 BSC 4.58 BSC
U H 0.034 0.040 0.87 1.01
K J 0.018 0.023 0.46 0.58
K 0.102 0.114 2.60 2.89
L 0.090 BSC 2.29 BSC
F J R 0.175 0.215 4.45 5.46
L STYLE 2: S 0.020 0.050 0.51 1.27
H PIN 1. GATE U 0.020 ––– 0.51 –––
2. DRAIN V 0.030 0.050 0.77 1.27
D 2 PL 3. SOURCE Z 0.138 ––– 3.51 –––
4. DRAIN
G 0.13 (0.005) M T

CASE 369A–13
ISSUE W

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different
applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does
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associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
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*MTD1N80E/D*
10 ◊ Motorola TMOS Power MOSFET Transistor Device Data
MTD1N80E/D