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Tutorial 1

1) The document discusses negative capacitance transistors, which use a ferroelectric material to achieve capacitance lower than what is normally possible. 2) By placing a ferroelectric material in series with a regular insulator, the total energy can be minimized when the ferroelectric is at a local maximum, resulting in an effective negative capacitance. 3) This negative capacitance can then allow transistors to have a higher transconductance and steeper subthreshold slope than normally possible.

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Ellen Sentovich
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© © All Rights Reserved
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0% found this document useful (0 votes)
53 views

Tutorial 1

1) The document discusses negative capacitance transistors, which use a ferroelectric material to achieve capacitance lower than what is normally possible. 2) By placing a ferroelectric material in series with a regular insulator, the total energy can be minimized when the ferroelectric is at a local maximum, resulting in an effective negative capacitance. 3) This negative capacitance can then allow transistors to have a higher transconductance and steeper subthreshold slope than normally possible.

Uploaded by

Ellen Sentovich
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Negative Capacitance Transistors

Sayeef Salahuddin
Electrical Engineering and Computer Sciences, UC Berkeley

Research group: http://leed.eecs.berkeley.edu


Hardware- Is it of any use?

[wikipedia]

[nvidia.com]

Salahuddin@Berkeley DAC-Tutorial-2020 2
Hardware- Is it of any use?

[wikipedia]

[nvidia.com]

Salahuddin@Berkeley DAC-Tutorial-2020 3
40%
17%
Compute Performance Gain of the PastCompilers
Decade
Power Management
Microarchitecture
15% 8% Additional Die Size
Additional TDP
Process Technology
Compilers 8% v Higher performance,
Power Management 12% denser logic transistors
Microarchitecture Compilers
v Back-end-of-line RC
Additional Die Size 40% Power Management
reduction
Additional
v Software TDP
Advancement 17% Microarchitecture
Process of
v Integration Technology
system Additional Die Size
components 15% Additional TDP
v Architectural Efficiency 8% Process Technology
Ø Bigger Die
Ø Enhanced thermal
management

More than half of compute performance gain overCompilers


last decade
Power Management
came from process technology innovation
Microarchitecture
Additional Die Size
Source: Lisa Su (AMD), ERI DARPA Summit, 2019 Additional TDP
Process Technology

[slide courtesy: S. Datta, Univ. Notre Dame]


Salahuddin@Berkeley DAC-Tutorial-2020 4
Ferroelectrics as a correlated system
Ferroelectric Dipoles

State up State down

Replace by a ferroelectric insulator In an ordered system fundamental


limit of energy dissipation for a state
transition becomes:

NkBT kBT

[Interacting systems for self-correcting low power switching,


Salahuddin and Datta., Appl. Phys. Lett.90, 093503 (2007)]

[S. Salahuddin and S. Datta, Nanoletters, 2008]

Salahuddin@Berkeley DAC-Tutorial-2020 5
Negative Capacitance in a Ferroelectric

Ferroelectric insulator Regular insulator

U
U

Q2
U= 2( C) Q2
U= 2C
Q

Salahuddin@Berkeley DAC-Tutorial-2020 6
Energy considerations

Q2
U= 2( C)

Salahuddin@Berkeley DAC-Tutorial-2020 7
Energy considerations
V
CFE

Cs

U
U DE
U

FE

U= Q2
2( C)
+ Q2
=
Q
U= 2C Q

Salahuddin@Berkeley DAC-Tutorial-2020 8
Energy considerations
V
CFE

Cs

U
U DE
U
FE+DE
FE

U= Q2
2( C)
+ Q2
=
Q
U= 2C Q
✏<0

Salahuddin@Berkeley DAC-Tutorial-2020 9
Energy considerations

U
V DE
CFE FE+DE
FE
Cs

Q
✏<0 Total energy is
minimized, where,
locally, FE is at a local
maxima

Salahuddin@Berkeley DAC-Tutorial-2020 10
Energy considerations

U
V DE
CFE FE+DE
FE
Cs

Q
✏<0 Total energy is
minimized, where,
|"!"||"#| locally, FE is at a local
𝐶 = " $"# maxima
!"
Less Energy for the same Q for FE+DE
𝑄!
𝑈=
2𝐶
Capacitance has increased!

Salahuddin@Berkeley DAC-Tutorial-2020 11
Negative capacitance transistors

𝐶)* 𝐶)* < 0 |"!"|


𝑑𝜓' = 𝑑𝑉
𝐶)* + 𝐶' +
𝑑𝜓𝑠 = 𝑑𝑉𝐺
"!" $"#
"#!
• A gain > 1 is possible
$%"
• The amount of gain is dependent upon
how well Cs is matched to |CFE|

log ID
Vg m<1

CFE m<1 𝜕𝑉& ION


𝑆= 2.3𝑘( 𝑇
ys 𝜕𝜓'
m 𝐶)* <0
Cs IOFF
S
D Vg
[S. Salahuddin et al, Nanoletters, 2008]

Salahuddin@Berkeley DAC-Tutorial-2020 12
Negative Capacitance Operation in a NCFET

Vg
CFE 𝑉)* = 𝑉𝑔 − 𝑉𝑠
,
= 𝑉& −
ys
-!

Cs Q = C. V/ − C. V01

𝑄 = 𝜖2 𝐸 + 𝑃

𝜖2 𝑡3*
𝑃 = 𝐶' 𝑉& − 𝐶' 𝑉)* 1 +
𝜖3* 𝑡)*

[Supplementary info, Salahuddin et al, Nanoletters, 2008]

Salahuddin@Berkeley DAC-Tutorial-2020 13
Negative Capacitance Operation in a NCFET
Vg
20 20
CFE a b

ys 10 10

P (μ C/cm )

P (μ C/cm )
2

2
Cs
z
Increasing Vg Increasing
0 0
Vg
y
-10 -10
𝑉)* = 𝑉𝑔 − 𝑉𝑠 x
,
= 𝑉& − -20 -20
-!
0
-1-100
0 100 1 -100 0 100
Fig. 5. (a) Conventional unit Eext (kV/cm)
cell of Eext (kV/cm)
a ferroelectric perovskite (ABO3 ). There are eight A cations (dar
𝑄 = 𝐶' 𝑉& − 𝐶'(black),
𝑉)* and six O anions (white).VWe FE(V)
divide the O ions into two groups: the two Ok ions at the ends
Fig. S1: The steady state solution of LK equation gives a S curve. The series capacitance ac
line, which denotes the line of B ion displacement; and the remaining four O? ions. For simplicity, we a
displacements are along the z-axis. (b) Schematic
Important of the dipole
to note:fields in the (200) plane. The Ok ions pro
(blue) at the B ion
as𝑡 awhile the O
load line on?it.ions
Theproduce
circles depolarizing
show orfields
the operating
• Polarization (red).
points
Charge The OVg
when
changes ions
kinistheare moreApolarized,
increasing.
same so
higher slop
𝜖 2 overall
The result is an 3* polarizing field at the B ion.
𝑃 = 𝐶' 𝑉& − 𝐶' 𝑉)* 1 + direction as the applied voltage
𝜖3* 𝑡)*
load line gives a steeper• ∂ψIts /is∂Vthe
g . internal voltage VFE which is changing in
If the slope of the load line is low, it cuts through th
the opposite direction
ferroelectric itself is acting in a region of negative capacitance. Note also that if Cs is l
(i.e.
[Supplementary info, if the slope
Salahuddin of the
et negative slopeload
al, Nanoletters, theline
of2008] is larger
S curve, samplingthan the slope
the curve of so
frequently dQ/dV in the
that we have ψ s negative ca
vs. Vg plot tha
then the load line will intersect at multiple points in the S curve, leading to a hystere
Salahuddin@Berkeley DAC-Tutorial-2020 14
load line consideration constitutes the design rules that should be followed for a ne
Fundamental Tests of Negative Capacitance

Salahuddin@Berkeley DAC-Tutorial-2020 15
Enhanced Capacitance

Vg
CFE |"!"||"#|
𝐶=
"!" $"#
ys
Cs

Salahuddin@Berkeley DAC-Tutorial-2020 16
Negative Capacitance: Coupling with a dielectric

Hy

First demonstration of negative capacitance effect in FE-DE bi-layer [A Khan et, al, APL, 2011]

[W. Gao, et al, Nanoletters, (2014), AI Khan et. al., Nature Materials, 2015
Appleby et al Nanoletters, (2014), Zubko et. al, Nature, (2016)]

Salahuddin@Berkeley DAC-Tutorial-2020 17
Energy considerations

U
DE
FE+DE
FE

Q
✏<0

Salahuddin@Berkeley DAC-Tutorial-2020 18
Microscopic imaging of negative capacitance

[Yadav et al (Nature, 2019)


in collaboration with Ramesh (Berkeley), D Muller (Cornell) and J. Jonquera groups]
Salahuddin@Berkeley DAC-Tutorial-2020 19
Microscopic Imaging of Negative Capacitance
Polarization
Electric Field

I = 𝜖2 𝐸K + 𝑃K
𝐷 K 𝑑𝐷
𝐺 = ∫ 𝐸. I
[Yadav et al Nature, 565, 7740, 468–471, 2019]

Salahuddin@Berkeley DAC-Tutorial-2020 20
Capacitance Enhancement

Extended Data Fig. 9 | Experimentally measured dielectric constant


as a function of [Yadav
voltage.etInalred, data are
Nature, shown
565, for468–471,
7740, (SrTiO3)12/
a 100 nm 2019]
(PbTiO3)12 superlattice where the existence of vortex states was confirmed.
Salahuddin@Berkeley In blue, for comparison, theDAC-Tutorial-2020
permittivity (dielectric constant) of a 50 nm 21
SrTiO sample is plotted (note that the combined thickness of SrTiO in
resistance corresponding to an increase in voltage takes place fe
when reaching a critical thickness of the product layer at which tr
the Fermi level of the electrode step-changes to the Fermi level th

Negative Capacitance
of the product layer, resulting in an “on/off” increase/decrease tr
of the charge accumulated at the interfaces to align the new in
electrolyte/electrode Fermi levels. W
The polarizations are nearly constant in the range −2 ≤ V (V)
REVIEWS FULL PAPER ca
−1
≤ 2 (−20 ≤ E (V·cm ) ≤ 20) once a steady equilibrium is www.advenergym fa
achieved, as observed in Figure 5a,b. The optimization and th
Negative slightlyCapacitance
higher temperature for Electrostatic
are reflected in an Supercapacitors
approximately 1 po
Ferroelectric negative capacitance order of magnitude increase in the relative permittivity (from εr
Jorge Íñiguez 1,2
*, Pavlo Zubko , Igor Luk’yanchuk and Andrés Cano
3 4 5,6
Michael Hoffmann,*
= 3.7 × 109Franz Paul Gustav
in Figure 5a to εFengler, Benjamin 10 Max, Uwe Schroeder,
r = 2.3 × 10 in Figure 5b). The
w
Abstract | The capacitor is a key element of electronic devices and is characterized by positive Stefan Slesazeck,
resistance andtoThomasformation Mikolajick
of the EDLC in the capacitor, obtained va
capacitance. However, a negative capacitance (NC) behaviour may occur in certain cases
from the slope of the[Adv. I versusEnergyV line of Mater. Figure 5c2019, (1/R = dI/dV), di
and implies a local voltage drop opposed to the overall applied bias. Therefore, a local NC
response results in voltage enhancement across the rest of the circuit. Within a suitably −1 braking energy 1901154]
in electric vehicles of or
designed heterostructure, ferroelectrics display such an NC effect, and various ferroelectric- The increasing shows
demand aforconductivity
efficient storage ofof about
electrical 26ismS·cm
energy one of the forvide a sweep
a backup rate powerof supply for cr
−1 ju
based microelectronic and nanoelectronic devices have been developed, showing improved
performance attributed to NC. However, the exact physical nature of the NC response and direct
main challenges 0.050in theV·s . In thetoward
transformation EISa spectrum
carbon neutralin Figure
society. While5d, the impedance
electrical systems. of
Recently, there [3,7]

electrostatic capacitors can achieve much higher power densities compared been increasing interest in purely ele
experimental evidence remain elusive or controversial thus far. In this Review, we discuss the the constant phase element Q2 in theareequivalent
physical mechanisms responsible for ferroelectric NC, tackling static and transient NC responses. to other storage technologies like batteries, their energy densities compar-
circuit
static solid in
stateFigure
supercapacitors base
We examine ferroelectric responses to voltage and charge, as well as ferroelectric switching, 5d can be related to the capacitance
atively low. Here, it is proposed and demonstrated that negative capacitance, C = (QR) 1/α
/R,
highly
where
polarizable
is e.g.,ofHf
Rmaterials,
electrics and antiferroelectrics. [8–11]
and discuss proof-of-concept experiments and possibilities for device implementation. Finally,
we highlight different approaches for the optimization of the intrinsic NC response to maximize which is present theinresistance to thecan
ferroelectric materials, formation of thethecapacitor
be used to improve energy and 0 < αand
we propose ≤ demonstrate
1, C2 Article a new F
× 10 by pubs.acs.org/JACS gl
storage of capacitors beyond fundamental limits. While negative capacitance
voltage amplification.
= 6.9 mF is used to calculate the permittivity, εr =tostatic
was previously mainly considered for low power electronics, it is shown
increase the9 energy density of ele
1.3 capacitors (high Cite This: J. Am. Chem. Soc. 2018, 140, 17968−17976
using negative ca
The capacitor is one of the most basic components of materials , which outperform traditional perovskite
15–18
frequency) at 200 °C, and ε ≃ 2.3 × 10 10
(low tance frequency)
(NC), which wasisrecently obsepo
electronic devices (BOX 1) and is characterized by its oxides in terms of complementary metal-oxide- that ferroelectric/dielectric capacitors using negative capacitance r are [12–18]
in ferroelectric materials. How
obtained from the CVProperties
curve in the
capacitance C, which relates the charges ±Q on the plates semiconductor compatibility. Ferroelectric NC is cur- promising for energy storage applications. Compared to earlier results using
of the capacitor to the voltage V between them as Q = CV. rently explored not only in proof-of-principle experiments
Extraordinary Dielectric at interval
Heterojunctions−2.0the≤concept
V (V) of ≤ be2.0applicable toioo
should
(anti)ferroelectric materials for electrostatic energy storage, much higher materials and structures exhibitingin
The capacitance further relates the electrical energy U and modelling but also for materials optimization and
stored in the capacitor to its charge, U = Q /(2C). This device implementation. Thus, this field gathers often
2
Amorphous
efficiencies
for this95%optimized
of more than Ferroelectrics
Au/Li+-glass/Au cell. The
even for ultrahigh energy densities beyond
permittivity
tive feedback mechanisms, which
Materials Research and
m
1
electrostatic energy is positive definite , and thus the distant research communities, including physicists,
f ≳ 500
1

capacitance is a positive quantity. In fact, according materials scientists and electrical engineers. Therefore, 100 J cm aredecreases
Braga,*,†,‡ rapidly with frequency
Tianhan Kai,for Hz; the† Allen
resistance
Technology Department, −3 ‡thin films suitable
§ proposed as the origin §of NC. In [19]
Luxembourg Institute of M. Helena demonstrated using nonepitaxial
Joana E. Oliveira, for
Andrew J. Murchison, J. Bard,
Science and Technology
(LIST), Esch/Alzette,
to the principle of minimum energy, a capacitor with fundamental concepts, including terminology, need to
negative capacitance (NC) would charge spontaneously. be clarified, and a common ground for NC research integration and Johnonseems
3D to decrease
B. substrates.
Goodenough* as well
Stable operation
,† 150 °C and
(0.625
up to Ω 10 8
≈ 10 mHzwasand
at fcharging/ trast to previous
0.022 research on
Ω at the switc NC, stw
focused on reducing
μ
Luxembourg. Despite this fundamental constraint, the hypothetical needs to be established. discharging cycles is further demonstrated.
2
Physics and Materials
Science Research Unit,
virtues of electronic circuits containing NC components
have long attracted the interest of electrical engineers . Global versus local capacitance
2–6
f ≳ Institute,
The Materials 300 mHz). †
Department of Mechanical Engineering, The University of Texas at energy of nanoscale
Austin, Austin, transistors,
Texas 78712, United we
[19]

University of Luxembourg,
Belvaux, Luxembourg. The realization of NC behaviour in ferroelectrics was The fundamental principle of minimum energy states
States
It is important
LAETA, Department to highlight
of Engineering Physics, FEUP, Universitythat Figures

of Porto, 4b,f,g
4200-465 Porto,
propose to use NC to increase the en
andin 5b
stored
Portugal clearly
capacitors beyond conventi
of
first proposed by Landauer in 1976 . Indeed, the that capacitance cannot be negative. This principle is
(REF.7)

and States exm


3
London Centre for
limits. This can be achieved by combining a ferroelectric
Nanotechnology and
Department of Physics and
appearance of a spontaneous polarization in a ferro- global and applies to the capacitor as a whole; how-
electric slab is reminiscent of the spontaneous charging ever, it allows considerable flexibility at the local level.
1. Introduction show
Center for negative
Electrochemistry, differential
Department of Chemistry, capacitance §
The University of Texas forat Austin, V (V)
3 < Austin, Texas<78712,
10 United
rial, which exhibits NC, with a regular dielectric mate
ringguidelines for options on how to legitimately share published articles.

Astronomy, University of a capacitor with NC (BOX 1). Thanks to the landmark An inhomogeneous capacitor with two dielectrics −1has a positive capacitance, in a capacitor structure
F CALIFORNIA BERKELEY on October 10, 2019 at 05:32:58 (UTC).

*S Supporting Information

( )
College London, London, UK. The storage of electrical energy has only been possible since the 2which
works of Bratkovsky and Levanyuk8,9, today we know between the plates can be modelled as two capacitors
dQ dU
4
Laboratory of Condensed
Matter Physics, University of
that an effective NC response is a hallmark of ferro-
electric domain structures with partial screening. The
in series C1 and C2 (FIG. 1a). The overall capacitance is
−1
then C = (C 1−1 + C 2−1) , which needs to be positive owing
−10 < V (V) < − 3, C =
invention of the capacitor in 1745.[1] When a voltage is applied =
diff constant are dQ 2 , where U is the potential
fixed charges at the interface between both layers. The resu an
Picardie, Amiens, France.
possibility of NC-based voltage amplification, envi- to thermodynamic stability. However, this relation is
ABSTRACT:
to a capacitor, energyMaterials
is storedhaving
in theaelectric
high dielectric
field in the dVdielec- nonlinear charge–voltage characteristics of this ferroelec
5
Institut Néel, CNRS & needed for a variety of electrical
tric material which separates the two conducting applications from electrodes.
transistors to dielectric capacitor improves the stored energy at a fixed vo
Université Grenoble Alpes, sioned by Salahuddin and Datta10, further increased also true if one of the local effective capacitances, for
Grenoble, France. the interest in ferroelectric NC effects11–14. In particular, example, C1, is negative, as long as the condition C ≥ 0 The major
capacitors. Ferroelectric amorphous-oxide (glass) alkali-ion
advantages of the energy storage in capacitors are a compared to the dielectric layer alone, which would 17973 be im
6
Department of Materials, ferroelectric NC can be used to overcome the so-called is fulfilled. electrolytes of composition A2.99Ba0.005ClO (A = Li, Na) are
ETH Zurich, Zurich, Boltzmann tyranny that limits the performance of In this scenario, the application of an external voltage
high energy
shownstorage
by twoefficiency,
different temperature, and cycling
types of measurement different sible with only positive capacitance materials. Moreover,
andstability
Switzerland. conventional transistors (FIG. 1). This possibility ena- V results in Vint = V(1 + C2/C1)−1 at the interface between as well as high power
consistent densities.
analyses to haveOn the other hand,high
extraordinarily regular die-
dielectric approach highlights a more general pathway toward impr
*e-mail: [email protected]; bles ultralow-power nanoelectronic applications with the two dielectrics, such that Vint/V > 1 if C1 < 0. That lectric capacitors cannot from
constants, varying compete 25 °C
109 atwith 1010 at
thetoorders of 220 °C if the energy storage systems by utilizing materials with other “n
magnitude
[email protected];
the potential to resolve the energy challenge associ- is, NC of one part of the system enables amplification
[email protected];
ated with very-large-scale-integration technologies. of the voltage at the interface (FIG. 1b). Contrary to the
glass is properly
higher energy storage conditioned.
densities of,These anomalously
e.g., batteries or high cells.[2] tive” properties, e.g., negative stiffness materials[20] for mec
fuel dielectric
[email protected]
The current outburst of activity in the NC field is also usual decrease in the overall capacitance when a regular However, properties
so-called coexist with alkali-ion conductivities
supercapacitors, which combine °C that
at 25 the highare ical energy storage systems.
https://doi.org/10.1038/
s41578-019-0089-0 related to the emergence of new HfO2-based ferroelectric (positive) capacitance is added in series, the addition of equivalent
power density of to those of the
capacitors withbest organic-liquid
much electrolytes
higher energy of a Li-
densities,
ion cell, and cyclic voltammetry (CV) in a Au/glass electrolyte/
are idealAuforcell
applications
is stable fromwhere −10a large
to +10amount of energy
V. A model has to
to interpret
NATURE REVIEWS | MATERIALS VOLUME 4 | APRIL 2019 | 243
be stored and releasedallin [3–6]
microscopically thea key
relatively
featuresshort
of thetime.
CV curvesCurrently,
shows that 2. Energy Storage in Nonlinear Capacitors
high energy density electrochemical
the electric-double-layer supercapacitors,
capacitors that form atwhich are
the gold/
mostly based on the
electrolyte double-layer
interfaces capacitance
in the Au/glass and pseudocapac-
electrolyte/Au heterojunctionInreverse
general, the electrostatic
polarization energy
at an applied V =in±2.1
density
voltage a dielectric
V, m
Salahuddin@Berkeley DAC-Tutorial-2020 resultingare
itance effects, in used,
three almost
e.g., toequivalent
stabilizedischarging
the power capacitances
grid, recover for a single
rial isphysical
given bycapacitor from −10 to +10 V. 22
D
w= E (D ) dD 5−7
Capacitance Matching
|"NO||"#|
𝐶 =
"!" $"#

Case: A:
Large Hysteresis
0.08 Case D: -CFE Significant improvement of SS in deep threshold
Case C: -CFE
Case: B:
0.06 Large Hysteresis
Cg (F/m2)

Significant improvement of SS in below threshold


0.04 Case C:
Case B: -CFE Small Hysteresis
0.02 Significant Improvement near threshold, hardly
any improvement in deep threshold
Case A: -CFE
0.00 Case D:
No Hysteresis
Significant Improvement near threshold, hardly
-2 -1 0 1 2 any improvement in deep threshold
VG (V)

Salahuddin@Berkeley DAC-Tutorial-2020 23
Negative capacitance transistors

𝐶)* 𝐶)* < 0 |"!"|


𝑑𝜓' = 𝑑𝑉
𝐶)* + 𝐶' +
𝑑𝜓𝑠 = 𝑑𝑉𝐺
"!" $"#
"#!
• A gain > 1 is possible
$%"

Case D: -CFE
0.08 log ID m<1
Case C: -CFE
0.06
ION
Cg (F/m2)

0.04 Largest gain comes


Case B: -CFE
at near threshold for 𝐶)* <0
0.02
Hysteresis free IOFF
Case A: -CFE
0.00 operation
-2 -1 0 1 2
VG (V) Vg

Salahuddin@Berkeley DAC-Tutorial-2020 24
Reverse DIBL in NCFETs

E
ys Vg
CFE
CD D
Efs
Cs EfD

S k
D

Short Channel Effect leads to DIBL, 𝑑𝜓'


Low Vds, >1
increased drain voltage increases 𝑑𝑉+
drain current

Salahuddin@Berkeley IEDM-2017 25
Reverse DIBL

E
ys Vg
CFE
CD D
Efs
Cs EfD

S k
D

High Vds, Total Q goes down


Short Channel Effect leads to DIBL,
Capacitance matching is worse
increased drain voltage increases
drain current gain 𝑑𝜓' is lower
𝑑𝑉+
Drain current goes down with increasing Vds

Salahuddin@Berkeley IEDM-2017 26
Reducing DIBL using Reverse DIBL effect

ID

Conventional
Combined effect

NC EFFECT

VD

Salahuddin@Berkeley IEDM-2017 27
(c)
Current Voltage Characteristic
FE gate: 5 nm Zr doped HfO2
Voltage reduction

& External gate HK dep.


internal gate
NCFET
(e)

BaseLine

erning FE dep. & Top gate pattering

ET process flow.

[Berkeley Group, IEDM, 2015]

HfZrO
Salahuddin@Berkeley DAC-Tutorial-2020 28
Ultra thin Ferroelectrics

[Lichtensteiger et al, Phys Rev. Lett, 94,


047603, 2005]

Junquera & Ghosez. Nature 422, 506 (2003)]


[Dawber et al. J. Phys.: Condens. Matter 15, L393
(2003)] [Stengel & Spaldin. Nature 433, 679 (2006)]
[Spaldin. Science 304, 1606 (2004)].

Salahuddin@Berkeley DAC-Tutorial-2020 29
Ultra thin Ferroelectrics
TiN
a

ArticleHZO
SiO2 a b c
90 1.8 GHz

Capacitance (a.u.)
P
Si [011] 2 nm

dC/dV phase (º)


Zr-HfO2 45

b 0
TiN SiO2 –45
P
Si –90
HZO
Hf (Zr) Si O –6 –4 –2 0 2 4 6
Voltage (V)
SiO2
(+) (-)
d e
2 μm 2 μm
Si [011] 90

PFM amplitude (a.u.)


1 nm

PFM phase (º)


45
(+) (–)
S4 Further evidence of highly-oriented ultrathin HZO via electron microscopy. 0
-sectional ADF STEM images of (A) 50 cycles (–) HZO, and (B) 10 cycles(+) HZO, depicting an
–45
ed film with a preferred high index planeUnpoled
orientation. Si substrateUnpoled
is oriented at the [110]
axis. The emergence of highly-oriented films in the ultrathin regime is further corroborated –90
ray diffraction (fig. S16). 0 30 60 90 120 150 180 –6 –4 –2 0 2 4 6
PFM phase (º) Voltage (V)

ig. 2 | Electric polarization switching in ultrathin HZO. a, Schematic of the overwritten into the opposite polarization state for a ten-cycle HZO film
[Cheema, Suraj
i/SiO2 (2 nm)/HZO (1 nm) heterostructure S. et. al.,
investigated by "Enhanced ferroelectricity
scanning probe notein ultrathin
that films outer
the unpoled grownperimeter
directly on
matches phase contrast with the
maging. b, Schematic of the HZOsilicon." Nature
unit cell in the580, no. 7804orthorhombic
ferroelectric (2020): 478-482.] positively poled regime regardless of the poling-polarity sequence; this
tructure (Pca21). The different-coloured oxygen atoms represent the indicates that ultrathin HZO exhibits spontaneous polarization without
isplaced oxygen atoms (cyan) and the centrosymmetric oxygen atoms (blue) requiring ‘wake-up’ effects to become ferroelectric. Time-dependent PF
Salahuddin@Berkeley
ithin the surrounding cation tetrahedron. The blue arrows labelled DAC-Tutorial-2020
P denote 30
imaging further demonstrates the robust ferroelectric contrast (Extend
he polarization directions corresponding to the acentric oxygen atomic Data Fig. 7). e, Phase and amplitude switching spectroscopy loops for a
Scaled SOI Planar Transistors with 16 cycle FE
(b)
(a)
Tungsten
Tungsten

(a)
~ 54 nm 1.8 nm HZO (b)
2 nm SiO2
HZO(HfZrO2) : 1.8 nm
SiO2 : 2 nm
Si Substrate

Si Substrate

Fig. 1. (a) Schematic drawing of the NCFET gate


stack. (b) TEM image of Si, SiO2, HZO, tungsten
Measured gate stack. Simulated
Fig. 2. (a) Detailed process flow of the NCFET. (b) Schematic drawing of
NCFET process flow and schematic structure of NCFET.
140
VD = 50 mV L= 30 nm
130

Drain Current [A]


Ref.
W : 10 µm
120 with incread e
SS [mV/dec]

NCFET Ref.
110
Ref.
100
90 (d)
80
70 (c)
(c) VD= 0.5 V

30 40 60 80 100 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0


Channel Length [nm] Gate Voltage [V]
Fig. 3. Ferroelectric characterization of 5 nm (a-c) and 1.8 nm (d-g) HZO films. (a) C-V loops taken on 5 nm HZO films in MIM capa
[D. Kwon et al, “Negative Capacitance FET with 1.8 nm thick Zr-doped HfO2 oxide,”IEEE Electron Device Letters,2019]
indicate ferroelectric counterclockwise hysteresis for the phase annealed sample; the non-annealed sample displays non-hysteretic die
behavior. PFM phase contrast imaging of phase annealed 5 nm (b) and 1.8nm HZO (d) demonstrate bistable, remnant polarization
Salahuddin@Berkeley DAC-Tutorial-2020 31 ann
for non-annealed 5 nm (c) and 1.8nm HZO (e), no clear phase contrast is observed. PFM switching spectroscopy loops of the phase
1.8 nm HZO (f) demonstrates ferroelectric 180° phase hysteresis and counterclockwise “butterfly” amplitude loops; for the non-ann
1.8nm HZO (g), non-ferroelectric PFM loops are observed. PFM imaging taken on bare HZO and PFM loops measured on MOS capa
Scaled SOI Planar Transistors with 16 cycle
FE

-4 -5 -5
10 10 10
L : 30 nm
Gate Voltage [V]

-5 Ref. DC
10
(a) tM : 10 us, 1 us, 0.3 us -6 -6
NCFET 10 tM (10 µs) 10 VD : 0.5 V
Drain Current [A]

Drain Current [A]


Drain Current [A]
-6
10 -7 tM (1 µs) -7 ILimit : 1 µA
10 10
-7 tM (0.3 µs)
10
10
-8
(b)
(b) 10
-8

VD = 0.5
10 V
(a) -8
-9 -9
-9 10 NCFET 10
10
-10 -10
-10 10 L : 30 nm 10
10
L = 30 nm VD : 0.5 V
tR : 10
10-11ns 10
-11
10
-11
VD= 0.5 V ILimit : 1 µA
-12
10 10
-12
10
-12

tD : 10 ns
-0.4-0.2 0.0 0.2 0.4 0.6 0.8 1.0 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 -0.4 -0.2 0.0
Gate Voltage [V] Gate Voltage [V] Gate Vo
140
VD = 50 mV L= 30 nm
130
Drain Current [A]
Ref.
W : 10 µm
Steeper
120 swing and lower OFF current with
goes opposite
incread to classical trend
SS [mV/dec]

e
NCFET Ref.
110
Ref.
100
[D. Kwon et al, “Negative (d)
90 Capacitance FET with 1.8 nm thick Zr-doped HfO2 oxide,”IEEE Electron Device Letters,2019]

80
32
Salahuddin@Berkeley
70 (c)
(c) DAC-Tutorial-2020
VD= 0.5 V
Short Channel Effect

All the classical metrics of short channel effect are improved

0.6 0.8 140


VD = 1 V 0.7 NCFET VD = 50 mV
0.5 130
W : 10 µm 0.6 Ref. W : 10 µm
120

SS [mV/dec]
0.4 0.5
DIBL [V]

NCFET 110 NCFET


Vth [V] 0.4
Ref. Ref.
0.3
0.3
(b) 100
0.2 0.2 VD = 0.5 V 90
0.1 Vth@ I D=10 A-8
80
0.1
(a) 0.0 W : 10 µm
70 (c)
0.0 -0.1
30 40 60 80 100 30 40 60 80 100 30 40 60 80 100
Channel Length [nm] Channel Length [nm] Channel Length [nm]

[Kwon et al. IEEE Electron Device Letters, 39, 2, 300–303, 2018]

Salahuddin@Berkeley DAC-Tutorial-2020 33
NC FINFETs

100 L /W =450 nm/30 nm 150


(b) V
-1
ch fin (a) DS=0.05V
10 VDS=0.05 V
120

SS (mV/dec)
10-2
ID (µA/Fin)

HfO2 FinFET HfO2 FinFET


-3
10
10-4 90
10-5
HZO NC-FinFET
10-6 60
60 mV/dec IG
10-7 HZO NC-FinFET

10-8 30 -7
0.0 0.2 0.4 0.6 0.8 1.0 10 10-5 10-3 10-1
VGS (V) ID (µA/Fin)

[Zhou et al, Symposium of VLSI 2018]

Salahuddin@Berkeley DAC-Tutorial-2020 34
NC FINFETs

200
HfO2 FinFET
180

SS (mV/dec)
160 WFin=
90 nm
140
60 nm
120 50 nm
100
80
60
HZO NC-FinFET
40
0.3 1 5 10
LCH / WFin
Short channel effect is substantially improved

[Zhou et al, Symposium of VLSI 2018]

Salahuddin@Berkeley DAC-Tutorial-2020 35
14 nm FINFET Demonstration
Negative Capacitance Transistors on 14 nm GF FINFET Platform

[Zoran Krivokapic et al, E3S Symposium, Berkeley, Oct 20, 2017; also, IEDM 2017]

Salahuddin@Berkeley DAC-Tutorial-2020 36
1/[1/SS n+1/SS p ](mV/dec)

Fig. 13: Active power of FO3 inverter


Energy Efficiency
RO vs. effective SS for Vdd=1.05V.
Figs. 1

Fig. 14: Active power of NCFET FO3 Figs. 1


[Zoran Krivokapic et al, IEDM 2017]
inverter RO with Wn=Wp=360nm, L=14nm.
Salahuddin@Berkeley DAC-Tutorial-2020 37
NCFET@Berkeley

log ID

ION
C1 < 0
IOFF

Vg

[DW Kown et al, IEEE EDL, 2019]

Salahuddin@Berkeley DAC-Tutorial-2020 38
Scaling Roadmap

2021 2024 2033 --

[Berkeley group (in review)]

Salahuddin@Berkeley DAC-Tutorial-2020 39
Conclusion
• Substantial charge and capacitance boost using NC effect have been
demonstrated in different material systems over the last decade
• In the recent years, negative capacitance gate stack has been
integrated on short channel Si transistors demonstrating:
▫ Swing improvement
▫ Lower IOFF
▫ Improved Short Channel Effect
• Negative capacitance gate stack has been demonstrated on GF 14
nm platform showing amenability to VLSI integration
• Simulations show that NC effect could allow FINFETs to scale down
two more generations beyond IRDS roadmap
• NC can provide better short channel effect, thereby allowing
transistors to scale down to smaller gate lengths for the same
𝑔$ 𝑟% à leading to improved and faster analog operation

Acknowledgement: DARPA, Berkeley Center for Negative Capacitance Transistors


Salahuddin@Berkeley DAC-Tutorial-2020 40
Acknowledgement

G Karbasian
Asif I Khan K Chatterjee

Ava Tan S Kim


D Kwon

Y Liao
S Smith S Cheema

A Yadav M Kao
Li-Chen
Wang

S Bakaul

Prof. Chenming Hu
W Gao
Y-K Lin Jason Hsu C Serrao
Salahuddin@Berkeley DAC-Tutorial-2020 41

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