CMOS RF Receiver Design for Wireless LAN Applications

Behzad Razavi
Electrical Engineering Department
University of California, Los Angeles

Abstract S N R = 174 dBm - IOlog(22 MI-Iz) - 80 dBm = 20.6 dB.

This paper describes design techniques for RE’ CMOS re- Assuming S N K R, 10 dB for the required FER and 2 dB o f
ceivers operating in the 2.4-GHz band. A direct-conversion loss in the front-end band-select filter, we arrive at a noise
receiver targetting spread-spectrumwireless LAN applica- figure of 8.6 dB for the receiver.
tions employs partial channel selection filtering, dc offset Another specification of the standard is an adjacent channel
removal, and baseband amplification. Fabricated in a 0.6- (blocker) rejection of 40 dB when the desired channel is at
pm CMOS technology, the receiver achieves a noise figure -74 dBm. This translates to a 1-dB compression point o f
of8.3dB, 1 4 of-9dBm, IPzoft22dBm,andvoltagegain roughly -30 dBm.
of 34 dB while dissipating 80 mW from a 3-V supply. Dy-
namic range and linearity requirements of A/D converters 111. ARCHITECTURE
AND CIRCUIT DESIGN
used in RE’ receivers are also presented. The receiver employs a direct-conversion architccture, a
choice particularly suited to the DS-SS standard because of
I. INTRODUCTION the wide channel bandwidth. The two principal difficulties
Wireless local areanetworks (WLANs) in the2.4-GHzrange of direct conversion, namely, dc offsets and nicker noise, are
have rapidly emerged in the consumer market. Providing flex- treated so as to impact the performance negligibly. Other
ibility and reconfigurability, WLAN standards allow data rates issues [2, 31 are resolved by circuit techniques. Note that local
o f several megabits per second and serve as high-speed links oscillator (LO) leakage to theantenna is less troublesome here
in office buildings, hospitals, factories, etc. For high-volume if it does not desensitize other receivers because it simply
portable applicalions such as laptop computers, both cost and appears as a “jammer” and its cffect is suppressed by the
power dissipation of WLAN transceivers become critical, ne- spread-spectrum nature of the communication scheme.
cessitating compact, efficient solutions. Fig. I shows the receiver architecture. In addition to a Iow-
This paper describes design techniques for RF CMOS re- Baseband
-..~ .
ccivers to be used in WLAN applications. In order to target
realistic specifications, the IEEE 802.11 standard [I] is con-
Channel-Select I
sidered as the framework. Section I1 reviews the standard
and its circuit design implications. Section 111 presents the LNA
architecture and circuit details of a 2.4-GHz receiver designed Vl,
for this standard and Section IV summarizes the experimen-
tal results obtained from the fabricated prototype. Section V Amplifier
deels with the dynamic range and linearity requirements of Channel-Select Q
analog-to-digital converters (ADCs) used in RF receiveFs.

11. IEEE 802.11 STANDARD Fig. I . Receivernrchitecture.

The IEEE 802.11 R F link incorporates spread-spectrum (SS) noise amplifier (LNA) and quadrature downconversion mixers,
techniques in the 2.4-GHz range. The standard offers two the circuit incorporates partial channel-selection filtering, ac
SS formats: frequency-hopped with Gaussian minimum shift coupling, and baseband amplification.
keying (GMSK) modulation and direct sequence (DS) with
quadrature phase shift keying (QPSK) modulation. The re- A. RF Section
ceiver reported herein is designed for the latter type. The design of the LNA and the mixers is determined by
The DS-SS standard spreads a 2-MHz channel by a factor of not only noise, linearity, and gain requirements, but also cC
I I , generating an output channel 22 MHz wide. The required fects related to direct conversion: LO leakage to the antenna
sensitivity across this bandwidth is -80 dBm for a frame error and second-order distortion in the R F path. The configura-
rate (FER) of 8 x IO-2, indicating that the sum of the noise tion depicted in Fig. 2 addresses these issues. The cascode
figure ( N F ) and the signal-to-noise ratio ( S N R ) is: N F + LNA reduces the LO leakage while the inductive loading in

27 s
IEEE
0-7803-S454-0/99/$10.00~1999

Authorized licensed use limited to: INDIAN INSTITUTE OF TECHNOLOGY ROORKEE. Downloaded on February 23,2021 at 10:59:21 UTC from IEEE Xplore. Restrictions apply.
 fiers. To relax thisconstraint, partial channel selection filtering
is interposed between the mixers and the baseband amplifiers,
thus lowering the magnitude of adjacent-channel interferers.
The channel-select filter must contribute little Hicker noise and
tolerate several tens of millivolts of d c offset that appears at
the output of the mixer due to the self-mixing of the LO. A
filter topology satisfying these conditions is the Sallen and
Key configuration depicted in Fig. 4(a), where the amplifier
is connected in unity gain and can therefore withstand large
C1

jLsL H-

~lp;~~
(1-Mixet
To

Fig. 2. LNAImixer circ~iit.

(a)
the LNA and capacitive degeneration in the mixer minimize
the products of second-order nonlinearity. The value of C2
is chosen such that it exhibits a negligible impedance at 2.4
GHz but ii relatively high impedance at frequencies below I I
MHz. As illustrated in Fig. 3, if two large interferers accom-
pany the desired signal, then second-order distortion in the

V0"W

r' M5 7VLO zcz

(b)
Fig. 4. (a) Simple Sallen and Key Iiller, (b) filter merged with output of mixer.
dc offsets. The amplifier must introduce few devices in the
signal path so as to achieve low flicker noise, but it must also
exhibit high linearity. For this reason, the amplifier is realized
..:::. :. as a source follower incorporating a relatively large transistor

-A& ( W / L = 1OOOpm/1.2/m).
The interface between the mixer and the subsequent fil-
ter would typically require a buffer stage with low output
impedance so that the filter characteristics remain unaltcrcd,
but at the cost of substantial noise and power dissipation due
Pig. 3. Effect alseeond-orderdislorlion in IW path.
to the buffer. We recognize that, since the output signal of the
RF path creates a low-frequency beat that, in the presence of mixer is available in the current domain, the input network of
asymmetries in the mixer, experiences direct feedthrough to the filter can be replaced by a Norton equivalent and merged
the baseband without frequency translation [4]. If the spacing with the mixer. Depicted in Fig. 4(b), this technique obvi-
between the interferers is less than I 1 MHz, then the direct ates theneed for interstage buffers. The bottom-plateparasitic
feedthrough component falls in the baseband, thereby corrupt- of C1 is placed at nodes X and Y so as to suppress the LO
ing thedownconverted signal. In thisdesign,on theother hand, feedthrough, which would otherwise desensitize the source
low-frequency beats generated by the LNA are suppressed by follower.
both L , and C;. Furthermore, the input transistor of themixer, The dc offsets resulting from the self-mixing of LO must
M4, creates negligible beat components because of the large be removed so as to avoid saturating the baseband amplifier.
impedance of C,at low frequencies. The effectiveness of these However, since QPSK signals translated to the baseband con-
techniques is evident from the measured second intercept point tain significant energy in the vicinity of zero frequency, the dc
( I & ) (+22 dBm). notch filter must providea very low corner frequency, fc Thus,
the choice of fc is determined by three questions: (I) How
B. Baseband Section does the notch filter affect the downconverted signal? (2) How
The LNNmixer combination exhibits a gain of approxi- high can fc be without excessive degradation of the signal?
mately 24 dB, mandating high linearity in the baseband ampli- (3) How can a notch filer with such a low fc be integrated?

2: 16

Authorized licensed use limited to: INDIAN INSTITUTE OF TECHNOLOGY ROORKEE. Downloaded on February 23,2021 at 10:59:21 UTC from IEEE Xplore. Restrictions apply.
 The first two questions are answered by simulations of a fer from enormous capacitance to the substrate, much greatcr
QPSK signal (with raised-cosine filtering) that is translated to than 10 pF! To resolve this issue, we employ MOS devices
dc and applied to a first-order high-pass RC filter. Shown in operating in deep triode rcgion with a well-co,itrul/ed gate-
Fig. 5 , the output waveforms reveal that the dc notch filter source overdrive voltage. Illustrated in Fig. 6(b), the idea is
based on the observation that, for long-channel deviccs, the
VDD

b
' w $ g r n l

I
1.0 2.0 3.0 4.0
(a)

r
(C)

Fig. 6 . (a) Simple high-pass filter with coiner liequcncy of 10 kHz, (b)
topology yieliliiig no,,*= ,:,y (c) high-pass filler alone wit11 hiscbnnd
arnplificr.
-2,010 1.0 2.0 3.0 4.0
transconductance of a saturated MOSFET (MI) is expressed
(b)
by the same equation, grnl = /LC,,(W/L)(VGS- Vrpf), as
the inverse of the on-resistance of a similar device i n deep tri-
oderegion(M2): R,f, = pC'o,c(W/L)(V~,s - I / T I I ) . That is,
if a saturated device and a linear dcvice have equal overdrive
voltages and equal dimensions, the on-resistance of the latter
is equal to the inverse transconductance of the former. Sincc
the transconductance of MOSFETs can be defined by means of
various analog techniques, this observation makes it possible
to achieve a very high on-resistance.
The design of Fig. 6(b) must nonetheless deal with two
issues. First, the threshold voltage mismatch between Dl1 and
I M2 yields some inaccuracy in the dcfinition of R,,,z. For
1.0 2.0 3.0 4.0

(C)
this reason, an overdrive voltage of 200 mV is chosen for
Fig. 5 . Effect of high-pass filtering on QPSK data translated to baseband: the transistors, suppressing the effect ofmismatches. Second,
(a) ideal QPSK waveform. (b) high-pass filtered data with a corner frequcncy the variation of the on-resistance of M 2 with the input signal
equal to I l l 0 0 of the data rate, (c) high-pass filtered data wilh a corner fre- level leads to distortion. Fortunately, however, the tolewble
quency equal to 1/1000of the data rate.
in-channel distortion is quite high (several perccnt) bccause
introduces intersymbol interference (ISI), quite excessively if of the nature of the signal waveform, and the out-of-channel
fc is on the order of O.Olrs, where rs is the symbol rate. For distortion is low because the coupling capacitor exhibits a IOW
fc 5 O.OOIrs, on the other hand, the eye is quite open and impedance at adjacent-channel frequencics. Simulated and
the residual IS1 can be removed by the equalizer in the digital measured in-channel and out-of-channel two-tone tests of the
domain. receiver confirm these results. Fig. 6(c) shows the differen-
This design incorporates a high-pass filter with a nominal tial implementation of the high-pass filter and the baseband
fc of 10 kHz. Setting the maximum allowable value of the amplifier. In this design, ( W / L ) l = Z(1.5 pm/40 pin) and
coupling capacitor to 10 pF (i.e., a total of 40 pF for differen- (W/L)z,,= 1.5 pm/40 pm.
tial I and Q signals), we arrive at a resistance of 1.G Mi2 [.Fig. The flicker noise in the baseband section corrupts the down-
6(a)]. Even using n-well material, such a resistor would suf- converted signal. However, since the baseband signal occu-

211

Authorized licensed use limited to: INDIAN INSTITUTE OF TECHNOLOGY ROORKEE. Downloaded on February 23,2021 at 10:59:21 UTC from IEEE Xplore. Restrictions apply.
 pies a bandwidth of I I MHz, tlicker noise corner frequencies Edge Of
as high as several hundred kilohertz affect the performance ...........
negligibly. With a corner frequency of 200 kHz, we can write:
S,/,(200 kHz) = Stb, where Si,/and S t h denote the power center Of
spectral densities of I / f noiseand thermal noise, respectively. Adjacent Channel
Assuming SI/,= K / f > where I< = (200 kHz) x Sth, and -10 .......................... :.......
integrating the total noise from 200 kHz to I 1 MHz as in Fig.
7, we have

Fig. 7. Contribution of flicker noise to thc overall S N f l Fig. 8. Measwed baseband tmnsfcr function. (Axes not to scale)

V. ADC REQUIREMENTS
v,,z
- = 1 200 kHz

, 10 k H Z
"Y+/
f
~ 1 1 MHz

200 kHz
Sthdf (1)
The digitization of the received signal can in principle take
place at the antenna, at the intermediate frequency (IF), or i n
% ( I 1.4MHz),St/,. (2)
the baseband. The required performance of the ADC in eacli
By contrast, if the circuit suffered from no flicker noise, the case is determined by the signal dynamic range as well as the
total noise power would be V , = (1 1 MHz)&, only 0.2 dB number and power of the interferers. Thus, both automatic
lower. Note that even if flicker noise frequencies as low as 100 gain control (AGC) and channel-selection filtering can relax
Hz are taken into account, the maximum degradation in S N R the ADC specifications.
is less than 0.6 dB. This is a pessimistic estimate because, The ADC parameters of interest in an R F receiver include
owing t o the relatively high gain in the RF section, the I / f resolution, linearity, full-scale voltage, noise floor (quantiza-
noise corner in the baseband is expected to bequite lower than tion, thermal, and tlicker noise), sampling rate, and power
200 kHz. dissipation. For our subsequent calculations, we review the
definitions of linearity in analog design and RF design.
Assuming a fully-differential architecture for thc ADC and
IV. EXPERIMENAL RESULTS
representing its inputloutput characteristic by
The receiver has been fabricated in a 0 . 6 - p 1 CMOS tech-
nology in an area of 680 pmx980 pm. Both inductors used Kut(t) M w % f L ( q N3V23n(l)> (3) +
in the cascade LNA are integrated on-chip with no process
we define the integral nonlinearity (INL) as the maximum
modifications. The circuit is tested with a 3-V supply.
deviation of V,,,t from a straight line passed through the end
Table I summarizes the measurement results. The out-of-
points of the characteristic (Fig. 9). Here, the end points
are given by the full-scale voltage Vp.9: (+Vps, + r u l VFS +
Input Frequency 2.4 GHz
Noise Figure 8.3 dB
+22 dBm
In-Channel IP3 -9 dBm
1-dB Compression Polnt -21 dBm
Out-of-Cnannel IP3 -4 dBm
Voltage Gain
LO Leakage -47 dBm
0 ~ 1 Offset
~ ~ Voltage
1 - 7 mV
Power Dlssipallon 80 mW

Table I . Measured pcrformanceafrecciver at 1.4 CHI

channel IP3 is measured by applying two tones 22 MHz apart

such that thcy fall at 22 MHz and 44 MHz after downcon-
version and their intermodulation product appears near zero Pig. 9. Dcflnilion of INL.
frequency. Fig. 8 plots the measured transfer function of the WV;s) and (-VFS, -alVr..s - cqV;,). Thus, the straight
baseband section, obtained by sweeping the RF input. Note line can be expressed as
that the corner frequency of the baseband dc notch filter is
approximatelyequal to 7 kHz, confirming the feasibilityof the
circuit topology shown in Fig. 6(c).

278

Authorized licensed use limited to: INDIAN INSTITUTE OF TECHNOLOGY ROORKEE. Downloaded on February 23,2021 at 10:59:21 UTC from IEEE Xplore. Restrictions apply.
 Subtracting V,,,,l from K,, and taking the derivative of the noiseis approximately 20dB below the minimum signal level.
result with respect to V,,, we obtain the input level K,,o at Thus, lOlog(V&,/Af) = -118 dBm - 1010g(200 kHz) =
which the nonlinearity is maximum: &! o = V ~ s / \ / s , and -171 dBm/I-Iz, suggesting that an cxtremely low noise floor
the maximum nonlinearity as I N L = 2 1 ~ ~ 3 I V > ~ / ( 3 f Ap-
i). (0.629 nV/d%) is required.
proximating the output full scale by 2 a l V ~ and
s normalizing The full-scale voltage of the ADC is given by the maximum
IINI,I to this value, we have: input level. In the simple test of Fig. 10, the two interferers
_ , , generate a maximum swing of approximately -50 dBm +6
(5) dB = -44 dBm (3.99 mVp, in a SO-Q system). Note that this
means 2 V ~ = s 3.99 mV in Fig. 9.
The abovecalculations reveil that an ADC digitizinga GSM
Note that the concept of full scale is central to the definition of
signal along with -SO-dBm interferers at the antenna would
nonlinearity in analog design but not utilized in R F design.
require an LSB of 0.995 p V and a full-scale voltage of 3.99
The most significant effect of (odd-order) nonlinearity from
mV, i.e., a resolution of approximately 12 bits.
the RF design point of view is intermodulation. If two in-
ADC Linearity. In order to determine the linearity required
terferers xnt1(t)= V,,tcosw~I and ! 4 , , 2 ( 1 ) = lintcoswzt
of the ADC, we assume the two interferers must create an
experience the nonlinearity described by (3), then the inter-
intermodulation product at least 20 dB below the signal level.
modulation products are given by
From (6),the signal-to-intermodulation ratio at the output can
be expressed as:
- wz)t + C O S ( ~-WW ~I ) ~ ] . (6)
303 3
V,,t,,u = --V,,,[COS(~W~
4
Signal -
- la1IVmin
Equations ( 5 ) and (6) prove useful in our subsequent deriva- Intermodulation (3/4)lo31V,i, ' (7)
tions.
where V,i, denotes the peak amplitude of the minimum input
A. Digitizationat RF signal level, i.e., the receiver sensitivity. Setting (7) equal to
As a simple case, we first assume the ADC directly digi- I O yields D3/011 = 2Vmi,/( 154il). It follows from ( 5 ) that
tizes the signal and the interferers at the antenna. In order to
compute the resolution, full scale, and linearity, we consider
a typical test for GSM receivers. Thc results can easily be
scaled for other standards as well. As shown in Fig. 10, a
-98-dBm signal is accompanied by two interferers located

This equation expresses the maximum allowable nonlinearity

in terms of the sensitivity, full-scale voltage, and interferer
levels. In a S O - 9 system, each of the -50-dBm interferers has
apeakamplitudeof Knt 4 1 mV and theminimum inputlevel
has a peak amplitude of V,i, 3 4 pV. Thus, with ~ V F S= 4
mV, we have INL,,, = 4.11 x i.e., a linearity of
approximately 11.3 bits.
An important result ot'(9) is that the required linearity does
Channel
Number " "+'
n+4 not change with preamplification because both the numerator
and the denominator scale by the third power of the voltage
Pig. IO. lnterrnadulaliantest in GSM. gain. For this reason, amplifier stages interposed between the
two and four channels away. GSM requires that in such a test antenna and the ADC relax the noise floor and offset require-
the signal-to-noise ratio at the end of the receiver be at least ments but not the linearity requirement.
9 dB, restricting both the noise figure and intermodulation be- In summary, our simple GSM example demands an ADC
havior of the overall receiver. For simplicity, we assume each with a resolutionof 12 bits, an LSB size of 0.995 AIV,a thermal
interferer has a magnitude of -50 dBm. noise floor of 0.629 nV/&, and a linearity of 11.3 bits.
ADC Resolution. The resolution is determined by the min- While the necessary dynamic range and linearity do not seem
imum signal level. To ensure that the ADC corrupts the signal prohibitive, the small magnitudes of the LSB and the input-
negligibly, we assume the quantization noise must be approx- referred noise present great difficulty in the design.
imately 20 dB below the signal level, arriving at a resolution In practice, both the resolution and the linearity may need
of about 3 bits. This yields a least significant bit (LSB) equal to be higher than those calculated above. Depending on the
to 0.995 ~ I V(in a 50-9 system). type of AGC, the maximum received signal level may demand
The thermal noise floor of the ADC is also critical. For a a greater full scale. Also, more than two interferers may be
channel bandwidth of 200 kHz in GSM, we calculate the input- received, necessitating a higher linearity. This is particularly
referred thermal noise density of the ADC such that the total important in time-division duplexing (TDD) systems such as

219

Authorized licensed use limited to: INDIAN INSTITUTE OF TECHNOLOGY ROORKEE. Downloaded on February 23,2021 at 10:59:21 UTC from IEEE Xplore. Restrictions apply.
 DECT and IEEE 802.11, where thestrong signals transmitted The first term in (IO) gives the in-channel intermodulation
by all of the users fall in the receive band. In these cases, product, which is lower than that in (6) by a factor ofA:A2.
the foregoing methods can be used in conjunction with the Thus, a3 can berelaxed byA:AZ. Noting that Vr.7 hasdropped
statistics of the interference levels to predict the resolution and +
by 2/(A1 Az), we can modify Eq. (9) as:
linearity.

B. Digitizarion at IF
In order to achieve acceptable image rejection by means of
low-loss, low-cost filters, modern receivers typically employ With the above numbers for AI and A z , INI,,,,,:, i s relaxed
a relatively high IF - from approximately 5 0 MHz to 200 MHz by a factor of 6.05, i.e., 2.6 bits.
[5]. Thus, thesamplingrateand input bandwidtbof an IFdigi- C. Digitization in Baseband
tizer would still be quite high. More importantly, even high-Q
off-chip filters used at the IF to perform channel-selection be- Thecost, size, and loss ofexternal IF filters make it desirable
come incapable of suppressing adjacent-channel interferers as to perform channel-selection filtering by means of monolithic
the IF increases. For example, for the NDK248SM01 (a SAW implementations. At high IFS, however, it is quite difficult
filter with a passband of 260 kHz centered around 248 MHz to design integrated passive or active filters that attenuate the
and an insertion loss of 6 dB), the attenuation is equal to 6 dB adjacent channels significantly. The precision and speed re-
at 260 kHz offset and 26 dB at 520 kHz offset. quired of the IFdigitizer in this case are still problematic, often
Effect of Partial Channel-Selection Filtering. Since IF necessitating that AID conversion be moved to the vicinity of
filters attenuate the interferers by only a moderate amount, the baseband.
it is important to quantify the effect of such filtering on the Our foregoing calculations of the effect of filters hint that
required ADC performance. The results also apply to base- even a moderate attenuation of interferers may lead to a rea-
band channel-selection filtering as well, revealing trade-offs sonable demand on the ADC performance. This is important
between the filter design and the ADC design. because complete channel selection in the analog domain typi-
Suppose, as shown in Fig. 11, the IF filter provides a cally entails high power dissipation and many large capacitors.
suppressionofAI < 1 in thecenteroftheadjacent channeland We consider two types of low-pass filters (LPFs) here.
First-Order LPF. A first-order filter can readily be incorpo-
rated in downconversion mixers by simply placing a capacitor
between the differential outputs. The key property of this ap-
1 ................. Channel Channel Channel
proach is that the filter does not contribute additional noise.
A1 ._______.
...... _____........._
.____.
For such a filter, the attenuation factors in the two adjacent
_ _ _ _ _ . .______
_____....______
A p _________...._____ .I _____. channels are A I = 0.447 and A2 = 0.243. Thus, the required
full-scale voltage drops by 1.5 bits and, from Eq. ( I I ) , the
0 1 0 2 w
INL is relaxed by a factor of 2.45, i.e., 1.3 bits.
Fig. 11. Baodpass filter frequency response
Sallen and Key Filter. For maximally-flat response, we
Az < 1 in the center of the alternate adjacent channel. Since chooseinFig. ~ R=IRz = R a n d C ~= 2C2,0btainiiigAl =
the additive amplitude of the two interferers is reduced by the 0.243 and A2 = 0.0624. As a result, both the resolution and
filter, the full-scalevoltageand hence theresolution ofthe ADC the INL are relaxed by 2.7 bits. This configuration is thcrefore
can be lowered. More importantly, smaller interferers allow an attractive solution even though its transfer characteristics
higher nonlinearity in the ADC input/output characteristic. are relatively sensitive to component variations.
Assuming- two equal interferers translated to the IF can be
+
expressed as V,,, cos w l t E,,, cos wzt, we can write the out- REFERENCES
put ofthe filter asA1I4,t c o s ( w ~ l + d ~ ) + A z Kcos(wzt+dn),
~t
where and $2 denote the phase shift introduced by the fil- [I]IEEE, P802.11. UraJ Sraiidardfor Wi,r/ess LAN Medieiii Ac-
cess Conrrol (MAC) and Physical Layer (PIIY) Specijicotion,
ter at W I and W Z , respectively. The peak-to-peak value of this
IEEE Standards Dept., 1997.
waveform gives the full scale: VFS= ( A l +Az)I&, relaxing
[ 2 ] A. A. Abidi, “Direct-conversion radio transceivers for digital
the ADC resolution by a factor of 2/(AI Az). For the NDK + cornmunicstions,”IEEE Journal of So/id-Slurc Circiiils,vol.
filter example, A , = 0.5 and Az = 0.05, indicating that the 30,pp. 1399-1410,Dec. 1995.
necessary resolution drops by 2/0.55, i.e., 1.9 bits. [3] B. Razavi, “Design Considerations for Direct-ConversionRc-
To compute the required linearity, we apply the output of ccivers,” IEEE Trans. Circuirs and Systems, Parr 11, vol. 44,
the filter to the ADC input/output characteristic [Eq. (3)] and pp, 428-435, June 1997.
obtain the intermodulation component: [4] B . Raravi, HF Microekcrronics, Upper Saddle River,
NJ:Prentice Hall, 1998.
) -A
V I M ( ~=
3Q3 2
-
I A9V3
rnt COS[(ZWI - wz)t + 241 - 421 [SI T. D. Stetzler era/, “A 2.7-4.5 V Single Chip CSM Transceiver
RF Integrated Circuit,” IEEE Journal of Solid-Stare Circuits,
+ -AIA~K:,
3a3
4
C O S [ ( ~ W Z- ~ +
j ) t 242 - 411.10)
vol. 30, pp. 1421-1429,Dec. 1995.

280

Authorized licensed use limited to: INDIAN INSTITUTE OF TECHNOLOGY ROORKEE. Downloaded on February 23,2021 at 10:59:21 UTC from IEEE Xplore. Restrictions apply.