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LGLite ATE LoadBoard

1. The document provides instructions for using an LGLite logic analyzer system with a built-in pattern generator to test a 74-series CMOS 2-input AND gate. 2. Key steps include connecting the pattern generator outputs to the AND gate inputs, connecting a logic analyzer channel to the AND gate output, loading a test vector, powering the chip, and running the test to observe the gate's response on the logic analyzer display. 3. The test demonstrates that the AND gate outputs a 1 only when both inputs are 1, and outputs 0 for the other input combinations, verifying correct gate function.

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Vijayakumar S
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93 views

LGLite ATE LoadBoard

1. The document provides instructions for using an LGLite logic analyzer system with a built-in pattern generator to test a 74-series CMOS 2-input AND gate. 2. Key steps include connecting the pattern generator outputs to the AND gate inputs, connecting a logic analyzer channel to the AND gate output, loading a test vector, powering the chip, and running the test to observe the gate's response on the logic analyzer display. 3. The test demonstrates that the AND gate outputs a 1 only when both inputs are 1, and outputs 0 for the other input combinations, verifying correct gate function.

Uploaded by

Vijayakumar S
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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LGLite & ATE

LGLite + Load Board

APPLIED DIGITAL MICROSYSTEMS PVT LTD


D-216, ANSA INDUSTRIAL ESTATE, SAKI VIHAR ROAD,
ANDHERI EAST, MUMBAI 400 072.
Tel: (91-22 -)28470817, 66924483/4
Email: [email protected]
YahooMessenger:admmum
Introduction to LGLite – ATE training

LGLite 32 channels are a new generation three-in-one product, an Interactive


Pattern Generator, Logic Analyzer and a Frequency Counter. The combination of
Pattern Generator and Logic Analyzer is a powerful tool for designing; debugging
and automated testing of digital discrete and C/CPLD/FPGA based designs.
LGLite, which is designed, as a PC hosted instrument is an ideal tool for learning
fundamentals of Digital In-Circuit testing and test program development.

To get started learning and testing embedded digital components we need to


understand:
1. How the digital components – (DUT – Device under Test) on the board
work before you can figure out how to test them.
2. How the LGLite tester Drive logic (Pattern Generator) and the
Response Sensor (Logic Analyzer) will be used for the test.

Objectives:
1. Learn to operate LGLite ATE with Load board.
2. Insert 74Series chip into ZIF socket on Load board.
3. Use LGLite Pattern Generator to provide stimulus to 74Series chip input.
4. LGLite Logic Analyzer records response from 74Series chip output.

A Load-board has been provided and should be in front of the logic analyzer for
your use. Plug your DUT into the Load-board ZIF socket for testing.

Digital logic is the foundation for embedded ATE testing. If you want to
understand the innards of ATE you need to know digital logic. First, there's
background you need to know - the basics of digital logic - things like zeros and
ones (0s and 1s) and how you can represent signals as sequences of zeroes and
ones.
You will also need to know things about digital circuits - gates, flip-flops and
memory elements and others - so that you can eventually test digitals circuits to
validate boards with digital components and digital signals moving between
them. We should note that all of these signals can and usually will change in
time, so that we really are looking at dynamic situations.

This document provides instruction on how to use LGLite Logic Analyzer system
with a built in pattern generator. A simple CMOS 2-input AND gate will be used
as an example test circuit. This lab experiment will provide you with enough
experience to test your own digital circuits using LGLite – ATE trainer.

In this tutorial, we will be using a CMOS Quad 2-input AND gate as our DUT. It
has a 14-pin package that has the PIN layout as shown below. For this tutorial,
we will only be testing the first AND gate in the package. Thus the input pins are
#1 – 1A & #2 – 1B, and the output pin is #3- 1Y.

An AND function can be implemented electrically using a device known as an


AND gate (7408) as shown above. Let us assume we have two logic signals, 1A
and 1B, which are an input set to some circuit that takes these two logic signals
as inputs, and has an output that is also a logic signal. The output, 1Y, depends
upon the inputs, A and B. There are many different ways that 1Y could depend
upon A and B. The output, 1Y is a function, - a logic function - of the inputs, A
and B. We will examine a few basic logic functions - AND, OR and NOT
functions and start learning the circuitry that you use to implement those
functions.

If we think of two signals, A and B, as representing a truth-value of two different


propositions, then A could be either TRUE (a logical 1) or FALSE (a logical 0).
B can take on the same values. Now consider a situation in which the output,
1Y, is TRUE only when both A is TRUE and B is TRUE. We can construct a
truth table for this situation. In that truth table, we insert all of the possible
combinations of inputs, A and B, and for every combination of A and B we list the
output, 1Y.
Step 1. Provide POWER to the chip
A logic analyzer is not meant to provide supply voltage to your DUT on Load-
board. If you attempt to do so, your chip may draw more current than the logic
analyzer can supply. So for any DUT, you will need to provide VCC & GND from
an external power supply.

Step 2. Attach Pattern Generator to your DUT:


Configure LG-Lite PG Channel #1 thru #8 as Pattern Generator. Using flat cable,
attach LGLite channel 1-8 to Load-board header 1-8. Connect output flying lead
wire #1 and #2 from Load-board to ZIF DUT PIN #1 and PIN #2 of AND gate.

Note, all components (the DUT, and all cables) must share a common-ground
point. This is true for any testing you do with LGLite.

Step 3. Attach Logic Analyzer to your DUT:


The pattern-generator provides stimulus to your DUT. We now need to attach the
logic analyzer cables to your DUT to monitor the output of the pattern generator
& the DUT‟s response to the stimulus. Connect LGLite LA input flying lead wire
#9 from Load-board to ZIF DUT PIN #3 of AND gate.
Step 4. Configure LGLite – LA/PG to Test CMOS device (DUT)

The config menu option allows the user to configure the channels in group of 8
as LA or PG. We configure first 8 channels (1-8) as PG and next 8 channels
(9-16) as LA.

The PG channels will provide 'stimulus' or a 'test pattern' to your DUT CHIP on
the Load board. LA channels will record output signals from your DUT CHIP in
response to the stimulus you create.

Step 5. From the Waveform menu, choose->clock or the clock button

Set the clock frequency to match the clock frequency of your DUT. Note, even if
your device is combinational, it still has a frequency at which the data must be
presented to the chip. Clocking can be from 50Mhz to 1Khz.

Step 6.From the LGATE menu, choose: OpenVCTfile


This is where you will setup the test vector (or pattern) to stimulate your DUT.
The Vector file is in plain text. The openVCTfile loads the vector and can be seen
in the waveform window.
Step 7: RUNNING THE TEST:

The Waveform window loads the test vector. Click on Go button. Make certain
that your DUT has “VDD” and “GND” properly connected to it from an outside
power supply, as discussed earlier. The waveforms below shows that the AND
gate is working. The top two lines represent the output from the pattern
generator, and the bottom waveform shows the output from the AND gate. Inputs
00, 10, and 01 produce 0, while input 11 produces a 1.

Summary of Test Procedure.

1. Select LGATE mode


2. Select DUT clocking speed
3. Configure LGLite Pattern Generator channels and LA channels
4. Load the test Vector
5. Hit the GO button
6. See the captured response to the input test vector.

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