LGLite ATE LoadBoard
LGLite ATE LoadBoard
Objectives:
1. Learn to operate LGLite ATE with Load board.
2. Insert 74Series chip into ZIF socket on Load board.
3. Use LGLite Pattern Generator to provide stimulus to 74Series chip input.
4. LGLite Logic Analyzer records response from 74Series chip output.
A Load-board has been provided and should be in front of the logic analyzer for
your use. Plug your DUT into the Load-board ZIF socket for testing.
Digital logic is the foundation for embedded ATE testing. If you want to
understand the innards of ATE you need to know digital logic. First, there's
background you need to know - the basics of digital logic - things like zeros and
ones (0s and 1s) and how you can represent signals as sequences of zeroes and
ones.
You will also need to know things about digital circuits - gates, flip-flops and
memory elements and others - so that you can eventually test digitals circuits to
validate boards with digital components and digital signals moving between
them. We should note that all of these signals can and usually will change in
time, so that we really are looking at dynamic situations.
This document provides instruction on how to use LGLite Logic Analyzer system
with a built in pattern generator. A simple CMOS 2-input AND gate will be used
as an example test circuit. This lab experiment will provide you with enough
experience to test your own digital circuits using LGLite – ATE trainer.
In this tutorial, we will be using a CMOS Quad 2-input AND gate as our DUT. It
has a 14-pin package that has the PIN layout as shown below. For this tutorial,
we will only be testing the first AND gate in the package. Thus the input pins are
#1 – 1A & #2 – 1B, and the output pin is #3- 1Y.
Note, all components (the DUT, and all cables) must share a common-ground
point. This is true for any testing you do with LGLite.
The config menu option allows the user to configure the channels in group of 8
as LA or PG. We configure first 8 channels (1-8) as PG and next 8 channels
(9-16) as LA.
The PG channels will provide 'stimulus' or a 'test pattern' to your DUT CHIP on
the Load board. LA channels will record output signals from your DUT CHIP in
response to the stimulus you create.
Set the clock frequency to match the clock frequency of your DUT. Note, even if
your device is combinational, it still has a frequency at which the data must be
presented to the chip. Clocking can be from 50Mhz to 1Khz.
The Waveform window loads the test vector. Click on Go button. Make certain
that your DUT has “VDD” and “GND” properly connected to it from an outside
power supply, as discussed earlier. The waveforms below shows that the AND
gate is working. The top two lines represent the output from the pattern
generator, and the bottom waveform shows the output from the AND gate. Inputs
00, 10, and 01 produce 0, while input 11 produces a 1.