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UCC27210, UCC27211
SLUSAT7F – NOVEMBER 2011 – REVISED DECEMBER 2014

UCC2721x 120-V Boot, 4-A Peak, High-Frequency High-Side and Low-Side Driver
1 Features 3 Description
1• Drives Two N-Channel MOSFETs in High-Side The UCC27210 and UCC27211 drivers are based on
and Low-Side Configuration With Independent the popular UCC27200 and UCC27201 MOSFET
drivers, but offer several significant performance
Inputs
improvements. Peak output pull-up and pull-down
• Maximum Boot Voltage 120-V DC current has been increased to 4-A source and 4-A
• 4-A Sink, 4-A Source Output Currents sink, and pull-up and pull-down resistance have been
• 0.9-Ω Pullup and Pulldown Resistance reduced to 0.9 Ω, thereby allowing for driving large
power MOSFETs with minimized switching losses
• Input Pins Can Tolerate –10 V to 20 V and Are during the transition through the Miller Plateau of the
Independent of Supply Voltage Range MOSFET. The input structure is now able to directly
• TTL or Pseudo-CMOS Compatible Input Versions handle –10 VDC, which increases robustness and
• 8-V to 17-V VDD Operating Range, (20-V also allows direct interface to gate-drive transformers
Absolute Maximum) without using rectification diodes. The inputs are also
independent of supply voltage and have a maximum
• 7.2-ns Rise and 5.5-ns Fall Time With 1000-pF rating of 20-V.
Load
• Fast Propagation Delay Times (18 ns Typical) Device Information(1)
• 2-ns Delay Matching PART NUMBER PACKAGE BODY SIZE (NOM)
• Symmetrical Undervoltage Lockout for High-Side SOIC (8) 4.90 mm × 3.91 mm
and Low-Side Driver UCC27210, PowerPAD (8) 4.89 mm × 3.90 mm
UCC27211 WSON (10)
• All Industry Standard Packages Available (SOIC- 4.00 mm × 4.00 mm
8, PowerPAD™ SOIC-8, 4-mm × 4-mm SON-8 VSON (8)
and 4-mm × 4-mm SON-10) (1) For all available packages, see the orderable addendum at
• Specified from –40 to 140 °C the end of the datasheet.

2 Applications
• Power Supplies for Telecom, Datacom, and
Merchant
• Half-Bridge and Full-Bridge Converters
• Push-Pull Converters
• High-Voltage Synchronous-Buck Converters
• Two-Switch Forward Converters
• Active-Clamp Forward Converters
• Class-D Audio Amplifiers
space
Typical Application: UCC27210 Typical Application: UCC27211
+12V +100V +12V

VDD +100V SECONDARY

SIDE
VDD SECONDARY CIRCUIT
HB
SIDE
HB CIRCUIT
HI DRIVE HO
CONTROL

HI
PWM HS
HI DRIVE HO CONTROLLER
CONTROL

LI
HI DRIVE LO
PWM HS LO
CONTROLLER
LI UCC27211
DRIVE LO
VSS
LO
+12V
UCC27210 VDD +100V
VSS HB

ISOLATION
AND HI DRIVE HO
CONTROL

FEEDBACK HI
HS

LI
DRIVE LO
LO

UCC27211

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCC27210, UCC27211
SLUSAT7F – NOVEMBER 2011 – REVISED DECEMBER 2014 www.ti.com

Table of Contents
1 Features .................................................................. 1 8.1 Overview ................................................................. 13
2 Applications ........................................................... 1 8.2 Functional Block Diagram ....................................... 14
3 Description ............................................................. 1 8.3 Feature Description................................................. 14
8.4 Device Functional Modes........................................ 15
4 Revision History..................................................... 2
5 Description (Continued) ........................................ 4 9 Application and Implementation ........................ 16
9.1 Application Information............................................ 16
6 Pin Configuration and Functions ......................... 4
9.2 Typical Application ................................................. 16
7 Specifications......................................................... 5
10 Power Supply Recommendations ..................... 21
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings ............................................................ 6 11 Layout................................................................... 21
11.1 Layout Guidelines ................................................. 21
7.3 Recommended Operating Conditions....................... 6
11.2 Layout Example .................................................... 22
7.4 Thermal Information .................................................. 6
11.3 Thermal Considerations ........................................ 22
7.5 Electrical Characteristics........................................... 7
7.6 Switching Characteristics: Propagation Delays ........ 8 12 Device and Documentation Support ................. 23
7.7 Switching Characteristics: Delay Matching ............... 8 12.1 Documentation Support ........................................ 23
7.8 Switching Characteristics: Output Rise and Fall 12.2 Related Links ........................................................ 23
Time ........................................................................... 8 12.3 Trademarks ........................................................... 23
7.9 Switching Characteristics: Miscellaneous ................. 8 12.4 Electrostatic Discharge Caution ............................ 23
7.10 Typical Characteristics .......................................... 10 12.5 Glossary ................................................................ 23
8 Detailed Description ............................................ 13 13 Mechanical, Packaging, and Orderable
Information ........................................................... 23

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision E (August 2013) to Revision F Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1

Changes from Revision D (November, 2012) to Revision E Page

• Added Note 2 to the Terminal Functions Table...................................................................................................................... 5

• Changed Repetitive pulse data from -18 V to -(24V-VDD). ................................................................................................... 5
• Added additional details to Note 2.......................................................................................................................................... 5
• Changed Voltage on HS, VHS (repetitive pulse <100 ns) data from -15 to -(24V-VDD)......................................................... 6
• Deleted 2.4-mA operating current min range in both places.................................................................................................. 7
• Changed operating current max range extended to 5.2 in both places. ................................................................................ 7
• Deleted 1.5 min Boot voltage operating current range........................................................................................................... 7
• Changed Boot voltage operating current max range from 4.2 to 5.0. .................................................................................... 7
• Changed HB to VSS operating current max range from 1.1 to 1.2. ........................................................................................ 7
• Changed LO Gate Driver's Low-level output voltage max range from 0.17 to 0.19............................................................... 7
• Changed HO GATE Driver's Low-level output voltage max range from 0.17 to 0.19. ........................................................... 7

Changes from Revision C (March, 2012) to Revision D Page

• Changed capacitor range from 1.0 µF to 4.7 µF. ................................................................................................................... 5

• Added Terminal Functions Note to HI and LI pin description................................................................................................. 5
• Changed bullet 2 in the Layout Recommendations. ........................................................................................................... 21
• Added Note: For systems using... ........................................................................................................................................ 21

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• Added Note: Care should be taken... ................................................................................................................................... 21

Changes from Revision B (February) to Revision C Page

• Changed VDD operating current max range of 4.3 to 4.4 in both places. ............................................................................... 7
• Changed Boot voltage operating current max range from 4.0 to 4.2. .................................................................................... 7
• Changed HB to VSS quiescent current max range from 0.13 to 1.0. ...................................................................................... 7
• Changed HB to VSS operating current max range from 0.9 to 1.1. ........................................................................................ 7
• Added Input UCC27210/11 (DDA Only) values. .................................................................................................................... 7
• Added Under-Voltage Lockout (UVLO) DDA only values, two places. .................................................................................. 7
• Changed LO Gate Driver's Low-level output voltage max range from 0.15 to 0.17............................................................... 7
• Changed LO Gate Driver's VLOH max range from 0.27 to 0.29. ............................................................................................. 7
• Changed HO GATE Driver's Low-level output voltage max range from 0.15 to 0.17. ........................................................... 7
• Changed VLI falling to VLO falling min value from 17 to 15. .................................................................................................... 8
• Changed VHI falling to VHO falling min value from 17 to 15. ................................................................................................... 8
• Changed VLI rising to VLO rising min value from 18 to 15....................................................................................................... 8
• Changed VHI rising to VHO rising min value from 18 to 15...................................................................................................... 8
• Changed Figure 17, Output Current vs. Output Voltage. ..................................................................................................... 12

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5 Description (Continued)
The switching node (HS pin) of the UCC2721x can handle –18 V maximum which allows the high-side channel to
be protected from inherent negative voltages caused parasitic inductance and stray capacitance. The UCC27210
(Pseudo-CMOS inputs) and UCC27211 (TTL inputs) have increased hysteresis allowing for interface to analog or
digital PWM controllers with enhanced noise immunity.
The low-side and high-side gate drivers are independently controlled and matched to 2 ns between the turnon
and turnoff of each other.
An on-chip 120-V rated bootstrap diode eliminates the external discrete diodes. Undervoltage lockout is provided
for both the high-side and the low-side drivers providing symmetric turnon and turnoff behavior and forcing the
outputs low if the drive voltage is below the specified threshold.
Both devices are offered in 8-pin SOIC (D), PowerPAD SOIC-8 (DDA), 4-mm × 4-mm SON-8 (DRM) and SON-
10 (DPR) packages.

6 Pin Configuration and Functions

SOIC-8 (D) Power PadTM SOIC-8 (DDA)
TOP VIEW TOP VIEW

VDD 1 8 LO VDD 1 8 LO

Exposed
2 7 2 Thermal 7
HB VSS HB VSS
Die Pad

HO 3 6 LI HO 3 6 LI

HS 4 5 HI HS 4 5 HI

SON-8 (DRM) SON-10 (DPR)

TOP VIEW TOP VIEW

VDD 1 8 LO VDD 1 10 LO

Exposed
Thermal HB 2 9 VSS
HB 2 7 VSS
Die Pad*
HO 3 8 LI
HO 3 6 LI
HS 4 7 HI

HS 4 5 HI NC 5 6 NC

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Pin Functions
PIN
I/O DESCRIPTION
NAME D/DDA/DRM DPR
Positive supply to the lower-gate driver. Decouple this pin to VSS (GND). Typical
VDD 1 1 P
decoupling capacitor range is 0.22 µF to 4.7 µF (See (1)).
High-side bootstrap supply. The bootstrap diode is on-chip but the external bootstrap
capacitor is required. Connect positive side of the bootstrap capacitor to this pin.
HB 2 2 P Typical range of HB bypass capacitor is 0.022 µF to 0.1 µF. The capacitor value is
dependant on the gate charge of the high-side MOSFET and should also be selected
based on speed and ripple criteria
HO 3 3 O High-side output. Connect to the gate of the high-side power MOSFET.
High-side source connection. Connect to source of high-side power MOSFET.
HS 4 4 P
Connect the negative side of bootstrap capacitor to this pin.
HI 5 7 I High-side input. (2)
LI 6 8 I Low-side input. (2)
VSS 7 9 G Negative supply terminal for the device which is generally grounded.
LO 8 10 O Low-side output. Connect to the gate of the low-side power MOSFET.
N/C — 5/6 — Not connected.
Used on the DDA, DRM and DPR packages only. Electrically referenced to VSS
PowerPAD
Pad Pad G (GND). Connect to a large thermal mass trace or GND plane to dramatically improve
™ (3)
thermal performance.

(1) For cold temperature applications we recommend the upper capacitance range. Attention should also be made to PCB layout - see
Layout.
(2) HI or LI input is assumed to connect to a low impedance source signal. The source output impedance is assumed less than 100 Ω. If the
source impedance is greater than 100 Ω, add a bypassing capacitor, each, between HI and VSS and between LI and VSS. The added
capacitor value depends on the noise levels presented on the pins, typically from 1 nF to 10 nF should be effective to eliminate the
possible noise effect. When noise is present on two pins, HI or LI, the effect is to cause HO and LO malfunctions to have wrong logic
outputs.
(3) The PowerPAD™ is not directly connected to any leads of the package. However it is electrically and thermally connected to the
substrate which is the ground of the device.

7 Specifications
7.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
(2)
Supply voltage range, VDD , VHB - VHS –0.3 20
Input voltages on LI and HI, VLI, VHI –10 20
DC –0.3 VDD + 0.3
Output voltage on LO, VLO
Repetitive pulse <100 ns (3) –2 VDD + 0.3
DC VHS – 0.3 VHB + 0.3 V
Output voltage on HO, VHO
Repetitive pulse <100 ns (3) VHS – 2 VHB + 0.3
DC –1 115
Voltage on HS, VHS
Repetitive pulse <100 ns (3) –(24 V-VDD) 115
Voltage on HB, VHB –0.3 120
Operating virtual junction temperature, TJ –40 150
°C
Lead temperature (soldering, 10 sec.) 300
Storage temperature, Tstg –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to VSS unless otherwise noted. Currents are positive into, negative out of the specified terminal.
(3) Verified at bench characterization. VDD is the value used in an application design.

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7.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22- ±1000 V
C101 (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

all voltages are with respect to VSS; currents are positive into and negative out of the specified terminal. –40°C < TJ = TA <
140°C (unless otherwise noted)
MIN TYP MAX UNIT
Supply voltage range, VDD, VHB-VHS 8 12 17
Voltage on HS, VHS –1 105
Voltage on HS, VHS (repetitive pulse <100 ns) –(24V-VDD) 110 V
VHS +8, VHS +17,
Voltage on HB, VHB
VDD –1 115
Voltage slew rate on HS 50 V/ns
Operating junction temperature range –40 140 °C

7.4 Thermal Information

UCC27210, UCC27211
THERMAL METRIC D DDA DRM DPR UNIT
8 PINS 8 PINS 8 PINS 10 PINS
θJA Junction-to-ambient thermal resistance (1) 111.8 37.7 33.9 36.8
θJCtop Junction-to-case (top) thermal resistance (2) 56.9 47.2 33.2 36.0
(3)
θJB Junction-to-board thermal resistance 53.0 9.6 11.4 14.0
°C/W
ψJT Junction-to-top characterization parameter (4) 7.8 2.8 0.4 0.3
ψJB Junction-to-board characterization parameter (5) 52.3 9.4 11.7 14.2
(6)
θJCbot Junction-to-case (bottom) thermal resistance n/a 3.6 2.3 3.4

(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(4) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
(5) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer

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7.5 Electrical Characteristics

VDD = VHB = 12 V, VHS = VSS = 0 V, no load on LO or HO, TA = TJ = –40°C to 140°C, (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENTS
IDD VDD quiescent current V(LI) = V(HI) = 0 V 0.05 0.085 0.17
IDDO UCC27210 2.6 5.2
VDD operating current f = 500 kHz, CLOAD = 0
UCC27211 2.5 5.2 mA
IHB Boot voltage quiescent current V(LI) = V(HI) = 0 V 0.015 0.065 0.1
IHBO Boot voltage operating current f = 500 kHz, CLOAD = 0 2.5 5.0
IHBS HB to VSS quiescent current V(HS) = V(HB) = 115 V 0.0005 1.0 µA
IHBSO HB to VSS operating current f = 500 kHz, CLOAD = 0 0.07 1.2 mA
INPUT
VHIT Input voltage threshold UCC27210 4.2 5.0 5.8
UCC27210 (DDA only) 4.2 5.0 5.9
VLIT Input voltage threshold UCC27210 2.4 3.2 4.0 V
UCC27210 (DDA only) 2.4 3.2 4.0
VIHYS Input voltage hysteresis 1.8
UCC27210
RIN Input pulldown resistance 102 kΩ
VHIT Input voltage threshold UCC27211 1.9 2.3 2.7
UCC27211 (DDA only) 1.9 2.3 2.8
V
VLIT Input voltage threshold UCC27211 1.3 1.6 1.9
UCC27211 (DDA only) 1.3 1.6 2.1
VIHYS Input voltage hysteresis 700 mV
UCC27211
RIN Input pulldown resistance 68 kΩ
UNDERVOLTAGE LOCKOUT (UVLO)
VDDR VDD turnon threshold 6.2 7.0 7.8
DDA only 5.8 7.0 8.1
VDDHYS Hysteresis 0.5
V
VHBR VHB turnon threshold 5.6 6.7 7.9
DDA only 5.3 6.7 8.0
VHBHYS Hysteresis 1.1
BOOTSTRAP DIODE
VF Low-current forward voltage IVDD-HB = 100 µA 0.65 0.8
V
VFI High-current forward voltage IVDD-HB = 100 mA 0.85 0.95
RD Dynamic resistance, ΔVF/ΔI IVDD-HB = 100 mA and 80 mA 0.3 0.5 0.85 Ω
LO GATE DRIVER
VLOL Low-level output voltage ILO = 100 mA 0.05 0.09 0.19
V
VLOH High level output voltage ILO = -100 mA, VLOH = VDD - VLO 0.1 0.16 0.29
Peak pull-up current (1) VLO = 0 V 3.7
A
Peak pull-down current (1) VLO = 12 V 4.5
HO GATE DRIVER
VHOL Low-level output voltage IHO = 100 mA 0.05 0.09 0.19
V
VHOH High-level output voltage IHO = -100 mA, VHOH = VHB - VHO 0.1 0.16 0.29
Peak pull-up current (1) VHO = 0 V 3.7
A
Peak pull-down current (1) VHO = 12 V 4.5

(1) Ensured by design.

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7.6 Switching Characteristics: Propagation Delays

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TDLFF VLI falling to VLO falling UCC27210, CLOAD = 0 15 21 37
TDHFF VHI falling to VHO falling 15 21 37
TDLRR VLI rising to VLO rising 15 24 46
TDHRR VHI rising to VHO rising 15 24 46
ns
TDLFF VLI falling to VLO falling UCC27211, CLOAD = 0 10 17 30
TDHFF VHI falling to VHO falling 10 17 30
TDLRR VLI rising to VLO rising 10 18 40
TDHRR VHI rising to VHO rising 10 18 40

7.7 Switching Characteristics: Delay Matching

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TMON From HO OFF to LO ON TJ = 25°C 3 11
ns
TJ = –40°C to 140°C 3 14
UCC27210
TMOFF From LO OFF to HO ON TJ = 25°C 3 11
ns
TJ = –40°C to 140°C 3 14
TMON From HO OFF to LO ON TJ = 25°C 2 9.5
ns
TJ = –40°C to 140°C 2 14
UCC27211
TMOFF From LO OFF to HO ON TJ = 25°C 2 9.5
ns
TJ = –40°C to 140°C 2 14

7.8 Switching Characteristics: Output Rise and Fall Time

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tR LO rise time CLOAD = 1000 pF, from 10% to 90% 7.2
tR HO rise time 7.2
ns
tF LO fall time CLOAD = 1000 pF, from 90% to 10% 5.5
tF HO fall time 5.5
tR LO, HO CLOAD = 0.1 µF, (3 V to 9 V) 0.36 0.6
µs
tF LO, HO CLOAD = 0.1 µF, (9 V to 3 V) 0.15 0.4

7.9 Switching Characteristics: Miscellaneous

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Minimum input pulse width that changes the output 50
ns
Bootstrap diode turnoff time (1) (2) IF = 20 mA, IREV = 0.5 A (3) 20

(1) Ensured by design.

(2) IF: Forward current applied to bootstrap diode, IREV: Reverse current applied to bootstrap diode.
(3) Typical values for TA = 25°C.

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LI

Input
(HI, LI) HI

TDLRR, TDHRR

LO

Output
(HO, LO)

TDLFF, TDHFF
HO

TMON TMOFF

Figure 1. Timing Diagrams

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7.10 Typical Characteristics

100 100
T = 25°C UCC27210, VDD = 12V
IDD, IHB − Quiescent Current (µA)

IDDO − Operating Current (mA)

80
10

60
1
40 CL=0pF, T=−40°C
CL=0pF, T=25°C
0.1 CL=0pF, T=140°C
20 CL=1000pF, T=25°C
UCC27210/1 IDD CL=1000pF, T=140°C
UCC27210/1 IHB CL=4700pF, T=140°C
0 0.01
0 2 4 6 8 10 12 14 16 18 20 10 100 1000
VDD = VHB − Supply Voltage (V) G001
Frequency (kHz) G002

Figure 2. Quiescent Current vs Supply Voltage Figure 3. UCC27210 IDD Operating Current vs Frequency
100 100
UCC27211, VDD = 12V UCC27210/1, VHB − VHS = 12V
IDDO − Operating Current (mA)

IHBO − Operating Current (mA)

10 10

1 1
CL=0pF, T=−40°C CL=0pF, T=−40°C
CL=0pF, T=25°C CL=0pF, T=25°C
0.1 CL=0pF, T=140°C 0.1 CL=0pF, T=140°C
CL=1000pF, T=25°C CL=1000pF, T=25°C
CL=1000pF, T=140°C CL=1000pF, T=140°C
CL=4700pF, T=140°C CL=4700pF, T=140°C
0.01 0.01
10 100 1000 10 100 1000
Frequency (kHz) G003
Frequency (kHz) G004

Figure 4. UCC27211 IDD Operating Current vs Frequency Figure 5. Boot Voltage Operating Current vs Frequency (HB
to HS)
6 6
T = 25°C VDD = 12V
HI, LI − Input Threshold Voltage (V)

HI, LI − Input Threshold Voltage (V)

5 5

4 4

3 3

2 2

1 UCC27210, Rising 1 UCC27210, Rising

UCC27210, Falling UCC27210, Falling
0 UCC27211, Rising 0 UCC27211, Rising
UCC27211, Falling UCC27211, Falling
−1 −1
8 12 16 20 −40 −20 0 20 40 60 80 100 120 140
VDD − Supply Voltage (V) G005
Temperature (°C) G006

Figure 6. UCC27210 and UCC27211 Input Threshold vs Figure 7. UCC27210 and UCC27211 Input Thresholds vs
Supply Voltage Temperature

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Typical Characteristics (continued)

0.32 0.2
IHO=ILO= 100mA IHO=ILO= 100mA
VOH − LO/HO Output Voltage (V)

VOL − LO/HO Output Voltage (V)

0.28
0.16
0.24

0.2 0.12
0.16

0.12 0.08

0.08 UCC27210/1, VDD=VHB=8V UCC27210/1, VDD=VHB=8V

UCC27210/1, VDD=VHB=12V 0.04 UCC27210/1, VDD=VHB=12V
0.04 UCC27210/1, VDD=VHB=16V UCC27210/1, VDD=VHB=16V
UCC27210/1, VDD=VHB=20V UCC27210/1, VDD=VHB=20V
0 0
−40 −20 0 20 40 60 80 100 120 140 −40 −20 0 20 40 60 80 100 120 140
Temperature (°C) G007
Temperature (°C) G008

Figure 8. LO and HO High Level Output Voltage vs Figure 9. LO and HO Low Level Output Voltage vs
Temperature Temperature
8 1.5

7.6
1.2
7.2
Hysteresis (V)
Threshold (V)

0.9
6.8

6.4
0.6

6
0.3
5.6 VDD Rising Threshold VDD UVLO Hysteresis
HB Rising Threshold HB UVLO Hysteresis
5.2 0
−40 −20 0 20 40 60 80 100 120 140 −40 −20 0 20 40 60 80 100 120 140
Temperature (°C) G009
Temperature (°C) G010

Figure 10. Undervoltage Lockout Threshold vs Temperature Figure 11. Undervoltage Lockout Threshold Hysteresis vs
Temperature
40 32
UCC27210, VDD=VHB=12V UCC27211, VDD=VHB=12V
36
32
Propagation Delay (ns)

Propagation Delay (ns)

24
28
24
20 16
16
12
TDLRR 8 TDLRR
8 TDLFF TDLFF
TDHRR TDHRR
4
TDHFF TDHFF
0 0
−40 −20 0 20 40 60 80 100 120 140 −40 −20 0 20 40 60 80 100 120 140
Temperature (°C) G011
Temperature (°C) G012

Figure 12. UCC27210 Propagation Delays vs Temperature Figure 13. UCC27211 Propagation Delays vs Temperature

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Typical Characteristics (continued)

32 32
UCC27210, T=25°C UCC27211, T=25°C
28 28
Propagation Delay (ns)

Propagation Delay (ns)

24 24

20 20

16 16

12 12

8 TDLRR 8 TDLRR
TDLFF TDLFF
4 TDHRR 4 TDHRR
TDHFF TDHFF
0 0
8 12 16 20 8 12 16 20
VDD=VHB − Supply Voltage (V) G012 VDD=VHB − Supply Voltage (V) G014

Figure 14. UCC27210 Propagation Delays vs Supply Voltage Figure 15. UCC27211 Propagation Delays vs Supply Voltage
10 5
VDD=VHB=12V VDD=VHB=12V
8

ILO, IHO − Output Current (A)

4
Delay Matching (ns)

6
3
4
2
2
UCC27210, TMon
UCC27210, TMoff 1
0
UCC27211, TMon Pull Down Current
UCC27211, TMoff Pull Up Current
−2 0
−40 −20 0 20 40 60 80 100 120 140 0 2 4 6 8 10 12
Temperature (°C) G015 VLO, VHO − Output Voltage (V) G016

Figure 16. Delay Matching vs Temperature Figure 17. Output Current vs Output Voltage
100

10
Diode Current (mA)

0.1

0.01

0.001
500 550 600 650 700 750 800 850
Diode Voltage (mV) G017

Figure 18. Diode Current vs Diode Voltage

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8 Detailed Description

8.1 Overview
The UCC27210 and UCC27211 devices represent Texas Instruments’ latest generation of high voltage gate
drivers which are designed to drive both the high side and low side of N-channel MOSFETs in a half-/full-bridge
or synchronous buck configuration. The floating high-side driver can operate with supply voltages of up to 120 V.
This allows for N-channel MOSFET control in half-bridge, full-bridge, push pull, two-switch forward and active
clamp forward converters.
The UCC27210 and UCC27211 devices feature 4-A source/sink capability, industry best-in-class switching
characteristics and a host of other features listed in Table 1. These features combine to ensure efficient, robust
and reliable operation in high-frequency switching power circuits.

Table 1. UCC27210 and UCC27211 Highlights

FEATURE BENEFIT
High peak current ideal for driving large power MOSFETs with
4-A source and sink current with 0.9-Ω output resistance
minimal power loss (fast-drive capability at Miller plateau)
Increased robustness and ability to handle under/overshoot. Can
Input pins (HI and LI) can directly handle –10 VDC up to 20 VDC interface directly to gate-drive transformers without having to use
rectification diodes
120-V internal boot diode Provides voltage margin to meet telecom 100-V surge requirements
Allows the high-side channel to have extra protection from inherent
Switch node (HS pin) able to handle –18 V maximum for 100 ns negative voltages caused parasitic inductance and stray
capacitance.
Robust ESD circuitry to handle voltage spikes Excellent immunity to large dV/dT conditions
Best-in-class switching characteristics and extremely low-pulse
18-ns propagation delay with 7.2-ns / 5.5-ns rise/fall Times
transmission distortion
2-ns (typ) delay matching between channels Avoids transformer volt-second offset in bridge
Symmetrical UVLO circuit Ensures high-side and low-side shut down at the same time
CMOS optimized threshold or TTL optimized thresholds with Complementary to analog or digital PWM controllers. Increased
increased hysteresis hysteresis offers added noise immunity

In the UCC27210 and UCC27211 devices, the high side and low side each have independent inputs which allow
maximum flexibility of input control signals in the application. The boot diode for the high-side driver bias supply
is internal to the UCC27210 and UCC27211. The UCC27210 is the Pseudo-CMOS compatible input version and
the UCC27211 is the TTL or logic compatible version. The high-side driver is referenced to the switch node (HS)
which is typically the source pin of the high-side MOSFET and drain pin of the low-side MOSFET. The low-side
driver is referenced to VSS which is typically ground. The functions contained are the input stages, UVLO
protection, level shift, boot diode, and output driver stages.

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8.2 Functional Block Diagram

2 HB

UVLO
Level 3 HO
Shift

4 HS
HI 5

VDD 1

UVLO
8 LO

LI 6 7 VSS

Copyright © 2016, Texas Instruments Incorporated

8.3 Feature Description

8.3.1 Input Stages
The input stages provide the interface to the PWM output signals. The input impedance of the UCC27210 is 100
kΩ nominal and input capacitance is approximately 2 pF. The 100 kΩ is a pull-down resistance to VSS (ground).
The UCC27210 Pseudo-CMOS input structure has been designed to provide large hysteresis and at the same
time to allows interfacing to a multitude of analog or digital PWM controllers. In some CMOS designs, the input
thresholds are determined as a percentage of VDD. By doing so, the high-level input threshold can become
unreasonably high and unusable. The UCC27210 recognizes the fact that VDD levels are trending downward
and it therefore provides a rising threshold with 5.0 V (typical) and falling threshold with 3.2 V (typical). The input
hysteresis of the UCC27210 is 1.8 V (typical).
The input stages of the UCC27211 have impedance of 70 kΩ nominal and input capacitance is approximately 2
pF. Pull-down resistance to VSS (ground) is 70 kΩ. The logic level compatible input provides a rising threshold of
2.3 V and a falling threshold of 1.6 V.

8.3.2 Undervoltage Lockout (UVLO)

The bias supplies for the high-side and low-side drivers have UVLO protection. VDD as well as VHB to VHS
differential voltages are monitored. The VDD UVLO disables both drivers when VDD is below the specified
threshold. The rising VDD threshold is 7.0 V with 0.5-V hysteresis. The VHB UVLO disables only the high-side
driver when the VHB to VHS differential voltage is below the specified threshold. The VHB UVLO rising threshold is
6.7 V with 1.1-V hysteresis.

8.3.3 Level Shift

The level shift circuit is the interface from the high-side input to the high-side driver stage which is referenced to
the switch node (HS). The level shift allows control of the HO output referenced to the HS pin and provides
excellent delay matching with the low-side driver.

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Feature Description (continued)

8.3.4 Boot Diode
The boot diode necessary to generate the high-side bias is included in the UCC27210 and UCC27211 family of
drivers. The diode anode is connected to VDD and cathode connected to VHB. With the VHB capacitor connected
to HB and the HS pins, the VHB capacitor charge is refreshed every switching cycle when HS transitions to
ground. The boot diode provides fast recovery times, low diode resistance, and voltage rating margin to allow for
efficient and reliable operation.

8.3.5 Output Stages

The output stages are the interface to the power MOSFETs in the power train. High slew rate, low resistance and
high peak current capability of both output drivers allow for efficient switching of the power MOSFETs. The low-
side output stage is referenced from VDD to VSS and the high side is referenced from VHB to VHS.

8.4 Device Functional Modes

The device operates in normal mode and UVLO mode. See the Undervoltage Lockout (UVLO) section for
information on UVLO operation mode. In the normal mode the output state is dependent on states of the HI and
LI pins. Table 2 lists the output states for different input pin combinations.

Table 2. Device Logic Table

HI Pin LI Pin HO (1) LO (2)
L L L L
L H L H
H L H L
H H H H

(1) HO is measured with respect to HS.

(2) LO is measured with respect to VSS.

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9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information

To effect fast switching of power devices and reduce associated switching power losses, a powerful gate driver is
employed between the PWM output of controllers and the gates of the power semiconductor devices. Also, gate
drivers are indispensable when it is impossible for the PWM controller to directly drive the gates of the switching
devices. With the advent of digital power, this situation will be often encountered because the PWM signal from
the digital controller is often a 3.3-V logic signal which cannot effectively turn on a power switch. Level shifting
circuitry is needed to boost the 3.3-V signal to the gate-drive voltage (such as 12 V) in order to fully turn on the
power device and minimize conduction losses. Traditional buffer drive circuits based on NPN/PNP bipolar
transistors in totem-pole arrangement, being emitter follower configurations, prove inadequate with digital power
because they lack level-shifting capability. Gate drivers effectively combine both the level-shifting and buffer-drive
functions. Gate drivers also find other needs such as minimizing the effect of high-frequency switching noise by
locating the high-current driver physically close to the power switch, driving gate-drive transformers and
controlling floating power-device gates, reducing power dissipation and thermal stress in controllers by moving
gate charge power losses from the controller into the driver.
Finally, emerging wide band-gap power device technologies such as GaN based switches, which are capable of
supporting very high switching frequency operation, are driving very special requirements in terms of gate drive
capability. These requirements include operation at low VDD voltages (5 V or lower), low propagation delays and
availability in compact, low-inductance packages with good thermal capability. In summary gate-driver devices
are extremely important components in switching power, combining benefits of high-performance, low-cost
component count and board-space reduction as well as simplified system design.

9.2 Typical Application

+12V +100V

VDD SECONDARY
SIDE
HB CIRCUIT

HI DRIVE HO
CONTROL

HI
PWM HS
CONTROLLER
LI
DRIVE LO
LO

UCC27210

VSS

ISOLATION
AND
FEEDBACK

Figure 19. Typical Application Diagram: UCC27210

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Typical Application (continued)

+12V

VDD +100V SECONDARY

SIDE
HB CIRCUIT

HI DRIVE HO

CONTROL
HI
PWM HS
CONTROLLER
LI
DRIVE LO
LO

UCC27211

VSS

+12V
VDD +100V

HB

HI DRIVE HO
CONTROL

HI
HS

LI
DRIVE LO
LO

UCC27211

Figure 20. Typical Application Diagram: UCC27211

9.2.1 Design Requirements

Table 3. Design Specifications

DESIGN PARAMETER EXAMPLE VALUE
Supply voltage, VDD 12 V
Voltage on HS, VHS 0 V to 100 V
Voltage on HB, VHB 12 V to 112 V
Output current rating, IO –4 A to 4 A
Operating frequency 500 kHz

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9.2.2 Detailed Design Procedure

9.2.2.1 Input Threshold Type

The UCC27210 and UCC27211 have an input maximum voltage range from –10 V to 20 V. This increased
robustness means that both parts can be directly interfaced to gate drive transformers. The UCC27210 features
pseudo CMOS compatible inputs and UCC27211 features TTL compatible input threshold logic, with wide
hysteresis. The threshold voltage levels are low voltage and independent of the VDD supply voltage, which
allows compatibility with both logic-level input signals from microcontrollers as well as higher-voltage input
signals from analog controllers. See the Electrical Characteristics table for the actual input threshold voltage
levels and hysteresis specifications for the UCC27210 and UCC27211 devices.

9.2.2.2 VDD Bias Supply Voltage

The bias supply voltage to be applied to the VDD pin of the device should never exceed the values listed in the
Recommended Operating Conditions table. However, different power switches demand different voltage levels to
be applied at the gate terminals for effective turnon and turnoff. With certain power switches, a positive gate
voltage may be required for turnon and a negative gate voltage may be required for turnoff, in which case the
VDD bias supply equals the voltage differential. With a wide operating range from 8 V to 17 V, the UCC27210
and UCC27211 devices can be used to drive a variety of power switches, such as Si MOSFETs, IGBTs, and
wide-bandgap power semiconductors (such as GaN, certain types of which allow no higher than 6 V to be
applied to the gate terminals).

9.2.2.3 Peak Source and Sink Currents

Generally, the switching speed of the power switch during turnon and turnoff should be as fast as possible in
order to minimize switching power losses. The gate driver device must be able to provide the required peak
current for achieving the targeted switching speeds with the targeted power MOSFET. The system requirement
for the switching speed is typically described in terms of the slew rate of the drain-to-source voltage of the power
MOSFET (such as dVDS/dt). For example, the system requirement might state that a SPP20N60C3 power
MOSFET must be turned-on with a dVDS/dt of 20V/ns or higher with a DC bus voltage of 400 V in a continuous-
conduction-mode (CCM) boost PFC-converter application. This type of application is an inductive hard-switching
application and reducing switching power losses is critical. This requirement means that the entire drain-to-
source voltage swing during power MOSFET turnon event (from 400 V in the OFF state to VDS(on) in on state)
must be completed in approximately 20 ns or less. When the drain-to-source voltage swing occurs, the Miller
charge of the power MOSFET (QGD parameter in SPP20N60C3 data sheet is 33 nC typical) is supplied by the
peak current of gate driver. According to power MOSFET inductive switching mechanism, the gate-to-source
voltage of the power MOSFET at this time is the Miller plateau voltage, which is typically a few volts higher than
the threshold voltage of the power MOSFET, VGS(TH).
To achieve the targeted dVDS/dt, the gate driver must be capable of providing the QGD charge in 20 ns or less. In
other words a peak current of 1.65 A (= 33 nC / 20 ns) or higher must be provided by the gate driver. The
UCC27210 and UCC27211 gate driver is capable of providing 4-A peak sourcing current which clearly exceeds
the design requirement and has the capability to meet the switching speed needed. The 2.4x overdrive capability
provides an extra margin against part-to-part variations in the QGD parameter of the power MOSFET along with
additional flexibility to insert external gate resistors and fine tune the switching speed for efficiency versus EMI
optimizations. However, in practical designs the parasitic trace inductance in the gate drive circuit of the PCB will
have a definitive role to play on the power MOSFET switching speed. The effect of this trace inductance is to
limit the dI/dt of the output current pulse of the gate driver. In order to illustrate this, consider output current pulse
waveform from the gate driver to be approximated to a triangular profile, where the area under the triangle (½
×IPEAK × time) would equal the total gate charge of the power MOSFET (QG parameter in SPP20N60C3 power
MOSFET datasheet = 87 nC typical). If the parasitic trace inductance limits the dI/dt then a situation may occur in
which the full peak current capability of the gate driver is not fully achieved in the time required to deliver the QG
required for the power MOSFET switching. In other words the time parameter in the equation would dominate
and the IPEAK value of the current pulse would be much less than the true peak current capability of the device,
while the required QG is still delivered. Because of this, the desired switching speed may not be realized, even
when theoretical calculations indicate the gate driver is capable of achieving the targeted switching speed. Thus,
placing the gate driver device very close to the power MOSFET and designing a tight gate drive-loop with
minimal PCB trace inductance is important to realize the full peak-current capability of the gate driver.

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9.2.2.4 Propagation Delay

The acceptable propagation delay from the gate driver is dependent on the switching frequency at which it is
used and the acceptable level of pulse distortion to the system. The UCC27210 features 21 ns and the
UCC27211 features 17 ns (typical) propagation delays which ensures very little pulse distortion and allows
operation at very high-frequencies. See the Electrical Characteristics table for the propagation and switching
characteristics of the UCC27210 and UCC27211 devices.

9.2.2.5 Power Dissipation

Power dissipation of the gate driver has two portions as shown in Equation 1.
PDISS = PDC + PSW (1)
The DC portion of the power dissipation is PDC = IQ x VDD where IQ is the quiescent current for the driver. The
quiescent current is the current consumed by the device to bias all internal circuits such as input stage, reference
voltage, logic circuits, protections, and also any current associated with switching of internal devices when the
driver output changes state (such as charging and discharging of parasitic capacitances, parasitic shoot-through,
and so forth). The UCC27210 and UCC27211 features very low quiescent currents (less than 0.17 mA, refer to
the Electrical Characteristics table and contain internal logic to eliminate any shoot-through in the output driver
stage. Thus the effect of the PDC on the total power dissipation within the gate driver can be safely assumed to
be negligible. The power dissipated in the gate-driver package during switching (PSW) depends on the following
factors:
• Gate charge required of the power device (usually a function of the drive voltage VG, which is very close to
input bias supply voltage VDD)
• Switching frequency
• Use of external gate resistors. When a driver device is tested with a discrete, capacitive load calculating the
power that is required from the bias supply is fairly simple. The energy that must be transferred from the bias
supply to charge the capacitor is given by Equation 2.
EG = ½CLOADVDD² fSW
where
• CLOAD is load capacitor
• VDD is bias voltage feeding the driver (2)
There is an equal amount of energy dissipated when the capacitor is charged. This leads to a total power loss
given by Equation 3.
PG = CLOADVDD² fSW
where
• fSW is the switching frequency (3)
The switching load presented by a power MOSFET/IGBT is converted to an equivalent capacitance by examining
the gate charge required to switch the device. This gate charge includes the effects of the input capacitance plus
the added charge needed to swing the drain voltage of the power device as it switches between the ON and OFF
states. Most manufacturers provide specifications of typical and maximum gate charge, in nC, to switch the
device under specified conditions. Using the gate charge Qg, determine the power that must be dissipated when
charging a capacitor which is calculated using the equation QG = CLOAD x VDD to provide Equation 4 for power.
PG = CLOADVDD² fSW = QGVDDfSW (4)
This power PG is dissipated in the resistive elements of the circuit when the MOSFET/IGBT is being turned on or
off. Half of the total power is dissipated when the load capacitor is charged during turnon, and the other half is
dissipated when the load capacitor is discharged during turnoff. When no external gate resistor is employed
between the driver and MOSFET/IGBT, this power is completely dissipated inside the driver package. With the
use of external gate-drive resistors, the power dissipation is shared between the internal resistance of driver and
external gate resistor.

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9.2.3 Application Curves

Figure 21. Negative 10-V Input Figure 22. Step Input

Figure 23. Symmetrical UVLO

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10 Power Supply Recommendations

The bias supply voltage range for which the UCC27210 and UCC27211 device is rated to operate is from 8 V to
17 V. The lower end of this range is governed by the internal undervoltage-lockout (UVLO) protection feature on
the VDD pin supply circuit blocks. Whenever the driver is in UVLO condition when the VDD pin voltage is below
the V(ON) supply start threshold, this feature holds the output low, regardless of the status of the inputs. The
upper end of this range is driven by the 20-V absolute maximum voltage rating of the VDD pin of the device
(which is a stress rating). Keeping a 3-V margin to allow for transient voltage spikes, the maximum
recommended voltage for the VDD pin is 17 V. The UVLO protection feature also involves a hysteresis function.
This means that when the VDD pin bias voltage has exceeded the threshold voltage and device begins to
operate, and if the voltage drops, then the device continues to deliver normal functionality unless the voltage
drop exceeds the hysteresis specification VDD(hys).Therefore, ensuring that, while operating at or near the 8-V
range, the voltage ripple on the auxiliary power supply output is smaller than the hysteresis specification of the
device is important to avoid triggering device shutdown. During system shutdown, the device operation continues
until the VDD pin voltage has dropped below the V(OFF) threshold which must be accounted for while evaluating
system shutdown timing design requirements. Likewise, at system startup, the device does not begin operation
until the VDD pin voltage has exceeded above the V(ON) threshold. The quiescent current consumed by the
internal circuit blocks of the device is supplied through the VDD pin. Although this fact is well known, recognizing
that the charge for source current pulses delivered by the HO pin is also supplied through the same VDD pin is
important. As a result, every time a current is sourced out of the HO pin a corresponding current pulse is
delivered into the device through the VDD pin. Thus ensuring that a local bypass capacitor is provided between
the VDD and GND pins and located as close to the device as possible for the purpose of decoupling is important.
A low ESR, ceramic surface mount capacitor is a must. TI recommends using a capacitor in the range 0.22 uF to
4.7 uF between VDD and GND. In a similar manner, the current pulses delivered by the LO pin are sourced from
the HB pin. Therefore a 0.022-uF to 0.1-uF local decoupling capacitor is recommended between the HB and HS
pins.

11 Layout

11.1 Layout Guidelines

To improve the switching characteristics and efficiency of a design, the following layout rules should be followed.
• Locate the driver as close as possible to the MOSFETs.
• Locate the VDD-VSS and VHB-VHS (bootstrap) capacitors as close as possible to the device (see Figure 24).
• Pay close attention to the GND trace. Use the thermal pad of the DDA and DRM package as GND by
connecting it to the VSS pin (GND). The GND trace from the driver goes directly to the source of the
MOSFET but should not be in the high current path of the MOSFET(S) drain or source current.
• Use similar rules for the HS node as for GND for the high-side driver.
• For systems using multiple UCC27210 and UCC27211 devices we recommend that dedicated decoupling
capacitors be located at VDD-VSS for each device.
• Care should be taken to avoid VDD traces being close to LO, HS, and HO signals.
• Use wide traces for LO and HO closely following the associated GND or HS traces. 60 to 100-mils width is
preferable where possible.
• Use as least two or more vias if the driver outputs or SW node must be routed from one layer to another. For
GND the number of vias must be a consideration of the thermal pad requirements as well as parasitic
inductance.
• Avoid LI and HI (driver input) going close to the HS node or any other high dV/dT traces that can induce
significant noise into the relatively high impedance leads.
Keep in mind that a poor layout can cause a significant drop in efficiency or system malfunction versus a good
PCB layout and can even lead to decreased reliability of the whole system.

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11.2 Layout Example

Figure 24. UCC27210/11 Component Placement

11.3 Thermal Considerations

The useful range of a driver is greatly affected by the drive-power requirements of the load and the thermal
characteristics of the package. In order for a gate driver to be useful over a particular temperature range the
package must allow for the efficient removal of the heat produced while keeping the junction temperature within
rated limits. The thermal metrics for the driver package is listed in Device Functional Modes. For detailed
information regarding the table, please refer to the Application Note from Texas Instruments entitled IC Package
Thermal Metrics (SPRA953). The UCC27210 and UCC27211 devices are offered in SOIC (8), PowerPad (8),
WSON (10) or VSON (8). The Thermal Information section lists the thermal performance metrics related to SOT-
23 package.

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation
These references and links to additional information may be found at www.ti.com
• Additional layout guidelines for PCB land patterns may be found in, QFN/SON PCB Attachment, Application
Brief (SLUA271)
• Additional thermal performance guidelines may be found in, PowerPAD™ Thermally Enhanced Package
Application Report, Application Report (SLMA002)
• Additional thermal performance guidelines may be found in, PowerPAD™ Made Easy, Application Report
(SLMA004)

12.2 Related Links

The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.

Table 4. Related Links

TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY
DOCUMENTS SOFTWARE COMMUNITY
UCC27210 Click here Click here Click here Click here Click here
UCC27211 Click here Click here Click here Click here Click here

12.3 Trademarks
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

UCC27210D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 140 27210

UCC27210DDA ACTIVE SO PowerPAD DDA 8 75 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 140 27210

UCC27210DDAR ACTIVE SO PowerPAD DDA 8 2500 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 140 27210

UCC27210DPRR ACTIVE WSON DPR 10 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 140 UCC
27210
UCC27210DPRT ACTIVE WSON DPR 10 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 140 UCC
27210
UCC27210DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 140 27210

UCC27210DRMR ACTIVE VSON DRM 8 3000 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 140 27210

UCC27210DRMT ACTIVE VSON DRM 8 250 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 140 27210

UCC27211D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 140 27211

UCC27211DDA ACTIVE SO PowerPAD DDA 8 75 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 140 27211

UCC27211DDAR ACTIVE SO PowerPAD DDA 8 2500 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 140 27211

UCC27211DPRR ACTIVE WSON DPR 10 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 140 UCC
27211
UCC27211DPRT ACTIVE WSON DPR 10 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 140 UCC
27211
UCC27211DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 140 27211

UCC27211DRMR ACTIVE VSON DRM 8 3000 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 140 27211

UCC27211DRMT ACTIVE VSON DRM 8 250 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 140 27211

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 18-Nov-2020

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
UCC27210DDAR SO DDA 8 2500 330.0 12.8 6.4 5.2 2.1 8.0 12.0 Q1
Power
PAD
UCC27210DPRR WSON DPR 10 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
UCC27210DPRT WSON DPR 10 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
UCC27210DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
UCC27210DRMR VSON DRM 8 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
UCC27210DRMT VSON DRM 8 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
UCC27211DDAR SO DDA 8 2500 330.0 12.8 6.4 5.2 2.1 8.0 12.0 Q1
Power
PAD
UCC27211DPRR WSON DPR 10 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
UCC27211DPRT WSON DPR 10 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
UCC27211DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
UCC27211DRMR VSON DRM 8 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
UCC27211DRMT VSON DRM 8 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 18-Nov-2020

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
UCC27210DDAR SO PowerPAD DDA 8 2500 364.0 364.0 27.0
UCC27210DPRR WSON DPR 10 3000 367.0 367.0 35.0
UCC27210DPRT WSON DPR 10 250 210.0 185.0 35.0
UCC27210DR SOIC D 8 2500 853.0 449.0 35.0
UCC27210DRMR VSON DRM 8 3000 853.0 449.0 35.0
UCC27210DRMT VSON DRM 8 250 210.0 185.0 35.0
UCC27211DDAR SO PowerPAD DDA 8 2500 364.0 364.0 27.0
UCC27211DPRR WSON DPR 10 3000 367.0 367.0 35.0
UCC27211DPRT WSON DPR 10 250 210.0 185.0 35.0
UCC27211DR SOIC D 8 2500 853.0 449.0 35.0
UCC27211DRMR VSON DRM 8 3000 853.0 449.0 35.0
UCC27211DRMT VSON DRM 8 250 210.0 185.0 35.0

Pack Materials-Page 2
 PACKAGE OUTLINE
DPR0010A SCALE 3.000
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

4.1 A
B
3.9

(0.2)

4.1
PIN 1 INDEX AREA 3.9 FULL R

BOTTOM VIEW SIDE VIEW

ALTERNATIVE LEAD
20.000

DETAIL

0.8
0.7
C

SEATING PLANE
0.05
0.00 0.08 C

EXPOSED
THERMAL PAD 2.6 0.1 (0.1) TYP
SEE ALTERNATIVE
LEAD DETAIL
5 6

2X
3.2 11
3 0.1

8X 0.8

1
10
0.35
10X
PIN 1 ID 0.5 0.25
10X
0.3 0.1 C A B
0.05 C
4218856/B 01/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com
 EXAMPLE BOARD LAYOUT
DPR0010A WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

(2.6)

10X (0.6) SYMM

1 10

10X (0.3)

(1.25)

SYMM 11
(3)

8X (0.8)

6
5
( 0.2) VIA (1.05)
(R0.05) TYP TYP

(3.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X

0.07 MIN
0.07 MAX
ALL AROUND
ALL AROUND

EXPOSED EXPOSED
METAL METAL

SOLDER MASK METAL METAL UNDER SOLDER MASK

OPENING EDGE SOLDER MASK OPENING

NON SOLDER MASK

DEFINED SOLDER MASK
(PREFERRED) DEFINED

SOLDER MASK DETAILS

4218856/B 01/2021

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).

www.ti.com
 EXAMPLE STENCIL DESIGN
DPR0010A WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

SYMM

10X (0.6)
METAL (0.68)
TYP
1 10

10X (0.3)

(0.76)
11 SYMM

8X (0.8)

4X
(1.31)

5 6

(R0.05) TYP 4X (1.15)

(3.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 11:

77% PRINTED SOLDER COVERAGE BY AREA
SCALE:20X

4218856/B 01/2021
NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
 GENERIC PACKAGE VIEW
DDA 8 PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE

Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4202561/G
 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

www.ti.com
 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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