135 MHz BW IF Diversity Receiver

Data Sheet AD6679

FEATURES APPLICATIONS
Parallel LVDS (DDR) outputs Diversity multiband, multimode digital receivers
In-band SFDR = 82 dBFS at 340 MHz (500 MSPS) 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE, LTE-A
In-band SNR = 67.8 dBFS at 340 MHz (500 MSPS) DOCSIS 3.0 CMTS upstream receive paths
1.1 W total power per channel at 500 MSPS (default settings) HFC digital reverse path receivers
Noise density = −153 dBFS/Hz at 500 MSPS
GENERAL DESCRIPTION
1.25 V, 2.50 V, and 3.3 V dc supply operation
Flexible input range The AD6679 is a 135 MHz bandwidth mixed-signal intermediate
1.46 V p-p to 2.06 V p-p (2.06 V p-p nominal) frequency (IF) receiver. It consists of two, 14-bit, 500 MSPS
95 dB channel isolation/crosstalk analog-to-digital converters (ADCs) and various digital signal
Amplitude detect bits for efficient automatic gain control processing blocks consisting of four wideband DDCs, an NSR,
(AGC) implementation and VDR monitoring. It has an on-chip buffer and a sample-and-
Noise shaping requantizer (NSR) option for main receiver hold circuit designed for low power, small size, and ease of use.
function This product is designed to support communications applications
Variable dynamic range (VDR) option for digital capable of sampling wide bandwidth analog signals of up to 2 GHz.
predistortion (DPD) function The AD6679 is optimized for wide input bandwidth, high sampling
2 integrated wideband digital processors per channel rates, excellent linearity, and low power in a small package.
12-bit numerically controlled oscillator (NCO), up to The dual ADC cores feature a multistage, differential pipelined
4 cascaded half-band filters architecture with integrated output error correction logic. Each
Differential clock inputs ADC features wide bandwidth inputs supporting a variety of
Integer clock divide by 1, 2, 4, or 8 user-selectable input ranges. An integrated voltage reference
Energy saving power-down modes eases design considerations.
Small signal dither

FUNCTIONAL BLOCK DIAGRAM

AVDD1 AVDD2 AVDD3 DVDD DRVDD SPIVDD
(1.25V) (2.50V) (3.3V) (1.25V) (1.25V) (1.22V TO 3.4V)

BUFFER
VIN+A
SIGNAL PROCESSING D0±
ADC D1±
VIN–A D2±
D3±
DIGITAL DOWN- D4±
CONVERSION D5±
FD_A (×4) 16 D6±
FAST SIGNAL D7±
DETECT MONITOR DATA LVDS D8±
OUTPUT LVDS D9±
FD_B ROUTER NOISE SHAPING OUTPUTS
MUX STAGING D10±
REQUANTIZER D11±
(×2) D12±
V_1P0 D13±
DCO±
BUFFER VARIABLE STATUS±
VIN+B DYNAMIC RANGE
ADC (×2)

VIN–B

FAST
CLOCK DETECT
CLK+ GENERATION
AND ADJUST AD6679
CLK–
÷2
SPI CONTROL SIGNAL PDWN/STBY
÷4 MONITOR

÷8
13059-001

AGND SYNC± SDIO SCLK CSB DGND DRGND

Figure 1.

Rev. B Document Feedback

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AD6679 Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1 General Description ................................................................... 46
Applications ....................................................................................... 1 DDC NCO Plus Mixer Loss and SFDR ................................... 47
General Description ......................................................................... 1 Numerically Controlled Oscillator .......................................... 47
Functional Block Diagram .............................................................. 1 FIR Filters ........................................................................................ 49
Revision History ............................................................................... 3 Overview ..................................................................................... 49
Product Highlights ........................................................................... 4 Half-Band Filters ........................................................................ 49
Specifications..................................................................................... 5 DDC Gain Stage ......................................................................... 51
DC Specifications ......................................................................... 5 DDC Complex to Real Conversion ......................................... 51
AC Specifications.......................................................................... 6 DDC Example Configurations ................................................. 52
Digital Specifications ................................................................... 7 Noise Shaping Requantizer (NSR) ............................................... 56
Switching Specifications .............................................................. 8 Decimating Half-Band Filter .................................................... 56
Timing Specifications .................................................................. 9 NSR Overview ............................................................................ 56
Absolute Maximum Ratings .......................................................... 18 Variable Dynamic Range (VDR) .................................................. 59
Thermal Characteristics ............................................................ 18 VDR Real Mode.......................................................................... 60
ESD Caution ................................................................................ 18 VDR Complex Mode ................................................................. 60
Pin Configurations and Function Descriptions ......................... 19 Digital Outputs ............................................................................... 62
Typical Performance Characteristics ........................................... 25 Timing.......................................................................................... 62
Equivalent Circuits ......................................................................... 28 Data Clock Output ..................................................................... 62
Theory of Operation ...................................................................... 30 ADC Overrange .......................................................................... 62
ADC Architecture ...................................................................... 30 Multichip Synchronization............................................................ 64
Analog Input Considerations.................................................... 30 SYNC± Setup and Hold Window Monitor ............................. 65
Voltage Reference ....................................................................... 32 Test Modes ....................................................................................... 67
Clock Input Considerations ...................................................... 33 ADC Test Modes ........................................................................ 67
Power-Down/Standby Mode..................................................... 35 Serial Port Interface (SPI) .............................................................. 68
Temperature Diode .................................................................... 35 Configuration Using the SPI ..................................................... 68
Virtual Converter Mapping ........................................................... 36 Hardware Interface ..................................................................... 68
ADC Overrange and Fast Detect .................................................. 38 SPI Accessible Features .............................................................. 68
ADC Overrange (OR) ................................................................ 38 Memory Map .................................................................................. 69
Fast Threshold Detection (FD_A and FD_B) ........................ 38 Reading the Memory Map Register Table............................... 69
Signal Monitor ................................................................................ 39 Memory Map Register Table ..................................................... 70
Digital Downconverter (DDC) ..................................................... 40 Applications Information .............................................................. 80
DDC I/Q Input Selection .......................................................... 40 Power Supply Recommendations............................................. 80
DDC I/Q Output Selection ....................................................... 40 Outline Dimensions ....................................................................... 81
DDC General Description ........................................................ 40 Ordering Guide .......................................................................... 81
Frequency Translation ................................................................... 46

Rev. B | Page 2 of 81
Data Sheet AD6679
REVISION HISTORY
4/16—Rev. A to Rev. B 9/15—Rev. 0 to Rev. A
Changes to Table 4 ............................................................................ 8 Changes to General Description Section ....................................... 3
Changes to Table 5 and Figure 3 ..................................................... 9 Changes to Figure 12 ...................................................................... 18
Changes to Figure 4 Caption .........................................................10 Changes to Figure 13 ...................................................................... 20
Changes to Figure 5 Caption .........................................................11 Changes to Figure 14 ...................................................................... 22
Changes to Figure 6 Caption .........................................................12 Changes to ADC Test Modes......................................................... 63
Changes to Figure 7 Caption .........................................................13
Changes to Figure 8 Caption .........................................................14 5/15—Revision 0: Initial Version
Changes to Figure 10 ......................................................................16
Changes to Table 6 ..........................................................................18
Changes to Input Clock Divider Section .....................................34
Added Virtual Converter Mapping Section and Table 12;
Renumbered Sequentially ..............................................................36
Added Figure 60; Renumbered Sequentially ...............................37
Changes to Table 35 ........................................................................62
Changes to Datapath Soft Reset Section ......................................69
Changes to Table 41 ........................................................................70

Rev. B | Page 3 of 81
AD6679 Data Sheet
The analog input and clock signals are differential inputs. The incoming signal power using the fast detect control bits in
ADC data outputs are internally connected to four DDCs Register 0x245 of the ADC. If the input signal level exceeds the
through a crossbar mux. Each DDC consists of up to five programmable threshold, the fast detect indicator goes high.
cascaded signal processing stages: a 12-bit frequency translator Because this threshold indicator has low latency, the user can
(NCO) and up to four half-band decimation filters. quickly reduce the system gain to avoid an overrange condition
Each ADC output is connected internally to an NSR block. The at the ADC input. In addition to the fast detect outputs, the
integrated NSR circuitry allows improved SNR performance in AD6679 also offers signal monitoring capability. The signal
a smaller frequency band within the Nyquist bandwidth. The monitoring block provides additional information about the
device supports two different output modes, selectable via the signal that the ADC digitized.
serial port interface (SPI). With the NSR feature enabled, the The output data is routed directly to the one external
outputs of the ADCs are processed such that the AD6679 supports 14-bit LVDS output port, supporting double data rate (DDR)
enhanced SNR performance within a limited portion of the formatting. An external data clock and a clock status bit are offered
Nyquist bandwidth while maintaining a 9-bit output resolution. for data capture flexibility.
Each ADC output is also connected internally to a VDR block. The AD6679 has flexible power-down options that allow
This optional mode allows full dynamic range for defined input significant power savings when desired. All of these features can
signals. Inputs that are within a defined mask (based on DPD be programmed using a 1.8 V capable 3-wire SPI.
applications) pass unaltered. Inputs that violate this defined The AD6679 is available in a Pb-free, 196-ball BGA_ED, and is
mask result in the reduction of the output resolution. specified over the −40°C to +85°C industrial temperature range.
With VDR, the dynamic range of the observation receiver is
PRODUCT HIGHLIGHTS
determined by a defined input frequency mask. For signals
falling within the mask, the outputs are presented at the 1. Wide full power bandwidth IF sampling of signals up to
maximum resolution allowed. For signals exceeding defined 2 GHz.
power levels within this frequency mask, the output resolution 2. Buffered inputs with programmable input termination
is truncated. This mask is based on DPD applications and eases filter design and implementation.
supports tunable real IF sampling, and zero IF or complex IF 3. Four integrated wideband decimation filters and NCO
receive architectures. blocks support multiband receivers.
4. Flexible SPI controls various product features and
Operation of the AD6679 between the DDC, NSR, and VDR functions to meet specific system requirements.
modes is selectable via SPI-programmable profiles. 5. Programmable fast overrange detection and signal
In addition to the DDC blocks, the AD6679 has several functions monitoring.
that simplify the AGC function in a communications receiver. 6. Programmable fast overrange detection.
The programmable threshold detector allows monitoring of the 7. 12 mm × 12 mm, 196-ball BGA_ED.

Rev. B | Page 4 of 81
Data Sheet AD6679

SPECIFICATIONS
DC SPECIFICATIONS
AVDD1 = 1.25 V, AVDD2 = 2.50 V, AVDD3 = 3.3 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling
rate, 1.0 V internal reference (VREF), AIN = −1.0 dBFS, clock divider = 2, default SPI settings, unless otherwise noted.
Table 1.
Parameter Temperature Min Typ Max Unit
RESOLUTION 14 Bits
ACCURACY
No Missing Codes Full Guaranteed
Offset Error Full −0.3 0 +0.3 % FSR
Offset Matching Full 0 0.3 % FSR
Gain Error Full −6.5 0 +6.5 % FSR
Gain Matching Full 0 5.0 % FSR
Differential Nonlinearity (DNL) Full −0.6 ±0.5 +0.7 LSB
Integral Nonlinearity (INL) Full −4.5 ±2.5 +5.0 LSB
TEMPERATURE DRIFT
Offset Error Full ±3 ppm/°C
Gain Error Full −39 ppm/°C
INTERNAL VOLTAGE REFERENCE
Voltage Full 1.0 V
INPUT REFERRED NOISE
VREF = 1.0 V 25°C 2.04 LSB rms
ANALOG INPUTS
Differential Input Voltage Range (Internal VREF = 1.0 V) Full 1.46 2.06 2.06 V p-p
Common-Mode Voltage (VCM) Full 2.05 V
Differential Input Capacitance1 Full 1.5 pF
Analog Full Power Bandwidth Full 2 GHz
POWER SUPPLY
AVDD1 Full 1.22 1.25 1.28 V
AVDD2 Full 2.44 2.50 2.56 V
AVDD3 Full 3.2 3.3 3.4 V
DVDD Full 1.22 1.25 1.28 V
DRVDD Full 1.22 1.25 1.28 V
SPIVDD Full 1.22 1.8 3.4 V
IAVDD1 Full 464 503 mA
IAVDD2 Full 396 455 mA
IAVDD32 Full 89 100 mA
IDVDD (Default SPI—NSR Mode) Full 141 164 mA
IDVDD (VDR Mode) Full 117 138 mA
IDRVDD3 Full 110 123 mA
ISPIVDD Full 5 6 mA
POWER CONSUMPTION
Total Power Dissipation
Default SPI—NSR Mode3 Full 2.2 2.37 W
VDR Mode3 Full 2.16 2.34 W
Power-Down Dissipation Full 0.71 W
Standby4 Full 1.4 W
1
Differential capacitance is measured between the VIN+x and VIN−x pins (x = A, B).
2
AVDD3 current changes based on the Buffer Control 1 setting (see Figure 46).
3
Parallel interleaved LVDS mode. The power dissipation on DRVDD changes with the output data mode used.
4
Standby can be controlled by the SPI.

Rev. B | Page 5 of 81
AD6679 Data Sheet
AC SPECIFICATIONS
AVDD1 = 1.25 V, AVDD2 = 2.50 V, AVDD3 = 3.3 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling
rate, 1.0 V internal reference, AIN = −1.0 dBFS, clock divider = 2, default SPI settings, unless otherwise noted.

Table 2.
Parameter 1 Temperature Min Typ Max Unit
ANALOG INPUT FULL SCALE Full 2.06 V p-p
NOISE DENSITY 2 Full −153 dBFS/Hz
SIGNAL-TO-NOISE RATIO (SNR) 3
VDR Mode (Input Mask Not Triggered)
fIN = 10 MHz 25°C 68.9 dBFS
fIN = 170 MHz Full 67.5 68.6 dBFS
fIN = 340 MHz 25°C 67.8 dBFS
fIN = 450 MHz 25°C 67.3 dBFS
fIN = 765 MHz 25°C 63.9 dBFS
fIN = 985 MHz 25°C 62.8 dBFS
fIN = 1950 MHz 25°C 59.0 dBFS
NSR Enabled (21% Bandwidth (BW) Mode)
fIN = 10 MHz 25°C 75.0 dBFS
fIN = 170 MHz 25°C 74.8 dBFS
fIN = 340 MHz 25°C 74.0 dBFS
fIN = 450 MHz 25°C 73.1 dBFS
fIN = 765 MHz 25°C 69.7 dBFS
fIN = 985 MHz 25°C 68.1 dBFS
fIN = 1950 MHz 25°C 64.6 dBFS
NSR Enabled (28% BW Mode)
fIN = 10 MHz 25°C 72.4 dBFS
fIN = 170 MHz 25°C 72.3 dBFS
fIN = 340 MHz 25°C 71.6 dBFS
fIN = 450 MHz 25°C 71.0 dBFS
fIN = 765 MHz 25°C 67.7 dBFS
fIN = 985 MHz 25°C 66.8 dBFS
fIN = 1950 MHz 25°C 63.1 dBFS
SIGNAL-TO-NOISE-AND-DISTORTION RATIO (SINAD)3
VDR Mode (Input Mask Not Triggered)
fIN = 10 MHz 25°C 68.7 dBFS
fIN = 170 MHz Full 67 68.5 dBFS
fIN = 340 MHz 25°C 67.6 dBFS
fIN = 450 MHz 25°C 67.2 dBFS
fIN = 765 MHz 25°C 63.8 dBFS
fIN = 985 MHz 25°C 62.5 dBFS
fIN = 1950 MHz 25°C 58.3 dBFS
EFFECTIVE NUMBER OF BITS (ENOB)3
VDR Mode (Input Mask Not Triggered)
fIN = 10 MHz 25°C 11.1 Bits
fIN = 170 MHz Full 10.8 10.9 Bits
fIN = 340 MHz 25°C 10.8 Bits
fIN = 450 MHz 25°C 10.8 Bits
fIN = 765 MHz 25°C 10.3 Bits
fIN = 985 MHz 25°C 10.1 Bits
fIN = 1950 MHz 25°C 9.5 Bits

Rev. B | Page 6 of 81
Data Sheet AD6679
Parameter 1 Temperature Min Typ Max Unit
SPURIOUS FREE DYNAMIC RANGE (SFDR), SECOND OR THIRD HARMONIC3
VDR Mode (Input Mask Not Triggered)
fIN = 10 MHz 25°C 83 dBFS
fIN = 170 MHz Full 76 85 dBFS
fIN = 340 MHz 25°C 82 dBFS
fIN = 450 MHz 25°C 86 dBFS
fIN = 765 MHz 25°C 81 dBFS
fIN = 985 MHz 25°C 76 dBFS
fIN = 1950 MHz 25°C 69 dBFS
WORST OTHER (EXCLUDING SECOND OR THIRD HARMONIC)3
VDR Mode (Input Mask Not Triggered)
fIN = 10 MHz 25°C −93 dBFS
fIN = 170 MHz Full −94 dBFS
fIN = 340 MHz 25°C −90 dBFS
fIN = 450 MHz 25°C −92 dBFS
fIN = 765 MHz 25°C −89 dBFS
fIN = 985 MHz 25°C −89 dBFS
fIN = 1950 MHz 25°C −85 dBFS
TWO-TONE INTERMODULATION DISTORTION (IMD)3, AIN1 AND AIN2 = −7.0 dBFS
fIN1 = 185 MHz, fIN2 = 188 MHz 25°C −88 dBFS
fIN1 = 338 MHz, fIN2 = 341 MHz 25°C −87 dBFS
CROSSTALK 4 25°C 95 dB
FULL POWER BANDWIDTH 25°C 2 GHz
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
2
Noise density is measured at a low analog input frequency (30 MHz).
3
See Table 11 for the recommended settings for full-scale voltage and buffer control settings.
4
Crosstalk is measured at 185 MHz with a −1.0 dBFS analog input on one channel and no input on the adjacent channel.

DIGITAL SPECIFICATIONS
AVDD1 = 1.25 V, AVDD2 = 2.50 V, AVDD3 = 3.3 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling
rate, 1.0 V internal reference, AIN = −1.0 dBFS, clock divider = 2, default SPI settings, unless otherwise noted.

Table 3.
Parameter Temperature Min Typ Max Unit
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance Full LVDS/LVPECL
Differential Input Voltage Full 600 1200 1800 mV p-p
Input Common-Mode Voltage Full 0.85 V
Input Resistance (Differential) Full 35 kΩ
Input Capacitance Full 2.5 pF
SYSTEM REFERENCE INPUTS (SYNC+, SYNC−)
Logic Compliance Full LVDS/LVPECL
Differential Input Voltage Full 400 1200 1800 mV p-p
Input Common-Mode Voltage Full 0.6 0.85 2.0 V
Input Resistance (Differential) Full 35 kΩ
Input Capacitance (Differential) Full 2.5 pF
LOGIC INPUTS (SDIO, SCLK, CSB, PDWN/STBY)
Logic Compliance Full CMOS
Logic 1 Voltage Full 0.8 × SPIVDD V
Logic 0 Voltage Full 0 0.2 × SPIVDD V
Input Resistance Full 30 kΩ

Rev. B | Page 7 of 81
AD6679 Data Sheet
Parameter Temperature Min Typ Max Unit
LOGIC OUTPUT (SDIO)
Logic Compliance Full CMOS
Logic 1 Voltage (IOH = 800 µA) Full 0.8 × SPIVDD V
Logic 0 Voltage (IOL = 50 µA) Full 0.2 × SPIVDD V
LOGIC OUTPUTS (FD_A, FD_B)
Logic Compliance Full CMOS
Logic 1 Voltage Full 0.8 SPIVDD V
Logic 0 Voltage Full 0 0 V
Input Resistance Full 30 kΩ
DIGITAL OUTPUTS (D0± to D13±, A Dx/Dy± and B Dx/Dy±,
DATA0± to DATA7±, DCO±, OVR±, FCO±, and STATUS±)
Logic Compliance Full LVDS
ANSI Mode
Differential Output Voltage (VOD) Full 230 350 430 mV
Output Offset Voltage (VOS) Full 0.58 0.70 0.85 V
Reduced Swing Mode
Differential Output Voltage (VOD) Full 120 200 235 mV
Output Offset Voltage (VOS) Full 0.59 0.70 0.83 V

SWITCHING SPECIFICATIONS
AVDD1 = 1.25 V, AVDD2 = 2.50 V, AVDD3 = 3.3 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling
rate, 1.0 V internal reference, AIN = −1.0 dBFS, clock divider = 2, default SPI settings, unless otherwise noted.

Table 4.
Parameter Temperature Min Typ Max Unit
CLOCK
Clock Rate (at CLK+/CLK− Pins) Full 0.3 4 GHz
Sample Rate
Maximum 1 Full 500 MSPS
Minimum 2 Full 250 MSPS
Clock Pulse Width
High Full 1000 ps
Low Full 1000 ps
LVDS DATA OUTPUT
Data Propagation Delay (tPD) 3 Full 2.225 ns
DCO± Propagation Delay (tDCO)3 Full 2.2 ns
DCO± to Data Skew—Rising Edge Data (tSKEWR)3 Full −150 −25 +100 ps
DCO± to Data Skew—Falling Edge Data (tSKEWF)3 Full −150 −25 +100 ps
DCO± and Data Duty Cycle Full 44 50 56 %
FCO± Propagation Delay (tFCO) 4 Full 2.2 ns
DCO± to FCO± Skew (tFRAME)4 Full −150 −25 +100 ps
DCO Output Frequency Full 500 MHz
Output Date Rate Full 1000 Mbps
LATENCY
Pipeline Latency Full 33 Clock cycles
NSR Latency 5 Full 8 Clock cycles
NSR HB Filter Latency5 Full 24 Clock cycles
VDR Latency5 Full 8 Clock cycles
HB1 Filter Latency5 Full 50 Clock cycles
HB1 + HB2 Filter Latency5 Full 101 Clock cycles
HB1 + HB2 + HB3 Filter Latency5 Full 217 Clock cycles
HB1 + HB2 + HB3 + HB4 Filter Latency5 Full 433 Clock cycles
Fast Detect Latency Full 28 Clock cycles
Rev. B | Page 8 of 81
Data Sheet AD6679
Parameter Temperature Min Typ Max Unit
Wake-Up Time 6
Standby 25°C 1 ms
Power-Down6 25°C 4 ms
APERTURE
Aperture Delay (tA) Full 530 ps
Aperture Uncertainty (Jitter, tJ) Full 55 fs rms
Out of Range Recovery Time Full 1 Clock cycles
1
The maximum sample rate is the clock rate after the divider.
2
The minimum sample rate operates at 300 MSPS with L = 2 or L = 1.
3
This specification is valid for parallel interleaved, channel multiplexed, and byte mode output modes.
4
This specification is valid for byte mode output mode only.
5
Add this value to the pipeline latency specification to achieve total latency through the AD6679.
6
Wake-up time is defined as the time required to return to normal operation from power-down mode or standby mode.

TIMING SPECIFICATIONS
Table 5.
Parameter Test Conditions/Comments Min Typ Max Unit
CLK± to SYNC± TIMING REQUIREMENTS
tSU_SR Device clock to SYNC± setup time 117 ps
tH_SR Device clock to SYNC± hold time −96 ps
SPI TIMING REQUIREMENTS See Figure 3
tDS Setup time between the data and the rising edge of SCLK 2 ns
tDH Hold time between the data and the rising edge of SCLK 2 ns
tCLK Period of the SCLK 40 ns
tS Setup time between CSB and SCLK 2 ns
tH Hold time between CSB and SCLK 2 ns
tHIGH Minimum period that SCLK is in a logic high state 10 ns
tLOW Minimum period that SCLK is in a logic low state 10 ns
tACCESS Maximum time delay between falling edge of SCLK and output 6 10 ns
data valid for a read operation
tDIS_SDIO Time required for the SDIO pin to switch from an output to an 10 ns
input relative to the SCLK rising edge (not shown in Figure 3)

Timing Diagrams
CLK–

CLK+

tSU_SR tH_SR
SYNC–
13059-002
SYNC+

Figure 2. SYNC± Setup and Hold Timing

tDS tHIGH tCLK tACCESS tH

tS tDH tLOW

CSB

SCLK DON’T CARE DON’T CARE

13059-003

SDIO DON’T CARE R/W A14 A13 A12 A11 A10 A9 A8 A7 D7 D6 D3 D2 D1 D0 DON’T CARE

Figure 3. Serial Port Interface Timing Diagram

Rev. B | Page 9 of 81
AD6679 Data Sheet
APERTURE DELAY
N N + 33 N + 34 N + 37
N + 38
VIN±x N–1
N+x N + 35
N+y
N + 36 N + 39
SYNCHRONOUS LOW TO HIGH TRANSITION OF THE SYNC SIGNAL CAPTURED ON THE RISING EDGE OF
THE CLK SIGNAL CAUSES THE DCO INTERNAL DIVIDER TO BE RESET
SYNC+

SYNC–
CLK+

CLK–
tCLK
tCH FIXED DELAY FROM SYNC EVENT TO DCO KNOWN PHASE
tDCO 2 × tCLK
tPD

DCO± (DATA CLOCK OUTPUT)

0° PHASE ADJUST

DCO± ((DATA CLOCK OUTPUT)

90° PHASE ADJUST 1

DCO± (DATA CLOCK OUTPUT)

180° PHASE ADJUST

DCO± (DATA CLOCK OUTPUT)

270° PHASE ADJUST 2

tSKEWR tSKEWF
STATUS BIT SELECTED BY
OUTPUT MODE CONTROL 1 BITS, REGISTER 0x559[2:0] CONVERTER 0 CONVERTER 0 CONVERTER 0 CONVERTER 0 CONVERTER 0
IN THE REGISTER MAP SAMPLE SAMPLE SAMPLE SAMPLE SAMPLE
[N] [N + 1] [N + 2] [N + 3] [N + 4]
OVR+
(OVERRANGE/STATUS BIT)
OVR OVR OVR OVR OVR OVR OVR
OVR–

D13± D13 D13 D13 D13 D13 D13 D13

D0± D0 D0 D0 D0 D0 D0 D0

13059-004
190° PHASE ADJUST IS GENERATED USING THE FALLING EDGE OF CLK±.
2270° PHASE ADJUST IS GENERATED USING THE FALLING EDGE OF CLK±.

Figure 4. Parallel Interleaved Mode—One Virtual Converter (Decimate by 1)

Rev. B | Page 10 of 81
Data Sheet AD6679
APERTURE DELAY
N N + 33 N + 35
VIN±x

N+x
N + 34

SYNCHRONOUS LOW TO HIGH TRANSITION OF THE SYNC SIGNAL CAPTURED ON THE RISING EDGE OF
THE CLK SIGNAL CAUSES THE DCO INTERNAL DIVIDER TO BE RESET
SYNC+

SYNC–

CLK+

CLK–

tDCO tCLK tCH

tPD

DCO± (DATA CLOCK OUTPUT)

0° PHASE ADJUST

DCO± (DATA CLOCK OUTPUT)

180° PHASE ADJUST
tSKEWR
STATUS BIT SELECTED BY tSKEWF
OUTPUT MODE CONTROL 1 BITS, REGISTER 0x559[2:0]
IN THE REGISTER MAP CONVERTER 0 CONVERTER 1 CONVERTER 0 CONVERTER 1 CONVERTER 0
SAMPLE SAMPLE SAMPLE SAMPLE SAMPLE
[N] [N] [N + 1] [N + 1] [N + 2]
OVR+
(OVERRANGE/STATUS BIT)
OVR OVR OVR OVR OVR OVR OVR OVR
OVR–

D13± D13 D13 D13 D13 D13 D13 D13 D13

13059-005
D0± D0 D0 D0 D0 D0 D0 D0 D0

Figure 5. Parallel Interleaved Mode—Two Virtual Converters (Decimate by 1)

Rev. B | Page 11 of 81
AD6679 Data Sheet
APERTURE DELAY
N N + 33 N + 35
VIN±x

N+x
N + 34

SYNCHRONOUS LOW TO HIGH TRANSITION OF THE SYSREF SIGNAL CAPTURED ON THE RISING EDGE OF
THE CLK SIGNAL CAUSES THE DCO INTERNAL DIVIDER TO BE RESET
SYNC+

SYNC–

CLK+

CLK–

tDCO tCLK tCH

tPD

DCO± (DATA CLOCK OUTPUT)

0° PHASE ADJUST

DCO± (DATA CLOCK OUTPUT)

180° PHASE ADJUST
tSKEWR
STATUS BIT SELECTED BY tSKEWF
OUTPUT MODE CONTROL 1 BITS, REGISTER 0x559[2:0]
IN THE REGISTER MAP CONVERTERS CONVERTERS CONVERTERS CONVERTERS CONVERTERS
SAMPLE SAMPLE SAMPLE SAMPLE SAMPLE
[N] [N] [N + 1] [N + 1] [N + 2]
OVR+
(OVERRANGE/STAUS BIT)
OVR OVR OVR OVR OVR OVR OVR OVR
OVR–

A D12/D13±

13059-006
S[N – y] S[N – x] S[N – 1] S[N] S[N] S[N + 1] S[N + 1] S[N + 2]
(ODD BITS) (EVEN BITS) (ODD BITS) (EVEN BITS) (ODD BITS) (EVEN BITS) (ODD BITS) (EVEN BITS)
A D0/D1±

Figure 6. Channel Multiplexed (Even/Odd) Mode—One Virtual Converter (Decimate by 1)

Rev. B | Page 12 of 81
Data Sheet AD6679
APERTURE DELAY
N N + 33 N + 35
VIN±x

N+x
N + 34

SYNCHRONOUS LOW TO HIGH TRANSITION OF THE SYNC SIGNAL CAPTURED ON THE RISING EDGE OF
THE CLK SIGNAL CAUSES THE DCO INTERNAL DIVIDER TO BE RESET
SYNC+

SYNC–

CLK+

CLK–

tDCO tCLK tCH

tPD

DCO± (DATA CLOCK OUTPUT)

0° PHASE ADJUST

DCO± (DATA CLOCK OUTPUT)

180° PHASE ADJUST
tSKEWR
STATUS BIT SELECTED BY tSKEWF
OUTPUT MODE CONTROL 1 BITS, REGISTER 0x559[2:0]
IN THE REGISTER MAP CONVERTERS CONVERTERS CONVERTERS CONVERTERS CONVERTERS
SAMPLE SAMPLE SAMPLE SAMPLE SAMPLE
[N] [N] [N + 1] [N + 1] [N + 2]
OVR+
(OVERRANGE/STATUS BIT)
OVR OVR OVR OVR OVR OVR OVR OVR
OVR–
A D12/D13±
S[N – y] S[N – x] S[N – 1] S[N] S[N] S[N + 1] S[N + 1] S[N + 2]
(ODD BITS) (EVEN BITS) (ODD BITS) (EVEN BITS) (ODD BITS) (EVEN BITS) (ODD BITS) (EVEN BITS)
A D0/D1±

B D12/D13±
S[N – y] S[N – x] S[N – 1] S[N] S[N] S[N + 1] S[N + 1] S[N + 2]

13059-007
(ODD BITS) (EVEN BITS) (ODD BITS) (EVEN BITS) (ODD BITS) (EVEN BITS) (ODD BITS) (EVEN BITS)
B D0/D1±

Figure 7. Channel Multiplexed (Even/Odd) Mode—Two Virtual Converters (Decimate by 1)

Rev. B | Page 13 of 81
AD6679 Data Sheet
APERTURE DELAY
N+z N + 33 N + 36
N N + 37
N + 39
VIN±x
N–1 N+x N + 34
N+y N + 35 N + 38
SYNCHRONOUS LOW TO HIGH TRANSITION OF THE SYNC SIGNAL CAPTURED ON THE RISING EDGE OF
THE CLK SIGNAL CAUSES THE DCO/FCO DIVIDERS TO BE RESET

SYNC+

SYNC–
CLK+

CLK– tCLK
tCH FIXED DELAY FROM SYNC EVENT
TO DCO KNOWN PHASE
tDCO 2 × tCLK
tPD
tFCO

DCO± (DATA CLOCK OUTPUT)

0° PHASE ADJUST

DCO± (DATA CLOCK OUTPUT)

90° PHASE ADJUST 1

DCO± (DATA CLOCK OUTPUT)

180° PHASE ADJUST

DCO± (DATA CLOCK OUTPUT)

270° PHASE ADJUST 2
tFRAME
tSKEWR tSKEWF
FCO–
(FRAME CLOCK OUTPUT)3 FRAME 0 FRAME 1 FRAME 2 FRAME 3
FCO+
I0[N] I0[N] I1[N] I1[N] I2[N + 1] I2[N + 1] I3[N + 1] I3[N + 1]
EVEN ODD EVEN ODD EVEN ODD EVEN ODD

STATUS+
(OVERRANGE STATUS BIT) PAR4 PAR OVR PAR OVR PAR OVR PAR OVR PAR
STATUS–

DATA7± D15 D15 D14 D15 D14 D15 D14 D15 D14 D15

DATA0± D1 D1 D0 D1 D0 D1 D0 D1 D0 D1

190° PHASE ADJUST IS GENERATED USING THE FALLING EDGE OF CLK±.

2270° PHASE ADJUST IS GENERATED USING THE FALLING EDGE OF CLK±.
3FRAME CLOCK OUTPUT SUPPORTS THREE MODES OF OPERATION:
1) ENABLED (ALWAYS ON)

13059-100
2) DISABLED (ALWAYS OFF)
3) GAPPED PERIODIC (CONDITIONALLY ENABLED BASED ON PSEUDORANDOM BIT)
4STATUS BIT SELECTED BY THE OUTPUT MODE CONTROL 1 BITS, REGISTER 0x559[2:0] IN THE REGISTER MAP.

Figure 8. LVDS Byte Mode—One Virtual Converter, One DDC (I Only, Decimate by 2)

Rev. B | Page 14 of 81
Data Sheet AD6679
APERTURE DELAY
N+z N + 33 N + 36
N N + 37
N + 39
VIN±x
N–1 N+x N + 34
N+y N + 35 N + 38
SYNCHRONOUS LOW TO HIGH TRANSITION OF THE SYNC SIGNAL CAPTURED ON THE RISING EDGE OF
THE CLK SIGNAL CAUSES THE DCO/FCO DIVIDERS TO BE RESET

SYNC+

SYNC–
CLK+

CLK– tCLK
tCH FIXED DELAY FROM SYNC EVENT
TO DCO KNOWN PHASE
tDCO 2 × tCLK
tPD
tFCO

DCO± (DATA CLOCK OUTPUT)

0° PHASE ADJUST

DCO± (DATA CLOCK OUTPUT)

90° PHASE ADJUST 1

DCO± (DATA CLOCK OUTPUT)

180° PHASE ADJUST

DCO± (DATA CLOCK OUTPUT)

270° PHASE ADJUST 2
tFRAME
FCO–
(FRAME CLOCK OUTPUT)3 FRAME 0 FRAME 1
FCO+
tSKEWR tSKEWF
I0[N] I0[N] Q 0[N] Q 0[N] I0[N + 1] I0[N + 1] Q 0[N + 1] Q 0[N + 1]
EVEN ODD EVEN ODD EVEN ODD EVEN ODD

STATUS+
(OVERRANGE STATUS BIT) PAR 4 PAR OVR PAR OVR PAR OVR PAR OVR PAR
STATUS–

DATA7± D15 D15 D14 D15 D14 D15 D14 D15 D14 D15

DATA0± D1 D1 D0 D1 D0 D1 D0 D1 D0 D1

190° PHASE ADJUST IS GENERATED USING THE FALLING EDGE OF CLK±.

2270° PHASE ADJUST IS GENERATED USING THE FALLING EDGE OF CLK±.
3FRAME CLOCK OUTPUT SUPPORTS THREE MODES OF OPERATION:
1) ENABLED (ALWAYS ON)

13059-008
2) DISABLED (ALWAYS OFF)
3) GAPPED PERIODIC (CONDITIONALLY ENABLED BASED ON PSEUDORANDOM BIT)
4STATUS BIT SELECTED BY THE OUTPUT MODE CONTROL 1 BITS, REGISTER 0x559[2:0] IN THE REGISTER MAP.

Figure 9. LVDS Byte Mode—Two Virtual Converters, One DDC (I/Q Decimate by 4)

Rev. B | Page 15 of 81
 AD6679

APERTURE DELAY
N+z N + 33 N + 36
N N + 37
N + 39
VIN±x
N–1 N+x N + 34
N+y N + 35 N + 38
SYNCHRONOUS LOW TO HIGH TRANSITION OF THE SYNC SIGNAL CAPTURED ON THE RISING EDGE OF THE CLK SIGNAL CAUSES THE DCO/FCO DIVIDERS TO BE RESET
SYNC+

SYNC–
CLK+

CLK– tCLK
tCH FIXED DELAY FROM SYNC EVENT TO DCO KNOWN PHASE
tDCO 2 × tCLK
tPD
tFCO FRAME 0 FRAME 1
DCO± (DATA CLOCK OUTPUT)
0° PHASE ADJUST

DCO± (DATA CLOCK OUTPUT)

90° PHASE ADJUST 1

DCO± (DATA CLOCK OUTPUT)

180° PHASE ADJUST

DCO± (DATA CLOCK OUTPUT)

270° PHASE ADJUST 2
FCO–
(FRAME CLOCK OUTPUT)3 FRAME 0 FRAME 1

Rev. B | Page 16 of 81
FCO+
tFRAME
tSKEWR tSKEWF
I0[N] I0[N] Q0[N] Q0[N] I1[N] I1[N] Q1[N] Q1[N] I0[N+1] I0[N+1] Q0[N+1] Q0[N+1] I1[N + 1] I1[N+1] Q1[N+1] Q1[N+1]
EVEN ODD EVEN ODD EVEN ODD EVEN ODD EVEN ODD EVEN ODD EVEN ODD EVEN ODD
STATUS+
(OVERRANGE STATUS BIT) PAR4 PAR OVR PAR OVR PAR OVR PAR OVR PAR OVR PAR OVR PAR OVR PAR OVR PAR
STATUS–

DATA7± D15 D15 D14 D15 D14 D15 D14 D15 D14 D15 D14 D15 D14 D15 D14 D15 D14 D15

Figure 10. LVDS Byte Mode—Four Virtual Converters, Two DDCs (I/Q Decimate by 8)
DATA0± D1 D1 D0 D1 D0 D1 D0 D1 D0 D1 D0 D1 D0 D1 D0 D1 D0 D1

190° PHASE ADJUST IS GENERATED USING THE FALLING EDGE OF CLK±.

2270° PHASE ADJUST IS GENERATED USING THE FALLING EDGE OF CLK±.
3FRAME CLOCK OUTPUT SUPPORTS THREE MODES OF OPERATION:
1) ENABLED (ALWAYS ON)
2) DISABLED (ALWAYS OFF)
13059-009

3) GAPPED PERIODIC (CONDITIONALLY ENABLED BASED ON PSEUDO-RANDOM BIT)

4STATUS BIT SELECTED BY OUTPUT MODE CONTROL 1 BITS, REGISTER 0x559[2:0] IN THE REGISTER MAP.
Data Sheet
 Data Sheet

APERTURE DELAY
N+z N + 33 N + 36
N N + 37
N + 39
VIN±x
N–1 N+x N + 34
N+y N + 35 N + 38
SYNCHRONOUS LOW TO HIGH TRANSITION OF THE SYNC SIGNAL CAPTURED ON THE RISING EDGE OF THE CLK SIGNAL CAUSES THE DCO/FCO DIVIDERS TO BE RESET
SYNC+

SYNC–
CLK+

CLK– tCLK
tCH FIXED DELAY FROM SYSNC EVENT TO DCO KNOWN PHASE
tDCO 2 × tCLK
tPD
tFCO FRAME 0
DCO± (DATA CLOCK OUTPUT)
0° PHASE ADJUST

DCO± (DATA CLOCK OUTPUT)

90° PHASE ADJUST 1

DCO± (DATA CLOCK OUTPUT)

180° PHASE ADJUST

DCO± (DATA CLOCK OUTPUT)

270° PHASE ADJUST 2
FCO–
(FRAME CLOCK OUTPUT) 3 FRAME 0

Rev. B | Page 17 of 81
FCO+
tFRAME
tSKEWR tSKEWF
I0[N] I0[N] Q0[N] Q0[N] I1[N] I1[N] Q1[N] Q1[N] I2[N] I2[N] Q2[N] Q2[N] I3[N] I3[N] Q3[N] Q3[N]
EVEN ODD EVEN ODD EVEN ODD EVEN ODD EVEN ODD EVEN ODD EVEN ODD EVEN ODD
STATUS+
(OVERRANGE STATUS BIT) PAR 4 PAR OVR PAR OVR PAR OVR PAR OVR PAR OVR PAR OVR PAR OVR PAR OVR PAR
STATUS–

DATA7± D15 D15 D14 D15 D14 D15 D14 D15 D14 D15 D14 D15 D14 D15 D14 D15 D14 D15

DATA0± D1 D1 D0 D1 D0 D1 D0 D1 D0 D1 D0 D1 D0 D1 D0 D1 D0 D1

Figure 11. LVDS Byte Mode—Eight Virtual Converters, Four DDCs (I/Q Decimate by 16)
190° PHASE ADJUST IS GENERATED USING THE FALLING EDGE OF CLK±.
2270° PHASE ADJUST IS GENERATED USING THE FALLING EDGE OF CLK±.
3FRAME CLOCK OUTPUT SUPPORTS THREE MODES OF OPERATION:
1) ENABLED (ALWAYS ON)
2) DISABLED (ALWAYS OFF)
3) GAPPED PERIODIC (CONDITIONALLY ENABLED BASED ON PSEUDORANDOM BIT)
4STATUS BIT SELECTED BY OUTPUT MODE CONTROL 1 BITS, REGISTER 0x559[2:0] IN THE REGISTER MAP.
13059-010
AD6679
AD6679 Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 6.
Parameter Rating THERMAL CHARACTERISTICS
Electrical Typical θJA, ΨJB, and ΨJT are specified vs. the number of printed
AVDD1 to AGND 1.32 V circuit board (PCB) layers in different airflow velocities (in
AVDD2 to AGND 2.75 V m/sec). Airflow increases heat dissipation, effectively reducing
AVDD3 to AGND 3.63 V θJA and ΨJB. In addition, metal in direct contact with the package
DVDD to DGND 1.32 V leads from metal traces, through holes, ground, and power planes
DRVDD to DRGND 1.32 V reduces the θJA. Thermal performance for actual applications
SPIVDD to AGND 3.63 V requires careful inspection of the conditions in an application.
AGND to DRGND −0.3 V to +0.3 V The use of appropriate thermal management techniques is recom-
VIN±x to AGND 3.2 V mended to ensure that the maximum junction temperature does
SCLK, SDIO, CSB to AGND −0.3 V to SPIVDD + 0.3 V not exceed the limits shown in Table 6.
PDWN/STBY to AGND −0.3 V to SPIVDD + 0.3 V
Environmental Table 7. Thermal Resistance
Operating Temperature Range −40°C to +85°C Airflow Velocity
Maximum Junction Temperature +125°C PCB Type (m/sec) θJA ΨJT ΨJB Unit
Storage Temperature Range −65°C to +150°C JEDEC 2s2p 0.0 27.01, 2 0.71, 3 7.31, 3 °C/W
Board
(Ambient)
Stresses at or above those listed under Absolute Maximum 1
Per JEDEC 51-7, plus JEDEC 51-5 2s2p test board.
2
Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
Ratings may cause permanent damage to the product. This is a 3
Per JEDEC JESD51-8 (still air).
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational ESD CAUTION
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.

Rev. B | Page 18 of 81
Data Sheet AD6679

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

1 2 3 4 5 6 7 8 9 10 11 12 13 14

A AGND AGND AGND AVDD2 AVDD1 AGND CLK+ CLK– AGND AVDD1 AVDD2 AGND AGND AGND A

B AVDD3 AGND AGND AVDD2 AVDD1 AGND AGND AGND AGND AVDD1 AVDD2 AGND AGND AVDD3 B

C AVDD3 AGND AGND AVDD2 AVDD1 AGND SYNC+ SYNC– AGND AVDD1 AVDD2 AGND AGND AVDD3 C

D AGND AGND AGND AVDD2 AVDD1 AGND AVDD1 AGND AGND AVDD1 AVDD2 AGND AGND AGND D

E VIN–B AGND AGND AVDD2 AVDD1 AGND AGND AGND AGND AVDD1 AVDD2 AGND AGND VIN–A E

F VIN+B AGND AGND AVDD2 AGND AGND AGND AGND AGND AGND AVDD2 AGND AGND VIN+A F

G AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AVDD2 AGND AGND AGND G

H AGND AGND AGND CSB AGND AGND AGND AGND AGND V_1P0 AGND AGND AGND AGND H

PDWN/
J FD_B AGND AGND SCLK SPIVDD AGND AGND AGND AGND AVDD2 SPIVDD AGND FD_A J
STBY

K DGND DGND AGND SDIO AGND AGND AGND AGND AGND AGND AGND AGND DCO– DCO+ K

L DVDD DVDD DGND DGND AGND AGND AGND AGND AGND AGND AGND AGND OVR– OVR+ L

M D1+ D1– DVDD DVDD DRVDD DRVDD DRVDD DRGND DRGND DRGND DRGND DRGND D13– D13+ M

N D2– D3– D4– D5– D6– D0– DRVDD DRGND D7– D8– D9– D10– D11– D12– N

P D2+ D3+ D4+ D5+ D6+ D0+ DRVDD DRGND D7+ D8+ D9+ D10+ D11+ D12+ P

1 2 3 4 5 6 7 8 9 10 11 12 13 14

1.25V ANALOG SUPPLY 1.25V DIGITAL SUPPLY ANALOG GROUND ADC I/O

13059-011
2.50V ANALOG SUPPLY 1.25V LVDS DRIVER SUPPLY DIGITAL GROUND LVDS INTERFACE
3.3V ANALOG SUPPLY 1.22V TO 3.4V SPI SUPPLY LVDS DRIVER GROUND SPI INTERFACE

Figure 12. Pin Configuration—Parallel Interleaved LVDS Mode (Top View)

Table 8. Pin Function Descriptions—Parallel Interleaved LVDS Mode

Pin No. Mnemonic Type Description
Power Supplies
A5, A10, B5, B10, C5, C10, D5, D7, D10, E5, E10 AVDD1 Supply Analog Power Supply (1.25 V Nominal).
A4, A11, B4, B11, C4, C11, D4, D11, E4, E11, F4, AVDD2 Supply Analog Power Supply (2.50 V Nominal).
F11, G11, J10
B1, B14, C1, C14 AVDD3 Supply Analog Power Supply (3.3 V Nominal)
L1, L2, M3, M4 DVDD Supply Digital Power Supply (1.25 V Nominal).
M5 to M7, N7, P7 DRVDD Supply Digital Driver Power Supply (1.25 V Nominal).
J5, J11 SPIVDD Supply Digital Power Supply for SPI (1.22 V to 3.4 V).
K1, K2, L3, L4 DGND Ground Ground Reference for DVDD.
M8 to M12, N8, P8 DRGND Ground Ground Reference for DRVDD.
A1 to A3, A6, A9, A12 to A14, B2, B3, B6 to B9, AGND Ground Analog Ground.
B12, B13, C2, C3, C6, C9, C12, C13, D1 to D3,
D6, D8, D9, D12 to D14, E2, E3, E6 to E9, E12,
E13, F2, F3, F5 to F10, F12, F13, G1 to G10, G12
to G14, H1 to H3, H5 to H9, H11 to H14, J2, J3,
J6 to J9, J12, K3, K5 to K12, L5 to L12
Analog
E14, F14 VIN−A, Input ADC A Analog Input Complement/True.
VIN+A
E1, F1 VIN−B, Input ADC B Analog Input Complement/True.
VIN+B

Rev. B | Page 19 of 81
AD6679 Data Sheet
Pin No. Mnemonic Type Description
H10 V_1P0 Input/DNC 1.0 V Reference Voltage Input/Do Not Connect. This pin
is configurable through the SPI as a no connect or as an
input. Do not connect this pin if using the internal
reference. This pin requires a 1.0 V reference voltage
input if using an external voltage reference source.
A7, A8 CLK+, CLK− Input Clock Input True/Complement.
CMOS Outputs
J14, J1 FD_A, FD_B Output Fast Detect Outputs for Channel A and Channel B.
Digital Inputs
C7, C8 SYNC+, Input Active High LVDS Sync Input—True/Complement.
SYNC−
Data Outputs
N6, P6 D0−, D0+ Output LVDS Lane 0 Output Data—Complement/True.
M2, M1 D1−, D1+ Output LVDS Lane 1 Output Data—Complement/True.
N1, P1 D2−, D2+ Output LVDS Lane 2 Output Data—Complement/True.
N2, P2 D3−, D3+ Output LVDS Lane 3 Output Data—Complement/True.
N3, P3 D4−, D4+ Output LVDS Lane 4 Output Data—Complement/True.
N4, P4 D5−, D5+ Output LVDS Lane 5 Output Data—Complement/True.
N5, P5 D6−, D6+ Output LVDS Lane 6 Output Data—Complement/True.
N9, P9 D7−, D7+ Output LVDS Lane 7 Output Data—Complement/True.
N10, P10 D8−, D8+ Output LVDS Lane 8 Output Data—Complement/True.
N11, P11 D9−, D9+ Output LVDS Lane 9 Output Data—Complement/True.
N12, P12 D10−, D10+ Output LVDS Lane 10 Output Data—Complement/True.
N13, P13 D11−, D11+ Output LVDS Lane 11 Output Data—Complement/True.
N14, P14 D12−, D12+ Output LVDS Lane 12 Output Data—Complement/True.
M13, M14 D13−, D13+ Output LVDS Lane 13 Output Data—Complement/True.
L13, L14 OVR−, OVR+ Output LVDS Overrange Output Data—Complement/True.
K13, K14 DCO−, DCO+ Output LVDS Digital Clock Output Data—Complement/True.
Device Under Test (DUT) Controls
K4 SDIO Input/output SPI Serial Data Input/Output.
J4 SCLK Input SPI Serial Clock.
H4 CSB Input SPI Chip Select (Active Low).
J13 PDWN/STBY Input Power-Down Input (Active High)/Standby. The
operation of this pin depends on the SPI mode and can
be configured in power-down or standby mode.

Rev. B | Page 20 of 81
Data Sheet AD6679
1 2 3 4 5 6 7 8 9 10 11 12 13 14

A AGND AGND AGND AVDD2 AVDD1 AGND CLK+ CLK– AGND AVDD1 AVDD2 AGND AGND AGND A

B AVDD3 AGND AGND AVDD2 AVDD1 AGND AGND AGND AGND AVDD1 AVDD2 AGND AGND AVDD3 B

C AVDD3 AGND AGND AVDD2 AVDD1 AGND SYNC+ SYNC– AGND AVDD1 AVDD2 AGND AGND AVDD3 C

D AGND AGND AGND AVDD2 AVDD1 AGND AVDD1 AGND AGND AVDD1 AVDD2 AGND AGND AGND D

E VIN–B AGND AGND AVDD2 AVDD1 AGND AGND AGND AGND AVDD1 AVDD2 AGND AGND VIN–A E

F VIN+B AGND AGND AVDD2 AGND AGND AGND AGND AGND AGND AVDD2 AGND AGND VIN+A F

G AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AVDD2 AGND AGND AGND G

H AGND AGND AGND CSB AGND AGND AGND AGND AGND V_1P0 AGND AGND AGND AGND H

PDWN/
J FD_B AGND AGND SCLK SPIVDD AGND AGND AGND AGND AVDD2 SPIVDD AGND
STBY
FD_A J

K DGND DGND AGND SDIO AGND AGND AGND AGND AGND AGND AGND AGND DCO– DCO+ K

L DVDD DVDD DGND DGND AGND AGND AGND AGND AGND AGND AGND AGND OVR– OVR+ L

M B D2/D3 + B D2/D3 – DVDD DVDD DRVDD DRVDD DRVDD DRGND DRGND DRGND DRGND DRGND A D12/D13– A D12/D13+ M

N B D4/D5– B D6/D7 – B D8/D9 – B D10/D11 – B D12/D13 – B D0/D1 – DRVDD DRGND A D0/D1 – A D2/D3 – A D4/D5– A D6/D7– A D8/D9– A D10/D11– N

P B D4/D5 + B D6/D7+ B D8/D9 + B D10/D11 + B D12/D13 + B D0/D1 + DRVDD DRGND A D0/D1 + A D2/D3 + A D4/D5 + A D6/D7 + A D8/D9 + A D10/D11 + P

1 2 3 4 5 6 7 8 9 10 11 12 13 14

1.25V ANALOG SUPPLY 1.25V DIGITAL SUPPLY ANALOG GROUND ADC I/O

13059-012
2.50V ANALOG SUPPLY 1.25V LVDS DRIVER SUPPLY DIGITAL GROUND LVDS INTERFACE
3.3V ANALOG SUPPLY 1.22V TO 3.4V SPI SUPPLY LVDS DRIVER GROUND SPI INTERFACE

Figure 13. Pin Configuration—Channel Multiplexed (Even/Odd) LVDS Mode (Top View)

Table 9. Pin Function Descriptions—Channel Multiplexed (Even/Odd) LVDS Mode 1

Pin No. Mnemonic Type Description
Power Supplies
A5, A10, B5, B10, C5, C10, D5, D7, D10, E5, AVDD1 Supply Analog Power Supply (1.25 V Nominal).
E10
A4, A11, B4, B11, C4, C11, D4, D11, E4, E11, AVDD2 Supply Analog Power Supply (2.50 V Nominal).
F4, F11, G11, J10
B1, B14, C1, C14 AVDD3 Supply Analog Power Supply (3.3 V Nominal)
L1, L2, M3, M4 DVDD Supply Digital Power Supply (1.25 V Nominal).
M5 to M7, N7, P7 DRVDD Supply Digital Driver Power Supply (1.25 V Nominal).
J5, J11 SPIVDD Supply Digital Power Supply for SPI (1.22 V to 3.4 V).
K1, K2, L3, L4 DGND Ground Ground Reference for DVDD.
M8 to M12, N8, P8 DRGND Ground Ground Reference for DRVDD.
A1 to A3, A6, A9, A12 to A14, B2, B3, B6 to AGND Ground Analog Ground.
B9, B12, B13, C2, C3, C6, C9, C12, C13, D1 to
D3, D6, D8, D9, D12 to D14, E2, E3, E6 to E9,
E12, E13, F2, F3, F5 to F10, F12, F13, G1 to
G10, G12 to G14, H1 to H3, H5 to H9, H11 to
H14, J2, J3, J6 to J9, J12, K3, K5 to K12, L5 to
L12
Analog
E14, F14 VIN−A, VIN+A Input ADC A Analog Input Complement/True.
E1, F1 VIN−B, VIN+B Input ADC B Analog Input Complement/True.
H10 V_1P0 Input/DNC 1.0 V Reference Voltage Input/Do Not Connect. This pin
is configurable through the SPI as a no connect or as an
input. Do not connect this pin if using the internal
reference. This pin requires a 1.0 V reference voltage
input if using an external voltage reference source.
A7, A8 CLK+, CLK− Input Clock Input True/Complement.
Rev. B | Page 21 of 81
AD6679 Data Sheet
Pin No. Mnemonic Type Description
CMOS Outputs
J14, J1 FD_A, FD_B Output Fast Detect Outputs for Channel A and Channel B.
Digital Inputs
C7, C8 SYNC+, Input Active High LVDS Sync Input—True/Complement.
SYNC−
Data Outputs
N9, P9 A D0/D1−, Output LVDS Channel A Data 0/Data 1 Output Data—
A D0/D1+ Complement/True.
N10, P10 A D2/D3−, Output LVDS Channel A Data 2/Data 3 Output Data—
A D2/D3+ Complement/True.
N11, P11 A D4/D5−, Output LVDS Channel A Data 4/Data 5 Output Data—
A D4/D5+ Complement/True.
N12, P12 A D6/D7−, Output LVDS Channel A Data 6/Data 7 Output Data—
A D6/D7+ Complement/True.
N13, P13 A D8/D9−, Output LVDS Channel A Data 8/Data 9 Output Data—
A D8/D9+ Complement/True.
N14, P14 A D10/D11−, Output LVDS Channel A Data 10/Data 11 Output Data—
A D10/D11+ Complement/True.
M13, M14 A D12/D13−, Output LVDS Channel A Data 12/Data 13 Output Data—
A D12/D13+ Complement/True.
N6, P6 B D0/D1−, Output LVDS Channel B Data 0/Data 1 Output Data—
B D0/D1+ Complement/True.
M2, M1 B D2/D3−, Output LVDS Channel B Data 2/Data 3 Output Data—
B D2/D3+ Complement/True.
N1, P1 B D4/D5−, Output LVDS Channel B Data 4/Data 5 Output Data—
B D4/D5+ Complement/True.
N2, P2 B D6/D7−, Output LVDS Channel B Data 6/Data 7 Output Data—
B D6/D7+ Complement/True.
N3, P3 B D8/D9−, Output LVDS Channel B Data 8/Data 9 Output Data—
B D8/D9+ Complement/True.
N4, P4 B D10/D11−, Output LVDS Channel B Data 10/Data 11 Output Data—
B D10/D11+ Complement/True.
N5, P5 B D12/D13−, Output LVDS Channel B Data 12/Data 13 Output Data—
B D12/D13+ Complement/True.
L13, L14 OVR−, OVR+ Output LVDS Overrange Output Data—Complement/True.
K13, K14 DCO−, DCO+ Output LVDS Digital Clock Output Data—Complement/True.
DUT Controls
K4 SDIO Input/output SPI Serial Data Input/Output.
J4 SCLK Input SPI Serial Clock.
H4 CSB Input SPI Chip Select (Active Low).
J13 PDWN/STBY Input Power-Down Input (Active High). The operation of this
pin depends on the SPI mode and can be configured in
power-down or standby mode.
1
When using channel multiplexed (even/odd) LVDS mode for one converter, the Channel B outputs are disabled and can be left unconnected.

Rev. B | Page 22 of 81
Data Sheet AD6679
1 2 3 4 5 6 7 8 9 10 11 12 13 14

A AGND AGND AGND AVDD2 AVDD1 AGND CLK+ CLK– AGND AVDD1 AVDD2 AGND AGND AGND A

B AVDD3 AGND AGND AVDD2 AVDD1 AGND AGND AGND AGND AVDD1 AVDD2 AGND AGND AVDD3 B

C AVDD3 AGND AGND AVDD2 AVDD1 AGND SYNC+ SYNC– AGND AVDD1 AVDD2 AGND AGND AVDD3 C

D AGND AGND AGND AVDD2 AVDD1 AGND AVDD1 AGND AGND AVDD1 AVDD2 AGND AGND AGND D

E VIN–B AGND AGND AVDD2 AVDD1 AGND AGND AGND AGND AVDD1 AVDD2 AGND AGND VIN–A E

F VIN+B AGND AGND AVDD2 AGND AGND AGND AGND AGND AGND AVDD2 AGND AGND VIN+A F

G AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AVDD2 AGND AGND AGND G

H AGND AGND AGND CSB AGND AGND AGND AGND AGND V_1P0 AGND AGND AGND AGND H

PDWN/
J FD_B AGND AGND SCLK SPIVDD AGND AGND AGND AGND AVDD2 SPIVDD AGND STBY FD_A J

K DGND DGND AGND SDIO AGND AGND AGND AGND AGND AGND AGND AGND DCO– DCO+ K

L DVDD DVDD DGND DGND AGND AGND AGND AGND AGND AGND AGND AGND FCO– FCO+ L

M DNC DNC DVDD DVDD DRVDD DRVDD DRVDD DRGND DRGND DRGND DRGND DRGND STATUS– STATUS+ M

N DNC DNC DNC DATA0 – DATA1 – DNC DRVDD DRGND DATA2– DATA3 – DATA4– DATA5– DATA 6– DATA7 – N

P DNC DNC DNC DATA0 + DATA1 + DNC DRVDD DRGND DATA2+ DATA3 + DATA4 + DATA5 + DATA6 + DATA7 + P

1 2 3 4 5 6 7 8 9 10 11 12 13 14

1.25V ANALOG SUPPLY 1.25V DIGITAL SUPPLY ANALOG GROUND ADC I/O DO NOT CONNECT

13059-013
2.50V ANALOG SUPPLY 1.25V LVDS DRIVER SUPPLY DIGITAL GROUND LVDS INTERFACE
3.3V ANALOG SUPPLY 1.22V TO 3.4V SPI SUPPLY LVDS DRIVER GROUND SPI INTERFACE

Figure 14. Pin Configuration—LVDS Byte Mode (Top View)

Table 10. Pin Function Descriptions—LVDS Byte Mode

Pin No. Mnemonic Type Description
Power Supplies
A5, A10, B5, B10, C5, C10, D5, D7, D10, E5, E10 AVDD1 Supply Analog Power Supply (1.25 V Nominal).
A4, A11, B4, B11, C4, C11, D4, D11, E4, E11, F4, AVDD2 Supply Analog Power Supply (2.50 V Nominal).
F11, G11, J10
B1, B14, C1, C14 AVDD3 Supply Analog Power Supply (3.3 V Nominal)
L1, L2, M3, M4 DVDD Supply Digital Power Supply (1.25 V Nominal).
M5 to M7, N7, P7 DRVDD Supply Digital Driver Power Supply (1.25 V Nominal).
J5, J11 SPIVDD Supply Digital Power Supply for SPI (1.22 V to 3.4 V).
K1, K2, L3, L4 DGND Ground Ground Reference for DVDD.
M8 to M12, N8, P8 DRGND Ground Ground Reference for DRVDD.
A1 to A3, A6, A9, A12 to A14, B2, B3, B6 to B9, AGND Ground Analog Ground.
B12, B13, C2, C3, C6, C9, C12, C13, D1 to D3,
D6, D8, D9, D12 to D14, E2, E3, E6 to E9, E12,
E13, F2, F3, F5 to F10, F12, F13, G1 to G10,
G12 to G14, H1 to H3, H5 to H9, H11 to H14,
J2, J3, J6 to J9, J12, K3, K5 to K12, L5 to L12
Analog
E14, F14 VIN−A, Input ADC A Analog Input Complement/True.
VIN+A
E1, F1 VIN−B, Input ADC B Analog Input Complement/True.
VIN+B
H10 V_1P0 Input/DNC 1.0 V Reference Voltage Input/Do Not Connect. This pin is
configurable through the SPI as a no connect or an input.
Do not connect this pin if using the internal reference.
This pin requires a 1.0 V reference voltage input if using
an external voltage reference source.
A7, A8 CLK+, CLK− Input Clock Input True/Complement.

Rev. B | Page 23 of 81
AD6679 Data Sheet
Pin No. Mnemonic Type Description
CMOS Outputs
J14, J1 FD_A, FD_B Output Fast Detect Outputs for Channel A and Channel B.
Digital Inputs
C7, C8 SYNC+, Input Active High LVDS Sync Input—True/Complement.
SYNC−
Data Outputs
N4, P4 DATA0−, Output LVDS Byte Data 0—Complement/True.
DATA0+
N5, P5 DATA1−, Output LVDS Byte Data 1—Complement/True.
DATA1+
N9, P9 DATA2−, Output LVDS Byte Data 2—Complement/True.
DATA2+
N10, P10 DATA3−, Output LVDS Byte Data 3—Complement/True.
DATA3+
N11, P11 DATA4−, Output LVDS Byte Data 4—Complement/True.
DATA4+
N12, P12 DATA5−, Output LVDS Byte Data 5—Complement/True.
DATA5+
N13, P13 DATA6−, Output LVDS Byte Data 6—Complement/True.
DATA6+
N14, P14 DATA7−, Output LVDS Byte Data 7—Complement/True.
DATA7+
M13, M14 STATUS−, Output LVDS Status Output Data—Complement/True.
STATUS+
L13, L14 FCO−, FCO+ Output LVDS Frame Clock Output Data—Complement/True.
K13, K14 DCO−, Output LVDS Digital Clock Output Data—Complement/True.
DCO+
DUT Controls
K4 SDIO Input/output SPI Serial Data Input/Output.
J4 SCLK Input SPI Serial Clock.
H4 CSB Input SPI Chip Select (Active Low).
J13 PDWN/STBY Input Power-Down Input (Active High). The operation of this
pin depends on the SPI mode and can be configured in
power-down or standby mode.
No Connects
M1, M2, N1 to N3, N6, P1 to P3, P6 DNC DNC Do Not Connect. Do not connect to these pins.

Rev. B | Page 24 of 81
Data Sheet AD6679

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD1 = 1.25 V, AVDD2 = 2.50 V, AVDD3 = 3.3 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, AIN = −1.0 dBFS, VDR mode
(no violation of VDR mask), clock divider = 2, otherwise default SPI settings, TA = 25°C, 128k FFT sample, unless otherwise noted.
0 0
AIN = −1dBFS AIN = −1dBFS
SNR = 68.9dBFS SNR = 67.3dBFS
–20 ENOB = 10.9 BITS –20 ENOB = 10.8 BITS
SFDR = 83dBFS SFDR = 86dBFS
BUFFER CONTROL 1 = 2.0× BUFFER CONTROL 1 = 4.5×
–40 –40
AMPLITUDE (dBFS)

AMPLITUDE (dBFS)
–60 –60

–80 –80

–100 –100

–120 –120

–140 –140
13059-014

13059-017
0 25 50 75 100 125 150 175 200 225 250 0 25 50 75 100 125 150 175 200 225 250
FREQUENCY (MHz) FREQUENCY (MHz)

Figure 15. Single Tone FFT with fIN = 10.3 MHz Figure 18. Single-Tone FFT with fIN = 450.3 MHz

0 0
AIN = −1dBFS AIN = −1dBFS
SNR = 68.7dBFS SNR = 63.9dBFS
–20 ENOB = 10.9 BITS –20 ENOB = 10.3 BITS
SFDR = 84dBFS SFDR = 81dBFS
BUFFER CONTROL 1 = 2.0× BUFFER CONTROL 1 = 5.0×
–40 –40
AMPLITUDE (dBFS)

AMPLITUDE (dBFS)

–60 –60

–80 –80

–100 –100

–120 –120

–140 –140
13059-015

13059-018
0 25 50 75 100 125 150 175 200 225 250 0 25 50 75 100 125 150 175 200 225 250
FREQUENCY (MHz) FREQUENCY (MHz)

Figure 16. Single-Tone FFT with fIN = 170.3 MHz Figure 19. Single-Tone FFT with fIN = 765.3 MHz

0 0
AIN = −1dBFS AIN = −1dBFS
SNR = 67.8dBFS SNR = 62.8dBFS
–20 ENOB = 10.8 BITS –20 ENOB = 10.1 BITS
SFDR = 82dBFS SFDR = 76dBFS
BUFFER CONTROL 1 = 4.5× BUFFER CONTROL 1 = 5.0×
–40 –40
AMPLITUDE (dBFS)

AMPLITUDE (dBFS)

–60 –60

–80 –80

–100 –100

–120 –120

–140 –140
13059-016

13059-019

0 25 50 75 100 125 150 175 200 225 250 0 25 50 75 100 125 150 175 200 225 250
FREQUENCY (MHz) FREQUENCY (MHz)

Figure 17. Single-Tone FFT with fIN = 340.3 MHz Figure 20. Single-Tone FFT with fIN = 985.3 MHz

Rev. B | Page 25 of 81
AD6679 Data Sheet
0 95
AIN = −1dBFS
SNR = 61.7dBFS
–20 ENOB = 9.9 BITS 90
SFDR = 70dBFS
BUFFER CONTROL 1 = 8.0× SFDR
–40
AMPLITUDE (dBFS)

SNR/SFDR (dBFS)
85

–60
80
–80

75
–100

–120 70 SNR

–140 65

13059-020

13059-023
0 25 50 75 100 125 150 175 200 225 250 200 250 300 350 400 450 500
FREQUENCY (MHz) SAMPLE RATE (MHz)

Figure 21. Single-Tone FFT with fIN = 1205.3 MHz Figure 24. SNR/SFDR vs. Sample Rate (fS); fIN = 170.3 MHz;

0
95
AIN = −1dBFS SFDR, 2.0×
SNR = 60.1dBFS SNRFS, 2.0×
–20 ENOB = 9.7 BITS SFDR, 3.0×
90
SFDR = 71dBFS SNRFS, 3.0×
BUFFER CONTROL 1 = 8.0× SFDR, 4.0×
–40 SNRFS, 4.0×
85
AMPLITUDE (dBFS)

SNR/SFDR (dBFS)
–60
80

–80
75

–100
70

–120
65

–140
13059-021

60

13059-024
0 25 50 75 100 125 150 175 200 225 250
50 100 150 200 250 300 350 400 450 500
FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
Figure 22. Single-Tone FFT with fIN = 1630.3 MHz Figure 25. SNR/SFDR vs. Analog Input Frequency (fIN);
fIN < 500 MHz; Buffer Control 1 Setting = 2.0×, 3.0×, and 4.0×
0
0
AIN = −1dBFS
SNR = 59.0dBFS AIN1 AND AIN2 = –7dBFS
–20 ENOB = 9.5 BITS SFDR = 88dBFS
SFDR = 69dBFS –20 IMD2 = 95dBFS
BUFFER CONTROL 1 = 8.0× IMD3 = 88dBFS
–40 BUFFER CONTROL 1 = 2.0×
AMPLITUDE (dBFS)

AMPLITUDE (dBFS)

–40
–60

–60
–80

–80
–100

–120 –100

–140
–120
13059-022

13059-025

0 25 50 75 100 125 150 175 200 225 250

0 50 100 150 200 250
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 23. Single-Tone FFT with fIN = 1950.3 MHz Figure 26. Two-Tone FFT; fIN1 = 184 MHz, fIN2 = 187 MHz

Rev. B | Page 26 of 81
Data Sheet AD6679
0 100
SFDR (dBc)
AIN1 AND AIN2 = –7dBFS
SFDR = 87dBFS 80
–20 IMD2 = 94dBFS
SNR (dBc)
IMD3 = 87dBFS

SNR/SFDR (dBc AND dBFS)

BUFFER CONTROL 1 = 2.0× 60
AMPLITUDE (dBFS)

–40
SFDR (dBFS)
40
–60
SNR (dBc)
20

–80
0

–100
–20

–120 –40

13059-026
0 50 100 150 200 250

13059-029
0
–6
–90

–84

–78
–72
–66

–60

–48
–42

–36

–30
–24

–18

–12
–54
FREQUENCY (MHz)
INPUT AMPLITUDE (dBFS)

Figure 27. Two-Tone FFT; fIN1 = 338 MHz, fIN2 = 341 MHz Figure 30. SNR/SFDR vs. Input Amplitude, fIN = 170.3 MHz

0 90

SFDR
–20
SFDR (dBc) 85
SFDR/IMD3 (dBc AND dBFS)

–40

SNR/SFDR (dBFS)
IMD3 (dBc)
80
–60

–80 75
SFDR (dBFS)
–100
70
IMD3 (dBFS)
–120 SNR

65

13059-030
–140 –40 –25 –10 0 15 25 40 55 70 85
13059-027

–90 –84 –78 –72 –66 –60 –54 –48 –42 –36 –30 –24 –18 –12 –6 TEMPERATURE (°C)
INPUT AMPLITUDE (dBFS)
Figure 31. SNR/SFDR vs. Temperature, fIN = 170.3 MHz
Figure 28. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 184 MHz
and fIN2 = 187 MHz
2.30
0
2.25
–20
2.20
SFDR (dBc)
SFDR/IMD3 (dBc AND dBFS)

–40 2.15
IMD3 (dBc)
POWER (W)

2.10
–60
2.05

–80 2.00
SFDR (dBFS) 1.95
–100
1.90

–120 IMD3 (dBFS) 1.85

1.80
–140
300

320

340

360

380

400

420

440

460

480

500
13059-031
13059-028

–90 –84 –78 –72 –66 –60 –54 –48 –42 –36 –30 –24 –18 –12 –6
SAMPLE RATE (MSPS)
INPUT AMPLITUDE (dBFS)

Figure 29. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 338 MHz Figure 32. Power Dissipation vs. Sample Rate (fS), Default SPI
and fIN2 = 341 MHz

Rev. B | Page 27 of 81
AD6679 Data Sheet

EQUIVALENT CIRCUITS
AVDD3
AVDD3

VIN+x

3pF 1.5pF AVDD3

200Ω

200Ω
28Ω
67Ω

SWING CONTROL
400Ω VCM (SPI)
BUFFER
10pF
200Ω

200Ω
28Ω
67Ω

DRVDD

AVDD3 DATA+ D0+ TO D13+;

AVDD3 A Dx/Dy+ AND B Dx/Dy+;
DATA0+ TO DATA7+

OUTPUT DRGND
VIN–x
DRIVER
DRVDD

AIN DATA– D0– TO D13–;

3pF 1.5pF A Dx/Dy– AND B Dx/Dy–;

13059-035
CONTROL
13059-032 DATA0– TO DATA7–
(SPI)
DRGND

Figure 33. Analog Inputs Figure 36. Digital Outputs

AVDD1 SPIVDD

25Ω ESD
CLK+ PROTECTED
SPIVDD
1kΩ
SCLK
30kΩ
AVDD1
ESD
25Ω PROTECTED

13059-036
CLK–

20kΩ 20kΩ
13059-033

VCM = 0.85V

Figure 34. Clock Inputs Figure 37. SCLK Inputs

AVDD1 SPIVDD

1kΩ ESD
SYNC+
PROTECTED
30kΩ

20kΩ 1kΩ
CSB
LEVEL
TRANSLATOR VCM = 0.85V
ESD
AVDD1 20kΩ PROTECTED
13059-037

1kΩ
SYNC–
13059-034

Figure 35. SYNC± Inputs Figure 38. CSB Input

Rev. B | Page 28 of 81
Data Sheet AD6679
SPIVDD SPIVDD

ESD ESD
PROTECTED SDO PROTECTED
SPIVDD 30kΩ
1kΩ SDI PDWN/ 1kΩ
SDIO STBY
30kΩ
ESD ESD PDWN
PROTECTED PROTECTED CONTROL (SPI)

13059-038

13059-040
Figure 39. SDIO Figure 41. PDWN/STBY Input

SPIVDD AVDD2

ESD ESD
PROTECTED PROTECTED
FD

FD_A/FD_B V_1P0

TEMPERATURE DIODE
ESD (FD_A ONLY) ESD
PROTECTED PROTECTED

13059-041
13059-039

V_1P0 PIN
FD_x PIN CONTROL (SPI) CONTROL (SPI)

Figure 40. FD_A/FD_B Outputs Figure 42. V_1P0 Input/Output

Rev. B | Page 29 of 81
AD6679 Data Sheet

THEORY OF OPERATION
The AD6679 has two analog input channels and 14 LVDS maximum bandwidth of the ADC. Such use of low Q inductors
output lane pairs. The AD6679 is designed to sample wide or ferrite beads is required when driving the converter front end
bandwidth analog signals of up to 2 GHz. The AD6679 is at high IF frequencies. Place either a differential capacitor or
optimized for wide input bandwidth, high sampling rates, two single-ended capacitors on the inputs to provide a matching
excellent linearity, and low power in a small package. passive network. This ultimately creates a low-pass filter (LPF)
The dual ADC cores feature a multistage, differential pipelined at the input, which limits unwanted broadband noise. For more
architecture with integrated output error correction logic. Each information, refer to the AN-742 Application Note, the AN-827
ADC features wide bandwidth inputs supporting a variety of Application Note, and the Analog Dialogue article “Transformer-
user-selectable input ranges. An integrated voltage reference Coupled Front-End for Wideband A/D Converters” (Volume 39,
eases design considerations. April 2005) at www.analog.com. In general, the precise values
depend on the application.
The AD6679 has several functions that simplify the AGC
function in a communications receiver. The programmable For best dynamic performance, match the source impedances
threshold detector allows monitoring of the incoming signal driving VIN+x and VIN−x such that common-mode settling
power using the fast detect bits of the ADC output data stream, errors are symmetrical. These errors are reduced by the common-
which are enabled and programmed via Register 0x245 through mode rejection of the ADC. An internal reference buffer creates
Register 0x24C. If the input signal level exceeds the programmable a differential reference that defines the span of the ADC core.
threshold, the fast detect indicator goes high. Because this Maximum SNR performance is achieved by setting the ADC to
threshold indicator has low latency, the user can quickly reduce the largest span in a differential configuration. In the case of the
the system gain to avoid an overrange condition at the ADC input. AD6679, the available span is programmable through the SPI
The LVDS outputs can be configured depending on the decimation port from 1.46 V p-p to 2.06 V p-p differential with 2.06 V p-p
ratio. Multiple device synchronization is supported through the differential being the default.
SYNC± input pins. Differential Input Configurations
ADC ARCHITECTURE There are several ways to drive the AD6679, either actively or
passively. However, optimum performance is achieved by
The architecture consists of an input buffered pipelined ADC.
driving the analog input differentially.
The input buffer provides a termination impedance to the
analog input signal. This termination impedance can be For applications in which SNR and SFDR are key parameters,
changed using the SPI to meet the termination needs of the differential transformer coupling is the recommended input
driver/amplifier. The default termination value is set to 400 Ω. The configuration (see Figure 43 and Figure 44) because the noise
equivalent circuit diagram of the analog input termination is performance of most amplifiers is not adequate to achieve the
shown in Figure 33. The input buffer is optimized for high true performance of the AD6679.
linearity, low noise, and low power. For low to midrange frequencies, it is recommended to use a
The input buffer provides a linear high input impedance (for double balun or double transformer network (see Figure 43) for
ease of drive) and reduces the kickback from the ADC. The optimum performance from the AD6679. For higher
quantized outputs from each stage are combined into a final frequencies in the second or third Nyquist zone, it is better to
16-bit result in the digital correction logic. The pipelined remove some of the front-end passive components to ensure
architecture permits the first stage to operate with a new input wideband operation (see Figure 44).
sample while the remaining stages operate with the preceding 10Ω 10Ω
ETC1-11-13/
samples. Sampling occurs on the rising edge of the clock. MABA007159
25Ω
0.1µF 4pF
1:1Z
ANALOG INPUT CONSIDERATIONS 0.1µF
2pF ADC
25Ω
The analog input to the AD6679 is a differential buffer. The 10Ω 10Ω
13059-042

internal common-mode voltage of the buffer is 2.05 V. The 0.1µF 4pF

clock signal alternately switches the input circuit between
Figure 43. Differential Transformer Coupled Configuration for First and
sample mode and hold mode. When the input circuit is switched Second Nyquist Frequencies
into sample mode, the signal source must be capable of charging 25Ω

the sample capacitors and settling within one-half of a clock cycle. 25Ω
0.1µF
A small resistor, in series with each input, can help reduce the MARKI
BAL-0006 ADC
peak transient current inserted from the output stage of the OR 0.1µF
BAL-0006SMG 25Ω
driving source. In addition, low Q inductors or ferrite beads can 25Ω
13059-043

be placed on each section of the input to reduce high differen- 0.1µF

tial capacitance at the analog inputs and, thus, achieve the Figure 44. Differential Transformer Coupled Configuration for Second and
Third Nyquist Frequencies
Rev. B | Page 30 of 81
Data Sheet AD6679
250
Input Common Mode
230
The analog inputs of the AD6679 are internally biased to the
common mode, as shown in Figure 45. The common-mode 210

buffer has a limited range in that the performance suffers 190

greatly if the common-mode voltage drops by more than 170

IAVDD3 (mA)
100 mV. Therefore, in dc-coupled applications, set the
150
common-mode voltage to 2.05 V ± 100 mV to ensure proper
130
ADC operation.
110
Analog Input Controls and SFDR Optimization
90
The AD6679 offers flexible controls for the analog inputs such
as input termination, buffer current, and input full-scale 70

adjustment. All of the available controls are shown in Figure 45. 50

13059-045
1.5× 2.5× 3.5× 4.5× 5.5× 6.5× 7.5× 8.5×
AVDD3
BUFFER CURRENT SETTING

Figure 46. Typical IAVDD3 vs. Buffer Current Setting in Register 0x018
VIN+x
3pF Register 0x019, Register 0x01A, Register 0x11A, and Register 0x935
offer secondary bias controls for the input buffer for frequencies
AVDD3
200Ω

200Ω

>500 MHz. Use Register 0x934 to reduce input capacitance to

28Ω
67Ω

achieve wider signal bandwidth but doing so may result in

400Ω VCM
BUFFER slightly lower linearity and noise performance. These register
10pF
settings do not affect the AVDD3 power as much as Register 0x018
200Ω

200Ω
28Ω
67Ω

AVDD3 does. For frequencies <500 MHz, it is recommended to use the

default settings for these registers. Table 11 shows the recom-
VIN–x mended values for the buffer current control registers for various
3pF speed grades.
AIN CONTROL
(SPI) REGISTERS Register 0x11A can be used when sampling in higher Nyquist
(REG 0x008, REG 0x015,
13059-044

REG 0x016, REG 0x018, zones (>1000 MHz) but is not necessary. Using Register 0x11A
REG 0x025)
can help the ADC sampling network to optimize the sampling
Figure 45. Analog Input Controls
and settling times internal to the ADC for high frequency opera-
Use Register 0x018, Register 0x019, Register 0x01A, Register 0x11A, tion. For frequencies greater than 500 MHz, it is recommended
Register 0x934, and Register 0x935 to adjust the buffer behavior on to operate the ADC core at a 1.46 V full-scale setting. This setting
each channel to optimize the SFDR over various input frequencies offers better SFDR without any significant decrease in SNR.
and bandwidths of interest. Figure 47, Figure 48, and Figure 49 show the SFDR vs. input
Input Buffer Control Registers (Register 0x018, frequency for various buffer settings for the AD6679. The
Register 0x019, Register 0x01A, Register 0x11A, recommended settings shown in Table 11 were used to collect
Register 0x934, Register 0x935) the data while changing the contents of register 0x018 only.
95
The input buffer has many registers that set the bias currents
and other settings for operation at different frequencies. These 4.5×
85
bias currents and settings can be changed to suit the input
frequency range of operation. Register 0x018 controls the buffer 3.0×
75
bias current to reduce the effects of charge kickback from the
SFDR (dBFS)

2.0×
ADC core. This setting can be scaled from a low setting of 1.0× to
65
a high setting of 8.5×. The default setting in Register 0x018 is 1.5×

2.0×. These settings are sufficient for operation in the first

55
Nyquist zone. As the input buffer currents are set, the amount 1.0×
of current required by the AVDD3 supply changes. This 45
relationship is shown in Figure 46. For a complete list of buffer
current settings, see Table 41. 35
13059-046

50 100 150 200 250 300 350 400 450 500

INPUT FREQUENCY (MHz)

Figure 47. Buffer Current Sweeps (SFDR vs. Input Frequency and IBUFF);
10 MHz < fIN < 500 MHz; Front-End Network Shown in Figure 43

Rev. B | Page 31 of 81
AD6679 Data Sheet
90
Absolute Maximum Input Swing
4.5× The absolute maximum input swing allowed at the inputs of the
5.0×
85 6.0× AD6679 is 4.3 V p-p differential. Signals operating near or at
7.0×
8.0× this level can cause permanent damage to the ADC.
SFDR (dBFS)

80
VOLTAGE REFERENCE
A stable and accurate 1.0 V voltage reference is built into the
75
AD6679. This internal 1.0 V reference sets the full-scale input
range of the ADC. The full-scale input range can be adjusted via
70 Register 0x025. For more information on adjusting the input
swing, see Table 41. Figure 50 shows the block diagram of the
internal 1.0 V reference controls.
65

13059-047
500 550 600 650 700 750 800 850 900 950 1000
VIN+A/
INPUT FREQUENCY (MHz) VIN+B
Figure 48. Buffer Current Sweeps (SFDR vs. Input Frequency and IBUFF); VIN–A/
VIN–B
500 MHz < fIN < 1000 MHz; Front-End Network Shown in Figure 44
80 ADC
INTERNAL CORE
V_1P0 FULL-SCALE
VOLTAGE
75 GENERATOR ADJUST

INPUT FULL-SCALE
70 RANGE ADJUST
SPI REGISTER
(REG 0x025 AND REG 0x024)
SFDR (dBFS)

V_1P0
65
V_1P0 PIN
CONTROL SPI
60 REGISTER

13059-049
(REG 0x025 AND
REG 0x024)
55 4.5×
5.0×
6.0× Figure 50. Internal Reference Configuration and Controls
7.0×
50
8.0×
8.0×
45
13059-048

1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000
INPUT FREQUENCY (MHz)

Figure 49. Buffer Current Sweeps (SFDR vs. Input Frequency and IBUFF);
1 GHz < fIN < 2 GHz; Front-End Network Shown in Figure 44

Table 11. SFDR Optimization for Input Frequencies

Input Full- Input Full-
Buffer Buffer Buffer Buffer Buffer Scale Scale Input Input
Control 1 Control 2 Control 3 Control 4 Control 5 Range Control Capacitance Termination
(Register (Register (Register (Register (Register (Register (Register (Register (Register
Frequency 0x018) 0x019) 0x01A) 0x11A) 0x935) 0x025) 0x030) 0x934) 0x016) 1
DC to 250 MHz 0x20 0x60 0x0A 0x00 (off) 0x04 (on) 0x0C 0x04 0x1F 0x0C/0x1C/0x6C
(2.0×) (Setting 3) (Setting 3) (2.06 V p-p)
250 MHz to 0x70 0x60 0x0A 0x00 (off) 0x04 (on) 0x0C 0x04 0x1F 0x0C/0x1C/0x6C
500 MHz (4.5×) (Setting 3) (Setting 3) (2.06 V p-p)
500 MHz to 0x80 0x40 0x08 0x00 (off) 0x00 (off) 0x08 0x18 0x1F/0x00 2 0x0C/0x1C/0x6C
1 GHz (5.0×) (Setting 1) (Setting 1) (1.46 V p-p)
1 GHz to 2 GHz 0xF0 0x40 0x08 0x00 (off) 0x00 (off) 0x08 0x18 0x1F/0x002 0x0C/0x1C/0x6C
(8.5×) (Setting 1) (Setting 1) (1.46 V p-p)
1
The input termination can be changed to accommodate the application with little or no impact to ac performance.
2
The input capacitance can be set to 1.5 pF to achieve wider input bandwidth but doing so results in slightly lower ac performance.

Rev. B | Page 32 of 81
Data Sheet AD6679
Register 0x024 enables the user to use either this internal 1.0 V 0.1µF
reference, or to provide an external 1.0 V reference. When using
CLOCK 1:1Z CLK+
an external voltage reference, provide a 1.0 V reference. The INPUT 100Ω ADC
50Ω
full-scale adjustment is made using the SPI, irrespective of the CLK–

13059-051
reference voltage. For more information on adjusting the full-
0.1µF
scale level of the AD6679, refer to the Memory Map Register
Figure 52. Transformer Coupled Differential Clock
Table section.
Another option is to ac couple a differential CML or LVDS
The use of an external reference may be necessary, in some
signal to the sample clock input pins as shown in Figure 53 and
applications, to enhance the gain accuracy of the ADC or
Figure 54.
improve thermal drift characteristics. Figure 51 shows the
3.3V
typical drift characteristics of the internal 1.0 V reference.
1.0010 71Ω 10pF

1.0009 33Ω 33Ω

1.0008 Z0 = 50Ω 0.1µF
CLK+
1.0007
ADC
V_1P0 VOLTAGE (V)

13059-052
1.0006
CLK–
1.0005 Z0 = 50Ω 0.1µF

1.0004 Figure 53. Differential CML Sample Clock

1.0003
1.0002
0.1µF 0.1µF
1.0001 CLOCK INPUT CLK+ CLK+

1.0000 LVDS
DRIVER 100Ω ADC
0.9999 0.1µF
CLOCK INPUT CLK– CLK–
0.9998 0.1µF
13059-050

–50 0 25 90 50Ω1 50Ω1

TEMPERATURE (°C)

13059-053
Figure 51. Typical V_1P0 Drift 150Ω RESISTORS ARE OPTIONAL.

The external reference must be a stable 1.0 V reference. The Figure 54. Differential LVDS Sample Clock
ADR130 is a good option for providing the 1.0 V reference. Clock Duty Cycle Considerations
Figure 55 shows how the ADR130 can be used to provide the
Typical high speed ADCs use both clock edges to generate a
external 1.0 V reference to the AD6679. The gray areas show
variety of internal timing signals. As a result, these ADCs may
unused blocks within the AD6679 while the ADR130 provides
be sensitive to the clock duty cycle. Commonly, a 5% tolerance
the external reference.
is required on the clock duty cycle to maintain dynamic
CLOCK INPUT CONSIDERATIONS performance characteristics. In applications where the clock
For optimum performance, drive the AD6679 sample clock duty cycle cannot be guaranteed to be 50%, a higher multiple
inputs (CLK+ and CLK−) with a differential signal. This signal frequency clock can be supplied to the AD6679. For example,
is typically ac-coupled to the CLK+ and CLK− pins via a the AD6679 can be clocked at 2 GHz with the internal clock
transformer or clock drivers. These pins are biased internally divider set to 4. This ensures a 50% duty cycle, high slew rate
and require no additional biasing. internal clock for the ADC. See the Memory Map section for
more details on using this feature.
Figure 52 shows one preferred method for clocking the
AD6679. The low jitter clock source is converted from a single-
ended signal to a differential signal using an RF transformer.

INTERNAL
V_1P0 FULL-SCALE
ADR130 VOLTAGE
GENERATOR ADJUST
1 NC NC 6

2 GND SET 5
INPUT V_1P0
3 VIN VOUT 4

0.1µF 0.1µF
FULL-SCALE
13059-054

CONTROL

Figure 55. External Reference Using the ADR130

Rev. B | Page 33 of 81
AD6679 Data Sheet
Input Clock Divider Clock Jitter Considerations
The AD6679 contains an input clock divider with the ability to High speed, high resolution ADCs are sensitive to the quality of the
divide the Nyquist input clock by 1, 2, 4, or 8. The divide ratio clock input. The degradation in SNR at a given input frequency
can be selected using Register 0x10B. This is shown in Figure 56. (fA) due only to aperture jitter (tJ) is calculated by
The maximum frequency at the output of the divider is 500 MHz. SNR = 20 × log10(2 × π × fA × tJ)
The maximum frequency at the CLK± inputs is 4 GHz. This is In this equation, the rms aperture jitter represents the root mean
the limit of the divider. In applications where the clock input is square of all jitter sources, including the clock input, analog input
a multiple of the sample clock, take care to program the signal, and ADC aperture jitter specifications. IF undersampling
appropriate divider ratio into the clock divider before applying applications are particularly sensitive to jitter (see Figure 57).
the clock signal. This ensures that the current transients during 130
device startup are controlled. RMS CLOCK JITTER REQUIREMENT
120
CLK+
110

CLK– ÷2 100 16 BITS

÷4 90 14 BITS

SNR (dB)
÷8
80
12 BITS
13059-055

70
REG 0x10B 10 BITS
60
0.125ps
Figure 56. Clock Divider Circuit 50
8 BITS
0.25ps
0.5ps
The AD6679 clock divider can be synchronized using the 40 1.0ps
2.0ps
external SYNC± input. A valid SYNC± input causes the clock 30

13059-056
divider to reset to a programmable state. This feature is enabled 1 10 100 1000
ANALOG INPUT FREQUENCY (MHz)
by setting Bit 7 of Register 0x10D. This synchronization feature
Figure 57. Ideal SNR vs. Analog Input Frequency and Jitter
allows multiple devices to have their clock dividers aligned to
guarantee simultaneous input sampling. Treat the clock input as an analog signal when aperture jitter
may affect the dynamic range of the AD6679. Separate the power
After programming the desired clock divider settings, changing
supplies for the clock drivers from the ADC output driver
the input clock frequency or glitching the input clock a datapath
supplies to avoid modulating the clock signal with digital noise.
soft reset is recommended by writing 0x02 to Register 0x001.
If the clock is generated from another type of source (by gating,
This reset function restarts all the datapath and clock generation
dividing, or other methods), retime it using the original clock at
circuitry in the device. The reset occurs on the first clock cycle
the last step. See the AN-501 Application Note and the AN-756
after the register is programmed, and the device requires 5 ms
Application Note for more in-depth information about jitter
to recover. This reset does not affect the contents of the memory
performance as it relates to ADCs.
map registers.
Figure 58 shows the estimated SNR of the AD6679 across input
Input Clock Divider ½ Period Delay Adjustment
frequency for different clock induced jitter values. Estimate the
The input clock divider inside the AD6679 provides phase delay SNR by using the following equation:
in increments of ½ the input clock cycle. Program Register 0x10C
to enable this delay independently for each channel.   − SNR ADC   − SNR JITTER  
 

SNR(dBFS) = 10log 10  10  + 10 10  
 
Clock Fine Delay Adjustment  
To adjust the AD6679 sampling edge instant, write to Register
0x117 and Register 0x118. Setting Bit 0 of Register 0x117 enables
the fine delay feature, and Register 0x118, Bits[7:0], set the value
of the delay. This value can be programmed individually for each
channel. The clock delay can be adjusted from −151.7 ps to
+150 ps in ~1.7 ps increments. The clock delay adjustment
takes effect immediately when it is enabled via SPI writes.
Enabling the clock fine delay adjustment in Register 0x117
causes a datapath reset.

Rev. B | Page 34 of 81
Data Sheet AD6679
75
The temperature diode voltage can be output to the FD_A pin
using the SPI. Use Register 0x028, Bit 0, to enable or disable the
70
diode. Register 0x028 is a local register. Channel A must be
selected in the device index register (Register 0x008) to enable
65
the temperature diode readout. Configure the FD_A pin to
SNR (dBFS)

25fs
50fs output the diode voltage by programming Register 0x040,
60 75fs
100fs Bits[2:0]. See Table 41 for more information.
125fs
55 150fs The voltage response of the temperature diode (with SPIVDD =
175fs
200fs 1.8 V) is shown in Figure 59.
50 0.90

TEMPERATURE DIODE VOLTAGE (V)

45 0.85

13059-057
1M 10M 100M 1G 10G
INPUT FREQUENCY (Hz)
0.80
Figure 58. Estimated SNR Degradation for the AD6679 vs.
Input Frequency and Jitter
0.75
POWER-DOWN/STANDBY MODE
The AD6679 has a PDWN/STBY pin that configures the device 0.70

in power-down or standby mode. The default operation is the

power-down function. The PDWN/STBY pin is a logic high 0.65

pin. The power-down option can also be set via Register 0x03F
and Register 0x040. 0.60

13059-058
–55 –45 –35 –25 –15 –5 5 15 25 35 45 55 65 75 85 95 105 115 125

TEMPERATURE DIODE TEMPERATURE (°C)

Figure 59. Temperature Diode Voltage vs. Temperature

The AD6679 contains a diode-based temperature sensor for
measuring the temperature of the die. This diode can output a
voltage and serve as a coarse temperature sensor to monitor the
internal die temperature.

Rev. B | Page 35 of 81
AD6679 Data Sheet

VIRTUAL CONVERTER MAPPING

The AD6679 contains a configurable signal path that allows To support the different application layer modes, the AD6679
different features to be enabled for different applications. These treats each sample stream (real or I or Q) as originating from
features are controlled through the chip application mode separate virtual converters. Table 12 shows the number of
register (0x200). The chip operating mode is controlled by virtual converters required for each chip mode.
Bits[3:0] and the Chip Q ignore is controlled by Bit 5. The AD6679 supports up to four digital DDC blocks. Each
The AD6679 contains the following digital features: DDC block outputs either two sample streams (I/Q) for the
complex data components (real + imaginary) or one sample
• Two analog-to-digital converter (ADC) cores
stream for real (I) data. The AD6679 can be configured to use up
• Four digital downconverter (DDC) channels
to eight virtual converters depending on the DDC configuration.
• Two noise shaped requantizer (NSR) blocks with optional
Figure 60 shows the virtual converters and their relationship to
decimate by two blocks
DDC outputs when complex outputs are used.
• Two variable dynamic range (VDR) blocks
Table 12 shows the virtual converter mapping for each chip
After the chip application mode has been selected, the output operating mode when channel swapping is disabled.
decimation ratio is set using the chip decimation ratio in
Register 0x201, Bits[2:0]. The output sample rate is the ADC
sample rate divided by the chip decimation ratio.

Table 12. Virtual Converter Mapping

Chip Virtual Converter Mapping1
No. of Operating Chip Q
Virtual Mode Ignore
Converters (Register (Register
Supported 0x200[3:0]) 0x200[5]) 0 1 2 3 4 5 6 7
1 One DDC Real DDC 0 N/A N/A N/A N/A N/A N/A N/A
mode (0x1) (I only) I samples
(0x1)
2 One DDC Complex DDC 0 DDC 0 N/A N/A N/A N/A N/A N/A
mode (0x1) (I/Q) I samples Q samples
(0x0)
2 Two DDC Real DDC 0 DDC 1 N/A N/A N/A N/A N/A N/A
mode (0x2) (I only) I samples I samples
(0x1)
4 Two DDC Complex DDC 0 DDC 0 DDC 1 DDC 1 N/A N/A N/A N/A
mode (0x2) (I/Q) I samples Q samples I samples Q samples
(0x0)
4 Four DDC Real DDC 0 DDC 1 DDC 2 DDC 3 N/A N/A N/A N/A
mode (0x3) (I only) I samples I samples I samples I samples
(0x1)
8 Four DDC Complex DDC 0 DDC 0 DDC 1 DDC 1 DDC 2 DDC 2 DDC 3 DDC 3
mode (0x3) (I/Q) I samples Q samples I samples Q samples I samples Q samples I samples Q samples
(0x0)
1 to 2 NSR mode Real or ADC A ADC B N/A N/A N/A N/A N/A N/A
(0x7) complex samples samples
(0x0)
1 to 2 VDR mode Real or ADC A ADC B N/A N/A N/A N/A N/A N/A
(0x8) complex samples samples
(0x0)
1
N/A means not applicable.

Rev. B | Page 36 of 81
Data Sheet AD6679
ADC A DDC 0
REAL/I REAL/I REAL/I
SAMPLING I I
CONVERTER 0
AT fS
REAL/Q Q
Q Q
CONVERTER 1

DDC 1
REAL/I REAL/I
I I
CONVERTER 2
REAL/Q Q
Q Q
I/Q CONVERTER 3 OUTPUT
CROSSBAR INTERFACE
MUX DDC 2
REAL/I REAL/I
I I
CONVERTER 4
REAL/Q Q
Q Q
CONVERTER 5

ADC B DDC 3
REAL/Q REAL/I REAL/I
SAMPLING I I
CONVERTER 6

13059-159
AT fS REAL/Q Q
Q Q
CONVERTER 7

Figure 60. DDCs and Virtual Converter Mapping

Rev. B | Page 37 of 81
AD6679 Data Sheet

ADC OVERRANGE AND FAST DETECT

In receiver applications, it is desirable to have a mechanism to The operation of the upper threshold and lower threshold registers,
reliably determine when the converter is about to be clipped. along with the dwell time registers, is shown in Figure 61.
The standard overrange bit, available via the STATUS±/OVR± The FD_x indicator is asserted if the input magnitude exceeds
pins, provides information on the state of the analog input the value programmed in the fast detect upper threshold
that is of limited usefulness. Therefore, it is helpful to have a registers, located in Register 0x247 and Register 0x248. The
programmable threshold below full scale that allows time to selected threshold register is compared with the signal
reduce the gain before the clip actually occurs. In addition, magnitude at the output of the ADC. The fast upper threshold
because input signals can have significant slew rates, the latency detection has a latency of 28 clock cycles. The approximate
of this function is of major concern. Highly pipelined converters upper threshold magnitude is defined by
can have significant latency. The AD6679 contains fast detect
circuitry for individual channels to monitor the threshold and Upper Threshold Magnitude (dBFS) = 20log(Threshold
assert the FD_A and FD_B pins. Magnitude/213)
The FD_x indicators are not cleared until the signal drops
ADC OVERRANGE (OR)
below the lower threshold for the programmed dwell time. The
The ADC overrange indicator is asserted when an overrange is lower threshold is programmed in the fast detect lower thresh-
detected on the input of the ADC. The overrange indicator can old registers, located in Register 0x249 and Register 0x24A. The
be output via the STATUS± pins. The latency of this overrange fast detect lower threshold register is a 13-bit register that is
indicator matches the sample latency. compared with the signal magnitude at the output of the ADC.
The AD6679 constantly monitors the analog input level and This comparison is subject to the ADC pipeline latency but is
records any overrange condition in any of the eight virtual accurate in terms of converter resolution. The lower threshold
converters. For more information on the virtual converters, magnitude is defined by
refer to Figure 63. The overrange status of each virtual converter Lower Threshold Magnitude (dBFS) = 20log(Threshold
is registered as a sticky bit (that is, it is set until cleared) in Magnitude/213)
Register 0x563. The contents of Register 0x563 can be cleared
using Register 0x562 by toggling the bits corresponding to the For example, to set an upper threshold of −6 dBFS, write
virtual converter to set and reset the position. 0x0FFF to Register 0x247 and Register 0x248; and to set a lower
threshold of −10 dBFS, write 0x0A1D to Register 0x249 and
FAST THRESHOLD DETECTION (FD_A AND FD_B) Register 0x24A.
The fast detect (FD) bit (enabled in the control bits via The dwell time can be programmed from 1 to 65,535 sample
Register 0x559) is set whenever the absolute value of the input clock cycles by placing the desired value in the fast detect dwell
signal exceeds the programmable upper threshold level. The FD time registers, located in Register 0x24B and Register 0x24C.
bit is cleared only when the absolute value of the input signal See the Memory Map section (Register 0x245 to Register 0x24C in
drops below the lower threshold level for greater than the Table 41) for more details.
programmable dwell time. This feature provides hysteresis and
prevents the FD bit from excessively toggling.

UPPER THRESHOLD

DWELL TIME

TIMER RESET BY
RISE ABOVE
LOWER LOWER THRESHOLD
THRESHOLD
MIDSCALE

DWELL TIME TIMER COMPLETES BEFORE

13059-059

SIGNAL RISES ABOVE

FD_A OR FD_B LOWER THRESHOLD

Figure 61. Threshold Settings for FD_A and FD_B Signals

Rev. B | Page 38 of 81
Data Sheet AD6679

SIGNAL MONITOR
The signal monitor block provides additional information about SMPR are supported. The peak detector function is enabled by
the signal being digitized by the ADC. The signal monitor setting Bit 1 of Register 0x270 in the signal monitor control
computes the peak magnitude of the digitized signal. This register. The 24-bit SMPR must be programmed before
information can be used to drive an AGC loop to optimize the activating this mode.
range of the ADC in the presence of real-world signals. After enabling this mode, the value in the SMPR is loaded into a
The results of the signal monitor block can be obtained by monitor period timer that decrements at the decimated clock
reading back the internal values from the SPI port. A global, 24- rate. The magnitude of the input signal is compared with the
bit programmable period controls the duration of the measure- value in the internal magnitude storage register (not accessible
ment. Figure 62 shows the simplified block diagram of the to the user), and the greater of the two is updated as the current
signal monitor block. peak level. The initial value of the magnitude storage register is
The peak detector captures the largest signal within the set to the current ADC input signal magnitude. This comparison
observation period. This period observes only the magnitude of continues until the monitor period timer reaches a count of 1.
the signal. The resolution of the peak detector is a 13-bit value When the monitor period timer reaches a count of 1, the 13-bit
and the observation period is 24 bits and represents converter peak level value is transferred to the signal monitor holding
output samples. The peak magnitude is derived by using the register, which can be read through the memory map. The
following equation: monitor period timer is reloaded with the value in the SMPR,
Peak Magnitude (dBFS) = 20 log(Peak Detector Value/213) and the countdown is restarted. In addition, the magnitude of
the first input sample is updated in the internal magnitude
The magnitude of the input port signal is monitored over a storage register, and the comparison and update procedure, as
programmable time period that is determined by the signal explained previously, continues.
monitor period registers (SMPRs). Only even values of the

SIGNAL MONITOR
FROM PERIOD REGISTER DOWN IS
MEMORY (SMPR) COUNTER COUNT = 1?
MAP REG 0x271, REG 0x272, REG 0x273
LOAD

CLEAR LOAD
FROM MAGNITUDE SIGNAL TO STATUS± PINS
INPUT STORAGE MONITOR AND MEMORY MAP
REGISTER HOLDING
REGISTER
LOAD
13059-060

COMPARE
A>B

Figure 62. Signal Monitor Block

Rev. B | Page 39 of 81
AD6679 Data Sheet

DIGITAL DOWNCONVERTER (DDC)

The AD6679 includes four digital downconverters (DDCs) that to use both DDC Output Port I and DDC Output Port Q. For
provide filtering and reduce the output data rate. This digital more information, see Figure 71.
processing section includes an NCO, up to four half-band
DDC GENERAL DESCRIPTION
decimating filter, a finite impulse response (FIR) filter, a gain
stage, and a complex to real conversion stage. Each of these The four DDC blocks extract a portion of the full digital
processing blocks has control lines that allow it to be spectrum captured by the ADC(s). They are intended for IF
independently enabled and disabled to provide the desired sampling or oversampled baseband radios requiring wide
processing function. The DDC can be configured to output bandwidth input signals.
either real data or complex output data. Each DDC block contains the following signal processing
stages:
DDC I/Q INPUT SELECTION
The AD6679 has two ADC channels and four DDC channels.  Frequency translation stage (optional)
Each DDC channel has two input ports that can be paired to  Filtering stage
support both real and complex inputs through the I/Q crossbar  Gain stage (optional)
mux. For real signals, both DDC input ports must select the  Complex to real conversion stage (optional)
same ADC channel (that is, DDC Input Port I = ADC Channel A
Frequency Translation Stage (Optional)
and DDC Input Port Q = ADC Channel A). For complex signals,
each DDC input port must select different ADC channels (that This stage consists of a 12-bit complex NCO and quadrature
is, DDC Input Port I = ADC Channel A and DDC Input Port Q mixers that can be used for frequency translation of both real
= ADC Channel B). and complex input signals. This stage shifts a portion of the
available digital spectrum down to baseband.
The inputs to each DDC are controlled by the DDC input selec-
tion registers (Register 0x311, Register 0x331, Register 0x351, and Filtering Stage
Register 0x371). See Table 41 for information on how to After shifting down to baseband, this stage decimates the
configure the DDCs. frequency spectrum using a chain of up to four half-band low-
pass filters for rate conversion. The decimation process lowers
DDC I/Q OUTPUT SELECTION the output data rate, which, in turn, reduces the output interface
Each DDC channel has two output ports that can be paired to rate.
support both real and complex outputs. For real output signals,
Gain Stage (Optional)
only the DDC Output Port I is used (the DDC Output Port Q is
invalid). For complex I/Q output signals, both DDC Output Due to losses associated with mixing a real input signal down to
Port I and DDC Output Port Q are used. baseband, this stage compensates by adding an additional 0 dB
or 6 dB of gain.
The I/Q outputs to each DDC channel are controlled by the
DDC complex to real enable bit, Bit 3, in the DDC control Complex to Real Conversion Stage (Optional)
registers (Register 0x310, Register 0x330, Register 0x350, and When real outputs are necessary, this stage converts the
Register 0x370). complex outputs back to real outputs by performing an fS/4
The Chip Q ignore bit in the chip mode register (Register 0x200, mixing operation together with a filter to remove the complex
Bit 5) controls the chip output muxing of all the DDC channels. component of the signal.
When all DDC channels use real outputs, set this bit high to Figure 63 shows the detailed block diagram of the DDCs
ignore all DDC Q output ports. When any of the DDC channels implemented in the AD6679.
are set to use complex I/Q outputs, the user must clear this bit

Rev. B | Page 40 of 81
Data Sheet AD6679
DDC 0

DCM = BYPASS OR 2

DCM = BYPASS OR 2

DCM = BYPASS OR 2

COMPLEX TO REAL
REAL/I I REAL/I
CONVERTER 0

CONVERSION
(OPTIONAL)
GAIN = 0dB
DCM = 2
NCO

HB4 FIR

HB3 FIR

HB2 FIR

HB1 FIR

OR 6dB
+
MIXER
(OPTIONAL)
REAL/Q Q Q CONVERTER 1

ADC
REAL/I SAMPLING SYNC±
AT fS
DDC 1

DCM = BYPASS OR 2

DCM = BYPASS OR 2

DCM = BYPASS OR 2

COMPLEX TO REAL
REAL/I I REAL/I
CONVERTER 2

CONVERSION
(OPTIONAL)
GAIN = 0dB
DCM = 2
NCO

HB4 FIR

HB3 FIR

HB2 FIR

HB1 FIR

OR 6dB
+
MIXER
(OPTIONAL)

OUTPUT INTERFACE
I/Q CROSSBAR MUX

REAL/Q Q Q CONVERTER 3

SYNC±

DDC 2
DCM = BYPASS OR 2

DCM = BYPASS OR 2

DCM = BYPASS OR 2

COMPLEX TO REAL
REAL/I I REAL/I
CONVERTER 4

CONVERSION
(OPTIONAL)
GAIN = 0dB
DCM = 2
NCO
HB4 FIR

HB3 FIR

HB2 FIR

HB1 FIR

OR 6dB
+
MIXER
(OPTIONAL)
REAL/Q Q Q CONVERTER 5

ADC
REAL/I SAMPLING
AT fS SYNC±

DDC 3
DCM = BYPASS OR 2

DCM = BYPASS OR 2

DCM = BYPASS OR 2

COMPLEX TO REAL
REAL/I I REAL/I
CONVERTER 6

CONVERSION
(OPTIONAL)
GAIN = 0dB
DCM = 2

NCO
HB4 FIR

HB3 FIR

HB2 FIR

HB1 FIR

OR 6dB
+
MIXER
(OPTIONAL)
REAL/Q Q Q CONVERTER 7

13059-061
SYNC± SYNCHRONIZATION SYNC
CONTROL CIRCUITS

Figure 63. DDC Detailed Block Diagram

Figure 64 shows an example usage of one of the four DDC If the DDC soft reset is not issued, the output may potentially
blocks with a real input signal and four half-band filters (HB4 + show amplitude variations.
HB3 + HB2 + HB1). It shows both complex (decimate by 16) Table 13 through Table 17 show the DDC samples when the
and real (decimate by 8) output options. chip decimation ratio is set to 1, 2, 4, 8, or 16, respectively.
When DDCs have different decimation ratios, the chip When DDCs have different decimation ratios, the chip decimation
decimation ratio (Register 0x201) must be set to the lowest ratio must be set to the lowest decimation ratio of all the DDC
decimation ratio of all the DDC blocks. In this scenario, channels. In this scenario, samples of higher decimation ratio
samples of higher decimation ratio DDCs are repeated to match DDCs are repeated to match the chip decimation ratio sample
the chip decimation ratio sample rate. Whenever the NCO rate.
frequency is set or changed, the DDC soft reset must be issued.

Rev. B | Page 41 of 81
AD6679 Data Sheet

ADC REAL ADC REAL

SAMPLING
REAL INPUT—SAMPLED AT fS AT fS
BANDWIDTH OF BANDWIDTH OF
INTEREST IMAGE INTEREST

–fS/32 fS/32
–fS/2 –fS/3 –fS/4 –fS/8 –fS/16 DC fS/16 fS/8 fS/4 fS/3 fS/2

FREQUENCY TRANSLATION STAGE (OPTIONAL)

DIGITAL MIXER + NCO FOR fS/3 TUNING, THE FREQUENCY I
TUNING WORD = ROUND ((fS/3)/fS × 4096) = +1365 (0x555) NCO TUNES CENTER OF
BANDWIDTH OF INTEREST
cos(wt) TO BASEBAND
REAL 12-BIT 90°
NCO 0°
–sin(wt)
Q

BANDWIDTH OF
DIGITAL FILTER INTEREST IMAGE
RESPONSE BANDWIDTH OF INTEREST (–6dB LOSS DUE TO
(–6dB LOSS DUE TO NCO + MIXER)
NCO + MIXER)

–fS/32 fS/32
–fS/2 –fS/3 –fS/4 –fS/8 –fS/16 DC fS/16 fS/8 fS/4 fS/3 fS/2

FILTERING STAGE
HB4 FIR HB3 FIR HB2 FIR HB1 FIR
4 DIGITAL HALF-BAND FILTERS
(HB4 + HB3 + HB2 + HB1) HALF- HALF- HALF- HALF-
BAND BAND BAND BAND
I FILTER FILTER FILTER FILTER
I
2 2 2

HB4 FIR HB3 FIR HB2 FIR HB1 FIR

HALF- HALF- HALF- HALF-
BAND BAND BAND BAND
Q FILTER FILTER FILTER FILTER
Q
2 2 2
6dB GAIN TO
COMPENSATE FOR
NCO + MIXER LOSS
COMPLEX (I/Q) OUTPUTS
GAIN STAGE (OPTIONAL) DECIMATE BY 16
DIGITAL FILTER
RESPONSE 0dB OR 6dB GAIN
I I
2 +6dB

GAIN STAGE (OPTIONAL) Q

2
Q
+6dB
0dB OR 6dB GAIN
–fS/32 fS/32 –fS/32 fS/32
COMPLEX TO REAL –fS/8 –fS/16 DC fS/16 fS/8 –fS/16 DC fS/16
CONVERSION STAGE (OPTIONAL)
DOWNSAMPLE BY 2
fS/4 MIXING + COMPLEX FILTER TO REMOVE Q
I I
REAL (I) OUTPUTS +6dB

DECIMATE BY 8 COMPLEX REAL/I

TO
REAL
Q Q
+6dB

6dB GAIN TO
COMPENSATE FOR
NCO + MIXER LOSS
13059-062

–fS/32 fS/32
–fS/8 –fS/16 DC fS/16 fS/8

Figure 64. DDC Theory of Operation Example (Real Input, Decimate by 16)

Rev. B | Page 42 of 81
Data Sheet AD6679
Table 13. DDC Samples When Chip Decimation Ratio = 1
Real (I) Output (Complex to Real Enabled) Complex (I/Q) Outputs (Complex to Real Disabled)
HB1 FIR HB2 FIR + HB3 FIR + HB2 HB4 FIR + HB3 FIR + HB2 FIR + HB3 FIR + HB2 HB4 FIR + HB3 FIR +
(DCM 1 = HB1 FIR FIR + HB1 FIR HB2 FIR + HB1 FIR HB1 FIR HB1 FIR FIR + HB1 FIR HB2 FIR + HB1 FIR
1) (DCM1 = 2) (DCM1 = 4) (DCM1 = 8) (DCM1 = 2) (DCM1 = 4) (DCM1 = 8) (DCM1 = 16)
N N N N N N N N
N+1 N+1 N+1 N+1 N+1 N+1 N+1 N+1
N+2 N N N N N N N
N+3 N+1 N+1 N+1 N+1 N+1 N+1 N+1
N+4 N+2 N N N+2 N N N
N+5 N+3 N+1 N+1 N+3 N+1 N+1 N+1
N+6 N+2 N N N+2 N N N
N+7 N+3 N+1 N+1 N+3 N+1 N+1 N+1
N+8 N+4 N+2 N N+4 N+2 N N
N+9 N+5 N+3 N+1 N+5 N+3 N+1 N+1
N + 10 N+4 N+2 N N+4 N+2 N N
N + 11 N+5 N+3 N+1 N+5 N+3 N+1 N+1
N + 12 N+6 N+2 N N+6 N+2 N N
N + 13 N+7 N+3 N+1 N+7 N+3 N+1 N+1
N + 14 N+6 N+2 N N+6 N+2 N N
N + 15 N+7 N+3 N+1 N+7 N+3 N+1 N+1
N + 16 N+8 N+4 N+2 N+8 N+4 N+2 N
N + 17 N+9 N+5 N+3 N+9 N+5 N+3 N+1
N + 18 N+8 N+4 N+2 N+8 N+4 N+2 N
N + 19 N+9 N+5 N+3 N+9 N+5 N+3 N+1
N + 20 N + 10 N+4 N+2 N + 10 N+4 N+2 N
N + 21 N + 11 N+5 N+3 N + 11 N+5 N+3 N+1
N + 22 N + 10 N+4 N+2 N + 10 N+4 N+2 N
N + 23 N + 11 N+5 N+3 N + 11 N+5 N+3 N+1
N + 24 N + 12 N+6 N+2 N + 12 N+6 N+2 N
N + 25 N + 13 N+7 N+3 N + 13 N+7 N+3 N+1
N + 26 N + 12 N+6 N+2 N + 12 N+6 N+2 N
N + 27 N + 13 N+7 N+3 N + 13 N+7 N+3 N+1
N + 28 N + 14 N+6 N+2 N + 14 N+6 N+2 N
N + 29 N + 15 N+7 N+3 N + 15 N+7 N+3 N+1
N + 30 N + 14 N+6 N+2 N + 14 N+6 N+2 N
N + 31 N + 15 N+7 N+3 N + 15 N+7 N+3 N+1
1
DCM means decimation.

Table 14. DDC Samples When Chip Decimation Ratio = 2

Real (I) Output (Complex to Real Enabled) Complex (I/Q) Outputs (Complex to Real Disabled)
HB4 FIR + HB4 FIR +
HB3 FIR + HB3 FIR + HB3 FIR + HB3 FIR +
HB2 FIR + HB2 FIR + HB2 FIR + HB2 FIR + HB2 FIR + HB2 FIR +
HB1 FIR HB1 FIR HB1 FIR HB1 FIR HB1 FIR HB1 FIR HB1 FIR
(DCM 1 = 2) (DCM1 = 4) (DCM1 = 8) (DCM1 = 2) (DCM1 = 4) (DCM1 = 8) (DCM1 = 16)
N N N N N N N
N+1 N+1 N+1 N+1 N+1 N+1 N+1
N+2 N N N+2 N N N
N+3 N+1 N+1 N+3 N+1 N+1 N+1
N+4 N+2 N N+4 N+2 N N
N+5 N+3 N+1 N+5 N+3 N+1 N+1
N+6 N+2 N N+6 N+2 N N
N+7 N+3 N+1 N+7 N+3 N+1 N+1
N+8 N+4 N+2 N+8 N+4 N+2 N
N+9 N+5 N+3 N+9 N+5 N+3 N+1
Rev. B | Page 43 of 81
AD6679 Data Sheet
Real (I) Output (Complex to Real Enabled) Complex (I/Q) Outputs (Complex to Real Disabled)
HB4 FIR + HB4 FIR +
HB3 FIR + HB3 FIR + HB3 FIR + HB3 FIR +
HB2 FIR + HB2 FIR + HB2 FIR + HB2 FIR + HB2 FIR + HB2 FIR +
HB1 FIR HB1 FIR HB1 FIR HB1 FIR HB1 FIR HB1 FIR HB1 FIR
(DCM 1 = 2) (DCM1 = 4) (DCM1 = 8) (DCM1 = 2) (DCM1 = 4) (DCM1 = 8) (DCM1 = 16)
N + 10 N+4 N+2 N + 10 N+4 N+2 N
N + 11 N+5 N+3 N + 11 N+5 N+3 N+1
N + 12 N+6 N+2 N + 12 N+6 N+2 N
N + 13 N+7 N+3 N + 13 N+7 N+3 N+1
N + 14 N+6 N+2 N + 14 N+6 N+2 N
N + 15 N+7 N+3 N + 15 N+7 N+3 N+1
1
DCM means decimation.

Table 15. DDC Samples When Chip Decimation Ratio = 4

Real (I) Output (Complex to Real Enabled) Complex (I/Q) Outputs (Complex to Real Disabled)
HB4 FIR + HB3 FIR + HB4 FIR + HB3 FIR +
HB3 FIR + HB2 FIR + HB2 FIR + HB1 FIR HB2 FIR + HB1 FIR HB3 FIR + HB2 FIR + HB2 FIR + HB1 FIR
HB1 FIR (DCM 1 = 4) (DCM1 = 8) (DCM1 = 4) HB1 FIR (DCM1 = 8) (DCM1 = 16)
N N N N N
N+1 N+1 N+1 N+1 N+1
N+2 N N+2 N N
N+3 N+1 N+3 N+1 N+1
N+4 N+2 N+4 N+2 N
N+5 N+3 N+5 N+3 N+1
N+6 N+2 N+6 N+2 N
N+7 N+3 N+7 N+3 N+1
1
DCM means decimation.

Table 16. DDC Samples When Chip Decimation Ratio = 8

Real (I) Output (Complex to Real Enabled) Complex (I/Q) Outputs (Complex to Real Disabled)
HB3 FIR + HB2 FIR + HB1 FIR HB4 FIR + HB3 FIR + HB2 FIR +
HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR (DCM 1 = 8) (DCM1 = 8) HB1 FIR (DCM1 = 16)
N N N
N+1 N+1 N+1
N+2 N+2 N
N+3 N+3 N+1
N+4 N+4 N+2
N+5 N+5 N+3
N+6 N+6 N+2
N+7 N+7 N+3
1
DCM means decimation.

Table 17. DDC Samples When Chip Decimation Ratio = 16

Real (I) Output (Complex to Real Enabled) Complex (I/Q) Outputs (Complex to Real Disabled)
HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR (DCM 1 = 16) HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR (DCM1 = 16)
Not applicable N
Not applicable N+1
Not applicable N+2
Not applicable N+3
1
DCM means decimation.

Rev. B | Page 44 of 81
Data Sheet AD6679
For example, if the chip decimation ratio is set to decimate by 4, (real outputs, decimate by 8). DDC 1 repeats its output data two
DDC 0 is set to use HB2 + HB1 filters (complex outputs, decimate times for every one DDC 0 output. The resulting output samples
by 4) and DDC 1 is set to use HB4 + HB3 + HB2 + HB1 filters are shown in Table 18.

Table 18. DDC Output Samples When Chip DCM 1 = 4, DDC 0 DCM1 = 4 (Complex), and DDC 1 DCM1 = 8 (Real)
DDC 0 DDC 1
DDC Input Samples Output Port I Output Port Q Output Port I Output Port Q
N I0 (N) Q0 (N) I1 (N) Not applicable
N+1
N+2
N+3
N+4 I0 (N + 1) Q0 (N + 1)
N+5
N+6
N+7
N+8 I0 (N + 2) Q0 (N + 2) I1 (N + 1) Not applicable
N+9
N + 10
N + 11
N + 12 I0 (N + 3) Q0 (N + 3)
N + 13
N + 14
N + 15
1
DCM means decimation.

Rev. B | Page 45 of 81
AD6679 Data Sheet

FREQUENCY TRANSLATION
GENERAL DESCRIPTION Variable IF Mode
Frequency translation is accomplished by using a 12-bit The NCO and the mixers are enabled. The NCO output
complex NCO with a digital quadrature mixer. This stage frequency can be used to digitally tune the IF frequency.
translates either a real or complex input signal from an IF to a 0 Hz IF (ZIF) Mode
baseband complex digital output (carrier frequency = 0 Hz).
The mixers are bypassed, and the NCO is disabled.
The frequency translation stage of each DDC can be controlled
fS/4 Hz IF Mode
individually and supports four different IF modes using Bits[5:4]
of the DDC control registers (Register 0x310, Register 0x330, The mixers and the NCO are enabled in a special downmixing
Register 0x350, and Register 0x370). These IF modes are by fS/4 mode to save power.

 Variable IF mode Test Mode

 0 Hz IF, or zero IF (ZIF), mode The input samples are forced to 0.999 to positive full scale. The
 fS/4 Hz IF mode NCO is enabled. This test mode allows the NCOs to drive the
 Test mode decimation filters directly.
Figure 65 and Figure 66 show examples of the frequency
translation stage for both real and complex inputs.

NCO FREQUENCY TUNING WORD (FTW) SELECTION

12-BIT NCO FTW = MIXING FREQUENCY/ADC SAMPLE RATE × 4096

cos(wt)
ADC + DIGITAL MIXER + NCO REAL ADC REAL 12-BIT 90°
SAMPLING COMPLEX
REAL INPUT—SAMPLED AT fS AT fS
NCO 0°
–sin(wt)
Q

BANDWIDTH OF BANDWIDTH OF
INTEREST IMAGE INTEREST

–fS/32 fS/32
–fS/2 –fS/3 –fS/4 –fS/8 –fS/16 DC fS/16 fS/8 fS/4 fS/3 fS/2

–6dB LOSS DUE TO

NCO + MIXER

POSITIVE FTW VALUES 12-BIT NCO FTW =

ROUND ((fS/3)/fS × 4096) = +1365 (0x555)

–fS/32 fS/32
DC

12-BIT NCO FTW =

ROUND ((fS/3)/fS × 4096) = –1365 (0xAAB) NEGATIVE FTW VALUES
13059-063

–fS/32 fS/32
DC

Figure 65. DDC NCO Frequency Tuning Word Selection—Real Inputs

Rev. B | Page 46 of 81
Data Sheet AD6679
NCO FREQUENCY TUNING WORD (FTW) SELECTION
12-BIT NCO FTW = MIXING FREQUENCY/ADC SAMPLE RATE × 4096

ADC QUADRATURE MIXER

I I I + I
SAMPLING
AT fS I –
Q

QUADRATURE ANALOG MIXER + Q

–sin(wt)
2 ADCs + QUADRATURE DIGITAL REAL 90° 12-BIT 90°
MIXER + NCO PHASE NCO 0° COMPLEX
COMPLEX INPUT—SAMPLED AT fS Q

I
Q ADC Q Q
I + Q
SAMPLING
+
AT fS

BANDWIDTH OF
INTEREST
IMAGE DUE TO
ANALOG I/Q
MISMATCH

–fS/32 fS/32
–fS/2 –fS/3 –fS/4 –fS/8 –fS/16 DC fS/16 fS/8 fS/4 fS/3 fS/2

12-BIT NCO FTW =

POSITIVE FTW VALUES ROUND ((fS/3)/fS × 4096) = +1365 (0x555)

–fS/32 fS/32

13059-064
DC

Figure 66. DDC NCO Frequency Tuning Word Selection—Complex Inputs

DDC NCO PLUS MIXER LOSS AND SFDR Setting Up the NCO FTW and POW
When mixing a real input signal down to baseband, 6 dB of loss The NCO frequency value is given by the 12-bit, twos
is introduced in the signal due to filtering of the negative image. complement number entered in the NCO FTW. Frequencies
The NCO introduces an additional 0.05 dB of loss. The total between −fS/2 and +fS/2 (fS/2 excluded) are represented using
loss of a real input signal mixed down to baseband is 6.05 dB. the following frequency words:
For this reason, it is recommended to compensate for this loss  0x800 represents a frequency of −fS/2.
by enabling the 6 dB of gain in the gain stage of the DDC to  0x000 represents dc (frequency is 0 Hz).
recenter the dynamic range of the signal within the full scale of
 0x7FF represents a frequency of +fS/2 − fS/212.
the output bits.
Calculate the NCO frequency tuning word using the following
When mixing a complex input signal down to baseband, the
equation:
maximum value each I/Q sample can reach is 1.414 × full scale
after it passes through the complex mixer. To avoid an  mod  f C , f S  
NCO _ FTW  round  2 12 

overrange of the I/Q samples and to keep the data bit-widths  fS 
aligned with real mixing, 3.06 dB of loss is introduced in the
mixer for complex signals. The NCO introduces an additional where:
0.05 dB of loss. The total loss of a complex input signal mixed NCO_FTW is a 12-bit, twos complement number representing
down to baseband is −3.11 dB. the NCO FTW.
fC is the desired carrier frequency in Hz.
The worst case spurious signal from the NCO is greater than fS is the AD6679 sampling frequency (clock rate) in Hz.
102 dBc SFDR for all output frequencies. mod( ) is a remainder function. For example, mod(110,100) =
NUMERICALLY CONTROLLED OSCILLATOR 10 and for negative numbers, mod(−32,10) = −2.
The AD6679 has a 12-bit NCO for each DDC that enables the round( ) is a rounding function. For example, round(3.6) = 4
and for negative numbers, round(−3.4) = −3.
frequency translation process. The NCO allows the input
spectrum to be tuned to dc, where it can be effectively filtered Note that this equation applies to the aliasing of signals in the
by the subsequent filter blocks to prevent aliasing. The NCO digital domain (that is, aliasing introduced when digitizing
can be set up by providing a frequency tuning word (FTW) and analog signals).
a phase offset word (POW).

Rev. B | Page 47 of 81
AD6679 Data Sheet
For example, if the ADC sampling frequency (fS) is 500 MSPS Use the following two methods to synchronize multiple PAWs
and the carrier frequency (fC) is 140.312 MHz, then within the chip:
 mod140.312,500   Using the SPI. Use the DDC NCO soft reset bit in the DDC
NCO _ FTW  round 212   1149 MHz
 500  synchronization control register (Register 0x300, Bit 4) to
reset all the PAWs in the chip. This is accomplished by
This, in turn, converts to 0x47D in the 12-bit twos complement setting the DDC NCO soft reset bit high and then setting
representation for NCO_FTW. Calculate the actual carrier this bit low. Note that this method synchronizes DDC
frequency, fC_ACTUAL, based on the following equation: channels within the same AD6679 chip only.
NCO_ FTW f S  Using the SYNC± pins. When the SYNC± pins are
fC _ ACTUAL   140.26 MHz enabled in the SYNC± control registers (Register 0x120
212
and Register 0x121) and the DDC synchronization is
A 12-bit POW is available for each NCO to create a known
enabled in the DDC synchronization control register
phase relationship between multiple AD6679 chips or
(Register 0x300, Bits[1:0]), any subsequent SYNC± event
individual DDC channels inside one AD6679 chip.
resets all the PAWs in the chip. Note that this method
The following procedure must be followed to update the FTW synchronizes DDC channels within the same AD6679 chip
and/or POW registers to ensure proper operation of the NCO: or DDC channels within separate AD6679 chips.
1. Write to the FTW registers for all the DDCs. Mixer
2. Write to the POW registers for all the DDCs.
The NCO is accompanied by a mixer. Its operation is similar to
3. Synchronize the NCOs either through the DDC NCO soft
an analog quadrature mixer. It performs the downconversion of
reset bit (Register 0x300, Bit 4), accessible through the SPI
input signals (real or complex) by using the NCO frequency as a
or through the assertion of the SYNC± pin.
local oscillator. For real input signals, this mixer performs a real
It is important to note that the NCOs must be synchronized mixer operation (with two multipliers). For complex input
either through the SPI or through the SYNC± pin after all signals, the mixer performs a complex mixer operation (with
writes to the FTW or POW registers are complete. This four multipliers and two adders). The mixer adjusts its
synchronization is necessary to ensure the proper operation operation based on the input signal (real or complex) provided
of the NCO. to each individual channel. The selection of real or complex
NCO Synchronization inputs can be controlled individually for each DDC block using
Bit 7 of the DDC control registers (Register 0x310, Register 0x330,
Each NCO contains a separate phase accumulator word (PAW)
Register 0x350, and Register 0x370).
that determines the instantaneous phase of the NCO. The initial
reset value of each PAW is determined by the POW. The phase
increment value of each PAW is determined by the FTW. See
the Setting Up the NCO FTW and POW section for more
information.

Rev. B | Page 48 of 81
Data Sheet AD6679

FIR FILTERS
OVERVIEW tion that is optimized for low power consumption. The HB4
There are four sets of decimate by 2, low-pass, half-band, FIR filter is used only when complex outputs (decimate by 16) or
filters (labeled HB1 FIR, HB2 FIR, HB3 FIR, and HB4 FIR in real outputs (decimate by 8) are enabled; otherwise, it is
Figure 63) following the frequency translation stage. After the bypassed. Table 19 and Figure 67 show the coefficients and
carrier of interest is tuned down to dc (carrier frequency = response of the HB4 filter.
0 Hz), these filters efficiently lower the sample rate, while Table 19. HB4 Filter Coefficients
providing sufficient alias rejection from unwanted adjacent HB4 Coefficient Normalized Decimal
carriers around the bandwidth of interest. Number Coefficient Coefficient (15-Bit)
HB1 FIR is always enabled and cannot be bypassed. The HB2, C1, C11 0.006042 99
HB3, and HB4 FIR filters are optional and can be bypassed for C2, C10 0 0
higher output sample rates. C3, C9 −0.049316 −808
C4, C8 0 0
Table 20 shows the different bandwidths selectable by including
C5, C7 0.293273 4805
different half-band filters. In all cases, the DDC filtering stage
C6 0.500000 8192
on the AD6679 provides <−0.001 dB of pass-band ripple and
>100 dB of stop band alias rejection. 0

Table 21 shows the amount of stop-band alias rejection for

–20
multiple pass-band ripple/cutoff points. The decimation ratio of
the filtering stage of each DDC can be controlled individually
MAGNITUDE (dB)
–40
through Bits[1:0] of the DDC control registers (Register 0x310,
Register 0x330, Register 0x350, and Register 0x370). –60

HALF-BAND FILTERS –80

The AD6679 offers four half-band filters to enable digital signal
processing of the ADC converted data. These half-band filters –100

are bypassable and can be individually selected.

–120
HB4 Filter

13059-065
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
The first decimate by 2, half-band, low-pass, FIR filter (HB4) NORMALIZED FREQUENCY (× π RAD/SAMPLE)

uses an 11-tap, symmetrical, fixed coefficient filter implementa- Figure 67. HB4 Filter Response

Table 20. DDC Filter Characteristics

ADC Real Output Complex (I/Q) Output Alias Pass-
Sample Output Decima- Protected Ideal SNR Band Alias
Rate Half Band Filter Decima- Sample Rate tion Output Sample Bandwidth Improve- Ripple Rejection
(MSPS) Selection tion Ratio (MSPS) Ratio Rate (MSPS) (MHz) ment 1 (dB) (dB) (dB)
500 HB1 1 500 2 250 (I) + 250 (Q) 192.5 1 <−0.001 >100
HB1 + HB2 2 250 4 125 (I) + 125 (Q) 96.3 4
HB1 + HB2 + HB3 4 125 8 62.5 (I) + 62.5 (Q) 48.1 7
HB1 + HB2 + HB3 8 62.5 16 31.25 (I) + 31.25 (Q) 24.1 10
+ HB4
1
Ideal SNR improvement due to oversampling and filtering = 10log(bandwidth/(fS/2)).
Table 21. DDC Filter Alias Rejection
Alias Rejection Pass-Band Ripple/Cutoff Alias Protected Bandwidth for Real Alias Protected Bandwidth for Complex
(dB) Point (dB) (I) Outputs 1 (I/Q) Outputs
>100 <−0.001 <38.5% × fOUT <77% × fOUT
90 <−0.001 <38.7% × fOUT <77.4% × fOUT
85 <−0.001 <38.9% × fOUT <77.8% × fOUT
63.3 <−0.006 <40% × fOUT <80% × fOUT
25 −0.5 44.4% × fOUT 88.8% × fOUT
19.3 −1.0 45.6% × fOUT 91.2% × fOUT
10.7 −3.0 48% × fOUT 96% × fOUT
1
fOUT = ADC input sample rate ÷ DDC decimation.

Rev. B | Page 49 of 81
AD6679 Data Sheet
HB3 Filter 0

The second decimate by 2, half-band, low-pass, FIR filter (HB3)

–20
uses an 11-tap, symmetrical, fixed coefficient filter implementa-
tion that is optimized for low power consumption. The HB3

MAGNITUDE (dB)
–40
filter is only used when complex outputs (decimate by 8 or 16)
or real outputs (decimate by 4 or 8) are enabled; otherwise, it is –60
bypassed. Table 22 and Figure 68 show the coefficients and
response of the HB3 filter. –80

Table 22. HB3 Filter Coefficients –100

HB3 Coefficient Normalized Decimal Coefficient
Number Coefficient (18-Bit) –120
C1, C11 0.006554 859

13059-067
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
C2, C10 0 0 NORMALIZED FREQUENCY (× π RAD/SAMPLE)

C3, C9 −0.050819 −6661 Figure 69. HB2 Filter Response

C4, C8 0 0
HB1 Filter
C5, C7 0.294266 38,570
C6 0.500000 65,536 The fourth and final decimate by 2, half-band, low-pass, FIR
filter (HB1) uses a 55-tap, symmetrical, fixed coefficient filter
0
implementation that is optimized for low power consumption.
–20 The HB1 filter is always enabled and cannot be bypassed. Table 24
and Figure 70 show the coefficients and response of the HB1 filter.
MAGNITUDE (dB)

–40
Table 24. HB1 Filter Coefficients
–60 HB1 Coefficient Normalized Decimal
Number Coefficient Coefficient (21-Bit)
–80 C1, C55 −0.000023 −24
C2, C54 0 0
–100 C3, C53 0.000097 102
C4, C52 0 0
–120
C5, C51 −0.000288 −302
13059-066

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

C6, C50 0 0
NORMALIZED FREQUENCY (× π RAD/SAMPLE)
C7, C49 0.000696 730
Figure 68. HB3 Filter Response
C8, C48 0 0
HB2 Filter C9, C47 −0.0014725 −1544
The third decimate by 2, half-band, low-pass, FIR filter (HB2) C10, C46 0 0
uses a 19-tap, symmetrical, fixed coefficient filter implementa- C11, C45 0.002827 2964
tion that is optimized for low power consumption. C12, C44 0 0
C13, C43 −0.005039 −5284
The HB2 filter is only used when complex or real outputs
C14, C42 0 0
(decimate by 4, 8, or 16) are enabled; otherwise, it is bypassed.
C15, C41 0.008491 8903
Table 23 and Figure 69 show the coefficients and response of C16, C40 0 0
the HB2 filter. C17, C39 −0.013717 −14,383
Table 23. HB2 Filter Coefficients C18, C38 0 0
HB2 Coefficient Normalized Decimal Coefficient C19, C37 0.021591 22,640
Number Coefficient (19-Bit) C20, C36 0 0
C1, C19 0.000614 161 C21, C35 −0.033833 −35,476
C2, C18 0 0 C22, C34 0 0
C3, C17 −0.005066 −1328 C23, C33 0.054806 57,468
C4, C16 0 0 C24, C32 0 0
C5, C15 0.022179 5814 C25, C31 −0.100557 −105,442
C6, C14 0 0 C26, C30 0 0
C7, C13 −0.073517 −19,272 C27, C29 0.316421 331,792
C8, C12 0 0 C28 0.500000 524,288
C9, C11 0.305786 80,160
C10 0.500000 131,072
Rev. B | Page 50 of 81
Data Sheet AD6679
0 DDC GAIN STAGE
Each DDC contains an independently controlled gain stage.
–20
The gain is selectable as either 0 dB or 6 dB. When mixing a real
input signal down to baseband, it is recommended that the user
MAGNITUDE (dB)

–40
enable the 6 dB of gain to recenter the dynamic range of the
–60 signal within the full scale of the output bits.
When mixing a complex input signal down to baseband, the
–80
mixer has already recentered the dynamic range of the signal
–100
within the full scale of the output bits, and no additional gain is
necessary. However, the optional 6 dB gain compensates for low
–120 signal strengths. The downsample by 2 portion of the HB1 FIR
filter is bypassed when using the complex to real conversion stage.

13059-068
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
NORMALIZED FREQUENCY (× π RAD/SAMPLE)
DDC COMPLEX TO REAL CONVERSION
Figure 70. HB1 Filter Response
Each DDC contains an independently controlled complex to
real conversion block. The complex to real conversion block
reuses the last filter (HB1 FIR) in the filtering stage along with
an fS/4 complex mixer to upconvert the signal. After upconvert-
ing the signal, the Q portion of the complex mixer is no longer
needed and is dropped.
Figure 71 shows a simplified block diagram of the complex to
real conversion.

HB1 FIR GAIN STAGE

COMPLEX TO
REAL ENABLE
LOW-PASS
FILTER
I 0dB I
2 OR 0 I/REAL
6dB
1

COMPLEX TO REAL CONVERSION

0dB I
OR
6dB
cos(wt)

fS/4 90° REAL

0°

–
sin(wt)
0dB Q
OR
6dB

LOW-PASS
Q FILTER 0dB Q Q
2 OR
6dB
13059-069

HB1 FIR

Figure 71. Complex to Real Conversion Block

Rev. B | Page 51 of 81
AD6679 Data Sheet
DDC EXAMPLE CONFIGURATIONS
Table 25 describes the register settings for multiple DDC example configurations.

Table 25. DDC Example Configurations

Chip Chip DDC DDC No. of Virtual
Application Decimation Input Output Bandwidth Converters
Layer Ratio Type Type Per DDC 1 Required Register Settings 2
One DDC 2 Complex Complex 38.5% × fS 2 Register 0x200 = 0x01 (one DDC; I/Q selected)
Register 0x201 = 0x01 (chip decimate by 2)
Register 0x310 = 0x83 (complex mixer, 0 dB gain,
variable IF, complex outputs, HB1 filter)
Register 0x311 = 0x04 (DDC I input = ADC
Channel A, DDC Q input = ADC Channel B)
Register 0x314, Register 0x315, Register 0x320,
Register 0x321 = FTW and POW set as required
by application for DDC 0
One DDC 4 Complex Complex 19.25% × fS 2 Register 0x200 = 0x01 (one DDC, I/Q selected)
Register 0x201 = 0x02 (chip decimate by 4)
Register 0x310= 0x80 (complex mixer, 0 dB gain,
variable IF, complex outputs, HB2 + HB1 filters)
Register 0x311 = 0x04 (DDC I input = ADC
Channel A, DDC Q input = ADC Channel B)
Register 0x314, Register 0x315= FTW and POW
set as required by application for DDC 0
Two DDCs 2 Real Real 19.25%× fS 2 Register 0x200 = 0x22 (two DDCs, I only selected)
Register 0x201 = 0x01 (chip decimate by 2)
Register 0x310, Register 0x330 = 0x48 (real mixer,
6 dB gain, variable IF, real output, HB2 + HB1
filters)
Register 0x311 = 0x00 (DDC 0 I input = ADC
Channel A, DDC 0 Q input = ADC Channel A)
Register 0x331 = 0x05 (DDC 1 I input = ADC
Channel B, DDC 1 Q input = ADC Channel B)
Register 0x314, Register 0x315, Register 0x320,
Register 0x321 = FTW and POW set as required
by application for DDC 0
Register 0x334, Register 0x335, Register 0x340,
Register 0x341 = FTW and POW set as required
by application for DDC 1
Two DDCs 2 Complex Complex 38.5%× fS 4 Register 0x200 = 0x22 (two DDCs, I only selected)
Register 0x201 = 0x01 (chip decimate by 2)
Register 0x310, Register 0x330 = 0x4B (complex
mixer, 6 dB gain, variable IF, complex output, HB1
filter)
Register 0x311, Register 0x331 = 0x04 (DDC 0
I input = ADC Channel A, DDC 0 Q input = ADC
Channel B)
Register 0x314, Register 0x315, Register 0x320,
Register 0x321 = FTW and POW set as required
by application for DDC 0
Register 0x334, Register 0x335, Register 0x340,
Register 0x341 = FTW and POW set as required
by application for DDC 1

Rev. B | Page 52 of 81
Data Sheet AD6679
Chip Chip DDC DDC No. of Virtual
Application Decimation Input Output Bandwidth Converters
Layer Ratio Type Type Per DDC 1 Required Register Settings 2
Two DDCs 4 Complex Complex 19.25% × fS 4 Register 0x200 = 0x02 (two DDCs, I/Q selected)
Register 0x201 = 0x02 (chip decimate by 4)
Register 0x310, Register 0x330 = 0x80 (complex
mixer, 0 dB gain, variable IF, complex outputs,
HB2 + HB1 filters)
Register 0x311, Register 0x331 = 0x04 (DDC I input
= ADC Channel A, DDC Q input = ADC Channel B)
Register 0x314, Register 0x315, Register 0x320,
Register 0x321 = FTW and POW set as required
by application for DDC 0
Register 0x334, Register 0x335, Register 0x340,
Register 0x341 = FTW and POW set as required
by application for DDC 1
Two DDCs 4 Complex Real 9.63% × fS 2 Register 0x200 = 0x22 (two DDCs, I only selected)
Register 0x201 = 0x02 (chip decimate by 4)
Register 0x310, Register 0x330 = 0x89 (complex
mixer, 0 dB gain, variable IF, real output, HB3 +
HB2 + HB1 filters)
Register 0x311, Register 0x331 = 0x04 (DDC I
input = ADC Channel A, DDC Q input = ADC
Channel B)
Register 0x314, Register 0x315, Register 0x320,
Register 0x321 = FTW and POW set as required
by application for DDC 0
Register 0x334, Register 0x335, Register 0x340,
Register 0x341 = FTW and POW set as required
by application for DDC 1
Two DDCs 4 Real Real 9.63% × fS 2 Register 0x200 = 0x22 (two DDCs, I only selected)
Register 0x201 = 0x02 (chip decimate by 4)
Register 0x310, Register 0x330 = 0x49 (real mixer,
6 dB gain, variable IF, real output, HB3 + HB2 +
HB1 filters)
Register 0x311 = 0x00 (DDC 0 I input = ADC
Channel A, DDC 0 Q input = ADC Channel A)
Register 0x331 = 0x05 (DDC 1 I input = ADC
Channel B, DDC 1 Q input = ADC Channel B)
Register 0x314, Register 0x315, Register 0x320,
Register 0x321 = FTW and POW set as required
by application for DDC 0
Register 0x334, Register 0x335, Register 0x340,
Register 0x341 = FTW and POW set as required
by application for DDC 1
Two DDCs 4 Real Complex 19.25% × fS 4 Register 0x200 = 0x02 (two DDCs, I/Q selected)
Register 0x201 = 0x02 (chip decimate by 4)
Register 0x310, Register 0x330 = 0x40 (real mixer,
6 dB gain, variable IF, complex output, HB2 +
HB1 filters)
Register 0x311 = 0x00 (DDC 0 I input = ADC
Channel A, DDC 0 Q input = ADC Channel A)
Register 0x331 = 0x05 (DDC 1 I input = ADC
Channel B, DDC 1 Q input = ADC Channel B)
Register 0x314, Register 0x315, Register 0x320,
Register 0x321 = FTW and POW set as required
by application for DDC 0
Register 0x334, Register 0x335, Register 0x340,
Register 0x341 = FTW and POW set as required
by application for DDC 1
Rev. B | Page 53 of 81
AD6679 Data Sheet
Chip Chip DDC DDC No. of Virtual
Application Decimation Input Output Bandwidth Converters
Layer Ratio Type Type Per DDC 1 Required Register Settings 2
Two DDCs 8 Real Real 4.81% × fS 2 Register 0x200 = 0x22 (two DDCs, I only selected)
Register 0x201 = 0x03 (chip decimate by 8)
Register 0x310, Register 0x330 = 0x4A (real
mixer, 6 dB gain, variable IF, real output, HB4 +
HB3 + HB2 + HB1 filters)
Register 0x311 = 0x00 (DDC 0 I input = ADC
Channel A, DDC 0 Q input = ADC Channel A)
Register 0x331 = 0x05 (DDC 1 I input = ADC
Channel B, DDC 1 Q input = ADC Channel B)
Register 0x314, Register 0x315, Register 0x320,
Register 0x321 = FTW and POW set as required
by application for DDC 0
Register 0x334, Register 0x335, Register 0x340,
Register 0x341 = FTW and POW set as required
by application for DDC 1
Four DDCs 8 Real Complex 9.63% × fS 8 Register 0x200 = 0x03 (four DDCs, I/Q selected)
Register 0x201 = 0x03 (chip decimate by 8)
Register 0x310, Register 0x330, Register 0x350,
Register 0x370 = 0x41 (real mixer, 6 dB gain,
variable IF, complex output, HB3 + HB2 + HB1
filters)
Register 0x311 = 0x00 (DDC 0 I input = ADC
Channel A, DDC 0 Q input = ADC Channel A)
Register 0x331 = 0x00 (DDC 1 I input = ADC
Channel A, DDC 1 Q input = ADC Channel A)
Register 0x351 = 0x05 (DDC 2 I input = ADC
Channel B, DDC 2 Q input = ADC Channel B)
Register 0x371 = 0x05 (DDC 3 I input = ADC
Channel B, DDC 3 Q input = ADC Channel B)
Register 0x314, Register 0x315, Register 0x320,
Register 0x321 = FTW and POW set as required
by application for DDC 0
Register 0x334, Register 0x335, Register 0x340,
Register 0x341 = FTW and POW set as required
by application for DDC 1
Register 0x354, Register 0x355, Register 0x360,
Register 0x361 = FTW and POW set as required
by application for DDC 2
Register 0x374, Register 0x375, Register 0x380,
Register 0x381 = FTW and POW set as required
by application for DDC 3
Four DDCs 8 Real Real 4.81% × fS 4 Register 0x200 = 0x23 (four DDCs, I only selected)
Register 0x201 = 0x03 (chip decimate by 8)
Register 0x310, Register 0x330, Register 0x350,
Register 0x370 = 0x4A (real mixer, 6 dB gain,
variable IF, real output, HB4 + HB3 + HB2 + HB1
filters)
Register 0x311 = 0x00 (DDC 0 I input = ADC
Channel A, DDC 0 Q input = ADC Channel A)
Register 0x331 = 0x00 (DDC 1 I input = ADC
Channel A, DDC 1 Q input = ADC Channel A)
Register 0x351 = 0x05 (DDC 2 I input = ADC
Channel B, DDC 2 Q input = ADC Channel B)
Register 0x371 = 0x05 (DDC 3 I input = ADC
Channel B, DDC 3 Q input = ADC Channel B)

Rev. B | Page 54 of 81
Data Sheet AD6679
Chip Chip DDC DDC No. of Virtual
Application Decimation Input Output Bandwidth Converters
Layer Ratio Type Type Per DDC 1 Required Register Settings 2
Register 0x314, Register 0x315, Register 0x320,
Register 0x321 = FTW and POW set as required
by application for DDC 0
Register 0x334, Register 0x335, Register 0x340,
Register 0x341 = FTW and POW set as required
by application for DDC 1
Register 0x354, Register 0x355, Register 0x360,
Register 0x361 = FTW and POW set as required
by application for DDC 2
Register 0x374, Register 0x375, Register 0x380,
Register 0x381 = FTW and POW set as required
by application for DDC 3
Four DDCs 16 Real Complex 4.81% × fS 8 Register 0x200 = 0x03 (four DDCs, I/Q selected)
Register 0x201 = 0x04 (chip decimate by 16)
Register 0x310, Register 0x330, Register 0x350,
Register 0x370 = 0x42 (real mixer, 6 dB gain,
variable IF, complex output, HB4 + HB3 + HB2 +
HB1 filters)
Register 0x311 = 0x00 (DDC 0 I input = ADC
Channel A, DDC 0 Q input = ADC Channel A)
Register 0x331 = 0x00 (DDC 1 I input = ADC
Channel A, DDC 1 Q input = ADC Channel A)
Register 0x351 = 0x05 (DDC 2 I input = ADC
Channel B, DDC 2 Q input = ADC Channel B)
Register 0x371 = 0x05 (DDC 3 I input = ADC
Channel B, DDC 3 Q input = ADC Channel B)
Register 0x314, Register 0x315, Register 0x320,
Register 0x321 = FTW and POW set as required
by application for DDC 0
Register 0x334, Register 0x335, Register 0x040,
Register 0x341 = FTW and POW set as required
by application for DDC 1
Register 0x354, Register 0x355, Register 0x360,
Register 0x361 = FTW and POW set as required
by application for DDC 2
Register 0x374, Register 0x375, Register 0x380,
Register 0x381 = FTW and POW set as required
by application for DDC 3
1
fS is the ADC sample rate. Bandwidths listed are <−0.001 dB of pass-band ripple and >100 dB of stop band alias rejection.
2
The NCOs must be synchronized either through the SPI or through the SYNC± pins after all writes to the FTW or POW registers are complete. This is necessary to
ensure the proper operation of the NCO. See the NCO Synchronization section for more information.

Rev. B | Page 55 of 81
AD6679 Data Sheet

NOISE SHAPING REQUANTIZER (NSR)

When operating the AD6679 with the NSR enabled, a 10

decimating half-band filter that is optimized at certain input 0

frequency bands can also be enabled. This filter offers the user –10
the flexibility in signal bandwidth process and image rejection.
–20
Careful frequency planning can offer advantages in analog

MAGNITUDE (dB)
filtering preceding the ADC. The filter can function either in –30

high-pass or low-pass mode. The filter can be optionally –40

enabled on the AD6679 when the NSR is enabled. When
–50
operating with NSR enabled, the decimating half-band filter
mode (low pass or high pass) is selected by setting Bit 7 in –60

Register 0x41E. –70

DECIMATING HALF-BAND FILTER –80

13059-070
0 0.05 0.10 0.150 0.20 0.25 0.30 0.35 0.40 0.45 0.50
The AD6679 optional decimating half-band filter reduces the NORMALIZED FREQUENCY (× RAD/SAMPLE)

input sample rate by a factor of 2 while rejecting aliases that fall Figure 72. Low-Pass Half-Band Filter Response
into the band of interest. For an input sample clock of 500 MHz,
The half-band filter can also be utilized in high-pass mode. The
this reduces the output sample rate to 250 MSPS. This filter is
usable bandwidth remains at 39.5% of the output sample rate
designed to provide >40 dB of alias protection for 39.5% of the
(19.75% of the input sample clock), which is the same as in low-
output sample rate (79% of the Nyquist band). For an ADC
pass mode). Figure 73 shows the normalized response of the
sample rate of 500 MSPS, the filter provides a maximum usable
half-band filter in high-pass mode. In high-pass mode, operation
bandwidth of 98.75 MHz.
is allowed in the second and third Nyquist zones, which includes
Half-Band Filter Coefficients frequencies from fS/2 to 3fS/2, where fS is the decimated sample
The 19-tap, symmetrical, fixed-coefficient half-band filter has rate. For example, with an input clock of 500 MHz, the output
low power consumption due to its polyphase implementation. sample rate is 250 MSPS, fS/2 = 125 MHz, and 3fS/2 = 375 MHz.
Table 26 lists the coefficients of the half-band filter in low-pass 10

mode. In high-pass mode, Coefficient C9 is multiplied by −1. 0

The normalized coefficients used in the implementation and
–10
the decimal equivalent values of the coefficients are listed.
Coefficients not listed in Table 26 are 0s. –20
MAGNITUDE (dB)

–30
Table 26. Fixed Coefficients for Half-Band Filter
–40
Coefficient Normalized Decimal Coefficient
Number Coefficient (12-Bit) –50
0 0.012207 25
–60
C2, C16 −0.022949 −47
–70
C4, C14 0.045410 93
C6, C12 −0.094726 −194 –80 13059-071

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
C8, C10 0.314453 644 NORMALIZED FREQUENCY (× π RAD/SAMPLE)
C9 0.500000 1024 Figure 73. High-Pass Half-Band Filter Response
Half-Band Filter Features NSR OVERVIEW
The half-band decimating filter provides approximately 39.5% The AD6679 features an NSR to allow higher than 9-bit SNR to
of the output sample rate in usable bandwidth (19.75% of the be maintained in a subset of the Nyquist band. The harmonic
input sample clock). The filter provides >40 dB of rejection. The performance of the receiver is unaffected by the NSR feature.
normalized response of the half-band filter in low-pass mode is When enabled, the NSR contributes an additional 3.0 dB of loss
shown in Figure 72. In low-pass mode, operation is allowed in to the input signal, such that a 0 dBFS input is reduced to
the first Nyquist zone, which includes frequencies of up to fS/2, −3.0 dBFS at the output pins. This loss does not degrade the SNR
where fS is the decimated sample rate. For example, with an performance of the AD6679.
input clock of 500 MHz, the output sample rate is 250 MSPS
The NSR feature can be independently controlled per channel
and fS/2 = 125 MHz.
via the SPI.
Two different bandwidth modes are provided; select the mode
from the SPI port. In each of the two modes, the center frequency

Rev. B | Page 56 of 81
Data Sheet AD6679
of the band can be tuned such that IFs can be placed anywhere 0
AIN = −1dBFS
in the Nyquist band. The NSR feature is enabled by default on –20
SNR = 75.0dBFS
ENOB = 11.6 BITS
the AD6679. The bandwidth and mode of the NSR operation SFDR = 85dBFS
BUFFER CONTROL 1 = 2.0×
are selected by setting the appropriate bits in Register 0x420 and –40

AMPLITUDE (dBFS)
Register 0x422. By selecting the appropriate profile and mode
bits in these two registers, the NSR feature can be enabled for –60

the desired mode of operation. –80

21% BW Mode (>100 MHz at 491.52 MSPS)
–100
The first NSR mode offers excellent noise performance across a
bandwidth that is 21% of the ADC output sample rate (42% of –120
the Nyquist band) and can be centered by setting the NSR mode
bits in the NSR mode register (Address 0x420) to 000. In this –140

13059-073
0 25 50 75 100 125 150 175 200 225 250
mode, the useful frequency range can be set using the 6-bit FREQUENCY (MHz)
tuning word in the NSR tuning register (Address 0x422). There Figure 75. 21% BW Mode, Tuning Word = 26 (fS/4 Tuning)
are 59 possible tuning words (TW), from 0 to 58; each step is 0
0.5% of the ADC sample rate. The following three equations AIN = −1dBFS
SNR = 74.9dBFS
describe the left band edge (f0), the channel center (fCENTER), and –20 ENOB = 11.6 BITS
SFDR = 90dBFS
the right band edge (f1), respectively: BUFFER CONTROL 1 = 2.0×
–40
f0 = fADC × 0.005 × TW

AMPLITUDE (dBFS)
–60
fCENTER = f0 + 0.105 × fADC
f1 = f0 + 0.21 × fADC –80

Figure 74 to Figure 76 show the typical spectrum that can be –100

expected from the AD6679 in the 21% BW mode for three
different tuning words. –120

0
AIN = −1dBFS –140

13059-074
SNR = 75.2dBFS 0 25 50 75 100 125 150 175 200 225 250
–20 ENOB = 11.6 BITS FREQUENCY (MHz)
SFDR = 87dBFS
BUFFER CONTROL 1 = 2.0× Figure 76. 21% BW Mode, Tuning Word = 58
–40
AMPLITUDE (dBFS)

28% BW Mode (>130 MHz at 491.52 MSPS)

–60
The second NSR mode offers excellent noise performance
–80 across a bandwidth that is 28% of the ADC output sample rate
(56% of the Nyquist band) and can be centered by setting the
–100
NSR mode bits in the NSR mode register (Address 0x420) to
001. In this mode, the useful frequency range can be set using
–120
the 6-bit tuning word in the NSR tuning register (Address 0x422).
–140 There are 44 possible tuning words (TW, from 0 to 43); each step is
13059-072

0 25 50 75 100 125 150 175 200 225 250

FREQUENCY (MHz)
0.5% of the ADC sample rate. The following three equations
describe the left band edge (f0), the channel center (fCENTER), and
Figure 74. 21% BW Mode, Tuning Word = 0
the right band edge (f1), respectively:
f0 = fADC × 0.005 × TW
fCENTER = f0 + 0.14 × fADC
f1 = f0 + 0.28 × fADC
Figure 77 to Figure 79 show the typical spectrum that can be
expected from the AD6679 in the 28% BW mode for three
different tuning words.

Rev. B | Page 57 of 81
AD6679 Data Sheet
0 0
AIN = −1dBFS AIN = −1dBFS
SNR = 72.5dBFS SNR = 71.6dBFS
–20 ENOB = 11.2 BITS –20 ENOB = 11.1 BITS
SFDR = 86dBFS SFDR = 90dBFS
BUFFER CONTROL 1 = 2.0× BUFFER CONTROL 1 = 2.0×
–40 –40
AMPLITUDE (dBFS)

AMPLITUDE (dBFS)
–60 –60

–80 –80

–100 –100

–120 –120

–140 –140

13059-075

13059-077
0 25 50 75 100 125 150 175 200 225 250 0 25 50 75 100 125 150 175 200 225 250
FREQUENCY (MHz) FREQUENCY (MHz)

Figure 77. 28% BW Mode, Tuning Word = 0 Figure 79. 28% BW Mode, Tuning Word = 43
0
AIN = −1dBFS
SNR = 71.7dBFS
–20 ENOB = 11.1 BITS
SFDR = 85dBFS
BUFFER CONTROL 1 = 2.0×
–40
AMPLITUDE (dBFS)

–60

–80

–100

–120

–140
13059-076

0 25 50 75 100 125 150 175 200 225 250

FREQUENCY (MHz)

Figure 78. 28% BW Mode, Tuning Word = 19 (fS/4 Tuning)

Rev. B | Page 58 of 81
Data Sheet AD6679

VARIABLE DYNAMIC RANGE (VDR)

The AD6679 features a variable dynamic range (VDR) digital Table 27. VDR Reduced Output Resolution Values
processing block to allow up to 14-bit dynamic range to be VDR High/Low Output Resolution
maintained in a subset of the Nyquist band. Across the full VDR Punish Bit Resolution Bit (Bits)
Nyquist band, a minimum of a 9-bit dynamic range is available 0 Not applicable 14 or 13
at all times. This operation is suitable for applications such as 1 Not applicable ≤12
digital predistortion processing (DPD). The harmonic Not applicable 0 14
performance of the receiver is unaffected by this feature. When Not applicable 1 ≤13
enabled, VDR does not contribute loss to the input signal but
operates by effectively changing the output resolution at the The frequency zones of the mask are defined by the bandwidth
output pins. This feature can be independently controlled per mode selected in Register 0x430. The upper amplitude limit for
channel via the SPI. input signals located in these frequency zones is −30 dBFS. If
the input signal level in the disallowed frequency zones goes
The VDR block operates in either complex or real mode. In above an amplitude level of −30 dBFS (into the gray shaded
complex mode, VDR has selectable bandwidths of 25% and 43% areas), the VDR block triggers a reduction in the output
of the output sample rate. In real mode, the bandwidth of resolution, as shown in Figure 80. The VDR block engages and
operation is limited to 25% of the output sample rate. The begins limiting output resolution gradually as the signal
bandwidth and mode of the VDR operation are selected by amplitudes increase in the mask regions. As the signal
setting the appropriate bits in Register 0x430. amplitude level increases into the mask regions, the output
When the VDR block is enabled, input signals that violate a resolution is gradually lowered. For every 6 dB increase in
defined mask (signified by gray shaded areas in Figure 80) signal level above −30 dBFS, one bit of output resolution is
result in the reduction of the output resolution of the AD6679. discarded from the output data by the VDR block, as shown in
The VDR block analyzes the peak value of the aggregate signal Table 28. These zones can be tuned within the Nyquist band by
level in the disallowed zones to determine the reduction of the setting Bits[3:0] in Register 0x434 to determine the VDR center
output resolution. To indicate that the AD6679 is reducing frequency (fVDR). The VDR center frequency in complex mode
output, the VDR punish bit or a VDR high/low resolution bit can be adjusted from 1/16 fS to 15/16 fS in 1/16 fS steps. In real
can optionally be on the STATUS±/OVR± pins by programming mode, fVDR can be adjusted from 1/8 fS to 3/8 fS in 1/16 fS steps.
the appropriate value into Register 0x559. The VDR high/low
resolution bit can alternatively be programmed to output on the Table 28. VDR Reduced Output Resolution Values
STATUS± pins and simply indicates if VDR is reducing output Signal Amplitude Violating Defined Output Resolution
VDR Mask (Bits)
resolution (bit value is a 1), or if full resolution is available (bit
value is a 0). These VDR high/low resolution and VDR punish Amplitude ≤ −30 dBFS 14
bits can be decoded by using Table 27. Note that only one can −30 dBFS < amplitude ≤ −24 dBFS 13
be output at a given time. −24 dBFS < amplitude ≤ −18 dBFS 12
−18 dBFS < amplitude ≤ −12 dBFS 11
−12 dBFS < amplitude ≤ −6 dBFS 10
−6 dBFS < amplitude ≤ 0 dBFS 9

dBFS

–30
13059-078

0 fS 0 fS
INTERMODULATION PRODUCTS < –30dBFS INTERMODULATION PRODUCTS > –30dBFS

Figure 80. VDR Operation—Reduction in Output Resolution

Rev. B | Page 59 of 81
AD6679 Data Sheet
VDR REAL MODE VDR COMPLEX MODE
The real mode of VDR works over a bandwidth of 25% of the The complex mode of VDR works with selectable bandwidths
sample rate (50% of the Nyquist band). The output bandwidth of 25% of the sample rate (50% of the Nyquist band) and 43% of
of the AD6679 can be 25% only when operating in real mode. the sample rate (86% of the Nyquist band). Figure 82 and Figure 83
Figure 81 shows the frequency zones for the 25% bandwidth show the frequency zones for VDR in the complex mode. When
real output VDR mode tuned to a center frequency (fVDR) of fS/4 operating VDR in complex mode, place in-phase (I) input
(tuning word = 0x04). The frequency zones where the signal data in Channel A and place quadrature (Q) signal data
amplitude may not exceed −30 dBFS are the upper and lower in Channel B.
portions of the Nyquist band signified by the red shaded areas. Figure 82 shows the frequency zones for the 25% bandwidth
dBFS
VDR mode with a center frequency of fS/4 (tuning word =
0x04). The frequency zones where the amplitude may not
exceed −30 dBFS are the upper and lower portions of the
Nyquist band extending into the complex domain.
dBFS

–30

–30

13059-080
–1/2 fS 0 1/8 fS 3/8 fS 1/2 fS
13059-079

0 1/8 fS 3/8 fS
Figure 82. 25% VDR Bandwidth, Complex Mode
1/2 fS

Figure 81. 25% VDR Bandwidth, Real Mode The center frequency (fVDR) of the VDR function can be tuned
within the Nyquist band from 0 to 15/16fS in 1/16 fS steps. In
The center frequency (fVDR) of the VDR function can be tuned
complex mode, Tuning Word 0 (0x00) through Tuning Word 15
within the Nyquist band from 1/8 fS to 3/8 fS in 1/16 fS steps. In
(0x0F) are valid. Table 31 and Table 32 show the tuning words
real mode, Tuning Word 2 (0x02) through Tuning Word 6
and frequency values for the 25% complex mode. Table 31
(0x06) are valid. Table 29 shows the relative frequency values,
shows the relative frequency values, and Table 32 shows the
and Table 30 shows the absolute frequency values based on a
absolute frequency values based on a sample rate of 491.52 MSPS.
sample rate of 491.52 MSPS.
Table 31. VDR Tuning Words and Relative Frequency
Table 29. VDR Tuning Words and Relative Frequency
Values, 25% BW, Complex Mode
Values, 25% BW, Real Mode
Lower Center Upper Band
Tuning Lower Band Center Upper Band Tuning Word Band Edge Frequency Edge
Word Edge Frequency Edge
0 (0x00) −1/8 fS 0 1/8 fS
2 (0x02) 0 1/8 fS 1/4 fS
1 (0x01) −1/16 fS 1/16 fS 3/16 fS
3 (0x03) 1/16 fS 3/16 fS 5/16 fS
2 (0x02) 0 1/8 fS 1/4 fS
4 (0x04) 1/8 fS 1/4 fS 3/8 fS
3 (0x03) 1/16 fS 3/16 fS 5/16 fS
5 (0x05) 3/16 fS 5/16 fS 7/16 fS
4 (0x04) 1/8 fS 1/4 fS 3/8 fS
6 (0x06) 1/4 fS 3/8 fS 1/2 fS
5 (0x05) 3/16 fS 5/16 fS 7/16 fS
Table 30. VDR Tuning Words and Absolute Frequency 6 (0x06) 1/4 fS 3/8 fS 1/2 fS
Values, 25% BW, Real Mode with fS = 491.52 MSPS 7 (0x07) 5/16 fS 7/16 fS 9/16 fS
Center 8 (0x08) 3/8 fS 1/2 fS 5/8 fS
Tuning Lower Band Frequency Upper Band 9 (0x09) 7/16 fS 9/16 fS 11/16 fS
Word Edge (MHz) (MHz) Edge (MHz) 10 (0x0A) 1/2 fS 5/8 fS 3/4 fS
2 (0x02) 0 61.44 122.88 11 (0x0B) 9/16 fS 11/16 fS 13/16 fS
3 (0x03) 30.72 92.16 153.6 12 (0x0C) 5/8 fS 3/4 fS 7/8 fS
4 (0x04) 61.44 122.88 184.32 13 (0x0D) 11/16 fS 13/16 fS 15/16 fS
5 (0x05) 92.16 153.6 215.04 14 (0x0E) 3/4 fS 7/8 fS fS
6 (0x06) 122.88 184.32 245.76 15 (0x0F) 13/16 fS 15/16 fS 17/16 fS

Rev. B | Page 60 of 81
Data Sheet AD6679
Table 32. VDR Tuning Words and Absolute Frequency Table 33. VDR Tuning Words and Relative Frequency
Values, 25% BW, Complex Mode (fS = 491.52 MSPS) Values, 43% BW, Complex Mode
Lower Center Center
Tuning Band Edge Frequency Upper Band Lower Band Frequency Upper Band
Word (MHz) (MHz) Edge (MHz) Tuning Word Edge (MHz) (MHz) Edge (MHz)
0 (0x00) −61.44 0.00 61.44 0 (0x00) −14/65 fS 0 14/65 fS
1 (0x01) −30.72 30.72 92.16 1 (0x01) −11/72 fS 1/16 fS 5/18 fS
2 (0x02) 0.00 61.44 122.88 2 (0x02) −1/11 fS 1/8 fS 16/47 fS
3 (0x03) 30.72 92.16 153.6 3 (0x03) −1/36 fS 3/16 fS 29/72 fS
4 (0x04) 61.44 122.88 184.32 4 (0x04) 1/29 fS 1/4 fS 20/43 fS
5 (0x05) 92.16 153.6 215.04 5 (0x05) 7/72 fS 5/16 fS 19/36 fS
6 (0x06) 122.88 184.32 245.76 6 (0x06) 4/25 fS 3/8 fS 49/83 fS
7 (0x07) 153.6 215.04 276.48 7 (0x07) 2/9 fS 7/16 fS 47/72 fS
8 (0x08) 184.32 245.76 307.2 8 (0x08) 2/7 fS 1/2 fS 5/7 fS
9 (0x09) 215.04 276.48 337.92 9 (0x09) 25/72 fS 9/16 fS 7/9 fS
10 (0x0A) 245.76 307.2 368.64 10 (0x0A) 34/83 fS 5/8 fS 21/25 fS
11 (0x0B) 276.48 337.92 399.36 11 (0x0B) 17/36 fS 11/16 fS 65/72 fS
12 (0x0C) 307.2 368.64 430.08 12 (0x0C) 23/43 fS 3/4 fS 28/29 fS
13 (0x0D) 337.92 399.36 460.8 13 (0x0D) 43/72 fS 13/16 fS 37/36 fS
14 (0x0E) 368.64 430.08 491.52 14 (0x0E) 31/47 fS 7/8 fS 12/11 fS
15 (0x0F) 399.36 460.8 522.24 15 (0x0F) 13/18 fS 15/16 fS 83/72 fS
Table 33 and Table 34 show the tuning words and frequency Table 34. VDR Tuning Words and Absolute Frequency
values for the 43% complex mode. Table 33 shows the relative Values, 43% BW, Complex Mode (fS = 491.52 MSPS)
frequency values, and Table 34 shows the absolute frequency Center
values based on a sample rate of 491.52 MSPS. Figure 83 shows Lower Band Frequency Upper Band
the frequency zones for the 43% BW VDR mode with a center Tuning Word Edge (MHz) (MHz) Edge (MHz)
frequency (fVDR) of fS/4 (tuning word = 0x04). The frequency 0 (0x00) −105.37 0.00 105.87
zones where the amplitude may not exceed −30 dBFS are the 1 (0x01) −75.09 30.72 136.53
upper and lower portions of the Nyquist band extending into 2 (0x02) −44.68 61.44 167.33
the complex domain. 3 (0x03) −13.65 92.16 197.97
dBFS 4 (0x04) 16.95 122.88 228.61
5 (0x05) 47.79 153.6 259.41
6 (0x06) 78.64 184.32 290.17
–30 7 (0x07) 109.23 215.04 320.85
8 (0x08) 140.43 245.76 351.09
9 (0x09) 170.67 276.48 382.29
10 (0x0A) 201.35 307.2 412.88
13059-081

–1/2 fS 0 1/4 fS 1/2 fS

1/29 fS 20/43 fS
11 (0x0B) 232.11 337.92 443.73
Figure 83. 43% VDR Bandwidth, Complex Mode 12 (0x0C) 262.91 368.64 474.57
13 (0x0D) 293.55 399.36 505.17
14 (0x0E) 324.19 430.08 536.2
15 (0x0F) 354.99 460.8 566.61

Rev. B | Page 61 of 81
AD6679 Data Sheet

DIGITAL OUTPUTS
The AD6679 output drivers are for standard ANSI LVDS, but The minimum conversion rate of the AD6679 is 300 MSPS. At
optionally the drive current can be reduced using Register 0x56A. clock rates below 300 MSPS, dynamic performance may degrade.
The reduced drive current for the LVDS outputs potentially
DATA CLOCK OUTPUT
reduces the digitally induced noise.
The AD6679 also provides a data clock output (DCO) intended
As detailed in the AN-877 Application Note, Interfacing to High for capturing the data in an external register. Figure 4 through
Speed ADCs via SPI, the data format can be selected for offset Figure 11 show the timing diagrams of the AD6679 output
binary, twos complement, or gray code when using the SPI control. modes. The DCO relative to the data output can be adjusted using
The AD6679 has a flexible three-state ability for the digital output Register 0x569. There are delay settings with approximately 90°
pins. The three-state mode is enabled when the device is set for per step ranging from 0° to 270°. Data is output in a DDR format
power-down mode. and is aligned to the rising and falling edges of the clock derived
TIMING from the DCO.

The AD6679 provides latched data with a pipeline delay of ADC OVERRANGE
33 input sample clock cycles. Data outputs are available one The ADC overrange (OR) indicator is asserted when an overrange
propagation delay (tPD) after the rising edge of the clock signal. is detected on the input of the ADC. The overrange condition is
Minimize the length of the output data lines and the corresponding determined at the output of the ADC pipeline and, therefore, is
loads to reduce transients within the AD6679. These transients subject to a latency of 33 ADC clocks. An overrange at the input is
can degrade converter dynamic performance. indicated by the OR bit, 33 clock cycles after it occurs.

Table 35. LVDS Output Configurations 1

Maximum DDC Decimation
Virtual NSR Rates Supported
No. of Virtual Converter Output Decimation
Converters Resolution Line VDR Rates Real Complex
Parallel Output Mode Supported (Bits) Rate 2, 3 Supported Supported Output Output Outputs Required
Parallel Interleaved, 1 14 1 × fOUT Yes 1, 2 1, 2, 4, 8 N/A DCO±, OVR±, and
One Virtual Converter D0± to D13±
(Register 0x568 = 0x0)
Parallel Interleaved, 2 14 2 × fOUT Yes 1, 2 1, 2, 4, 8 2, 4, 8, 16 DCO±, OVR±, and
Two Virtual Converters D0± to D13±
(Register 0x568 = 0x1)
Channel Multiplexed, 1 14 2 × fOUT Yes 1, 2 1, 2, 4, 8 N/A DCO±, OVR±,
One Virtual Converter A Dx/Dy±
(Register 0x568 = 0x2)
Channel Multiplexed, 2 14 2 × fOUT Yes 1, 2 1, 2, 4, 8 2, 4, 8, 16 DCO±, OVR±, A Dx/
Two Virtual Converters Dy±, and B Dx/Dy±
(Register 0x568 = 0x3)
Byte Mode, One Virtual 1 16 2 × fOUT No 1, 2 1, 2, 4, 8 N/A DCO±, STATUS±, and
Converter DATA0± to DATA7±
(Register 0x568 = 0x4)
Byte Mode, Two Virtual 2 16 4 × fOUT No 2 2, 4, 8 2, 4, 8, 16 DCO±, STATUS±, and
Converters DATA0± to DATA7±
(Register 0x568 = 0x5)
Byte Mode, Four Virtual 4 16 8 × fOUT No N/A 2 4, 4, 8 24, 4, 8, 16 DCO±, STATUS±, and
Converters DATA0± to DATA7±
(Register 0x568 = 0x6)
Byte Mode, Eight Virtual 8 16 16 × fOUT No N/A N/A 44, 8, 16 DCO±, STATUS±, and
Converters DATA0± to DATA7±
(Register 0x568 = 0x7)
1
N/A means not applicable.
2
fOUT = ADC Sample Rate ÷ chip decimation ratio, where fOUT is the output sample rate.
3
Maximum output line rate is 1000 Mbps.
4
fOUT ≤ 125 MSPS.

Rev. B | Page 62 of 81
Data Sheet AD6679
Table 36. Pin Mapping Comparison Between Parallel Interleaved, Channel Multiplexed, and Byte Modes
Pin No. Parallel Interleaved Output Channel Multiplexed (Even/Odd) Output Byte Output
K13, K14 DCO−, DCO+ DCO−, DCO+ DCO−, DCO+
L13, L14 OVR−, OVR+ OVR−, OVR+ FCO−, FCO+
M13, M14 D13−, D13+ A D12/D13−, A D12/D13+ STATUS−, STATUS+
N14, P14 D12−, D12+ A D10/D11−, A D10/D11+ DATA7−, DATA7+
N13, P13 D11−, D11+ A D8/D9−, A D8/D9+ DATA6−, DATA6+
N12, P12 D10−, D10+ A D6/D7−, A D6/D7+ DATA5−, DATA5+
N11, P11 D9−, D9+ A D4/D5−, A D4/D5+ DATA4−, DATA4+
N10, P10 D8−, D8+ A D2/D3−, A D2/D3+ DATA3−, DATA3+
N9, P9 D7−, D7+ A D0/D1−, A D0/D1+ DATA2−, DATA2+
N5, P5 D6−, D6+ B D12/D13−, B D12/D13+ DATA1−, DATA1+
N4, P4 D5−, D5+ B D10/D11−, B D10/D11+ DATA0−, DATA0+
N3, P3 D4−, D4+ B D8/D9−, B D8/D9+ Not applicable
N2, P2 D3−, D3+ B D6/D7−, B D6/D7+ Not applicable
N1, P1 D2−, D2+ B D4/D5−, B D4/D5+ Not applicable
M2, M1 D1−, D1+ B D2/D3−, B D2/D3+ Not applicable
N6, P6 D0−, D0+ B D0/D1−, B D0/D1+ Not applicable

Rev. B | Page 63 of 81
AD6679 Data Sheet

MULTICHIP SYNCHRONIZATION
The AD6679 has a SYNC± input that allows the user flexible The AD6679 supports several features that aid users in meeting
options for synchronizing the internal blocks. The SYNC± the requirements for capturing a SYNC± signal. The SYNC±
input is a source synchronous system reference signal that sample event is defined as either a synchronous low to high
enables multichip synchronization. The input clock divider, transition or a synchronous high to low transition. Additionally,
DDCs, and signal monitor block can be synchronized using the the AD6679 allows the SYNC± signal to be sampled using
SYNC± input. For the highest level of timing accuracy, SYNC± either the rising edge or falling edge of the CLK± input. The
must meet the setup and hold requirements relative to the AD6679 also can ignore a programmable number (up to 16) of
CLK± input. SYNC± events. The SYNC± control options can be selected using
The flowchart in Figure 84 shows the internal mechanism by Register 0x120 and Register 0x121.
which multichip synchronization can be achieved in the AD6679.

START

INCREMENT
SYNC± IGNORE
COUNTER

NO NO NO

SYNC±
RESET UPDATE IGNORE
SYNC± COUNTER
SYNC± IGNORE NO ENABLED? YES SYNC± YES SETUP/HOLD
COUNTER ASSERTED? DETECTOR STATUS EXPIRED?
(REG 0x120) (REG 0x121)
(REG 0x128)

YES

INPUT CLOCK
ALIGN CLOCK CLOCK DIVIDER CLOCK INCREMENT
YES YES YES DIVIDER SYNC±
DIVIDER DIVIDER AUTO ADJUST
> 1?
PHASE TO ALIGNMENT ENABLED? COUNTER
(REG 0x10D) (REG 0x10B)
SYNC REQUIRED? (REG 0x12A)

NO NO NO

CLOCK YES ALIGN PHASE OF ALL

ALIGNMENT INTERNAL CLOCKS
REQUIRED? TO SYNC±

NO

SIGNAL
MONITOR ALIGN SIGNAL DDC NCO ALIGN DDC
SYNC YES ALIGNMENT YES NCO PHASE
MONITOR BACK TO START
ENABLED? COUNTERS ENABLED? ACCUMULATOR
(REG 0x26F) (REG 0x300)
13059-082

NO NO

Figure 84. Multichip Synchronization

Rev. B | Page 64 of 81
Data Sheet AD6679
SYNC± SETUP AND HOLD WINDOW MONITOR status values, respectively, for different phases of SYNC±. The
To assist in ensuring a valid SYNC± capture, the AD6679 has a setup detector returns the status of the SYNC± signal before the
SYNC± setup and hold window monitor. This feature allows the CLK± edge and the hold detector returns the status of the
system designer to determine the location of the SYNC± signals SYNC± signal after the CLK± edge. Register 0x128 stores the
relative to the CLK± signals by reading back the amount of status of SYNC± and indicates whether the SYNC± signal was
setup and hold margin on the interface through the memory captured by the ADC.
map. Figure 85 and Figure 86 show both the setup and hold

–1
–2
–3
–4
–5
–6
–7
REG 0x128[3:0] –8
7
6
5
4
3
2
1
0

CLK±
INPUT

SYNC± VALID
INPUT

FLIP FLOP FLIP FLOP

HOLD (MIN) SETUP (MIN)

13059-083
FLIP FLOP
HOLD (MIN)

Figure 85. SYNC ± Setup Detector

Rev. B | Page 65 of 81
AD6679 Data Sheet
–1
–2
–3
–4
–5
–6
–7
REG 0x128[7:4] –8
7
6
5
4
3
2
1
0

CLK±
INPUT

SYNC± VALID
INPUT

FLIP FLOP
FLIP FLOP SETUP (MIN)

13059-084
HOLD (MIN)
FLIP FLOP
HOLD (MIN)

Figure 86. SYNC± Hold Detector

Table 37 shows the description of the contents of Register 0x128 and how to interpret them.

Table 37. SYNC± Setup and Hold Monitor, Register 0x128

Register 0x128, Bits[7:4] Hold Register 0x128, Bits[3:0] Setup
Status Status Description
0x0 0x0 to 0x7 Possible setup error; the smaller this number, the smaller the setup
margin
0x0 to 0x8 0x8 No setup or hold error (best hold margin)
0x8 0x9 to 0xF No setup or hold error (best setup and hold margin)
0x8 0x0 No setup or hold error (best setup margin)
0x9 to 0xF 0x0 Possible hold error; the larger this number, the smaller the hold
margin
0x0 0x0 Possible setup or hold error

Rev. B | Page 66 of 81
Data Sheet AD6679

TEST MODES
ADC TEST MODES (if present, the analog signal is ignored); however, they do
The AD6679 has various test options that aid in the system level require an encode clock.
implementation. The AD6679 has ADC test modes that are If the application mode has been set to select a DDC mode of
available in Register 0x550. These test modes are described in operation, the test modes must be enabled for each DDC
Table 38. When an output test mode is enabled, the analog enabled. The test patterns can be enabled via Bit 2 and Bit 0 of
section of the ADC is disconnected from the digital back-end Register 0x327, Register 0x347, Register 0x367, and Register 0x387,
blocks and the test pattern is run through the output formatting depending on which DDC(s) have been selected. The (I) output
block. Some of the test patterns are subject to output formatting, data uses the test patterns selected for Channel A and the (Q)
and some are not. The PN generators from the PN sequence output data uses the test patterns selected for Channel B. For
tests can be reset by setting Bit 4 or Bit 5 of Register 0x550. more information, see the AN-877 Application Note, Interfacing
These tests can be performed with or without an analog signal to High Speed ADCs via SPI.

Table 38. ADC Test Modes

Output Test Mode Default/Seed
Bit Sequence Pattern Name Expression Value Sample (N, N + 1, N + 2, …)
0000 Off (default) Not applicable Not applicable Not applicable
0001 Midscale short 00 0000 0000 0000 Not applicable Not applicable
0010 Positive Full-scale 01 1111 1111 1111 Not applicable Not applicable
short
0011 Negative Full-scale 10 0000 0000 0000 Not applicable Not applicable
short
0100 Checkerboard 10 1010 1010 1010 Not applicable 0x1555, 0x2AAA, 0x1555, 0x2AAA, 0x1555
0101 PN sequence, long x23 + x18 + 1 0x3AFF 0x3FD7, 0x0002, 0x26E0, 0x0A3D, 0x1CA6
0110 PN sequence, short x9 + x5 + 1 0x0092 0x125B, 0x3C9A, 0x2660, 0x0c65, 0x0697
0111 One-/zero-word 11 1111 1111 1111 Not applicable 0x0000, 0x3FFF, 0x0000, 0x3FFF, 0x0000
toggle
1000 User input Register 0x551 to Not applicable For repeat mode: User Pattern 1[15:2], User Pattern 2[15:2],
Register 0x558 User Pattern 3[15:2], User Pattern 4[15:2], User Pattern 1[15:2]…
For single mode: User Pattern 1[15:2], User Pattern 2[15:2],
User Pattern 3[15:2], User Pattern 4[15:2], 0x0000…
1111 Ramp output (x) % 214 Not applicable (x) % 214, (x + 1) % 214, (x + 2) % 214, (x + 3) % 214

Rev. B | Page 67 of 81
AD6679 Data Sheet

SERIAL PORT INTERFACE (SPI)

The AD6679 SPI allows the user to configure the converter for command is issued. This bit allows the SDIO pin to change
specific functions or operations through a structured register direction from an input to an output.
space provided inside the ADC. The SPI gives the user added In addition to word length, the instruction phase determines
flexibility and customization, depending on the application. whether the serial frame is a read or write operation, allowing
Addresses are accessed via the serial port and can be written to the serial port to be used both to program the chip and to read
or read from via the serial port. Memory is organized into bytes the contents of the on-chip memory. If the instruction is a readback
that can be further divided into fields. These fields are docu- operation, performing a readback causes the SDIO pin to change
mented in the Memory Map section. For detailed operational direction from an input to an output at the appropriate point in
information, see the Serial Control Interface Standard. the serial frame.
CONFIGURATION USING THE SPI Data can be sent in MSB first mode or in LSB first mode. MSB
Three pins define the SPI of this ADC: the SCLK pin, the SDIO first is the default configuration on power-up and can be
pin, and the CSB pin (see Table 39). The SCLK (serial clock) pin is changed via the SPI port configuration register. For more
used to synchronize the read and write data presented from/to the information about this and other features, see the Serial Control
ADC. The SDIO (serial data input/output) pin is a dual-purpose Interface Standard.
pin that allows data to be sent to and read from the internal HARDWARE INTERFACE
ADC memory map registers. The CSB (chip select bar) pin is an
active low control that enables or disables the read and write The pins described in Table 39 compose the physical interface
cycles. between the user programming device and the serial port of the
AD6679. The SCLK pin and the CSB pin function as inputs
Table 39. Serial Port Interface Pins when using the SPI. The SDIO pin is bidirectional, functioning
Pin Function as an input during write phases and as an output during
SCLK Serial clock. The serial shift clock input, which readback.
synchronizes serial interface reads and writes.
The SPI is flexible enough to be controlled by either FPGAs or
SDIO Serial data input/output. A dual-purpose pin that
microcontrollers. One method for SPI configuration is described
typically serves as an input or an output, depending on
the instruction being sent and the relative position in the in detail in the AN-812 Application Note, Microcontroller-
timing frame. Based Serial Port Interface (SPI) Boot Circuit.
CSB Chip select bar. An active low control that gates the read Do not activate the SPI port during periods when the full
and write cycles. dynamic performance of the converter is required. Because the
The falling edge of CSB, in conjunction with the rising edge of SCLK signal, the CSB signal, and the SDIO signal are typically
SCLK, determines the start of the framing. See Figure 3 and asynchronous to the ADC clock, noise from these signals can
Table 5 for an example of the serial timing and its definitions. degrade converter performance. If the on-board SPI bus is used
Other modes involving the CSB pin are available. The CSB pin for other devices, it may be necessary to provide buffers between
can be held low indefinitely, which permanently enables the this bus and the AD6679 to prevent these signals from
device; this is called streaming. The CSB pin can stall high transitioning at the converter inputs during critical sampling
between bytes to allow additional external timing. When CSB is periods.
tied high, SPI functions are placed in a high impedance mode. SPI ACCESSIBLE FEATURES
This mode turns on any SPI pin secondary functions. Table 40 provides a brief description of the general features that
All data is composed of 8-bit words. The first bit of each are accessible via the SPI. These features are described in detail
individual byte of serial data indicates whether a read or write in the Serial Control Interface Standard. The AD6679 device
specific features are described in the Memory Map section.

Table 40. Features Accessible Using the SPI

Feature Name Description
Mode Allows the user to set either power-down mode or standby mode
Clock Allows the user to access the clock divider via the SPI
Test Input/Output Allows the user to set test modes to have known data on output bits
Output Mode Allows the user to set up outputs
Serializer/Deserializer (SERDES) Output Setup Allows the user to vary SERDES settings, including swing and emphasis

Rev. B | Page 68 of 81
Data Sheet AD6679

MEMORY MAP
READING THE MEMORY MAP REGISTER TABLE Channel Specific Registers
Each row in the memory map register table has eight bit locations. Some channel setup functions such as analog input differential
The memory map is roughly divided into seven sections: the termination (Register 0x016) can be programmed to a different
Analog Devices, Inc., SPI registers, the analog input buffer value for each channel. In these cases, channel address locations
control registers, ADC function registers, the DDC function are internally duplicated for each channel. These registers and bits
registers, NSR decimate by 2 and noise shaping requantizer are designated in Table 41 as local. These local registers and bits
registers, variable dynamic range registers, and the digital can be accessed by setting the appropriate Channel A or
outputs and test modes registers. Channel B bits in Register 0x008. If both bits are set, the
subsequent write affects the registers of both channels. In a read
Table 41 (see the Memory Map Register Table section)
cycle, set only Channel A or Channel B to read one of the two
documents the default hexadecimal value for each hexadecimal
registers. If both bits are set during an SPI read cycle, the device
address shown. The column with the heading Bit 7 (MSB) is the
returns the value for Channel A. Registers and bits designated as
start of the default hexadecimal value given. For example,
global in Table 41 affect the entire device and the channel features
Address 0x561, the output format register, has a hexadecimal
for which independent settings are not allowed between
default value of 0x01. This means that Bit 0 = 1, and the
channels. The settings in Register 0x008 do not affect the global
remaining bits are 0s. This setting is the default output format
registers and bits.
value, which is twos complement. For more information on this
function and others, see Table 41. SPI Soft Reset
Open and Reserved Locations After issuing a soft reset by programming 0x81 to Register 0x000,
the AD6679 requires 5 ms to recover. Therefore, when program-
All address and bit locations that are not included in Table 41
ming the AD6679 for application setup, ensure that an adequate
are not currently supported for this device. Write unused bits of
delay is programmed into the firmware after asserting the soft
a valid address location with 0s unless the default value is set
reset and before starting the device setup.
otherwise. Writing to these locations is required only when part
of an address location is open (for example, Address 0x561). If Datapath Soft Reset
the entire address location is open (for example, Address 0x013), After programming the desired clock divider settings, changing
do not write to this address location. the input clock frequency, or glitching the input clock, a datapath
Default Values soft reset is recommended by writing 0x02 to Register 0x001.
This reset function restarts all the datapath and clock generation
After the AD6679 is reset, critical registers are loaded with
circuitry in the device. The reset occurs on the first clock cycle
default values. The default values for the registers are given in
after the register is programmed and the device requires 5 ms to
the memory map register table, Table 41.
recover. This reset does not affect the contents of the memory
Logic Levels map registers.
An explanation of logic level terminology follows:
• “Bit is set” is synonymous with “bit is set to Logic 1” or
“writing Logic 1 for the bit.”
• “Clear a bit” is synonymous with “bit is set to Logic 0” or
“writing Logic 0 for the bit.”
• “X” denotes “don’t care”.

Rev. B | Page 69 of 81
AD6679 Data Sheet
MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 41 are not currently supported for this device.

Table 41. Memory Map Registers

Reg.
Addr. Bit 7 Bit 0
(Hex) Register Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) Default Notes
Analog Devices SPI Registers
0x000 INTERFACE_CONFIG_ Soft LSB first Address 0 0 Address LSB first Soft reset 0x00
A reset 0 = MSB ascension ascension 0 = MSB (self
(self 1 = LSB 1 = LSB clearing):
clearing): clears
clears memory
memory map
map registers
registers
0x001 INTERFACE_CONFIG_B Single 0 0 0 0 0 Datapath 0 0x00
instruc- soft
tion reset
(self
clearing):
does not
clear
memory
map
registers
0x002 DEVICE_CONFIG 0 0 0 0 0 0 00 = normal 0x00
(local) operation
10 = standby
11 = power-down
0x003 CHIP_TYPE 011 = high speed ADC 0x03 Read
only
0x004 CHIP_ID (low byte) 0xD3 Read
only
0x005 CHIP_ID (high byte) 0 0 0 0 0 0 0 0 0x00 Read
only
0x006 CHIP_GRADE Chip speed grade 0 1 0 X X Read
0101 = 500 MSPS only
0x008 Device index 0 0 0 0 0 0 Channel Channel 0x03
B A
0x00A Scratch pad 0 0 0 0 0 0 0 0 0x00
0x00B SPI revision 0 0 0 0 0 0 0 1 0x01
0x00C Vendor ID (low byte) 0 1 0 1 0 1 1 0 0x56 Read
only
0x00D Vendor ID (high byte) 0 0 0 0 0 1 0 0 0x04 Read
only
Analog Input Buffer Control Registers
0x015 Analog Input (local) 0 0 0 0 0 0 0 Input 0x00
disable
0=
normal
operation
1 = input
disabled
0x016 Input termination Analog input differential termination 1 1 0 0 0x0C
(local) 0000 = 400 Ω (default)
0001 = 200 Ω
0010 = 100 Ω
0110 = 50 Ω
0x934 Input capacitance 0 0 0 0x1F = 3 pF to GND (default) 0x1F
0x00 = 1.5 pF to GND

Rev. B | Page 70 of 81
Data Sheet AD6679
Reg.
Addr. Bit 7 Bit 0
(Hex) Register Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) Default Notes
0x018 Buffer Control 1 0000 = 1.0× buffer current 0 0 0 0 0x20
(local) 0001 = 1.5× buffer current
0010 = 2.0× buffer current (default)
0011 = 2.5× buffer current
0100 = 3.0× buffer current
0101 = 3.5× buffer current
…
1111 = 8.5× buffer current
0x019 Buffer Control 2 0100 = Setting 1 0 0 0 0 0x60
(local) 0101 = Setting 2
0110 = Setting 3 (default)
0111 = Setting 4
(see Table 11 for setting per frequency range)
0x01A Buffer Control 3 (local) 0 0 0 0 1000 = Setting 1 0x0A
1001 = Setting 2
1010 = Setting 3 (default)
(see Table 11 for setting per frequency range)
0x11A Buffer Control 4 (local) 0 0 High 0 0 0 0 0 0x00
frequency
setting
0 = off
(default)
1 = on
0x935 Buffer Control 5 (local) 0 0 0 0 0 Low 0 0 0x04
frequency
operation
0 = off
1 = on
(default)
0x025 Input full-scale range 0 0 0 0 Full-scale adjust 0x0C Differ-
(local) 0000 = 1.94 V p-p ential;
1000 = 1.46 V p-p use in
1001 = 1.58 V p-p con-
1010 = 1.70 V p-p junction
1011 = 1.82 V p-p with
1100 = 2.06 V p-p (default) Reg.
0x030
0x030 Input full-scale control 0 0 0 Full-scale control 0 0 0x04 Used in
(local) See Table 11 for recommended con-
settings for different frequency bands; junction
default values: with
Full scale range ≥ 1.82 V = 001 Reg.
Full scale range < 1.82 V = 110 0x025
ADC Function Registers
0x024 V_1P0 control 0 0 0 0 0 0 0 1.0 V 0x00
reference
select
0=
internal
1=
external
0x028 Temperature diode 0 0 0 0 0 0 0 Diode 0x00
(local) selection
0 = no
diode
selected
1=
temper-
ature
diode
selected
0x03F PDWN/STBY pin 0= 0 0 0 0 0 0 0 0x00 Used in
control (local) PDWN/ con-
STBY junction
enabled with
1= Reg.
disabled 0x040
Rev. B | Page 71 of 81
AD6679 Data Sheet
Reg.
Addr. Bit 7 Bit 0
(Hex) Register Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) Default Notes
0x040 Chip pin control PDWN/STBY function Fast Detect B (FD_B) Fast Detect A (FD_A) 0x3F
00 = power down 000 = Fast Detect B output 000 = Fast Detect A output
01 = standby 111 = disabled 011 = temperature diode
10 = disabled 111 = disabled
0x10B Clock divider 0 0 0 0 0 000 = divide by 1 0x00
001 = divide by 2
011 = divide by 4
111 = divide by 8
0x10C Clock divider phase 0 0 0 0 Independently controls Channel A and 0x00
(local) Channel B clock divider phase offset
0000 = 0 input clock cycles delayed
0001 = ½ input clock cycles delayed
0010 = 1 input clock cycles delayed
0011 = 1½ input clock cycles delayed
0100 = 2 input clock cycles delayed
0101 = 2½ input clock cycles delayed
…
1111 = 7½ input clock cycles delayed
0x10D Clock divider and Clock 0 0 0 Clock divider Clock divider positive 0x00 Clock
SYNC± control divider negative skew skew window divider
auto- window 00 = no positive skew must be
phase 00 = no negative 01 = 1 device clock of >1
adjust skew positive skew
0= 01 = 1 device clock of 10 = 2 device clocks
disabled negative skew of positive skew
1= 10 = 2 device clocks 11 = 3 device clocks
enabled of negative skew of positive skew
11 = 3 device clocks
of negative skew
0x117 Clock delay control 0 0 0 0 0 0 0 Clock fine 0x00 Enabling
delay the clock
adjust fine
enable delay
0= adjust
disabled causes a
1= data-
enabled path
soft
reset
0x118 Clock fine delay Clock Fine Delay Adjust[7:0] 0x00 Used in
Twos complement coded control to adjust the fine sample clock skew in ~1.7 ps steps con-
≤−88 = −151.7 ps skew junction
−87 = −150.0 ps skew with
… Reg.
0 = 0 ps skew 0x117
…
≥ +87 = +150 ps skew
0x11C Clock status 0 0 0 0 0 0 0 0 = no 0x00 Read
input only
clock
detected
1 = input
clock
detected
0x120 SYNC± Control 1 0 0 0 SYNC± CLK± SYNC± mode select 0 0x00
transition edge 00 = disabled
select select 01 = continuous
0 = low to 0= 10 = N shot
high rising
1 = high to 1=
low falling
0x121 SYNC± Control 2 0 0 0 0 SYNC± N-shot ignore counter select 0x00 Mode
0000 = next SYNC± only select
0001 = ignore the first SYNC± transitions (Reg.
0010 = ignore the first two SYNC± transitions 0x120,
… Bits[2:1])
1111 = ignore the first 16 SYNC± transitions must be
N-shot
Rev. B | Page 72 of 81
Data Sheet AD6679
Reg.
Addr. Bit 7 Bit 0
(Hex) Register Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) Default Notes
0x128 SYNC± Status 1 SYNC± hold status SYNC± setup status Read
See Table 37 See Table 37 only
0x129 SYNC± and clock 0 0 0 0 Clock divider phase when SYNC± is captured Read
divider status 0000 = in phase only
0001 = SYNC ± is ½ cycle delayed from clock
0010 = SYNC ± is 1 cycle delayed from clock
0011 = 1½ input clock cycles delayed
0100 = 2 input clock cycles delayed
0101 = 2½ input clock cycles delayed
…
1111 = 7½ input clock cycles delayed
0x12A SYNC± counter SYNC± counter, Bits[7:0] increment when a SYNC± signal is captured Read
only
0x200 Chip application 0 0 Chip Q 0 Chip operating mode 0x07
mode ignore 0001 = DDC 0 on
0= 0010 = DDC 0 and DDC 1 on
normal 0011 = DDC 0, DDC 1, DDC 2, and DDC 3 on
(I/Q) 0111 = NSR enabled (default)
1= 1000 = VDR enabled
ignore
(I only)
0x201 Chip decimation ratio 0 0 0 0 0 Chip decimation ratio select 0x00
000 = decimate by 1
001 = decimate by 2
010 = decimate by 4
011 = decimate by 8
100 = decimate by 16
0x228 Customer offset Offset adjust in LSBs from +127 to −128 (twos complement format) 0x00
0x245 Fast detect (FD) 0 0 0 0 Force Force 0 Enable 0x00
control (local) FD_A/ value of fast
FD_B FD_A/ detect
pins FD_B output
0= pins; if
normal force pins
func- is true,
tion this value
1= is output
force to on FD_x
value pins
0x247 FD upper threshold Fast Detect Upper Threshold[7:0] 0x00
LSB (local)
0x248 FD upper threshold 0 0 0 Fast Detect Upper Threshold[12:8] 0x00
MSB (local)
0x249 FD lower threshold Fast Detect Lower Threshold[7:0] 0x00
LSB (local)
0x24A FD lower threshold 0 0 0 Fast Detect Lower Threshold[12:8] 0x00
MSB (local)
0x24B FD dwell time LSB Fast Detect Dwell Time[7:0] 0x00
(local)
0x24C FD dwell time MSB Fast Detect Dwell Time[15:8] 0x00
(local)
0x26F Signal monitor 0 0 0 0 0 0 Synchronization 0x00 See the
synchronization mode Signal
control 00 = disabled Monitor
01 = continuous section
11 = one-shot
0x270 Signal monitor 0 0 0 0 0 0 Peak 0 0x00
control (local) detector
0=
disabled
1=
enabled

Rev. B | Page 73 of 81
AD6679 Data Sheet
Reg.
Addr. Bit 7 Bit 0
(Hex) Register Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) Default Notes
0x271 Signal Monitor Period Signal Monitor Period[7:1] 0 0x80 In dec-
Register 0 (local) imated
output
clock
cycles
0x272 Signal Monitor Period Signal Monitor Period[15:8] 0x00 In dec-
Register 1 (local) imated
output
clock
cycles
0x273 Signal Monitor Period Signal Monitor Period[23:16] 0x00 In dec-
Register 2 (local) imated
output
clock
cycles
0x274 Signal monitor result 0 0 0 Result 0 0 0 Result 0x01
control (local) update selection
1 = update 0=
results (self Reserved
clear) 1 = peak
detector
0x275 Signal Monitor Result Signal Monitor Result[7:0] Read
Register 0 (local) When Register 0x0274, Bit 0 = 1, Result Bits[19:7] = Peak Detector Absolute Value[12:0]; only,
Result Bits[6:0] = 0 updated
based
on Reg.
0x274,
Bit 4
0x276 Signal Monitor Result Signal Monitor Result[15:8] Read
Register 1 (local) only,
updated
based
on Reg.
0x274,
Bit 4
0x277 Signal Monitor Result 0 0 0 0 Signal Monitor Result[19:16] Read
Register 1 (local) only,
updated
based
on Reg.
0x274,
Bit 4
0x278 Signal monitor period Period Count Result[7:0] Read
counter result (local) only,
updated
based
on Reg
0x274,
Bit 4
Digital Downconverter (DDC) Function Registers—See the Digital Downconverter (DDC) Section
0x300 DDC synchronization 0 0 0 DDC NCO 0 0 Synchronization 0x00
control soft reset mode
0 = normal 00 = disabled
operation 01 = continuous
1 = reset 11 = one shot

Rev. B | Page 74 of 81
Data Sheet AD6679
Reg.
Addr. Bit 7 Bit 0
(Hex) Register Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) Default Notes
0x310 DDC 0 control Mixer Gain IF mode Complex 0 Decimation rate 0x00
select select 00 = variable IF mode to real select
0 = real 0 = 0 dB (mixers and NCO enable (complex to real
mixer gain enabled) 0= disabled)
1= 1 = 6 dB 01 = 0 Hz IF mode disabled 11 = decimate by 2
complex gain (mixer bypassed, NCO 1= 00 = decimate by 4
mixer disabled) enabled 01 = decimate by 8
10 = fADC/4 Hz IF mode 10 = decimate by 16
(fADC/4 downmixing (complex to real
mode) enabled)
11 = test mode (mixer 11 = decimate by 1
inputs forced to +FS, 00 = decimate by 2
NCO enabled) 01 = decimate by 4
10 = decimate by 8
0x311 DDC 0 input selection 0 0 0 0 0 Q input 0 I input 0x00
select select
0 = Ch. A 0 = Ch. A
1 = Ch. B 1 = Ch. B
0x314 DDC 0 frequency LSB DDC 0 NCO FTW[7:0], twos complement 0x00
0x315 DDC 0 frequency MSB X X X X DDC 0 NCO FTW[11:8], twos complement 0x00
0x320 DDC 0 phase LSB DDC 0 NCO POW[7:0], twos complement 0x00
0x321 DDC 0 phase MSB X X X X DDC 0 NCO POW[11:8], twos complement 0x00
0x327 DDC 0 output test 0 0 0 0 0 Q output 0 I output 0x00
mode selection test test
mode mode
enable enable
0= 0=
disabled disabled
1= 1=
enabled enabled
from from
Ch. B Ch. A
0x330 DDC 1 control Mixer Gain IF mode Complex 0 Decimation rate 0x00
select select 00 = variable IF mode to real select
0 = real 0 = 0 dB (mixers and NCO enable (complex to real
mixer gain enabled) 0= disabled)
1= 1 = 6 dB 01 = 0 Hz IF mode disabled 11 = decimate by 2
complex gain (mixer bypassed, NCO 1= 00 = decimate by 4
mixer disabled) enabled 01 = decimate by 8
10 = fADC/4 Hz IF mode 10 = decimate by 16
(fADC/4 downmixing (complex to real
mode) enabled)
11 = test mode (mixer 11 = decimate by 1
inputs forced to +FS, 00 = decimate by 2
NCO enabled) 01 = decimate by 4
10 = decimate by 8
0x331 DDC 1 input selection 0 0 0 0 0 Q input 0 I input 0x05
select select
0 = Ch. A 0 = Ch. A
1 = Ch. B 1 = Ch. B
0x334 DDC 1 frequency LSB DDC 1 NCO FTW[7:0], twos complement 0x00
0x335 DDC 1 frequency MSB X X X X DDC1 NCO FTW[11:8], twos complement 0x00
0x340 DDC 1 phase LSB DDC 1 NCO POW[7:0], twos complement 0x00
0x341 DDC 1 phase MSB X X X X DDC1 NCO POW[11:8], twos complement 0x00
0x347 DDC 1 output test 0 0 0 0 0 Q output 0 I output 0x00
mode selection test test
mode mode
enable enable
0= 0=
disabled disabled
1= 1=
enabled enabled
from from
Ch. B Ch. A

Rev. B | Page 75 of 81
AD6679 Data Sheet
Reg.
Addr. Bit 7 Bit 0
(Hex) Register Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) Default Notes
0x350 DDC 2 control Mixer Gain IF mode Complex 0 Decimation rate 0x00
select select 00 = variable IF mode to real select
0 = real 0 = 0 dB (mixers and NCO enable (complex to real
mixer gain enabled) 0= disabled)
1= 1 = 6 dB 01 = 0 Hz IF mode disabled 11 = decimate by 2
complex gain (mixer bypassed, NCO 1= 00 = decimate by 4
mixer disabled) enabled 01 = decimate by 8
10 = fADC/4 Hz IF mode 10 = decimate by 16
(fADC/4 downmixing (complex to real
mode) enabled)
11 = test mode (mixer 11 = decimate by 1
inputs forced to +FS, 00 = decimate by 2
NCO enabled) 01 = decimate by 4
10 = decimate by 8
0x351 DDC 2 input selection 0 0 0 0 0 Q input 0 I input 0x00
select select
0 = Ch. A 0 = Ch. A
1 = Ch. B 1 = Ch. B
0x354 DDC 2 frequency LSB DDC 2 NCO FTW[7:0], twos complement 0x00
0x355 DDC 2 frequency MSB X X X X DDC 2 NCO FTW[11:8], twos complement 0x00
0x360 DDC 2 phase LSB DDC 2 NCO POW[7:0], twos complement 0x00
0x361 DDC 2 phase MSB X X X X DDC 2 NCO POW[11:8], twos complement 0x00
0x367 DDC 2 output test 0 0 0 0 0 Q output 0 I output 0x00
mode selection test test
mode mode
enable enable
0= 0=
disabled disabled
1= 1=
enabled enabled
from from
Ch. B Ch. A
0x370 DDC 3 control Mixer Gain IF mode Complex 0 Decimation rate 0x00
select select 00 = variable IF mode to real select
0 = real 0 = 0 dB (mixers and NCO enable (complex to real
mixer gain enabled) 0= disabled)
1= 1 = 6 dB 01 = 0 Hz IF mode disabled 11 = decimate by 2
complex gain (mixer bypassed, NCO 1= 00 = decimate by 4
mixer disabled) enabled 01 = decimate by 8
10 = fADC/4 Hz IF mode 10 = decimate by 16
(fADC/4 downmixing (complex to real
mode) enabled)
11 = test mode (mixer 11 = decimate by 1
inputs forced to +FS, 00 = decimate by 2
NCO enabled) 01 = decimate by 4
10 = decimate by 8
0x371 DDC 3 input selection 0 0 0 0 0 Q input 0 I input 0x05
select select
0 = Ch. A 0 = Ch. A
1 = Ch. B 1 = Ch. B
0x374 DDC 3 frequency LSB DDC 3 NCO FTW[7:0], twos complement 0x00
0x375 DDC 3 frequency MSB X X X X DDC 3 NCO FTW[11:8], twos complement 0x00
0x380 DDC 3 phase LSB DDC 3 NCO POW[7:0], twos complement 0x00
0x381 DDC 3 phase MSB X X X X DDC 3 NCO POW[11:8], twos complement 0x00
0x387 DDC 3 output test 0 0 0 0 0 Q output 0 I output 0x00
mode selection test test
mode mode
enable enable
0= 0=
disabled disabled
1= 1=
enabled enabled
from from
Ch. B Ch. A
NSR Decimate by 2 and Noise Shaping Requantizer (NSR)

Rev. B | Page 76 of 81
Data Sheet AD6679
Reg.
Addr. Bit 7 Bit 0
(Hex) Register Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) Default Notes
0x41E NSR decimate by 2 High- X 0 0 X X X NSR 0x00
pass decimate
filter by 2
(HPF)/ enable
low-pass 0=
filter disabled
mode 1=
0= enabled
enable
LPF
1=
enable
HPF
0x420 NSR mode X X X X NSR mode X 0x00
000 = 21% BW mode
001 = 28% BW mode
0x422 NSR tuning X X NSR tuning word; see the Noise Shaping Requantizer (NSR) section; 0x00
equations for the tuning word are dependent on the NSR mode
Variable Dynamic Range (VDR)
0x430 VDR control X X X 0 X X VDR BW 0 = dual 0x01
mode real
0 = 25% mode
BW 1 = dual
mode complex
1 = 43% mode
BW (Channel
mode A = I,
(only Channel
available B = Q)
for dual
complex
mode)
0x434 VDR tuning X X X X VDR center frequency; see the Variable 0x00
Dynamic Range (VDR) section for more details
on the center frequency, which is dependent
on the VDR mode
Digital Outputs and Test Modes
0x550 ADC test modes User 0 Reset PN Reset PN Test mode selection 0x00
(local) pattern long gen short gen 0000 = off (normal operation)
selection 0 = long 0 = short 0001 = midscale short
0= PN PN enable 0010 = positive full scale
contin- enable 1 = short 0011 = negative full scale
uous 1 = long PN reset 0100 = alternating checkerboard
repeat PN reset 0101 = PN sequence, long
1= 0110 = PN sequence, short
single 0111 = 1/0 word toggle
pattern 1000 = user pattern test mode (used with
Register 0x550, Bit 7, and User Pattern 1 to
User Pattern 4 registers)
1111 = ramp output
0x551 User Pattern 1 LSB 0 0 0 0 0 0 0 0 0x00 Used
with
Reg.
0x550
0x552 User Pattern 1 MSB 0 0 0 0 0 0 0 0 0x00 Used
with
Reg.
0x550
0x553 User Pattern 2 LSB 0 0 0 0 0 0 0 0 0x00 Used
with
Reg.
0x550
0x554 User Pattern 2 MSB 0 0 0 0 0 0 0 0 0x00 Used
with
Reg.
0x550

Rev. B | Page 77 of 81
AD6679 Data Sheet
Reg.
Addr. Bit 7 Bit 0
(Hex) Register Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) Default Notes
0x555 User Pattern 3 LSB 0 0 0 0 0 0 0 0 0x00 Used
with
Reg.
0x550
0x556 User Pattern 3 MSB 0 0 0 0 0 0 0 0 0x00 Used
with
Reg.
0x550
0x557 User Pattern 4 LSB 0 0 0 0 0 0 0 0 0x00 Used
with
Reg.
0x550
0x558 User Pattern 4 MSB 0 0 0 0 0 0 0 0 0x00 Used
with
Reg.
0x550
0x559 Output Mode 0 0 0 0 0 Status bit selection 0x00
Control 1 000 = tie low (1’b0)
001 = overrange bit
010 = signal monitor bit
011 = fast detect (FD) bit or VDR
punish bit
100 = VDR high/low resolution bit
101 = system reference
0x561 Output format 0 0 0 0 0 Sample Data format select 0x01
invert 00 = offset binary
0= 01 = twos
normal complement (default)
1=
sample
invert
0x562 Output overrange Virtual Virtual Virtual Virtual Virtual Virtual Virtual Virtual 0x00
(OR) clear Con- Con- Con- Converter 4 Con- Con- Con- Con-
verter 7 verter 6 verter 5 OR verter 3 verter 2 verter 1 verter 0
OR OR OR 0 = OR bit OR OR OR OR
0 = OR 0 = OR 0 = OR enabled 0 = OR 0 = OR bit 0 = OR 0 = OR bit
bit bit bit 1 = OR bit bit enabled bit enabled
enabled enabled enabled cleared enabled 1 = OR bit enabled 1 = OR bit
1 = OR 1 = OR 1 = OR 1 = OR cleared 1 = OR cleared
bit bit bit bit bit
cleared cleared cleared cleared cleared
0x563 Output overrange Virtual Virtual Virtual Virtual Virtual Virtual Virtual Virtual 0x00 Read
status Con- Con- Con- Converter 4 Con- Con- Con- Con- only
verter 7 verter 6 verter 5 OR verter 3 verter 2 verter 1 verter 0
OR OR OR 0 = no OR OR OR OR OR
0 = no 0 = no 0 = no 1 = OR 0 = no 0 = no OR 0 = no 0 = no OR
OR OR OR occurred OR 1 = OR OR 1 = OR
1 = OR 1 = OR 1 = OR 1 = OR occurred 1 = OR occurred
occurred occurred occurred occurred occurred
0x564 Output channel select 0 0 0 0 0 0 0 Converter 0x00
channel
swap
0=
normal
channel
ordering
1=
channel
swap
enabled

Rev. B | Page 78 of 81
Data Sheet AD6679
Reg.
Addr. Bit 7 Bit 0
(Hex) Register Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) Default Notes
0x568 Output mode 0 0 Frame clock mode (only 0 Output data mode
used when in output 000 = parallel interleaved mode
data mode is in byte (one virtual converter)
mode) 001 = parallel interleaved mode
00 = frame clock always (two virtual converters)
off 010 = channel multiplexed
01 = frame clock always (even/odd) mode
on (one virtual converter)
10 = reserved 011 = channel multiplexed
11 = frame clock (even/odd) mode
conditionally on based (two virtual converters)
on PN23 sequence 100 = byte mode
(one virtual converter)
101 = byte mode
(two virtual converters)
110 = byte mode
(four virtual converters)
111 = byte mode
(eight virtual converters)
0x569 DCO output delay 0 0 0 0 0 0 DCO clock delay 0x01
00 = 0°
01 = 90° (available
when DCO rate is less
than sample clock
rate)
10 = 180°
11 = 270° (available
when DCO rate is less
than sample clock
rate)
0x56A Output adjust 0 1 0 0 LVDS output drive current adjust 0 0x4C
000 = 2 mA
001 = 2.25 mA
010 = 2.5 mA
011 = 2.75 mA
100 = 3.0 mA
101 = 3.25 mA
110 = 3.5 mA (default)
111 = 3.75 mA
0x56B Output slew rate 0 0 0 0 0 0 Output slew rate 0x00
adjust control
00 = 80 ps
01 = 150 ps
10 = 200 ps
11 = 250 ps

Rev. B | Page 79 of 81
AD6679 Data Sheet

APPLICATIONS INFORMATION
POWER SUPPLY RECOMMENDATIONS 1.8V ADP1741
AVDD1
1.25V

The AD6679 must be powered by the following six supplies:

AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, DVDD =
1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V. For applications
requiring an optimal high power efficiency and low noise
DVDD
performance, it is recommended that the ADP2164 and ADP1741 1.25V
ADP2370 switching regulators be used to convert the 3.3 V, DRVDD
1.25V
5.0 V, or 12 V input rails to an intermediate rail (1.8 V and
SPIVDD
3.8 V). These intermediate rails are then postregulated by very (1.8V OR 3.3V)

low noise, low dropout (LDO) regulators (ADP1741, ADM7172,

3.6V
and ADP125). Figure 87 shows the recommended method. ADP125 AVDD3
3.3V
For more detailed information on the recommended power ADM7172

13059-085
3.3V AVDD2
solution, see the AD6679 evaluation board wiki, Evaluating the OR
ADP1741 2.5V
AD6679 IF Diversity Receiver. Figure 87. High Efficiency, Low Noise Power Solution for the AD6679

It is not necessary to split all of these power domains in all

cases. The recommended solution shown in Figure 87 provides
the lowest noise, highest efficiency power delivery system for
the AD6679. If only one 1.25 V supply is available, it must be
routed to AVDD1 first and then tapped off and isolated with a
ferrite bead or a filter choke preceded by decoupling capacitors
for SPIVDD, DVDD, and DRVDD, in that order. The user can
use several different decoupling capacitors to cover both high
and low frequencies. These capacitors must be located close to
the point of entry at the PCB level and close to the devices, with
minimal trace lengths.

Rev. B | Page 80 of 81
Data Sheet AD6679

OUTLINE DIMENSIONS

12.10
12.00 SQ A1 BALL
A1 BALL 11.90 PAD CORNER
PAD CORNER 14 13 12 11 10 9 8 7 6 5 4 3 2 1

A
B
C
D
E
8.20 SQ 10.40 REF F
SQ G
H
J
0.80 K
11.20 SQ L
M
N
P
TOP VIEW BOTTOM VIEW
0.80 REF

DETAIL A
1.49 1.15
1.38 1.05
1.27 DETAIL A 0.95
0.75
REF
0.38
0.33
0.28
0.30 REF

SEATING 0.50 COPLANARITY

PLANE 0.45 0.12
0.40
BALL DIAMETER

04-24-2015-A
PKG-004472

COMPLIANT TO JEDEC STANDARDS MO-275-GGAB-1.

Figure 88. 196-Ball Ball Grid Array, Thermally Enhanced [BGA_ED]

(BP-196-3)
Dimensions shown in millimeters

ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD6679BBPZ-500 −40°C to +85°C 196-Ball Ball Grid Array, Thermally Enhanced [BGA_ED] BP-196-3
AD6679BBPZRL7-500 −40°C to +85°C 196-Ball Ball Grid Array, Thermally Enhanced [BGA_ED] BP-196-3
AD6679-500EBZ Evaluation Board for AD6679-500
1
Z = RoHS Compliant Part.

©2015–2016 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D13059-0-4/16(B)

Rev. B | Page 81 of 81